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Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
9102d871 NF |
12 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
13 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
14 | * found on AT91SAM9263. | |
dc78baa2 NF |
15 | */ |
16 | ||
62971b29 | 17 | #include <dt-bindings/dma/at91.h> |
dc78baa2 NF |
18 | #include <linux/clk.h> |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
bbe89c8e | 28 | #include <linux/of_dma.h> |
dc78baa2 NF |
29 | |
30 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 31 | #include "dmaengine.h" |
dc78baa2 NF |
32 | |
33 | /* | |
34 | * Glossary | |
35 | * -------- | |
36 | * | |
37 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
38 | * at_dma_ / atdma : ATmel DMA controller entity related | |
39 | * atc_ / atchan : ATmel DMA Channel entity related | |
40 | */ | |
41 | ||
42 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
816070ed LD |
45 | #define ATC_DMA_BUSWIDTHS\ |
46 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
47 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
48 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
49 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
dc78baa2 | 50 | |
93dce3a6 CP |
51 | #define ATC_MAX_DSCR_TRIALS 10 |
52 | ||
dc78baa2 NF |
53 | /* |
54 | * Initial number of descriptors to allocate for each channel. This could | |
55 | * be increased during dma usage. | |
56 | */ | |
57 | static unsigned int init_nr_desc_per_channel = 64; | |
58 | module_param(init_nr_desc_per_channel, uint, 0644); | |
59 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
60 | "initial descriptors per channel (default: 64)"); | |
61 | ||
62 | ||
63 | /* prototypes */ | |
64 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
d48de6f1 | 65 | static void atc_issue_pending(struct dma_chan *chan); |
dc78baa2 NF |
66 | |
67 | ||
68 | /*----------------------------------------------------------------------*/ | |
69 | ||
265567fb TF |
70 | static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst, |
71 | size_t len) | |
72 | { | |
73 | unsigned int width; | |
74 | ||
75 | if (!((src | dst | len) & 3)) | |
76 | width = 2; | |
77 | else if (!((src | dst | len) & 1)) | |
78 | width = 1; | |
79 | else | |
80 | width = 0; | |
81 | ||
82 | return width; | |
83 | } | |
84 | ||
dc78baa2 NF |
85 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) |
86 | { | |
87 | return list_first_entry(&atchan->active_list, | |
88 | struct at_desc, desc_node); | |
89 | } | |
90 | ||
91 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
92 | { | |
93 | return list_first_entry(&atchan->queue, | |
94 | struct at_desc, desc_node); | |
95 | } | |
96 | ||
97 | /** | |
421f91d2 | 98 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
99 | * @chan: the channel to allocate descriptors for |
100 | * @gfp_flags: GFP allocation flags | |
101 | * | |
102 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
103 | * to make initial allocation more convenient. This bit will be cleared | |
104 | * and control will be given to client at usage time (during | |
105 | * preparation functions). | |
106 | */ | |
107 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
108 | gfp_t gfp_flags) | |
109 | { | |
110 | struct at_desc *desc = NULL; | |
111 | struct at_dma *atdma = to_at_dma(chan->device); | |
112 | dma_addr_t phys; | |
113 | ||
114 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
115 | if (desc) { | |
116 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 117 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
118 | dma_async_tx_descriptor_init(&desc->txd, chan); |
119 | /* txd.flags will be overwritten in prep functions */ | |
120 | desc->txd.flags = DMA_CTRL_ACK; | |
121 | desc->txd.tx_submit = atc_tx_submit; | |
122 | desc->txd.phys = phys; | |
123 | } | |
124 | ||
125 | return desc; | |
126 | } | |
127 | ||
128 | /** | |
af901ca1 | 129 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
130 | * @atchan: channel we want a new descriptor for |
131 | */ | |
132 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
133 | { | |
134 | struct at_desc *desc, *_desc; | |
135 | struct at_desc *ret = NULL; | |
d8cb04b0 | 136 | unsigned long flags; |
dc78baa2 NF |
137 | unsigned int i = 0; |
138 | LIST_HEAD(tmp_list); | |
139 | ||
d8cb04b0 | 140 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
141 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
142 | i++; | |
143 | if (async_tx_test_ack(&desc->txd)) { | |
144 | list_del(&desc->desc_node); | |
145 | ret = desc; | |
146 | break; | |
147 | } | |
148 | dev_dbg(chan2dev(&atchan->chan_common), | |
149 | "desc %p not ACKed\n", desc); | |
150 | } | |
d8cb04b0 | 151 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
152 | dev_vdbg(chan2dev(&atchan->chan_common), |
153 | "scanned %u descriptors on freelist\n", i); | |
154 | ||
155 | /* no more descriptor available in initial pool: create one more */ | |
156 | if (!ret) { | |
157 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
158 | if (ret) { | |
d8cb04b0 | 159 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 160 | atchan->descs_allocated++; |
d8cb04b0 | 161 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
162 | } else { |
163 | dev_err(chan2dev(&atchan->chan_common), | |
164 | "not enough descriptors available\n"); | |
165 | } | |
166 | } | |
167 | ||
168 | return ret; | |
169 | } | |
170 | ||
171 | /** | |
172 | * atc_desc_put - move a descriptor, including any children, to the free list | |
173 | * @atchan: channel we work on | |
174 | * @desc: descriptor, at the head of a chain, to move to free list | |
175 | */ | |
176 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
177 | { | |
178 | if (desc) { | |
179 | struct at_desc *child; | |
d8cb04b0 | 180 | unsigned long flags; |
dc78baa2 | 181 | |
d8cb04b0 | 182 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 183 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
184 | dev_vdbg(chan2dev(&atchan->chan_common), |
185 | "moving child desc %p to freelist\n", | |
186 | child); | |
285a3c71 | 187 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
188 | dev_vdbg(chan2dev(&atchan->chan_common), |
189 | "moving desc %p to freelist\n", desc); | |
190 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 191 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
192 | } |
193 | } | |
194 | ||
53830cc7 | 195 | /** |
d73111c6 MI |
196 | * atc_desc_chain - build chain adding a descriptor |
197 | * @first: address of first descriptor of the chain | |
198 | * @prev: address of previous descriptor of the chain | |
53830cc7 NF |
199 | * @desc: descriptor to queue |
200 | * | |
201 | * Called from prep_* functions | |
202 | */ | |
203 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
204 | struct at_desc *desc) | |
205 | { | |
206 | if (!(*first)) { | |
207 | *first = desc; | |
208 | } else { | |
209 | /* inform the HW lli about chaining */ | |
210 | (*prev)->lli.dscr = desc->txd.phys; | |
211 | /* insert the link descriptor to the LD ring */ | |
212 | list_add_tail(&desc->desc_node, | |
213 | &(*first)->tx_list); | |
214 | } | |
215 | *prev = desc; | |
216 | } | |
217 | ||
dc78baa2 NF |
218 | /** |
219 | * atc_dostart - starts the DMA engine for real | |
220 | * @atchan: the channel we want to start | |
221 | * @first: first descriptor in the list we want to begin with | |
222 | * | |
223 | * Called with atchan->lock held and bh disabled | |
224 | */ | |
225 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
226 | { | |
227 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
228 | ||
229 | /* ASSERT: channel is idle */ | |
230 | if (atc_chan_is_enabled(atchan)) { | |
231 | dev_err(chan2dev(&atchan->chan_common), | |
232 | "BUG: Attempted to start non-idle channel\n"); | |
233 | dev_err(chan2dev(&atchan->chan_common), | |
234 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
235 | channel_readl(atchan, SADDR), | |
236 | channel_readl(atchan, DADDR), | |
237 | channel_readl(atchan, CTRLA), | |
238 | channel_readl(atchan, CTRLB), | |
239 | channel_readl(atchan, DSCR)); | |
240 | ||
241 | /* The tasklet will hopefully advance the queue... */ | |
242 | return; | |
243 | } | |
244 | ||
245 | vdbg_dump_regs(atchan); | |
246 | ||
dc78baa2 NF |
247 | channel_writel(atchan, SADDR, 0); |
248 | channel_writel(atchan, DADDR, 0); | |
249 | channel_writel(atchan, CTRLA, 0); | |
250 | channel_writel(atchan, CTRLB, 0); | |
251 | channel_writel(atchan, DSCR, first->txd.phys); | |
5abecfa5 MR |
252 | channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) | |
253 | ATC_SPIP_BOUNDARY(first->boundary)); | |
254 | channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) | | |
255 | ATC_DPIP_BOUNDARY(first->boundary)); | |
dc78baa2 NF |
256 | dma_writel(atdma, CHER, atchan->mask); |
257 | ||
258 | vdbg_dump_regs(atchan); | |
259 | } | |
260 | ||
d48de6f1 | 261 | /* |
bdf6c792 TF |
262 | * atc_get_desc_by_cookie - get the descriptor of a cookie |
263 | * @atchan: the DMA channel | |
264 | * @cookie: the cookie to get the descriptor for | |
d48de6f1 | 265 | */ |
bdf6c792 TF |
266 | static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan, |
267 | dma_cookie_t cookie) | |
d48de6f1 | 268 | { |
bdf6c792 | 269 | struct at_desc *desc, *_desc; |
d48de6f1 | 270 | |
bdf6c792 TF |
271 | list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) { |
272 | if (desc->txd.cookie == cookie) | |
273 | return desc; | |
274 | } | |
d48de6f1 | 275 | |
bdf6c792 TF |
276 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { |
277 | if (desc->txd.cookie == cookie) | |
278 | return desc; | |
d48de6f1 ES |
279 | } |
280 | ||
bdf6c792 | 281 | return NULL; |
d48de6f1 ES |
282 | } |
283 | ||
bdf6c792 TF |
284 | /** |
285 | * atc_calc_bytes_left - calculates the number of bytes left according to the | |
286 | * value read from CTRLA. | |
287 | * | |
288 | * @current_len: the number of bytes left before reading CTRLA | |
289 | * @ctrla: the value of CTRLA | |
bdf6c792 | 290 | */ |
93dce3a6 | 291 | static inline int atc_calc_bytes_left(int current_len, u32 ctrla) |
bdf6c792 | 292 | { |
93dce3a6 CP |
293 | u32 btsize = (ctrla & ATC_BTSIZE_MAX); |
294 | u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla); | |
bdf6c792 | 295 | |
93dce3a6 CP |
296 | /* |
297 | * According to the datasheet, when reading the Control A Register | |
298 | * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the | |
299 | * number of transfers completed on the Source Interface. | |
300 | * So btsize is always a number of source width transfers. | |
301 | */ | |
302 | return current_len - (btsize << src_width); | |
bdf6c792 TF |
303 | } |
304 | ||
305 | /** | |
306 | * atc_get_bytes_left - get the number of bytes residue for a cookie | |
307 | * @chan: DMA channel | |
308 | * @cookie: transaction identifier to check status of | |
d48de6f1 | 309 | */ |
bdf6c792 | 310 | static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) |
d48de6f1 ES |
311 | { |
312 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d48de6f1 | 313 | struct at_desc *desc_first = atc_first_active(atchan); |
bdf6c792 TF |
314 | struct at_desc *desc; |
315 | int ret; | |
93dce3a6 | 316 | u32 ctrla, dscr, trials; |
d48de6f1 ES |
317 | |
318 | /* | |
bdf6c792 TF |
319 | * If the cookie doesn't match to the currently running transfer then |
320 | * we can return the total length of the associated DMA transfer, | |
321 | * because it is still queued. | |
d48de6f1 | 322 | */ |
bdf6c792 TF |
323 | desc = atc_get_desc_by_cookie(atchan, cookie); |
324 | if (desc == NULL) | |
325 | return -EINVAL; | |
326 | else if (desc != desc_first) | |
327 | return desc->total_len; | |
d48de6f1 | 328 | |
bdf6c792 TF |
329 | /* cookie matches to the currently running transfer */ |
330 | ret = desc_first->total_len; | |
6758ddaf | 331 | |
bdf6c792 TF |
332 | if (desc_first->lli.dscr) { |
333 | /* hardware linked list transfer */ | |
334 | ||
335 | /* | |
336 | * Calculate the residue by removing the length of the child | |
337 | * descriptors already transferred from the total length. | |
338 | * To get the current child descriptor we can use the value of | |
339 | * the channel's DSCR register and compare it against the value | |
340 | * of the hardware linked list structure of each child | |
341 | * descriptor. | |
93dce3a6 CP |
342 | * |
343 | * The CTRLA register provides us with the amount of data | |
344 | * already read from the source for the current child | |
345 | * descriptor. So we can compute a more accurate residue by also | |
346 | * removing the number of bytes corresponding to this amount of | |
347 | * data. | |
348 | * | |
349 | * However, the DSCR and CTRLA registers cannot be read both | |
350 | * atomically. Hence a race condition may occur: the first read | |
351 | * register may refer to one child descriptor whereas the second | |
352 | * read may refer to a later child descriptor in the list | |
353 | * because of the DMA transfer progression inbetween the two | |
354 | * reads. | |
355 | * | |
356 | * One solution could have been to pause the DMA transfer, read | |
357 | * the DSCR and CTRLA then resume the DMA transfer. Nonetheless, | |
358 | * this approach presents some drawbacks: | |
359 | * - If the DMA transfer is paused, RX overruns or TX underruns | |
360 | * are more likey to occur depending on the system latency. | |
361 | * Taking the USART driver as an example, it uses a cyclic DMA | |
362 | * transfer to read data from the Receive Holding Register | |
363 | * (RHR) to avoid RX overruns since the RHR is not protected | |
364 | * by any FIFO on most Atmel SoCs. So pausing the DMA transfer | |
365 | * to compute the residue would break the USART driver design. | |
366 | * - The atc_pause() function masks interrupts but we'd rather | |
367 | * avoid to do so for system latency purpose. | |
368 | * | |
369 | * Then we'd rather use another solution: the DSCR is read a | |
370 | * first time, the CTRLA is read in turn, next the DSCR is read | |
371 | * a second time. If the two consecutive read values of the DSCR | |
372 | * are the same then we assume both refers to the very same | |
373 | * child descriptor as well as the CTRLA value read inbetween | |
374 | * does. For cyclic tranfers, the assumption is that a full loop | |
375 | * is "not so fast". | |
376 | * If the two DSCR values are different, we read again the CTRLA | |
377 | * then the DSCR till two consecutive read values from DSCR are | |
378 | * equal or till the maxium trials is reach. | |
379 | * This algorithm is very unlikely not to find a stable value for | |
380 | * DSCR. | |
bdf6c792 TF |
381 | */ |
382 | ||
bdf6c792 | 383 | dscr = channel_readl(atchan, DSCR); |
93dce3a6 CP |
384 | rmb(); /* ensure DSCR is read before CTRLA */ |
385 | ctrla = channel_readl(atchan, CTRLA); | |
386 | for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) { | |
387 | u32 new_dscr; | |
388 | ||
389 | rmb(); /* ensure DSCR is read after CTRLA */ | |
390 | new_dscr = channel_readl(atchan, DSCR); | |
391 | ||
392 | /* | |
393 | * If the DSCR register value has not changed inside the | |
394 | * DMA controller since the previous read, we assume | |
395 | * that both the dscr and ctrla values refers to the | |
396 | * very same descriptor. | |
397 | */ | |
398 | if (likely(new_dscr == dscr)) | |
399 | break; | |
400 | ||
401 | /* | |
402 | * DSCR has changed inside the DMA controller, so the | |
403 | * previouly read value of CTRLA may refer to an already | |
404 | * processed descriptor hence could be outdated. | |
405 | * We need to update ctrla to match the current | |
406 | * descriptor. | |
407 | */ | |
408 | dscr = new_dscr; | |
409 | rmb(); /* ensure DSCR is read before CTRLA */ | |
410 | ctrla = channel_readl(atchan, CTRLA); | |
411 | } | |
412 | if (unlikely(trials >= ATC_MAX_DSCR_TRIALS)) | |
413 | return -ETIMEDOUT; | |
bdf6c792 TF |
414 | |
415 | /* for the first descriptor we can be more accurate */ | |
416 | if (desc_first->lli.dscr == dscr) | |
93dce3a6 | 417 | return atc_calc_bytes_left(ret, ctrla); |
bdf6c792 TF |
418 | |
419 | ret -= desc_first->len; | |
420 | list_for_each_entry(desc, &desc_first->tx_list, desc_node) { | |
421 | if (desc->lli.dscr == dscr) | |
422 | break; | |
423 | ||
424 | ret -= desc->len; | |
c3dbc60c | 425 | } |
6758ddaf | 426 | |
d48de6f1 | 427 | /* |
93dce3a6 | 428 | * For the current descriptor in the chain we can calculate |
bdf6c792 | 429 | * the remaining bytes using the channel's register. |
d48de6f1 | 430 | */ |
93dce3a6 | 431 | ret = atc_calc_bytes_left(ret, ctrla); |
bdf6c792 TF |
432 | } else { |
433 | /* single transfer */ | |
93dce3a6 CP |
434 | ctrla = channel_readl(atchan, CTRLA); |
435 | ret = atc_calc_bytes_left(ret, ctrla); | |
d48de6f1 | 436 | } |
d48de6f1 | 437 | |
d48de6f1 ES |
438 | return ret; |
439 | } | |
440 | ||
dc78baa2 NF |
441 | /** |
442 | * atc_chain_complete - finish work for one transaction chain | |
443 | * @atchan: channel we work on | |
444 | * @desc: descriptor at the head of the chain we want do complete | |
445 | * | |
446 | * Called with atchan->lock held and bh disabled */ | |
447 | static void | |
448 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
449 | { | |
dc78baa2 | 450 | struct dma_async_tx_descriptor *txd = &desc->txd; |
4d112426 | 451 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); |
dc78baa2 NF |
452 | |
453 | dev_vdbg(chan2dev(&atchan->chan_common), | |
454 | "descriptor %u complete\n", txd->cookie); | |
455 | ||
d4116052 VK |
456 | /* mark the descriptor as complete for non cyclic cases only */ |
457 | if (!atc_chan_is_cyclic(atchan)) | |
458 | dma_cookie_complete(txd); | |
dc78baa2 | 459 | |
4d112426 | 460 | /* If the transfer was a memset, free our temporary buffer */ |
ce2a673d | 461 | if (desc->memset_buffer) { |
4d112426 MR |
462 | dma_pool_free(atdma->memset_pool, desc->memset_vaddr, |
463 | desc->memset_paddr); | |
ce2a673d | 464 | desc->memset_buffer = false; |
4d112426 MR |
465 | } |
466 | ||
dc78baa2 | 467 | /* move children to free_list */ |
285a3c71 | 468 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
469 | /* move myself to free_list */ |
470 | list_move(&desc->desc_node, &atchan->free_list); | |
471 | ||
d38a8c62 | 472 | dma_descriptor_unmap(txd); |
53830cc7 NF |
473 | /* for cyclic transfers, |
474 | * no need to replay callback function while stopping */ | |
3c477482 | 475 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
476 | dma_async_tx_callback callback = txd->callback; |
477 | void *param = txd->callback_param; | |
478 | ||
479 | /* | |
480 | * The API requires that no submissions are done from a | |
481 | * callback, so we don't need to drop the lock here | |
482 | */ | |
483 | if (callback) | |
484 | callback(param); | |
485 | } | |
dc78baa2 NF |
486 | |
487 | dma_run_dependencies(txd); | |
488 | } | |
489 | ||
490 | /** | |
491 | * atc_complete_all - finish work for all transactions | |
492 | * @atchan: channel to complete transactions for | |
493 | * | |
494 | * Eventually submit queued descriptors if any | |
495 | * | |
496 | * Assume channel is idle while calling this function | |
497 | * Called with atchan->lock held and bh disabled | |
498 | */ | |
499 | static void atc_complete_all(struct at_dma_chan *atchan) | |
500 | { | |
501 | struct at_desc *desc, *_desc; | |
502 | LIST_HEAD(list); | |
503 | ||
504 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
505 | ||
dc78baa2 NF |
506 | /* |
507 | * Submit queued descriptors ASAP, i.e. before we go through | |
508 | * the completed ones. | |
509 | */ | |
510 | if (!list_empty(&atchan->queue)) | |
511 | atc_dostart(atchan, atc_first_queued(atchan)); | |
512 | /* empty active_list now it is completed */ | |
513 | list_splice_init(&atchan->active_list, &list); | |
514 | /* empty queue list by moving descriptors (if any) to active_list */ | |
515 | list_splice_init(&atchan->queue, &atchan->active_list); | |
516 | ||
517 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
518 | atc_chain_complete(atchan, desc); | |
519 | } | |
520 | ||
dc78baa2 NF |
521 | /** |
522 | * atc_advance_work - at the end of a transaction, move forward | |
523 | * @atchan: channel where the transaction ended | |
524 | * | |
525 | * Called with atchan->lock held and bh disabled | |
526 | */ | |
527 | static void atc_advance_work(struct at_dma_chan *atchan) | |
528 | { | |
529 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
530 | ||
d202f051 LD |
531 | if (atc_chan_is_enabled(atchan)) |
532 | return; | |
533 | ||
dc78baa2 NF |
534 | if (list_empty(&atchan->active_list) || |
535 | list_is_singular(&atchan->active_list)) { | |
536 | atc_complete_all(atchan); | |
537 | } else { | |
538 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
539 | /* advance work */ | |
540 | atc_dostart(atchan, atc_first_active(atchan)); | |
541 | } | |
542 | } | |
543 | ||
544 | ||
545 | /** | |
546 | * atc_handle_error - handle errors reported by DMA controller | |
547 | * @atchan: channel where error occurs | |
548 | * | |
549 | * Called with atchan->lock held and bh disabled | |
550 | */ | |
551 | static void atc_handle_error(struct at_dma_chan *atchan) | |
552 | { | |
553 | struct at_desc *bad_desc; | |
554 | struct at_desc *child; | |
555 | ||
556 | /* | |
557 | * The descriptor currently at the head of the active list is | |
558 | * broked. Since we don't have any way to report errors, we'll | |
559 | * just have to scream loudly and try to carry on. | |
560 | */ | |
561 | bad_desc = atc_first_active(atchan); | |
562 | list_del_init(&bad_desc->desc_node); | |
563 | ||
564 | /* As we are stopped, take advantage to push queued descriptors | |
565 | * in active_list */ | |
566 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
567 | ||
568 | /* Try to restart the controller */ | |
569 | if (!list_empty(&atchan->active_list)) | |
570 | atc_dostart(atchan, atc_first_active(atchan)); | |
571 | ||
572 | /* | |
573 | * KERN_CRITICAL may seem harsh, but since this only happens | |
574 | * when someone submits a bad physical address in a | |
575 | * descriptor, we should consider ourselves lucky that the | |
576 | * controller flagged an error instead of scribbling over | |
577 | * random memory locations. | |
578 | */ | |
579 | dev_crit(chan2dev(&atchan->chan_common), | |
580 | "Bad descriptor submitted for DMA!\n"); | |
581 | dev_crit(chan2dev(&atchan->chan_common), | |
582 | " cookie: %d\n", bad_desc->txd.cookie); | |
583 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 584 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
585 | atc_dump_lli(atchan, &child->lli); |
586 | ||
587 | /* Pretend the descriptor completed successfully */ | |
588 | atc_chain_complete(atchan, bad_desc); | |
589 | } | |
590 | ||
53830cc7 NF |
591 | /** |
592 | * atc_handle_cyclic - at the end of a period, run callback function | |
593 | * @atchan: channel used for cyclic operations | |
594 | * | |
595 | * Called with atchan->lock held and bh disabled | |
596 | */ | |
597 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
598 | { | |
599 | struct at_desc *first = atc_first_active(atchan); | |
600 | struct dma_async_tx_descriptor *txd = &first->txd; | |
601 | dma_async_tx_callback callback = txd->callback; | |
602 | void *param = txd->callback_param; | |
603 | ||
604 | dev_vdbg(chan2dev(&atchan->chan_common), | |
605 | "new cyclic period llp 0x%08x\n", | |
606 | channel_readl(atchan, DSCR)); | |
607 | ||
608 | if (callback) | |
609 | callback(param); | |
610 | } | |
dc78baa2 NF |
611 | |
612 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
613 | ||
614 | static void atc_tasklet(unsigned long data) | |
615 | { | |
616 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 617 | unsigned long flags; |
dc78baa2 | 618 | |
d8cb04b0 | 619 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 620 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 621 | atc_handle_error(atchan); |
3c477482 | 622 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 623 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
624 | else |
625 | atc_advance_work(atchan); | |
626 | ||
d8cb04b0 | 627 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
628 | } |
629 | ||
630 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
631 | { | |
632 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
633 | struct at_dma_chan *atchan; | |
634 | int i; | |
635 | u32 status, pending, imr; | |
636 | int ret = IRQ_NONE; | |
637 | ||
638 | do { | |
639 | imr = dma_readl(atdma, EBCIMR); | |
640 | status = dma_readl(atdma, EBCISR); | |
641 | pending = status & imr; | |
642 | ||
643 | if (!pending) | |
644 | break; | |
645 | ||
646 | dev_vdbg(atdma->dma_common.dev, | |
647 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
648 | status, imr, pending); | |
649 | ||
650 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
651 | atchan = &atdma->chan[i]; | |
9b3aa589 | 652 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
653 | if (pending & AT_DMA_ERR(i)) { |
654 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
655 | dma_writel(atdma, CHDR, |
656 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 657 | /* Give information to tasklet */ |
53830cc7 | 658 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
659 | } |
660 | tasklet_schedule(&atchan->tasklet); | |
661 | ret = IRQ_HANDLED; | |
662 | } | |
663 | } | |
664 | ||
665 | } while (pending); | |
666 | ||
667 | return ret; | |
668 | } | |
669 | ||
670 | ||
671 | /*-- DMA Engine API --------------------------------------------------*/ | |
672 | ||
673 | /** | |
674 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
675 | * @desc: descriptor at the head of the transaction chain | |
676 | * | |
677 | * Queue chain if DMA engine is working already | |
678 | * | |
679 | * Cookie increment and adding to active_list or queue must be atomic | |
680 | */ | |
681 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
682 | { | |
683 | struct at_desc *desc = txd_to_at_desc(tx); | |
684 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
685 | dma_cookie_t cookie; | |
d8cb04b0 | 686 | unsigned long flags; |
dc78baa2 | 687 | |
d8cb04b0 | 688 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 689 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
690 | |
691 | if (list_empty(&atchan->active_list)) { | |
692 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
693 | desc->txd.cookie); | |
694 | atc_dostart(atchan, desc); | |
695 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
696 | } else { | |
697 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
698 | desc->txd.cookie); | |
699 | list_add_tail(&desc->desc_node, &atchan->queue); | |
700 | } | |
701 | ||
d8cb04b0 | 702 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
703 | |
704 | return cookie; | |
705 | } | |
706 | ||
5abecfa5 MR |
707 | /** |
708 | * atc_prep_dma_interleaved - prepare memory to memory interleaved operation | |
709 | * @chan: the channel to prepare operation on | |
710 | * @xt: Interleaved transfer template | |
711 | * @flags: tx descriptor status flags | |
712 | */ | |
713 | static struct dma_async_tx_descriptor * | |
714 | atc_prep_dma_interleaved(struct dma_chan *chan, | |
715 | struct dma_interleaved_template *xt, | |
716 | unsigned long flags) | |
717 | { | |
718 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
719 | struct data_chunk *first = xt->sgl; | |
720 | struct at_desc *desc = NULL; | |
721 | size_t xfer_count; | |
722 | unsigned int dwidth; | |
723 | u32 ctrla; | |
724 | u32 ctrlb; | |
725 | size_t len = 0; | |
726 | int i; | |
727 | ||
4483320e MS |
728 | if (unlikely(!xt || xt->numf != 1 || !xt->frame_size)) |
729 | return NULL; | |
730 | ||
5abecfa5 MR |
731 | dev_info(chan2dev(chan), |
732 | "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n", | |
733 | __func__, xt->src_start, xt->dst_start, xt->numf, | |
734 | xt->frame_size, flags); | |
735 | ||
5abecfa5 MR |
736 | /* |
737 | * The controller can only "skip" X bytes every Y bytes, so we | |
738 | * need to make sure we are given a template that fit that | |
739 | * description, ie a template with chunks that always have the | |
740 | * same size, with the same ICGs. | |
741 | */ | |
742 | for (i = 0; i < xt->frame_size; i++) { | |
743 | struct data_chunk *chunk = xt->sgl + i; | |
744 | ||
745 | if ((chunk->size != xt->sgl->size) || | |
746 | (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) || | |
747 | (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) { | |
748 | dev_err(chan2dev(chan), | |
749 | "%s: the controller can transfer only identical chunks\n", | |
750 | __func__); | |
751 | return NULL; | |
752 | } | |
753 | ||
754 | len += chunk->size; | |
755 | } | |
756 | ||
757 | dwidth = atc_get_xfer_width(xt->src_start, | |
758 | xt->dst_start, len); | |
759 | ||
760 | xfer_count = len >> dwidth; | |
761 | if (xfer_count > ATC_BTSIZE_MAX) { | |
762 | dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); | |
763 | return NULL; | |
764 | } | |
765 | ||
766 | ctrla = ATC_SRC_WIDTH(dwidth) | | |
767 | ATC_DST_WIDTH(dwidth); | |
768 | ||
769 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
770 | | ATC_SRC_ADDR_MODE_INCR | |
771 | | ATC_DST_ADDR_MODE_INCR | |
772 | | ATC_SRC_PIP | |
773 | | ATC_DST_PIP | |
774 | | ATC_FC_MEM2MEM; | |
775 | ||
776 | /* create the transfer */ | |
777 | desc = atc_desc_get(atchan); | |
778 | if (!desc) { | |
779 | dev_err(chan2dev(chan), | |
780 | "%s: couldn't allocate our descriptor\n", __func__); | |
781 | return NULL; | |
782 | } | |
783 | ||
784 | desc->lli.saddr = xt->src_start; | |
785 | desc->lli.daddr = xt->dst_start; | |
786 | desc->lli.ctrla = ctrla | xfer_count; | |
787 | desc->lli.ctrlb = ctrlb; | |
788 | ||
789 | desc->boundary = first->size >> dwidth; | |
790 | desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1; | |
791 | desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1; | |
792 | ||
793 | desc->txd.cookie = -EBUSY; | |
794 | desc->total_len = desc->len = len; | |
5abecfa5 MR |
795 | |
796 | /* set end-of-link to the last link descriptor of list*/ | |
797 | set_desc_eol(desc); | |
798 | ||
799 | desc->txd.flags = flags; /* client is in control of this ack */ | |
800 | ||
801 | return &desc->txd; | |
802 | } | |
803 | ||
dc78baa2 NF |
804 | /** |
805 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
806 | * @chan: the channel to prepare operation on | |
807 | * @dest: operation virtual destination address | |
808 | * @src: operation virtual source address | |
809 | * @len: operation length | |
810 | * @flags: tx descriptor status flags | |
811 | */ | |
812 | static struct dma_async_tx_descriptor * | |
813 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
814 | size_t len, unsigned long flags) | |
815 | { | |
816 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
817 | struct at_desc *desc = NULL; | |
818 | struct at_desc *first = NULL; | |
819 | struct at_desc *prev = NULL; | |
820 | size_t xfer_count; | |
821 | size_t offset; | |
822 | unsigned int src_width; | |
823 | unsigned int dst_width; | |
824 | u32 ctrla; | |
825 | u32 ctrlb; | |
826 | ||
827 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
828 | dest, src, len, flags); | |
829 | ||
830 | if (unlikely(!len)) { | |
831 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
832 | return NULL; | |
833 | } | |
834 | ||
9b3aa589 | 835 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
836 | | ATC_SRC_ADDR_MODE_INCR |
837 | | ATC_DST_ADDR_MODE_INCR | |
838 | | ATC_FC_MEM2MEM; | |
839 | ||
840 | /* | |
841 | * We can be a lot more clever here, but this should take care | |
842 | * of the most common optimization. | |
843 | */ | |
265567fb TF |
844 | src_width = dst_width = atc_get_xfer_width(src, dest, len); |
845 | ||
846 | ctrla = ATC_SRC_WIDTH(src_width) | | |
847 | ATC_DST_WIDTH(dst_width); | |
dc78baa2 NF |
848 | |
849 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
850 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
851 | ATC_BTSIZE_MAX); | |
852 | ||
853 | desc = atc_desc_get(atchan); | |
854 | if (!desc) | |
855 | goto err_desc_get; | |
856 | ||
857 | desc->lli.saddr = src + offset; | |
858 | desc->lli.daddr = dest + offset; | |
859 | desc->lli.ctrla = ctrla | xfer_count; | |
860 | desc->lli.ctrlb = ctrlb; | |
861 | ||
862 | desc->txd.cookie = 0; | |
bdf6c792 | 863 | desc->len = xfer_count << src_width; |
dc78baa2 | 864 | |
e257e156 | 865 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
866 | } |
867 | ||
868 | /* First descriptor of the chain embedds additional information */ | |
869 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
870 | first->total_len = len; |
871 | ||
dc78baa2 NF |
872 | /* set end-of-link to the last link descriptor of list*/ |
873 | set_desc_eol(desc); | |
874 | ||
568f7f0c | 875 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
876 | |
877 | return &first->txd; | |
878 | ||
879 | err_desc_get: | |
880 | atc_desc_put(atchan, first); | |
881 | return NULL; | |
882 | } | |
883 | ||
ce2a673d MR |
884 | static struct at_desc *atc_create_memset_desc(struct dma_chan *chan, |
885 | dma_addr_t psrc, | |
886 | dma_addr_t pdst, | |
887 | size_t len) | |
888 | { | |
889 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
890 | struct at_desc *desc; | |
891 | size_t xfer_count; | |
892 | ||
893 | u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2); | |
894 | u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | | |
895 | ATC_SRC_ADDR_MODE_FIXED | | |
896 | ATC_DST_ADDR_MODE_INCR | | |
897 | ATC_FC_MEM2MEM; | |
898 | ||
899 | xfer_count = len >> 2; | |
900 | if (xfer_count > ATC_BTSIZE_MAX) { | |
901 | dev_err(chan2dev(chan), "%s: buffer is too big\n", | |
902 | __func__); | |
903 | return NULL; | |
904 | } | |
905 | ||
906 | desc = atc_desc_get(atchan); | |
907 | if (!desc) { | |
908 | dev_err(chan2dev(chan), "%s: can't get a descriptor\n", | |
909 | __func__); | |
910 | return NULL; | |
911 | } | |
912 | ||
913 | desc->lli.saddr = psrc; | |
914 | desc->lli.daddr = pdst; | |
915 | desc->lli.ctrla = ctrla | xfer_count; | |
916 | desc->lli.ctrlb = ctrlb; | |
917 | ||
918 | desc->txd.cookie = 0; | |
919 | desc->len = len; | |
920 | ||
921 | return desc; | |
922 | } | |
923 | ||
4d112426 MR |
924 | /** |
925 | * atc_prep_dma_memset - prepare a memcpy operation | |
926 | * @chan: the channel to prepare operation on | |
927 | * @dest: operation virtual destination address | |
928 | * @value: value to set memory buffer to | |
929 | * @len: operation length | |
930 | * @flags: tx descriptor status flags | |
931 | */ | |
932 | static struct dma_async_tx_descriptor * | |
933 | atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, | |
934 | size_t len, unsigned long flags) | |
935 | { | |
4d112426 | 936 | struct at_dma *atdma = to_at_dma(chan->device); |
ce2a673d MR |
937 | struct at_desc *desc; |
938 | void __iomem *vaddr; | |
939 | dma_addr_t paddr; | |
4d112426 MR |
940 | |
941 | dev_vdbg(chan2dev(chan), "%s: d0x%x v0x%x l0x%zx f0x%lx\n", __func__, | |
942 | dest, value, len, flags); | |
943 | ||
944 | if (unlikely(!len)) { | |
945 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); | |
946 | return NULL; | |
947 | } | |
948 | ||
949 | if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { | |
950 | dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n", | |
951 | __func__); | |
952 | return NULL; | |
953 | } | |
954 | ||
ce2a673d MR |
955 | vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr); |
956 | if (!vaddr) { | |
957 | dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", | |
4d112426 MR |
958 | __func__); |
959 | return NULL; | |
960 | } | |
ce2a673d | 961 | *(u32*)vaddr = value; |
4d112426 | 962 | |
ce2a673d | 963 | desc = atc_create_memset_desc(chan, paddr, dest, len); |
4d112426 | 964 | if (!desc) { |
ce2a673d | 965 | dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n", |
4d112426 | 966 | __func__); |
ce2a673d | 967 | goto err_free_buffer; |
4d112426 MR |
968 | } |
969 | ||
ce2a673d MR |
970 | desc->memset_paddr = paddr; |
971 | desc->memset_vaddr = vaddr; | |
972 | desc->memset_buffer = true; | |
4d112426 MR |
973 | |
974 | desc->txd.cookie = -EBUSY; | |
4d112426 MR |
975 | desc->total_len = len; |
976 | ||
977 | /* set end-of-link on the descriptor */ | |
978 | set_desc_eol(desc); | |
979 | ||
980 | desc->txd.flags = flags; | |
981 | ||
982 | return &desc->txd; | |
983 | ||
ce2a673d MR |
984 | err_free_buffer: |
985 | dma_pool_free(atdma->memset_pool, vaddr, paddr); | |
4d112426 MR |
986 | return NULL; |
987 | } | |
988 | ||
808347f6 NF |
989 | /** |
990 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
991 | * @chan: DMA channel | |
992 | * @sgl: scatterlist to transfer to/from | |
993 | * @sg_len: number of entries in @scatterlist | |
994 | * @direction: DMA direction | |
995 | * @flags: tx descriptor status flags | |
185ecb5f | 996 | * @context: transaction context (ignored) |
808347f6 NF |
997 | */ |
998 | static struct dma_async_tx_descriptor * | |
999 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1000 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1001 | unsigned long flags, void *context) |
808347f6 NF |
1002 | { |
1003 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1004 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1005 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
808347f6 NF |
1006 | struct at_desc *first = NULL; |
1007 | struct at_desc *prev = NULL; | |
1008 | u32 ctrla; | |
1009 | u32 ctrlb; | |
1010 | dma_addr_t reg; | |
1011 | unsigned int reg_width; | |
1012 | unsigned int mem_width; | |
1013 | unsigned int i; | |
1014 | struct scatterlist *sg; | |
1015 | size_t total_len = 0; | |
1016 | ||
cc52a10a NF |
1017 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
1018 | sg_len, | |
db8196df | 1019 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
1020 | flags); |
1021 | ||
1022 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 1023 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
1024 | return NULL; |
1025 | } | |
1026 | ||
1dd1ea8e NF |
1027 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
1028 | | ATC_DCSIZE(sconfig->dst_maxburst); | |
ae14d4b5 | 1029 | ctrlb = ATC_IEN; |
808347f6 NF |
1030 | |
1031 | switch (direction) { | |
db8196df | 1032 | case DMA_MEM_TO_DEV: |
beeaa103 | 1033 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
808347f6 NF |
1034 | ctrla |= ATC_DST_WIDTH(reg_width); |
1035 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
1036 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 | 1037 | | ATC_FC_MEM2PER |
bbe89c8e | 1038 | | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if); |
beeaa103 | 1039 | reg = sconfig->dst_addr; |
808347f6 NF |
1040 | for_each_sg(sgl, sg, sg_len, i) { |
1041 | struct at_desc *desc; | |
1042 | u32 len; | |
1043 | u32 mem; | |
1044 | ||
1045 | desc = atc_desc_get(atchan); | |
1046 | if (!desc) | |
1047 | goto err_desc_get; | |
1048 | ||
0f70e8ce | 1049 | mem = sg_dma_address(sg); |
808347f6 | 1050 | len = sg_dma_len(sg); |
c4567976 NF |
1051 | if (unlikely(!len)) { |
1052 | dev_dbg(chan2dev(chan), | |
1053 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1054 | goto err; | |
1055 | } | |
808347f6 NF |
1056 | mem_width = 2; |
1057 | if (unlikely(mem & 3 || len & 3)) | |
1058 | mem_width = 0; | |
1059 | ||
1060 | desc->lli.saddr = mem; | |
1061 | desc->lli.daddr = reg; | |
1062 | desc->lli.ctrla = ctrla | |
1063 | | ATC_SRC_WIDTH(mem_width) | |
1064 | | len >> mem_width; | |
1065 | desc->lli.ctrlb = ctrlb; | |
bdf6c792 | 1066 | desc->len = len; |
808347f6 | 1067 | |
e257e156 | 1068 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
1069 | total_len += len; |
1070 | } | |
1071 | break; | |
db8196df | 1072 | case DMA_DEV_TO_MEM: |
beeaa103 | 1073 | reg_width = convert_buswidth(sconfig->src_addr_width); |
808347f6 NF |
1074 | ctrla |= ATC_SRC_WIDTH(reg_width); |
1075 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
1076 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 | 1077 | | ATC_FC_PER2MEM |
bbe89c8e | 1078 | | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if); |
808347f6 | 1079 | |
beeaa103 | 1080 | reg = sconfig->src_addr; |
808347f6 NF |
1081 | for_each_sg(sgl, sg, sg_len, i) { |
1082 | struct at_desc *desc; | |
1083 | u32 len; | |
1084 | u32 mem; | |
1085 | ||
1086 | desc = atc_desc_get(atchan); | |
1087 | if (!desc) | |
1088 | goto err_desc_get; | |
1089 | ||
0f70e8ce | 1090 | mem = sg_dma_address(sg); |
808347f6 | 1091 | len = sg_dma_len(sg); |
c4567976 NF |
1092 | if (unlikely(!len)) { |
1093 | dev_dbg(chan2dev(chan), | |
1094 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
1095 | goto err; | |
1096 | } | |
808347f6 NF |
1097 | mem_width = 2; |
1098 | if (unlikely(mem & 3 || len & 3)) | |
1099 | mem_width = 0; | |
1100 | ||
1101 | desc->lli.saddr = reg; | |
1102 | desc->lli.daddr = mem; | |
1103 | desc->lli.ctrla = ctrla | |
1104 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 1105 | | len >> reg_width; |
808347f6 | 1106 | desc->lli.ctrlb = ctrlb; |
bdf6c792 | 1107 | desc->len = len; |
808347f6 | 1108 | |
e257e156 | 1109 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
1110 | total_len += len; |
1111 | } | |
1112 | break; | |
1113 | default: | |
1114 | return NULL; | |
1115 | } | |
1116 | ||
1117 | /* set end-of-link to the last link descriptor of list*/ | |
1118 | set_desc_eol(prev); | |
1119 | ||
1120 | /* First descriptor of the chain embedds additional information */ | |
1121 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
1122 | first->total_len = total_len; |
1123 | ||
568f7f0c NF |
1124 | /* first link descriptor of list is responsible of flags */ |
1125 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
1126 | |
1127 | return &first->txd; | |
1128 | ||
1129 | err_desc_get: | |
1130 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 1131 | err: |
808347f6 NF |
1132 | atc_desc_put(atchan, first); |
1133 | return NULL; | |
1134 | } | |
1135 | ||
265567fb TF |
1136 | /** |
1137 | * atc_prep_dma_sg - prepare memory to memory scather-gather operation | |
1138 | * @chan: the channel to prepare operation on | |
1139 | * @dst_sg: destination scatterlist | |
1140 | * @dst_nents: number of destination scatterlist entries | |
1141 | * @src_sg: source scatterlist | |
1142 | * @src_nents: number of source scatterlist entries | |
1143 | * @flags: tx descriptor status flags | |
1144 | */ | |
1145 | static struct dma_async_tx_descriptor * | |
1146 | atc_prep_dma_sg(struct dma_chan *chan, | |
1147 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
1148 | struct scatterlist *src_sg, unsigned int src_nents, | |
1149 | unsigned long flags) | |
1150 | { | |
1151 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1152 | struct at_desc *desc = NULL; | |
1153 | struct at_desc *first = NULL; | |
1154 | struct at_desc *prev = NULL; | |
1155 | unsigned int src_width; | |
1156 | unsigned int dst_width; | |
1157 | size_t xfer_count; | |
1158 | u32 ctrla; | |
1159 | u32 ctrlb; | |
1160 | size_t dst_len = 0, src_len = 0; | |
1161 | dma_addr_t dst = 0, src = 0; | |
1162 | size_t len = 0, total_len = 0; | |
1163 | ||
1164 | if (unlikely(dst_nents == 0 || src_nents == 0)) | |
1165 | return NULL; | |
1166 | ||
1167 | if (unlikely(dst_sg == NULL || src_sg == NULL)) | |
1168 | return NULL; | |
1169 | ||
1170 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
1171 | | ATC_SRC_ADDR_MODE_INCR | |
1172 | | ATC_DST_ADDR_MODE_INCR | |
1173 | | ATC_FC_MEM2MEM; | |
1174 | ||
1175 | /* | |
1176 | * loop until there is either no more source or no more destination | |
1177 | * scatterlist entry | |
1178 | */ | |
1179 | while (true) { | |
1180 | ||
1181 | /* prepare the next transfer */ | |
1182 | if (dst_len == 0) { | |
1183 | ||
1184 | /* no more destination scatterlist entries */ | |
1185 | if (!dst_sg || !dst_nents) | |
1186 | break; | |
1187 | ||
1188 | dst = sg_dma_address(dst_sg); | |
1189 | dst_len = sg_dma_len(dst_sg); | |
1190 | ||
1191 | dst_sg = sg_next(dst_sg); | |
1192 | dst_nents--; | |
1193 | } | |
1194 | ||
1195 | if (src_len == 0) { | |
1196 | ||
1197 | /* no more source scatterlist entries */ | |
1198 | if (!src_sg || !src_nents) | |
1199 | break; | |
1200 | ||
1201 | src = sg_dma_address(src_sg); | |
1202 | src_len = sg_dma_len(src_sg); | |
1203 | ||
1204 | src_sg = sg_next(src_sg); | |
1205 | src_nents--; | |
1206 | } | |
1207 | ||
1208 | len = min_t(size_t, src_len, dst_len); | |
1209 | if (len == 0) | |
1210 | continue; | |
1211 | ||
1212 | /* take care for the alignment */ | |
1213 | src_width = dst_width = atc_get_xfer_width(src, dst, len); | |
1214 | ||
1215 | ctrla = ATC_SRC_WIDTH(src_width) | | |
1216 | ATC_DST_WIDTH(dst_width); | |
1217 | ||
1218 | /* | |
1219 | * The number of transfers to set up refer to the source width | |
1220 | * that depends on the alignment. | |
1221 | */ | |
1222 | xfer_count = len >> src_width; | |
1223 | if (xfer_count > ATC_BTSIZE_MAX) { | |
1224 | xfer_count = ATC_BTSIZE_MAX; | |
1225 | len = ATC_BTSIZE_MAX << src_width; | |
1226 | } | |
1227 | ||
1228 | /* create the transfer */ | |
1229 | desc = atc_desc_get(atchan); | |
1230 | if (!desc) | |
1231 | goto err_desc_get; | |
1232 | ||
1233 | desc->lli.saddr = src; | |
1234 | desc->lli.daddr = dst; | |
1235 | desc->lli.ctrla = ctrla | xfer_count; | |
1236 | desc->lli.ctrlb = ctrlb; | |
1237 | ||
1238 | desc->txd.cookie = 0; | |
1239 | desc->len = len; | |
1240 | ||
265567fb TF |
1241 | atc_desc_chain(&first, &prev, desc); |
1242 | ||
1243 | /* update the lengths and addresses for the next loop cycle */ | |
1244 | dst_len -= len; | |
1245 | src_len -= len; | |
1246 | dst += len; | |
1247 | src += len; | |
1248 | ||
1249 | total_len += len; | |
1250 | } | |
1251 | ||
1252 | /* First descriptor of the chain embedds additional information */ | |
1253 | first->txd.cookie = -EBUSY; | |
1254 | first->total_len = total_len; | |
1255 | ||
1256 | /* set end-of-link to the last link descriptor of list*/ | |
1257 | set_desc_eol(desc); | |
1258 | ||
1259 | first->txd.flags = flags; /* client is in control of this ack */ | |
1260 | ||
1261 | return &first->txd; | |
1262 | ||
1263 | err_desc_get: | |
1264 | atc_desc_put(atchan, first); | |
1265 | return NULL; | |
1266 | } | |
1267 | ||
53830cc7 NF |
1268 | /** |
1269 | * atc_dma_cyclic_check_values | |
1270 | * Check for too big/unaligned periods and unaligned DMA buffer | |
1271 | */ | |
1272 | static int | |
1273 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 1274 | size_t period_len) |
53830cc7 NF |
1275 | { |
1276 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
1277 | goto err_out; | |
1278 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1279 | goto err_out; | |
1280 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1281 | goto err_out; | |
53830cc7 NF |
1282 | |
1283 | return 0; | |
1284 | ||
1285 | err_out: | |
1286 | return -EINVAL; | |
1287 | } | |
1288 | ||
1289 | /** | |
d73111c6 | 1290 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
1291 | */ |
1292 | static int | |
beeaa103 | 1293 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
53830cc7 | 1294 | unsigned int period_index, dma_addr_t buf_addr, |
beeaa103 NF |
1295 | unsigned int reg_width, size_t period_len, |
1296 | enum dma_transfer_direction direction) | |
53830cc7 | 1297 | { |
beeaa103 | 1298 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 NF |
1299 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
1300 | u32 ctrla; | |
53830cc7 NF |
1301 | |
1302 | /* prepare common CRTLA value */ | |
1dd1ea8e NF |
1303 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
1304 | | ATC_DCSIZE(sconfig->dst_maxburst) | |
53830cc7 NF |
1305 | | ATC_DST_WIDTH(reg_width) |
1306 | | ATC_SRC_WIDTH(reg_width) | |
1307 | | period_len >> reg_width; | |
1308 | ||
1309 | switch (direction) { | |
db8196df | 1310 | case DMA_MEM_TO_DEV: |
53830cc7 | 1311 | desc->lli.saddr = buf_addr + (period_len * period_index); |
beeaa103 | 1312 | desc->lli.daddr = sconfig->dst_addr; |
53830cc7 | 1313 | desc->lli.ctrla = ctrla; |
ae14d4b5 | 1314 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 1315 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 | 1316 | | ATC_FC_MEM2PER |
bbe89c8e LD |
1317 | | ATC_SIF(atchan->mem_if) |
1318 | | ATC_DIF(atchan->per_if); | |
bdf6c792 | 1319 | desc->len = period_len; |
53830cc7 NF |
1320 | break; |
1321 | ||
db8196df | 1322 | case DMA_DEV_TO_MEM: |
beeaa103 | 1323 | desc->lli.saddr = sconfig->src_addr; |
53830cc7 NF |
1324 | desc->lli.daddr = buf_addr + (period_len * period_index); |
1325 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 1326 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 1327 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 | 1328 | | ATC_FC_PER2MEM |
bbe89c8e LD |
1329 | | ATC_SIF(atchan->per_if) |
1330 | | ATC_DIF(atchan->mem_if); | |
bdf6c792 | 1331 | desc->len = period_len; |
53830cc7 NF |
1332 | break; |
1333 | ||
1334 | default: | |
1335 | return -EINVAL; | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | /** | |
1342 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
1343 | * @chan: the DMA channel to prepare | |
1344 | * @buf_addr: physical DMA address where the buffer starts | |
1345 | * @buf_len: total number of bytes for the entire buffer | |
1346 | * @period_len: number of bytes for each period | |
1347 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 1348 | * @flags: tx descriptor status flags |
53830cc7 NF |
1349 | */ |
1350 | static struct dma_async_tx_descriptor * | |
1351 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 1352 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1353 | unsigned long flags) |
53830cc7 NF |
1354 | { |
1355 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1356 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1357 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
53830cc7 NF |
1358 | struct at_desc *first = NULL; |
1359 | struct at_desc *prev = NULL; | |
1360 | unsigned long was_cyclic; | |
beeaa103 | 1361 | unsigned int reg_width; |
53830cc7 NF |
1362 | unsigned int periods = buf_len / period_len; |
1363 | unsigned int i; | |
1364 | ||
1365 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 1366 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
1367 | buf_addr, |
1368 | periods, buf_len, period_len); | |
1369 | ||
1370 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
1371 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
1372 | return NULL; | |
1373 | } | |
1374 | ||
1375 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
1376 | if (was_cyclic) { | |
1377 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
1378 | return NULL; | |
1379 | } | |
1380 | ||
0e7264cc AS |
1381 | if (unlikely(!is_slave_direction(direction))) |
1382 | goto err_out; | |
1383 | ||
beeaa103 NF |
1384 | if (sconfig->direction == DMA_MEM_TO_DEV) |
1385 | reg_width = convert_buswidth(sconfig->dst_addr_width); | |
1386 | else | |
1387 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
1388 | ||
53830cc7 | 1389 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 1390 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
1391 | goto err_out; |
1392 | ||
1393 | /* build cyclic linked list */ | |
1394 | for (i = 0; i < periods; i++) { | |
1395 | struct at_desc *desc; | |
1396 | ||
1397 | desc = atc_desc_get(atchan); | |
1398 | if (!desc) | |
1399 | goto err_desc_get; | |
1400 | ||
beeaa103 NF |
1401 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
1402 | reg_width, period_len, direction)) | |
53830cc7 NF |
1403 | goto err_desc_get; |
1404 | ||
1405 | atc_desc_chain(&first, &prev, desc); | |
1406 | } | |
1407 | ||
1408 | /* lets make a cyclic list */ | |
1409 | prev->lli.dscr = first->txd.phys; | |
1410 | ||
1411 | /* First descriptor of the chain embedds additional information */ | |
1412 | first->txd.cookie = -EBUSY; | |
bdf6c792 | 1413 | first->total_len = buf_len; |
53830cc7 NF |
1414 | |
1415 | return &first->txd; | |
1416 | ||
1417 | err_desc_get: | |
1418 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
1419 | atc_desc_put(atchan, first); | |
1420 | err_out: | |
1421 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1422 | return NULL; | |
1423 | } | |
1424 | ||
4facfe7f MR |
1425 | static int atc_config(struct dma_chan *chan, |
1426 | struct dma_slave_config *sconfig) | |
beeaa103 NF |
1427 | { |
1428 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1429 | ||
4facfe7f MR |
1430 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1431 | ||
beeaa103 NF |
1432 | /* Check if it is chan is configured for slave transfers */ |
1433 | if (!chan->private) | |
1434 | return -EINVAL; | |
1435 | ||
1436 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1437 | ||
1438 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1439 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
4facfe7f MR |
1444 | static int atc_pause(struct dma_chan *chan) |
1445 | { | |
1446 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1447 | struct at_dma *atdma = to_at_dma(chan->device); | |
1448 | int chan_id = atchan->chan_common.chan_id; | |
1449 | unsigned long flags; | |
53830cc7 | 1450 | |
4facfe7f MR |
1451 | LIST_HEAD(list); |
1452 | ||
1453 | dev_vdbg(chan2dev(chan), "%s\n", __func__); | |
1454 | ||
1455 | spin_lock_irqsave(&atchan->lock, flags); | |
1456 | ||
1457 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); | |
1458 | set_bit(ATC_IS_PAUSED, &atchan->status); | |
1459 | ||
1460 | spin_unlock_irqrestore(&atchan->lock, flags); | |
1461 | ||
1462 | return 0; | |
1463 | } | |
1464 | ||
1465 | static int atc_resume(struct dma_chan *chan) | |
808347f6 NF |
1466 | { |
1467 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1468 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 1469 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 1470 | unsigned long flags; |
23b5e3ad | 1471 | |
808347f6 NF |
1472 | LIST_HEAD(list); |
1473 | ||
4facfe7f | 1474 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
c3635c78 | 1475 | |
4facfe7f MR |
1476 | if (!atc_chan_is_paused(atchan)) |
1477 | return 0; | |
808347f6 | 1478 | |
4facfe7f | 1479 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1480 | |
4facfe7f MR |
1481 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1482 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
808347f6 | 1483 | |
4facfe7f | 1484 | spin_unlock_irqrestore(&atchan->lock, flags); |
808347f6 | 1485 | |
4facfe7f MR |
1486 | return 0; |
1487 | } | |
c3635c78 | 1488 | |
4facfe7f MR |
1489 | static int atc_terminate_all(struct dma_chan *chan) |
1490 | { | |
1491 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1492 | struct at_dma *atdma = to_at_dma(chan->device); | |
1493 | int chan_id = atchan->chan_common.chan_id; | |
1494 | struct at_desc *desc, *_desc; | |
1495 | unsigned long flags; | |
23b5e3ad | 1496 | |
4facfe7f | 1497 | LIST_HEAD(list); |
23b5e3ad | 1498 | |
4facfe7f | 1499 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
23b5e3ad | 1500 | |
4facfe7f MR |
1501 | /* |
1502 | * This is only called when something went wrong elsewhere, so | |
1503 | * we don't really care about the data. Just disable the | |
1504 | * channel. We still have to poll the channel enable bit due | |
1505 | * to AHB/HSB limitations. | |
1506 | */ | |
1507 | spin_lock_irqsave(&atchan->lock, flags); | |
23b5e3ad | 1508 | |
4facfe7f MR |
1509 | /* disabling channel: must also remove suspend state */ |
1510 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
23b5e3ad | 1511 | |
4facfe7f MR |
1512 | /* confirm that this channel is disabled */ |
1513 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1514 | cpu_relax(); | |
23b5e3ad | 1515 | |
4facfe7f MR |
1516 | /* active_list entries will end up before queued entries */ |
1517 | list_splice_init(&atchan->queue, &list); | |
1518 | list_splice_init(&atchan->active_list, &list); | |
1519 | ||
1520 | /* Flush all pending and queued descriptors */ | |
1521 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1522 | atc_chain_complete(atchan, desc); | |
1523 | ||
1524 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1525 | /* if channel dedicated to cyclic operations, free it */ | |
1526 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1527 | ||
1528 | spin_unlock_irqrestore(&atchan->lock, flags); | |
b0ebeb9c | 1529 | |
c3635c78 | 1530 | return 0; |
808347f6 NF |
1531 | } |
1532 | ||
dc78baa2 | 1533 | /** |
07934481 | 1534 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1535 | * @chan: DMA channel |
1536 | * @cookie: transaction identifier to check status of | |
07934481 | 1537 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1538 | * |
07934481 | 1539 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1540 | * internal state and can be used with dma_async_is_complete() to check |
1541 | * the status of multiple cookies without re-checking hardware state. | |
1542 | */ | |
1543 | static enum dma_status | |
07934481 | 1544 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1545 | dma_cookie_t cookie, |
07934481 | 1546 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1547 | { |
1548 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1549 | unsigned long flags; |
dc78baa2 | 1550 | enum dma_status ret; |
d48de6f1 | 1551 | int bytes = 0; |
dc78baa2 | 1552 | |
96a2af41 | 1553 | ret = dma_cookie_status(chan, cookie, txstate); |
6d203d1e | 1554 | if (ret == DMA_COMPLETE) |
d48de6f1 ES |
1555 | return ret; |
1556 | /* | |
1557 | * There's no point calculating the residue if there's | |
1558 | * no txstate to store the value. | |
1559 | */ | |
1560 | if (!txstate) | |
1561 | return DMA_ERROR; | |
dc78baa2 | 1562 | |
d48de6f1 | 1563 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1564 | |
d48de6f1 | 1565 | /* Get number of bytes left in the active transactions */ |
bdf6c792 | 1566 | bytes = atc_get_bytes_left(chan, cookie); |
96a2af41 | 1567 | |
d8cb04b0 | 1568 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1569 | |
d48de6f1 ES |
1570 | if (unlikely(bytes < 0)) { |
1571 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); | |
1572 | return DMA_ERROR; | |
c3dbc60c | 1573 | } else { |
d48de6f1 | 1574 | dma_set_residue(txstate, bytes); |
c3dbc60c | 1575 | } |
23b5e3ad | 1576 | |
d48de6f1 ES |
1577 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n", |
1578 | ret, cookie, bytes); | |
dc78baa2 NF |
1579 | |
1580 | return ret; | |
1581 | } | |
1582 | ||
1583 | /** | |
1584 | * atc_issue_pending - try to finish work | |
1585 | * @chan: target DMA channel | |
1586 | */ | |
1587 | static void atc_issue_pending(struct dma_chan *chan) | |
1588 | { | |
1589 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1590 | unsigned long flags; |
dc78baa2 NF |
1591 | |
1592 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1593 | ||
53830cc7 | 1594 | /* Not needed for cyclic transfers */ |
3c477482 | 1595 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1596 | return; |
1597 | ||
d8cb04b0 | 1598 | spin_lock_irqsave(&atchan->lock, flags); |
d202f051 | 1599 | atc_advance_work(atchan); |
d8cb04b0 | 1600 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1601 | } |
1602 | ||
1603 | /** | |
1604 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1605 | * @chan: allocate descriptor resources for this channel | |
1606 | * @client: current client requesting the channel be ready for requests | |
1607 | * | |
1608 | * return - the number of allocated descriptors | |
1609 | */ | |
1610 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1611 | { | |
1612 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1613 | struct at_dma *atdma = to_at_dma(chan->device); | |
1614 | struct at_desc *desc; | |
808347f6 | 1615 | struct at_dma_slave *atslave; |
d8cb04b0 | 1616 | unsigned long flags; |
dc78baa2 | 1617 | int i; |
808347f6 | 1618 | u32 cfg; |
dc78baa2 NF |
1619 | LIST_HEAD(tmp_list); |
1620 | ||
1621 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1622 | ||
1623 | /* ASSERT: channel is idle */ | |
1624 | if (atc_chan_is_enabled(atchan)) { | |
1625 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1626 | return -EIO; | |
1627 | } | |
1628 | ||
808347f6 NF |
1629 | cfg = ATC_DEFAULT_CFG; |
1630 | ||
1631 | atslave = chan->private; | |
1632 | if (atslave) { | |
1633 | /* | |
1634 | * We need controller-specific data to set up slave | |
1635 | * transfers. | |
1636 | */ | |
1637 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1638 | ||
ea7e7906 | 1639 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1640 | if (atslave->cfg) |
1641 | cfg = atslave->cfg; | |
1642 | } | |
1643 | ||
1644 | /* have we already been set up? | |
1645 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1646 | if (!list_empty(&atchan->free_list)) |
1647 | return atchan->descs_allocated; | |
1648 | ||
1649 | /* Allocate initial pool of descriptors */ | |
1650 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1651 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1652 | if (!desc) { | |
1653 | dev_err(atdma->dma_common.dev, | |
1654 | "Only %d initial descriptors\n", i); | |
1655 | break; | |
1656 | } | |
1657 | list_add_tail(&desc->desc_node, &tmp_list); | |
1658 | } | |
1659 | ||
d8cb04b0 | 1660 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
1661 | atchan->descs_allocated = i; |
1662 | list_splice(&tmp_list, &atchan->free_list); | |
d3ee98cd | 1663 | dma_cookie_init(chan); |
d8cb04b0 | 1664 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1665 | |
1666 | /* channel parameters */ | |
808347f6 | 1667 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1668 | |
1669 | dev_dbg(chan2dev(chan), | |
1670 | "alloc_chan_resources: allocated %d descriptors\n", | |
1671 | atchan->descs_allocated); | |
1672 | ||
1673 | return atchan->descs_allocated; | |
1674 | } | |
1675 | ||
1676 | /** | |
1677 | * atc_free_chan_resources - free all channel resources | |
1678 | * @chan: DMA channel | |
1679 | */ | |
1680 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1681 | { | |
1682 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1683 | struct at_dma *atdma = to_at_dma(chan->device); | |
1684 | struct at_desc *desc, *_desc; | |
1685 | LIST_HEAD(list); | |
1686 | ||
1687 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1688 | atchan->descs_allocated); | |
1689 | ||
1690 | /* ASSERT: channel is idle */ | |
1691 | BUG_ON(!list_empty(&atchan->active_list)); | |
1692 | BUG_ON(!list_empty(&atchan->queue)); | |
1693 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1694 | ||
1695 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1696 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1697 | list_del(&desc->desc_node); | |
1698 | /* free link descriptor */ | |
1699 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1700 | } | |
1701 | list_splice_init(&atchan->free_list, &list); | |
1702 | atchan->descs_allocated = 0; | |
53830cc7 | 1703 | atchan->status = 0; |
dc78baa2 NF |
1704 | |
1705 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1706 | } | |
1707 | ||
bbe89c8e LD |
1708 | #ifdef CONFIG_OF |
1709 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1710 | { | |
1711 | struct at_dma_slave *atslave = slave; | |
1712 | ||
1713 | if (atslave->dma_dev == chan->device->dev) { | |
1714 | chan->private = atslave; | |
1715 | return true; | |
1716 | } else { | |
1717 | return false; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1722 | struct of_dma *of_dma) | |
1723 | { | |
1724 | struct dma_chan *chan; | |
1725 | struct at_dma_chan *atchan; | |
1726 | struct at_dma_slave *atslave; | |
1727 | dma_cap_mask_t mask; | |
1728 | unsigned int per_id; | |
1729 | struct platform_device *dmac_pdev; | |
1730 | ||
1731 | if (dma_spec->args_count != 2) | |
1732 | return NULL; | |
1733 | ||
1734 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
1735 | ||
1736 | dma_cap_zero(mask); | |
1737 | dma_cap_set(DMA_SLAVE, mask); | |
1738 | ||
1739 | atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL); | |
1740 | if (!atslave) | |
1741 | return NULL; | |
62971b29 LD |
1742 | |
1743 | atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW; | |
bbe89c8e LD |
1744 | /* |
1745 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1746 | * ignored depending on DMA transfer direction. | |
1747 | */ | |
62971b29 LD |
1748 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
1749 | atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id) | |
6c22770f | 1750 | | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id); |
62971b29 LD |
1751 | /* |
1752 | * We have to translate the value we get from the device tree since | |
1753 | * the half FIFO configuration value had to be 0 to keep backward | |
1754 | * compatibility. | |
1755 | */ | |
1756 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1757 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
1758 | atslave->cfg |= ATC_FIFOCFG_LARGESTBURST; | |
1759 | break; | |
1760 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
1761 | atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE; | |
1762 | break; | |
1763 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1764 | default: | |
1765 | atslave->cfg |= ATC_FIFOCFG_HALFFIFO; | |
1766 | } | |
bbe89c8e LD |
1767 | atslave->dma_dev = &dmac_pdev->dev; |
1768 | ||
1769 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
1770 | if (!chan) | |
1771 | return NULL; | |
1772 | ||
1773 | atchan = to_at_dma_chan(chan); | |
1774 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1775 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1776 | ||
1777 | return chan; | |
1778 | } | |
1779 | #else | |
1780 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1781 | struct of_dma *of_dma) | |
1782 | { | |
1783 | return NULL; | |
1784 | } | |
1785 | #endif | |
dc78baa2 NF |
1786 | |
1787 | /*-- Module Management -----------------------------------------------*/ | |
1788 | ||
02f88be9 NF |
1789 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1790 | static struct at_dma_platform_data at91sam9rl_config = { | |
1791 | .nr_channels = 2, | |
1792 | }; | |
1793 | static struct at_dma_platform_data at91sam9g45_config = { | |
1794 | .nr_channels = 8, | |
1795 | }; | |
1796 | ||
c5115953 NF |
1797 | #if defined(CONFIG_OF) |
1798 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1799 | { | |
1800 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1801 | .data = &at91sam9rl_config, |
c5115953 NF |
1802 | }, { |
1803 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1804 | .data = &at91sam9g45_config, |
dcc81734 NF |
1805 | }, { |
1806 | /* sentinel */ | |
1807 | } | |
c5115953 NF |
1808 | }; |
1809 | ||
1810 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1811 | #endif | |
1812 | ||
0ab88a01 | 1813 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1814 | { |
1815 | .name = "at91sam9rl_dma", | |
02f88be9 | 1816 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1817 | }, { |
1818 | .name = "at91sam9g45_dma", | |
02f88be9 | 1819 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1820 | }, { |
1821 | /* sentinel */ | |
1822 | } | |
1823 | }; | |
1824 | ||
7fd63ccd | 1825 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1826 | struct platform_device *pdev) |
c5115953 NF |
1827 | { |
1828 | if (pdev->dev.of_node) { | |
1829 | const struct of_device_id *match; | |
1830 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1831 | if (match == NULL) | |
02f88be9 NF |
1832 | return NULL; |
1833 | return match->data; | |
c5115953 | 1834 | } |
02f88be9 NF |
1835 | return (struct at_dma_platform_data *) |
1836 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1837 | } |
1838 | ||
dc78baa2 NF |
1839 | /** |
1840 | * at_dma_off - disable DMA controller | |
1841 | * @atdma: the Atmel HDAMC device | |
1842 | */ | |
1843 | static void at_dma_off(struct at_dma *atdma) | |
1844 | { | |
1845 | dma_writel(atdma, EN, 0); | |
1846 | ||
1847 | /* disable all interrupts */ | |
1848 | dma_writel(atdma, EBCIDR, -1L); | |
1849 | ||
1850 | /* confirm that all channels are disabled */ | |
1851 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1852 | cpu_relax(); | |
1853 | } | |
1854 | ||
1855 | static int __init at_dma_probe(struct platform_device *pdev) | |
1856 | { | |
dc78baa2 NF |
1857 | struct resource *io; |
1858 | struct at_dma *atdma; | |
1859 | size_t size; | |
1860 | int irq; | |
1861 | int err; | |
1862 | int i; | |
7fd63ccd | 1863 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1864 | |
02f88be9 NF |
1865 | /* setup platform data for each SoC */ |
1866 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
265567fb | 1867 | dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask); |
5abecfa5 | 1868 | dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask); |
02f88be9 | 1869 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); |
4d112426 MR |
1870 | dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask); |
1871 | dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask); | |
02f88be9 | 1872 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); |
265567fb | 1873 | dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask); |
67348450 NF |
1874 | |
1875 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1876 | plat_dat = at_dma_get_driver_data(pdev); |
1877 | if (!plat_dat) | |
1878 | return -ENODEV; | |
dc78baa2 NF |
1879 | |
1880 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1881 | if (!io) | |
1882 | return -EINVAL; | |
1883 | ||
1884 | irq = platform_get_irq(pdev, 0); | |
1885 | if (irq < 0) | |
1886 | return irq; | |
1887 | ||
1888 | size = sizeof(struct at_dma); | |
02f88be9 | 1889 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1890 | atdma = kzalloc(size, GFP_KERNEL); |
1891 | if (!atdma) | |
1892 | return -ENOMEM; | |
1893 | ||
67348450 | 1894 | /* discover transaction capabilities */ |
02f88be9 NF |
1895 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1896 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1897 | |
114df7d6 | 1898 | size = resource_size(io); |
dc78baa2 NF |
1899 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1900 | err = -EBUSY; | |
1901 | goto err_kfree; | |
1902 | } | |
1903 | ||
1904 | atdma->regs = ioremap(io->start, size); | |
1905 | if (!atdma->regs) { | |
1906 | err = -ENOMEM; | |
1907 | goto err_release_r; | |
1908 | } | |
1909 | ||
1910 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1911 | if (IS_ERR(atdma->clk)) { | |
1912 | err = PTR_ERR(atdma->clk); | |
1913 | goto err_clk; | |
1914 | } | |
f784d9c9 BB |
1915 | err = clk_prepare_enable(atdma->clk); |
1916 | if (err) | |
1917 | goto err_clk_prepare; | |
dc78baa2 NF |
1918 | |
1919 | /* force dma off, just in case */ | |
1920 | at_dma_off(atdma); | |
1921 | ||
1922 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1923 | if (err) | |
1924 | goto err_irq; | |
1925 | ||
1926 | platform_set_drvdata(pdev, atdma); | |
1927 | ||
1928 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1929 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1930 | &pdev->dev, sizeof(struct at_desc), | |
1931 | 4 /* word alignment */, 0); | |
1932 | if (!atdma->dma_desc_pool) { | |
1933 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1934 | err = -ENOMEM; | |
4d112426 MR |
1935 | goto err_desc_pool_create; |
1936 | } | |
1937 | ||
1938 | /* create a pool of consistent memory blocks for memset blocks */ | |
1939 | atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool", | |
1940 | &pdev->dev, sizeof(int), 4, 0); | |
1941 | if (!atdma->memset_pool) { | |
1942 | dev_err(&pdev->dev, "No memory for memset dma pool\n"); | |
1943 | err = -ENOMEM; | |
1944 | goto err_memset_pool_create; | |
dc78baa2 NF |
1945 | } |
1946 | ||
1947 | /* clear any pending interrupt */ | |
1948 | while (dma_readl(atdma, EBCISR)) | |
1949 | cpu_relax(); | |
1950 | ||
1951 | /* initialize channels related values */ | |
1952 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1953 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1954 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1955 | ||
bbe89c8e LD |
1956 | atchan->mem_if = AT_DMA_MEM_IF; |
1957 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 | 1958 | atchan->chan_common.device = &atdma->dma_common; |
d3ee98cd | 1959 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1960 | list_add_tail(&atchan->chan_common.device_node, |
1961 | &atdma->dma_common.channels); | |
1962 | ||
1963 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1964 | spin_lock_init(&atchan->lock); | |
1965 | atchan->mask = 1 << i; | |
1966 | ||
1967 | INIT_LIST_HEAD(&atchan->active_list); | |
1968 | INIT_LIST_HEAD(&atchan->queue); | |
1969 | INIT_LIST_HEAD(&atchan->free_list); | |
1970 | ||
1971 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1972 | (unsigned long)atchan); | |
bda3a47c | 1973 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1974 | } |
1975 | ||
1976 | /* set base routines */ | |
1977 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1978 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1979 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1980 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1981 | atdma->dma_common.dev = &pdev->dev; | |
1982 | ||
1983 | /* set prep routines based on capability */ | |
5abecfa5 MR |
1984 | if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask)) |
1985 | atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved; | |
1986 | ||
dc78baa2 NF |
1987 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) |
1988 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1989 | ||
4d112426 MR |
1990 | if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) { |
1991 | atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset; | |
1992 | atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES; | |
1993 | } | |
1994 | ||
d7db8080 | 1995 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1996 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1997 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1998 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1999 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
4facfe7f MR |
2000 | atdma->dma_common.device_config = atc_config; |
2001 | atdma->dma_common.device_pause = atc_pause; | |
2002 | atdma->dma_common.device_resume = atc_resume; | |
2003 | atdma->dma_common.device_terminate_all = atc_terminate_all; | |
816070ed LD |
2004 | atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS; |
2005 | atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS; | |
2006 | atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2007 | atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
d7db8080 | 2008 | } |
808347f6 | 2009 | |
265567fb TF |
2010 | if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask)) |
2011 | atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg; | |
2012 | ||
dc78baa2 NF |
2013 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
2014 | ||
4d112426 | 2015 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s%s), %d channels\n", |
dc78baa2 | 2016 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", |
4d112426 | 2017 | dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask) ? "set " : "", |
dc78baa2 | 2018 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", |
265567fb | 2019 | dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "", |
02f88be9 | 2020 | plat_dat->nr_channels); |
dc78baa2 NF |
2021 | |
2022 | dma_async_device_register(&atdma->dma_common); | |
2023 | ||
bbe89c8e LD |
2024 | /* |
2025 | * Do not return an error if the dmac node is not present in order to | |
2026 | * not break the existing way of requesting channel with | |
2027 | * dma_request_channel(). | |
2028 | */ | |
2029 | if (pdev->dev.of_node) { | |
2030 | err = of_dma_controller_register(pdev->dev.of_node, | |
2031 | at_dma_xlate, atdma); | |
2032 | if (err) { | |
2033 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
2034 | goto err_of_dma_controller_register; | |
2035 | } | |
2036 | } | |
2037 | ||
dc78baa2 NF |
2038 | return 0; |
2039 | ||
bbe89c8e LD |
2040 | err_of_dma_controller_register: |
2041 | dma_async_device_unregister(&atdma->dma_common); | |
4d112426 MR |
2042 | dma_pool_destroy(atdma->memset_pool); |
2043 | err_memset_pool_create: | |
bbe89c8e | 2044 | dma_pool_destroy(atdma->dma_desc_pool); |
4d112426 | 2045 | err_desc_pool_create: |
dc78baa2 NF |
2046 | free_irq(platform_get_irq(pdev, 0), atdma); |
2047 | err_irq: | |
f784d9c9 BB |
2048 | clk_disable_unprepare(atdma->clk); |
2049 | err_clk_prepare: | |
dc78baa2 NF |
2050 | clk_put(atdma->clk); |
2051 | err_clk: | |
2052 | iounmap(atdma->regs); | |
2053 | atdma->regs = NULL; | |
2054 | err_release_r: | |
2055 | release_mem_region(io->start, size); | |
2056 | err_kfree: | |
2057 | kfree(atdma); | |
2058 | return err; | |
2059 | } | |
2060 | ||
1d1bbd30 | 2061 | static int at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
2062 | { |
2063 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2064 | struct dma_chan *chan, *_chan; | |
2065 | struct resource *io; | |
2066 | ||
2067 | at_dma_off(atdma); | |
2068 | dma_async_device_unregister(&atdma->dma_common); | |
2069 | ||
4d112426 | 2070 | dma_pool_destroy(atdma->memset_pool); |
dc78baa2 | 2071 | dma_pool_destroy(atdma->dma_desc_pool); |
dc78baa2 NF |
2072 | free_irq(platform_get_irq(pdev, 0), atdma); |
2073 | ||
2074 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2075 | device_node) { | |
2076 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2077 | ||
2078 | /* Disable interrupts */ | |
bda3a47c | 2079 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
2080 | |
2081 | tasklet_kill(&atchan->tasklet); | |
2082 | list_del(&chan->device_node); | |
2083 | } | |
2084 | ||
f784d9c9 | 2085 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2086 | clk_put(atdma->clk); |
2087 | ||
2088 | iounmap(atdma->regs); | |
2089 | atdma->regs = NULL; | |
2090 | ||
2091 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 2092 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
2093 | |
2094 | kfree(atdma); | |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
2099 | static void at_dma_shutdown(struct platform_device *pdev) | |
2100 | { | |
2101 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2102 | ||
2103 | at_dma_off(platform_get_drvdata(pdev)); | |
f784d9c9 | 2104 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2105 | } |
2106 | ||
c0ba5947 NF |
2107 | static int at_dma_prepare(struct device *dev) |
2108 | { | |
2109 | struct platform_device *pdev = to_platform_device(dev); | |
2110 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
2111 | struct dma_chan *chan, *_chan; | |
2112 | ||
2113 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2114 | device_node) { | |
2115 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2116 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 2117 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2118 | return -EAGAIN; |
2119 | } | |
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
2124 | { | |
2125 | struct dma_chan *chan = &atchan->chan_common; | |
2126 | ||
2127 | /* Channel should be paused by user | |
2128 | * do it anyway even if it is not done already */ | |
3c477482 | 2129 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
2130 | dev_warn(chan2dev(chan), |
2131 | "cyclic channel not paused, should be done by channel user\n"); | |
4facfe7f | 2132 | atc_pause(chan); |
c0ba5947 NF |
2133 | } |
2134 | ||
2135 | /* now preserve additional data for cyclic operations */ | |
2136 | /* next descriptor address in the cyclic list */ | |
2137 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
2138 | ||
2139 | vdbg_dump_regs(atchan); | |
2140 | } | |
2141 | ||
33f82d14 | 2142 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 2143 | { |
33f82d14 DW |
2144 | struct platform_device *pdev = to_platform_device(dev); |
2145 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 2146 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2147 | |
c0ba5947 NF |
2148 | /* preserve data */ |
2149 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2150 | device_node) { | |
2151 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2152 | ||
3c477482 | 2153 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2154 | atc_suspend_cyclic(atchan); |
2155 | atchan->save_cfg = channel_readl(atchan, CFG); | |
2156 | } | |
2157 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
2158 | ||
2159 | /* disable DMA controller */ | |
2160 | at_dma_off(atdma); | |
f784d9c9 | 2161 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
2162 | return 0; |
2163 | } | |
2164 | ||
c0ba5947 NF |
2165 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
2166 | { | |
2167 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
2168 | ||
2169 | /* restore channel status for cyclic descriptors list: | |
2170 | * next descriptor in the cyclic list at the time of suspend */ | |
2171 | channel_writel(atchan, SADDR, 0); | |
2172 | channel_writel(atchan, DADDR, 0); | |
2173 | channel_writel(atchan, CTRLA, 0); | |
2174 | channel_writel(atchan, CTRLB, 0); | |
2175 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
2176 | dma_writel(atdma, CHER, atchan->mask); | |
2177 | ||
2178 | /* channel pause status should be removed by channel user | |
2179 | * We cannot take the initiative to do it here */ | |
2180 | ||
2181 | vdbg_dump_regs(atchan); | |
2182 | } | |
2183 | ||
33f82d14 | 2184 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 2185 | { |
33f82d14 DW |
2186 | struct platform_device *pdev = to_platform_device(dev); |
2187 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 2188 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2189 | |
c0ba5947 | 2190 | /* bring back DMA controller */ |
f784d9c9 | 2191 | clk_prepare_enable(atdma->clk); |
dc78baa2 | 2192 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
c0ba5947 NF |
2193 | |
2194 | /* clear any pending interrupt */ | |
2195 | while (dma_readl(atdma, EBCISR)) | |
2196 | cpu_relax(); | |
2197 | ||
2198 | /* restore saved data */ | |
2199 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
2200 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2201 | device_node) { | |
2202 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2203 | ||
2204 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 2205 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2206 | atc_resume_cyclic(atchan); |
2207 | } | |
dc78baa2 | 2208 | return 0; |
dc78baa2 NF |
2209 | } |
2210 | ||
47145210 | 2211 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 2212 | .prepare = at_dma_prepare, |
33f82d14 DW |
2213 | .suspend_noirq = at_dma_suspend_noirq, |
2214 | .resume_noirq = at_dma_resume_noirq, | |
2215 | }; | |
2216 | ||
dc78baa2 | 2217 | static struct platform_driver at_dma_driver = { |
1d1bbd30 | 2218 | .remove = at_dma_remove, |
dc78baa2 | 2219 | .shutdown = at_dma_shutdown, |
67348450 | 2220 | .id_table = atdma_devtypes, |
dc78baa2 NF |
2221 | .driver = { |
2222 | .name = "at_hdmac", | |
33f82d14 | 2223 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 2224 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
2225 | }, |
2226 | }; | |
2227 | ||
2228 | static int __init at_dma_init(void) | |
2229 | { | |
2230 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
2231 | } | |
93d0bec2 | 2232 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
2233 | |
2234 | static void __exit at_dma_exit(void) | |
2235 | { | |
2236 | platform_driver_unregister(&at_dma_driver); | |
2237 | } | |
2238 | module_exit(at_dma_exit); | |
2239 | ||
2240 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
2241 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
2242 | MODULE_LICENSE("GPL"); | |
2243 | MODULE_ALIAS("platform:at_hdmac"); |