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Commit | Line | Data |
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dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
9102d871 NF |
12 | * This supports the Atmel AHB DMA Controller found in several Atmel SoCs. |
13 | * The only Atmel DMA Controller that is not covered by this driver is the one | |
14 | * found on AT91SAM9263. | |
dc78baa2 NF |
15 | */ |
16 | ||
62971b29 | 17 | #include <dt-bindings/dma/at91.h> |
dc78baa2 NF |
18 | #include <linux/clk.h> |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
c5115953 NF |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
bbe89c8e | 28 | #include <linux/of_dma.h> |
dc78baa2 NF |
29 | |
30 | #include "at_hdmac_regs.h" | |
d2ebfb33 | 31 | #include "dmaengine.h" |
dc78baa2 NF |
32 | |
33 | /* | |
34 | * Glossary | |
35 | * -------- | |
36 | * | |
37 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
38 | * at_dma_ / atdma : ATmel DMA controller entity related | |
39 | * atc_ / atchan : ATmel DMA Channel entity related | |
40 | */ | |
41 | ||
42 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
ae14d4b5 NF |
43 | #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ |
44 | |ATC_DIF(AT_DMA_MEM_IF)) | |
816070ed LD |
45 | #define ATC_DMA_BUSWIDTHS\ |
46 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
47 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
48 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
49 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
dc78baa2 NF |
50 | |
51 | /* | |
52 | * Initial number of descriptors to allocate for each channel. This could | |
53 | * be increased during dma usage. | |
54 | */ | |
55 | static unsigned int init_nr_desc_per_channel = 64; | |
56 | module_param(init_nr_desc_per_channel, uint, 0644); | |
57 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
58 | "initial descriptors per channel (default: 64)"); | |
59 | ||
60 | ||
61 | /* prototypes */ | |
62 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
d48de6f1 | 63 | static void atc_issue_pending(struct dma_chan *chan); |
dc78baa2 NF |
64 | |
65 | ||
66 | /*----------------------------------------------------------------------*/ | |
67 | ||
265567fb TF |
68 | static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst, |
69 | size_t len) | |
70 | { | |
71 | unsigned int width; | |
72 | ||
73 | if (!((src | dst | len) & 3)) | |
74 | width = 2; | |
75 | else if (!((src | dst | len) & 1)) | |
76 | width = 1; | |
77 | else | |
78 | width = 0; | |
79 | ||
80 | return width; | |
81 | } | |
82 | ||
dc78baa2 NF |
83 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) |
84 | { | |
85 | return list_first_entry(&atchan->active_list, | |
86 | struct at_desc, desc_node); | |
87 | } | |
88 | ||
89 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
90 | { | |
91 | return list_first_entry(&atchan->queue, | |
92 | struct at_desc, desc_node); | |
93 | } | |
94 | ||
95 | /** | |
421f91d2 | 96 | * atc_alloc_descriptor - allocate and return an initialized descriptor |
dc78baa2 NF |
97 | * @chan: the channel to allocate descriptors for |
98 | * @gfp_flags: GFP allocation flags | |
99 | * | |
100 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
101 | * to make initial allocation more convenient. This bit will be cleared | |
102 | * and control will be given to client at usage time (during | |
103 | * preparation functions). | |
104 | */ | |
105 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
106 | gfp_t gfp_flags) | |
107 | { | |
108 | struct at_desc *desc = NULL; | |
109 | struct at_dma *atdma = to_at_dma(chan->device); | |
110 | dma_addr_t phys; | |
111 | ||
112 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
113 | if (desc) { | |
114 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 115 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
116 | dma_async_tx_descriptor_init(&desc->txd, chan); |
117 | /* txd.flags will be overwritten in prep functions */ | |
118 | desc->txd.flags = DMA_CTRL_ACK; | |
119 | desc->txd.tx_submit = atc_tx_submit; | |
120 | desc->txd.phys = phys; | |
121 | } | |
122 | ||
123 | return desc; | |
124 | } | |
125 | ||
126 | /** | |
af901ca1 | 127 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
128 | * @atchan: channel we want a new descriptor for |
129 | */ | |
130 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
131 | { | |
132 | struct at_desc *desc, *_desc; | |
133 | struct at_desc *ret = NULL; | |
d8cb04b0 | 134 | unsigned long flags; |
dc78baa2 NF |
135 | unsigned int i = 0; |
136 | LIST_HEAD(tmp_list); | |
137 | ||
d8cb04b0 | 138 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
139 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { |
140 | i++; | |
141 | if (async_tx_test_ack(&desc->txd)) { | |
142 | list_del(&desc->desc_node); | |
143 | ret = desc; | |
144 | break; | |
145 | } | |
146 | dev_dbg(chan2dev(&atchan->chan_common), | |
147 | "desc %p not ACKed\n", desc); | |
148 | } | |
d8cb04b0 | 149 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
150 | dev_vdbg(chan2dev(&atchan->chan_common), |
151 | "scanned %u descriptors on freelist\n", i); | |
152 | ||
153 | /* no more descriptor available in initial pool: create one more */ | |
154 | if (!ret) { | |
155 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
156 | if (ret) { | |
d8cb04b0 | 157 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 158 | atchan->descs_allocated++; |
d8cb04b0 | 159 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
160 | } else { |
161 | dev_err(chan2dev(&atchan->chan_common), | |
162 | "not enough descriptors available\n"); | |
163 | } | |
164 | } | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | /** | |
170 | * atc_desc_put - move a descriptor, including any children, to the free list | |
171 | * @atchan: channel we work on | |
172 | * @desc: descriptor, at the head of a chain, to move to free list | |
173 | */ | |
174 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
175 | { | |
176 | if (desc) { | |
177 | struct at_desc *child; | |
d8cb04b0 | 178 | unsigned long flags; |
dc78baa2 | 179 | |
d8cb04b0 | 180 | spin_lock_irqsave(&atchan->lock, flags); |
285a3c71 | 181 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
182 | dev_vdbg(chan2dev(&atchan->chan_common), |
183 | "moving child desc %p to freelist\n", | |
184 | child); | |
285a3c71 | 185 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
186 | dev_vdbg(chan2dev(&atchan->chan_common), |
187 | "moving desc %p to freelist\n", desc); | |
188 | list_add(&desc->desc_node, &atchan->free_list); | |
d8cb04b0 | 189 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
190 | } |
191 | } | |
192 | ||
53830cc7 | 193 | /** |
d73111c6 MI |
194 | * atc_desc_chain - build chain adding a descriptor |
195 | * @first: address of first descriptor of the chain | |
196 | * @prev: address of previous descriptor of the chain | |
53830cc7 NF |
197 | * @desc: descriptor to queue |
198 | * | |
199 | * Called from prep_* functions | |
200 | */ | |
201 | static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, | |
202 | struct at_desc *desc) | |
203 | { | |
204 | if (!(*first)) { | |
205 | *first = desc; | |
206 | } else { | |
207 | /* inform the HW lli about chaining */ | |
208 | (*prev)->lli.dscr = desc->txd.phys; | |
209 | /* insert the link descriptor to the LD ring */ | |
210 | list_add_tail(&desc->desc_node, | |
211 | &(*first)->tx_list); | |
212 | } | |
213 | *prev = desc; | |
214 | } | |
215 | ||
dc78baa2 NF |
216 | /** |
217 | * atc_dostart - starts the DMA engine for real | |
218 | * @atchan: the channel we want to start | |
219 | * @first: first descriptor in the list we want to begin with | |
220 | * | |
221 | * Called with atchan->lock held and bh disabled | |
222 | */ | |
223 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
224 | { | |
225 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
226 | ||
227 | /* ASSERT: channel is idle */ | |
228 | if (atc_chan_is_enabled(atchan)) { | |
229 | dev_err(chan2dev(&atchan->chan_common), | |
230 | "BUG: Attempted to start non-idle channel\n"); | |
231 | dev_err(chan2dev(&atchan->chan_common), | |
232 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
233 | channel_readl(atchan, SADDR), | |
234 | channel_readl(atchan, DADDR), | |
235 | channel_readl(atchan, CTRLA), | |
236 | channel_readl(atchan, CTRLB), | |
237 | channel_readl(atchan, DSCR)); | |
238 | ||
239 | /* The tasklet will hopefully advance the queue... */ | |
240 | return; | |
241 | } | |
242 | ||
243 | vdbg_dump_regs(atchan); | |
244 | ||
dc78baa2 NF |
245 | channel_writel(atchan, SADDR, 0); |
246 | channel_writel(atchan, DADDR, 0); | |
247 | channel_writel(atchan, CTRLA, 0); | |
248 | channel_writel(atchan, CTRLB, 0); | |
249 | channel_writel(atchan, DSCR, first->txd.phys); | |
5abecfa5 MR |
250 | channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) | |
251 | ATC_SPIP_BOUNDARY(first->boundary)); | |
252 | channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) | | |
253 | ATC_DPIP_BOUNDARY(first->boundary)); | |
dc78baa2 NF |
254 | dma_writel(atdma, CHER, atchan->mask); |
255 | ||
256 | vdbg_dump_regs(atchan); | |
257 | } | |
258 | ||
d48de6f1 | 259 | /* |
bdf6c792 TF |
260 | * atc_get_desc_by_cookie - get the descriptor of a cookie |
261 | * @atchan: the DMA channel | |
262 | * @cookie: the cookie to get the descriptor for | |
d48de6f1 | 263 | */ |
bdf6c792 TF |
264 | static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan, |
265 | dma_cookie_t cookie) | |
d48de6f1 | 266 | { |
bdf6c792 | 267 | struct at_desc *desc, *_desc; |
d48de6f1 | 268 | |
bdf6c792 TF |
269 | list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) { |
270 | if (desc->txd.cookie == cookie) | |
271 | return desc; | |
272 | } | |
d48de6f1 | 273 | |
bdf6c792 TF |
274 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { |
275 | if (desc->txd.cookie == cookie) | |
276 | return desc; | |
d48de6f1 ES |
277 | } |
278 | ||
bdf6c792 | 279 | return NULL; |
d48de6f1 ES |
280 | } |
281 | ||
bdf6c792 TF |
282 | /** |
283 | * atc_calc_bytes_left - calculates the number of bytes left according to the | |
284 | * value read from CTRLA. | |
285 | * | |
286 | * @current_len: the number of bytes left before reading CTRLA | |
287 | * @ctrla: the value of CTRLA | |
288 | * @desc: the descriptor containing the transfer width | |
289 | */ | |
290 | static inline int atc_calc_bytes_left(int current_len, u32 ctrla, | |
291 | struct at_desc *desc) | |
292 | { | |
293 | return current_len - ((ctrla & ATC_BTSIZE_MAX) << desc->tx_width); | |
294 | } | |
295 | ||
296 | /** | |
297 | * atc_calc_bytes_left_from_reg - calculates the number of bytes left according | |
298 | * to the current value of CTRLA. | |
299 | * | |
300 | * @current_len: the number of bytes left before reading CTRLA | |
301 | * @atchan: the channel to read CTRLA for | |
302 | * @desc: the descriptor containing the transfer width | |
303 | */ | |
304 | static inline int atc_calc_bytes_left_from_reg(int current_len, | |
305 | struct at_dma_chan *atchan, struct at_desc *desc) | |
306 | { | |
307 | u32 ctrla = channel_readl(atchan, CTRLA); | |
308 | ||
309 | return atc_calc_bytes_left(current_len, ctrla, desc); | |
310 | } | |
311 | ||
312 | /** | |
313 | * atc_get_bytes_left - get the number of bytes residue for a cookie | |
314 | * @chan: DMA channel | |
315 | * @cookie: transaction identifier to check status of | |
d48de6f1 | 316 | */ |
bdf6c792 | 317 | static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie) |
d48de6f1 ES |
318 | { |
319 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d48de6f1 | 320 | struct at_desc *desc_first = atc_first_active(atchan); |
bdf6c792 TF |
321 | struct at_desc *desc; |
322 | int ret; | |
323 | u32 ctrla, dscr; | |
d48de6f1 ES |
324 | |
325 | /* | |
bdf6c792 TF |
326 | * If the cookie doesn't match to the currently running transfer then |
327 | * we can return the total length of the associated DMA transfer, | |
328 | * because it is still queued. | |
d48de6f1 | 329 | */ |
bdf6c792 TF |
330 | desc = atc_get_desc_by_cookie(atchan, cookie); |
331 | if (desc == NULL) | |
332 | return -EINVAL; | |
333 | else if (desc != desc_first) | |
334 | return desc->total_len; | |
d48de6f1 | 335 | |
bdf6c792 TF |
336 | /* cookie matches to the currently running transfer */ |
337 | ret = desc_first->total_len; | |
6758ddaf | 338 | |
bdf6c792 TF |
339 | if (desc_first->lli.dscr) { |
340 | /* hardware linked list transfer */ | |
341 | ||
342 | /* | |
343 | * Calculate the residue by removing the length of the child | |
344 | * descriptors already transferred from the total length. | |
345 | * To get the current child descriptor we can use the value of | |
346 | * the channel's DSCR register and compare it against the value | |
347 | * of the hardware linked list structure of each child | |
348 | * descriptor. | |
349 | */ | |
350 | ||
351 | ctrla = channel_readl(atchan, CTRLA); | |
352 | rmb(); /* ensure CTRLA is read before DSCR */ | |
353 | dscr = channel_readl(atchan, DSCR); | |
354 | ||
355 | /* for the first descriptor we can be more accurate */ | |
356 | if (desc_first->lli.dscr == dscr) | |
357 | return atc_calc_bytes_left(ret, ctrla, desc_first); | |
358 | ||
359 | ret -= desc_first->len; | |
360 | list_for_each_entry(desc, &desc_first->tx_list, desc_node) { | |
361 | if (desc->lli.dscr == dscr) | |
362 | break; | |
363 | ||
364 | ret -= desc->len; | |
c3dbc60c | 365 | } |
6758ddaf | 366 | |
d48de6f1 | 367 | /* |
bdf6c792 TF |
368 | * For the last descriptor in the chain we can calculate |
369 | * the remaining bytes using the channel's register. | |
370 | * Note that the transfer width of the first and last | |
371 | * descriptor may differ. | |
d48de6f1 | 372 | */ |
bdf6c792 TF |
373 | if (!desc->lli.dscr) |
374 | ret = atc_calc_bytes_left_from_reg(ret, atchan, desc); | |
375 | } else { | |
376 | /* single transfer */ | |
377 | ret = atc_calc_bytes_left_from_reg(ret, atchan, desc_first); | |
d48de6f1 | 378 | } |
d48de6f1 | 379 | |
d48de6f1 ES |
380 | return ret; |
381 | } | |
382 | ||
dc78baa2 NF |
383 | /** |
384 | * atc_chain_complete - finish work for one transaction chain | |
385 | * @atchan: channel we work on | |
386 | * @desc: descriptor at the head of the chain we want do complete | |
387 | * | |
388 | * Called with atchan->lock held and bh disabled */ | |
389 | static void | |
390 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
391 | { | |
dc78baa2 NF |
392 | struct dma_async_tx_descriptor *txd = &desc->txd; |
393 | ||
394 | dev_vdbg(chan2dev(&atchan->chan_common), | |
395 | "descriptor %u complete\n", txd->cookie); | |
396 | ||
d4116052 VK |
397 | /* mark the descriptor as complete for non cyclic cases only */ |
398 | if (!atc_chan_is_cyclic(atchan)) | |
399 | dma_cookie_complete(txd); | |
dc78baa2 NF |
400 | |
401 | /* move children to free_list */ | |
285a3c71 | 402 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
403 | /* move myself to free_list */ |
404 | list_move(&desc->desc_node, &atchan->free_list); | |
405 | ||
d38a8c62 | 406 | dma_descriptor_unmap(txd); |
53830cc7 NF |
407 | /* for cyclic transfers, |
408 | * no need to replay callback function while stopping */ | |
3c477482 | 409 | if (!atc_chan_is_cyclic(atchan)) { |
53830cc7 NF |
410 | dma_async_tx_callback callback = txd->callback; |
411 | void *param = txd->callback_param; | |
412 | ||
413 | /* | |
414 | * The API requires that no submissions are done from a | |
415 | * callback, so we don't need to drop the lock here | |
416 | */ | |
417 | if (callback) | |
418 | callback(param); | |
419 | } | |
dc78baa2 NF |
420 | |
421 | dma_run_dependencies(txd); | |
422 | } | |
423 | ||
424 | /** | |
425 | * atc_complete_all - finish work for all transactions | |
426 | * @atchan: channel to complete transactions for | |
427 | * | |
428 | * Eventually submit queued descriptors if any | |
429 | * | |
430 | * Assume channel is idle while calling this function | |
431 | * Called with atchan->lock held and bh disabled | |
432 | */ | |
433 | static void atc_complete_all(struct at_dma_chan *atchan) | |
434 | { | |
435 | struct at_desc *desc, *_desc; | |
436 | LIST_HEAD(list); | |
437 | ||
438 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
439 | ||
dc78baa2 NF |
440 | /* |
441 | * Submit queued descriptors ASAP, i.e. before we go through | |
442 | * the completed ones. | |
443 | */ | |
444 | if (!list_empty(&atchan->queue)) | |
445 | atc_dostart(atchan, atc_first_queued(atchan)); | |
446 | /* empty active_list now it is completed */ | |
447 | list_splice_init(&atchan->active_list, &list); | |
448 | /* empty queue list by moving descriptors (if any) to active_list */ | |
449 | list_splice_init(&atchan->queue, &atchan->active_list); | |
450 | ||
451 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
452 | atc_chain_complete(atchan, desc); | |
453 | } | |
454 | ||
dc78baa2 NF |
455 | /** |
456 | * atc_advance_work - at the end of a transaction, move forward | |
457 | * @atchan: channel where the transaction ended | |
458 | * | |
459 | * Called with atchan->lock held and bh disabled | |
460 | */ | |
461 | static void atc_advance_work(struct at_dma_chan *atchan) | |
462 | { | |
463 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
464 | ||
d202f051 LD |
465 | if (atc_chan_is_enabled(atchan)) |
466 | return; | |
467 | ||
dc78baa2 NF |
468 | if (list_empty(&atchan->active_list) || |
469 | list_is_singular(&atchan->active_list)) { | |
470 | atc_complete_all(atchan); | |
471 | } else { | |
472 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
473 | /* advance work */ | |
474 | atc_dostart(atchan, atc_first_active(atchan)); | |
475 | } | |
476 | } | |
477 | ||
478 | ||
479 | /** | |
480 | * atc_handle_error - handle errors reported by DMA controller | |
481 | * @atchan: channel where error occurs | |
482 | * | |
483 | * Called with atchan->lock held and bh disabled | |
484 | */ | |
485 | static void atc_handle_error(struct at_dma_chan *atchan) | |
486 | { | |
487 | struct at_desc *bad_desc; | |
488 | struct at_desc *child; | |
489 | ||
490 | /* | |
491 | * The descriptor currently at the head of the active list is | |
492 | * broked. Since we don't have any way to report errors, we'll | |
493 | * just have to scream loudly and try to carry on. | |
494 | */ | |
495 | bad_desc = atc_first_active(atchan); | |
496 | list_del_init(&bad_desc->desc_node); | |
497 | ||
498 | /* As we are stopped, take advantage to push queued descriptors | |
499 | * in active_list */ | |
500 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
501 | ||
502 | /* Try to restart the controller */ | |
503 | if (!list_empty(&atchan->active_list)) | |
504 | atc_dostart(atchan, atc_first_active(atchan)); | |
505 | ||
506 | /* | |
507 | * KERN_CRITICAL may seem harsh, but since this only happens | |
508 | * when someone submits a bad physical address in a | |
509 | * descriptor, we should consider ourselves lucky that the | |
510 | * controller flagged an error instead of scribbling over | |
511 | * random memory locations. | |
512 | */ | |
513 | dev_crit(chan2dev(&atchan->chan_common), | |
514 | "Bad descriptor submitted for DMA!\n"); | |
515 | dev_crit(chan2dev(&atchan->chan_common), | |
516 | " cookie: %d\n", bad_desc->txd.cookie); | |
517 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 518 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
519 | atc_dump_lli(atchan, &child->lli); |
520 | ||
521 | /* Pretend the descriptor completed successfully */ | |
522 | atc_chain_complete(atchan, bad_desc); | |
523 | } | |
524 | ||
53830cc7 NF |
525 | /** |
526 | * atc_handle_cyclic - at the end of a period, run callback function | |
527 | * @atchan: channel used for cyclic operations | |
528 | * | |
529 | * Called with atchan->lock held and bh disabled | |
530 | */ | |
531 | static void atc_handle_cyclic(struct at_dma_chan *atchan) | |
532 | { | |
533 | struct at_desc *first = atc_first_active(atchan); | |
534 | struct dma_async_tx_descriptor *txd = &first->txd; | |
535 | dma_async_tx_callback callback = txd->callback; | |
536 | void *param = txd->callback_param; | |
537 | ||
538 | dev_vdbg(chan2dev(&atchan->chan_common), | |
539 | "new cyclic period llp 0x%08x\n", | |
540 | channel_readl(atchan, DSCR)); | |
541 | ||
542 | if (callback) | |
543 | callback(param); | |
544 | } | |
dc78baa2 NF |
545 | |
546 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
547 | ||
548 | static void atc_tasklet(unsigned long data) | |
549 | { | |
550 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
d8cb04b0 | 551 | unsigned long flags; |
dc78baa2 | 552 | |
d8cb04b0 | 553 | spin_lock_irqsave(&atchan->lock, flags); |
53830cc7 | 554 | if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) |
dc78baa2 | 555 | atc_handle_error(atchan); |
3c477482 | 556 | else if (atc_chan_is_cyclic(atchan)) |
53830cc7 | 557 | atc_handle_cyclic(atchan); |
dc78baa2 NF |
558 | else |
559 | atc_advance_work(atchan); | |
560 | ||
d8cb04b0 | 561 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
562 | } |
563 | ||
564 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
565 | { | |
566 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
567 | struct at_dma_chan *atchan; | |
568 | int i; | |
569 | u32 status, pending, imr; | |
570 | int ret = IRQ_NONE; | |
571 | ||
572 | do { | |
573 | imr = dma_readl(atdma, EBCIMR); | |
574 | status = dma_readl(atdma, EBCISR); | |
575 | pending = status & imr; | |
576 | ||
577 | if (!pending) | |
578 | break; | |
579 | ||
580 | dev_vdbg(atdma->dma_common.dev, | |
581 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
582 | status, imr, pending); | |
583 | ||
584 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
585 | atchan = &atdma->chan[i]; | |
9b3aa589 | 586 | if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { |
dc78baa2 NF |
587 | if (pending & AT_DMA_ERR(i)) { |
588 | /* Disable channel on AHB error */ | |
23b5e3ad NF |
589 | dma_writel(atdma, CHDR, |
590 | AT_DMA_RES(i) | atchan->mask); | |
dc78baa2 | 591 | /* Give information to tasklet */ |
53830cc7 | 592 | set_bit(ATC_IS_ERROR, &atchan->status); |
dc78baa2 NF |
593 | } |
594 | tasklet_schedule(&atchan->tasklet); | |
595 | ret = IRQ_HANDLED; | |
596 | } | |
597 | } | |
598 | ||
599 | } while (pending); | |
600 | ||
601 | return ret; | |
602 | } | |
603 | ||
604 | ||
605 | /*-- DMA Engine API --------------------------------------------------*/ | |
606 | ||
607 | /** | |
608 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
609 | * @desc: descriptor at the head of the transaction chain | |
610 | * | |
611 | * Queue chain if DMA engine is working already | |
612 | * | |
613 | * Cookie increment and adding to active_list or queue must be atomic | |
614 | */ | |
615 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
616 | { | |
617 | struct at_desc *desc = txd_to_at_desc(tx); | |
618 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
619 | dma_cookie_t cookie; | |
d8cb04b0 | 620 | unsigned long flags; |
dc78baa2 | 621 | |
d8cb04b0 | 622 | spin_lock_irqsave(&atchan->lock, flags); |
884485e1 | 623 | cookie = dma_cookie_assign(tx); |
dc78baa2 NF |
624 | |
625 | if (list_empty(&atchan->active_list)) { | |
626 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
627 | desc->txd.cookie); | |
628 | atc_dostart(atchan, desc); | |
629 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
630 | } else { | |
631 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
632 | desc->txd.cookie); | |
633 | list_add_tail(&desc->desc_node, &atchan->queue); | |
634 | } | |
635 | ||
d8cb04b0 | 636 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
637 | |
638 | return cookie; | |
639 | } | |
640 | ||
5abecfa5 MR |
641 | /** |
642 | * atc_prep_dma_interleaved - prepare memory to memory interleaved operation | |
643 | * @chan: the channel to prepare operation on | |
644 | * @xt: Interleaved transfer template | |
645 | * @flags: tx descriptor status flags | |
646 | */ | |
647 | static struct dma_async_tx_descriptor * | |
648 | atc_prep_dma_interleaved(struct dma_chan *chan, | |
649 | struct dma_interleaved_template *xt, | |
650 | unsigned long flags) | |
651 | { | |
652 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
653 | struct data_chunk *first = xt->sgl; | |
654 | struct at_desc *desc = NULL; | |
655 | size_t xfer_count; | |
656 | unsigned int dwidth; | |
657 | u32 ctrla; | |
658 | u32 ctrlb; | |
659 | size_t len = 0; | |
660 | int i; | |
661 | ||
662 | dev_info(chan2dev(chan), | |
663 | "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n", | |
664 | __func__, xt->src_start, xt->dst_start, xt->numf, | |
665 | xt->frame_size, flags); | |
666 | ||
667 | if (unlikely(!xt || xt->numf != 1 || !xt->frame_size)) | |
668 | return NULL; | |
669 | ||
670 | /* | |
671 | * The controller can only "skip" X bytes every Y bytes, so we | |
672 | * need to make sure we are given a template that fit that | |
673 | * description, ie a template with chunks that always have the | |
674 | * same size, with the same ICGs. | |
675 | */ | |
676 | for (i = 0; i < xt->frame_size; i++) { | |
677 | struct data_chunk *chunk = xt->sgl + i; | |
678 | ||
679 | if ((chunk->size != xt->sgl->size) || | |
680 | (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) || | |
681 | (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) { | |
682 | dev_err(chan2dev(chan), | |
683 | "%s: the controller can transfer only identical chunks\n", | |
684 | __func__); | |
685 | return NULL; | |
686 | } | |
687 | ||
688 | len += chunk->size; | |
689 | } | |
690 | ||
691 | dwidth = atc_get_xfer_width(xt->src_start, | |
692 | xt->dst_start, len); | |
693 | ||
694 | xfer_count = len >> dwidth; | |
695 | if (xfer_count > ATC_BTSIZE_MAX) { | |
696 | dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__); | |
697 | return NULL; | |
698 | } | |
699 | ||
700 | ctrla = ATC_SRC_WIDTH(dwidth) | | |
701 | ATC_DST_WIDTH(dwidth); | |
702 | ||
703 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
704 | | ATC_SRC_ADDR_MODE_INCR | |
705 | | ATC_DST_ADDR_MODE_INCR | |
706 | | ATC_SRC_PIP | |
707 | | ATC_DST_PIP | |
708 | | ATC_FC_MEM2MEM; | |
709 | ||
710 | /* create the transfer */ | |
711 | desc = atc_desc_get(atchan); | |
712 | if (!desc) { | |
713 | dev_err(chan2dev(chan), | |
714 | "%s: couldn't allocate our descriptor\n", __func__); | |
715 | return NULL; | |
716 | } | |
717 | ||
718 | desc->lli.saddr = xt->src_start; | |
719 | desc->lli.daddr = xt->dst_start; | |
720 | desc->lli.ctrla = ctrla | xfer_count; | |
721 | desc->lli.ctrlb = ctrlb; | |
722 | ||
723 | desc->boundary = first->size >> dwidth; | |
724 | desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1; | |
725 | desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1; | |
726 | ||
727 | desc->txd.cookie = -EBUSY; | |
728 | desc->total_len = desc->len = len; | |
729 | desc->tx_width = dwidth; | |
730 | ||
731 | /* set end-of-link to the last link descriptor of list*/ | |
732 | set_desc_eol(desc); | |
733 | ||
734 | desc->txd.flags = flags; /* client is in control of this ack */ | |
735 | ||
736 | return &desc->txd; | |
737 | } | |
738 | ||
dc78baa2 NF |
739 | /** |
740 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
741 | * @chan: the channel to prepare operation on | |
742 | * @dest: operation virtual destination address | |
743 | * @src: operation virtual source address | |
744 | * @len: operation length | |
745 | * @flags: tx descriptor status flags | |
746 | */ | |
747 | static struct dma_async_tx_descriptor * | |
748 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
749 | size_t len, unsigned long flags) | |
750 | { | |
751 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
752 | struct at_desc *desc = NULL; | |
753 | struct at_desc *first = NULL; | |
754 | struct at_desc *prev = NULL; | |
755 | size_t xfer_count; | |
756 | size_t offset; | |
757 | unsigned int src_width; | |
758 | unsigned int dst_width; | |
759 | u32 ctrla; | |
760 | u32 ctrlb; | |
761 | ||
762 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
763 | dest, src, len, flags); | |
764 | ||
765 | if (unlikely(!len)) { | |
766 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
767 | return NULL; | |
768 | } | |
769 | ||
9b3aa589 | 770 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
dc78baa2 NF |
771 | | ATC_SRC_ADDR_MODE_INCR |
772 | | ATC_DST_ADDR_MODE_INCR | |
773 | | ATC_FC_MEM2MEM; | |
774 | ||
775 | /* | |
776 | * We can be a lot more clever here, but this should take care | |
777 | * of the most common optimization. | |
778 | */ | |
265567fb TF |
779 | src_width = dst_width = atc_get_xfer_width(src, dest, len); |
780 | ||
781 | ctrla = ATC_SRC_WIDTH(src_width) | | |
782 | ATC_DST_WIDTH(dst_width); | |
dc78baa2 NF |
783 | |
784 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
785 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
786 | ATC_BTSIZE_MAX); | |
787 | ||
788 | desc = atc_desc_get(atchan); | |
789 | if (!desc) | |
790 | goto err_desc_get; | |
791 | ||
792 | desc->lli.saddr = src + offset; | |
793 | desc->lli.daddr = dest + offset; | |
794 | desc->lli.ctrla = ctrla | xfer_count; | |
795 | desc->lli.ctrlb = ctrlb; | |
796 | ||
797 | desc->txd.cookie = 0; | |
bdf6c792 | 798 | desc->len = xfer_count << src_width; |
dc78baa2 | 799 | |
e257e156 | 800 | atc_desc_chain(&first, &prev, desc); |
dc78baa2 NF |
801 | } |
802 | ||
803 | /* First descriptor of the chain embedds additional information */ | |
804 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
805 | first->total_len = len; |
806 | ||
807 | /* set transfer width for the calculation of the residue */ | |
d088c33b | 808 | first->tx_width = src_width; |
bdf6c792 | 809 | prev->tx_width = src_width; |
dc78baa2 NF |
810 | |
811 | /* set end-of-link to the last link descriptor of list*/ | |
812 | set_desc_eol(desc); | |
813 | ||
568f7f0c | 814 | first->txd.flags = flags; /* client is in control of this ack */ |
dc78baa2 NF |
815 | |
816 | return &first->txd; | |
817 | ||
818 | err_desc_get: | |
819 | atc_desc_put(atchan, first); | |
820 | return NULL; | |
821 | } | |
822 | ||
808347f6 NF |
823 | |
824 | /** | |
825 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
826 | * @chan: DMA channel | |
827 | * @sgl: scatterlist to transfer to/from | |
828 | * @sg_len: number of entries in @scatterlist | |
829 | * @direction: DMA direction | |
830 | * @flags: tx descriptor status flags | |
185ecb5f | 831 | * @context: transaction context (ignored) |
808347f6 NF |
832 | */ |
833 | static struct dma_async_tx_descriptor * | |
834 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 835 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 836 | unsigned long flags, void *context) |
808347f6 NF |
837 | { |
838 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
839 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 840 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
808347f6 NF |
841 | struct at_desc *first = NULL; |
842 | struct at_desc *prev = NULL; | |
843 | u32 ctrla; | |
844 | u32 ctrlb; | |
845 | dma_addr_t reg; | |
846 | unsigned int reg_width; | |
847 | unsigned int mem_width; | |
848 | unsigned int i; | |
849 | struct scatterlist *sg; | |
850 | size_t total_len = 0; | |
851 | ||
cc52a10a NF |
852 | dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", |
853 | sg_len, | |
db8196df | 854 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
808347f6 NF |
855 | flags); |
856 | ||
857 | if (unlikely(!atslave || !sg_len)) { | |
c618a9be | 858 | dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n"); |
808347f6 NF |
859 | return NULL; |
860 | } | |
861 | ||
1dd1ea8e NF |
862 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
863 | | ATC_DCSIZE(sconfig->dst_maxburst); | |
ae14d4b5 | 864 | ctrlb = ATC_IEN; |
808347f6 NF |
865 | |
866 | switch (direction) { | |
db8196df | 867 | case DMA_MEM_TO_DEV: |
beeaa103 | 868 | reg_width = convert_buswidth(sconfig->dst_addr_width); |
808347f6 NF |
869 | ctrla |= ATC_DST_WIDTH(reg_width); |
870 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
871 | | ATC_SRC_ADDR_MODE_INCR | |
ae14d4b5 | 872 | | ATC_FC_MEM2PER |
bbe89c8e | 873 | | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if); |
beeaa103 | 874 | reg = sconfig->dst_addr; |
808347f6 NF |
875 | for_each_sg(sgl, sg, sg_len, i) { |
876 | struct at_desc *desc; | |
877 | u32 len; | |
878 | u32 mem; | |
879 | ||
880 | desc = atc_desc_get(atchan); | |
881 | if (!desc) | |
882 | goto err_desc_get; | |
883 | ||
0f70e8ce | 884 | mem = sg_dma_address(sg); |
808347f6 | 885 | len = sg_dma_len(sg); |
c4567976 NF |
886 | if (unlikely(!len)) { |
887 | dev_dbg(chan2dev(chan), | |
888 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
889 | goto err; | |
890 | } | |
808347f6 NF |
891 | mem_width = 2; |
892 | if (unlikely(mem & 3 || len & 3)) | |
893 | mem_width = 0; | |
894 | ||
895 | desc->lli.saddr = mem; | |
896 | desc->lli.daddr = reg; | |
897 | desc->lli.ctrla = ctrla | |
898 | | ATC_SRC_WIDTH(mem_width) | |
899 | | len >> mem_width; | |
900 | desc->lli.ctrlb = ctrlb; | |
bdf6c792 | 901 | desc->len = len; |
808347f6 | 902 | |
e257e156 | 903 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
904 | total_len += len; |
905 | } | |
906 | break; | |
db8196df | 907 | case DMA_DEV_TO_MEM: |
beeaa103 | 908 | reg_width = convert_buswidth(sconfig->src_addr_width); |
808347f6 NF |
909 | ctrla |= ATC_SRC_WIDTH(reg_width); |
910 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
911 | | ATC_SRC_ADDR_MODE_FIXED | |
ae14d4b5 | 912 | | ATC_FC_PER2MEM |
bbe89c8e | 913 | | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if); |
808347f6 | 914 | |
beeaa103 | 915 | reg = sconfig->src_addr; |
808347f6 NF |
916 | for_each_sg(sgl, sg, sg_len, i) { |
917 | struct at_desc *desc; | |
918 | u32 len; | |
919 | u32 mem; | |
920 | ||
921 | desc = atc_desc_get(atchan); | |
922 | if (!desc) | |
923 | goto err_desc_get; | |
924 | ||
0f70e8ce | 925 | mem = sg_dma_address(sg); |
808347f6 | 926 | len = sg_dma_len(sg); |
c4567976 NF |
927 | if (unlikely(!len)) { |
928 | dev_dbg(chan2dev(chan), | |
929 | "prep_slave_sg: sg(%d) data length is zero\n", i); | |
930 | goto err; | |
931 | } | |
808347f6 NF |
932 | mem_width = 2; |
933 | if (unlikely(mem & 3 || len & 3)) | |
934 | mem_width = 0; | |
935 | ||
936 | desc->lli.saddr = reg; | |
937 | desc->lli.daddr = mem; | |
938 | desc->lli.ctrla = ctrla | |
939 | | ATC_DST_WIDTH(mem_width) | |
59a609d9 | 940 | | len >> reg_width; |
808347f6 | 941 | desc->lli.ctrlb = ctrlb; |
bdf6c792 | 942 | desc->len = len; |
808347f6 | 943 | |
e257e156 | 944 | atc_desc_chain(&first, &prev, desc); |
808347f6 NF |
945 | total_len += len; |
946 | } | |
947 | break; | |
948 | default: | |
949 | return NULL; | |
950 | } | |
951 | ||
952 | /* set end-of-link to the last link descriptor of list*/ | |
953 | set_desc_eol(prev); | |
954 | ||
955 | /* First descriptor of the chain embedds additional information */ | |
956 | first->txd.cookie = -EBUSY; | |
bdf6c792 TF |
957 | first->total_len = total_len; |
958 | ||
959 | /* set transfer width for the calculation of the residue */ | |
d088c33b | 960 | first->tx_width = reg_width; |
bdf6c792 | 961 | prev->tx_width = reg_width; |
808347f6 | 962 | |
568f7f0c NF |
963 | /* first link descriptor of list is responsible of flags */ |
964 | first->txd.flags = flags; /* client is in control of this ack */ | |
808347f6 NF |
965 | |
966 | return &first->txd; | |
967 | ||
968 | err_desc_get: | |
969 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
c4567976 | 970 | err: |
808347f6 NF |
971 | atc_desc_put(atchan, first); |
972 | return NULL; | |
973 | } | |
974 | ||
265567fb TF |
975 | /** |
976 | * atc_prep_dma_sg - prepare memory to memory scather-gather operation | |
977 | * @chan: the channel to prepare operation on | |
978 | * @dst_sg: destination scatterlist | |
979 | * @dst_nents: number of destination scatterlist entries | |
980 | * @src_sg: source scatterlist | |
981 | * @src_nents: number of source scatterlist entries | |
982 | * @flags: tx descriptor status flags | |
983 | */ | |
984 | static struct dma_async_tx_descriptor * | |
985 | atc_prep_dma_sg(struct dma_chan *chan, | |
986 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
987 | struct scatterlist *src_sg, unsigned int src_nents, | |
988 | unsigned long flags) | |
989 | { | |
990 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
991 | struct at_desc *desc = NULL; | |
992 | struct at_desc *first = NULL; | |
993 | struct at_desc *prev = NULL; | |
994 | unsigned int src_width; | |
995 | unsigned int dst_width; | |
996 | size_t xfer_count; | |
997 | u32 ctrla; | |
998 | u32 ctrlb; | |
999 | size_t dst_len = 0, src_len = 0; | |
1000 | dma_addr_t dst = 0, src = 0; | |
1001 | size_t len = 0, total_len = 0; | |
1002 | ||
1003 | if (unlikely(dst_nents == 0 || src_nents == 0)) | |
1004 | return NULL; | |
1005 | ||
1006 | if (unlikely(dst_sg == NULL || src_sg == NULL)) | |
1007 | return NULL; | |
1008 | ||
1009 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | |
1010 | | ATC_SRC_ADDR_MODE_INCR | |
1011 | | ATC_DST_ADDR_MODE_INCR | |
1012 | | ATC_FC_MEM2MEM; | |
1013 | ||
1014 | /* | |
1015 | * loop until there is either no more source or no more destination | |
1016 | * scatterlist entry | |
1017 | */ | |
1018 | while (true) { | |
1019 | ||
1020 | /* prepare the next transfer */ | |
1021 | if (dst_len == 0) { | |
1022 | ||
1023 | /* no more destination scatterlist entries */ | |
1024 | if (!dst_sg || !dst_nents) | |
1025 | break; | |
1026 | ||
1027 | dst = sg_dma_address(dst_sg); | |
1028 | dst_len = sg_dma_len(dst_sg); | |
1029 | ||
1030 | dst_sg = sg_next(dst_sg); | |
1031 | dst_nents--; | |
1032 | } | |
1033 | ||
1034 | if (src_len == 0) { | |
1035 | ||
1036 | /* no more source scatterlist entries */ | |
1037 | if (!src_sg || !src_nents) | |
1038 | break; | |
1039 | ||
1040 | src = sg_dma_address(src_sg); | |
1041 | src_len = sg_dma_len(src_sg); | |
1042 | ||
1043 | src_sg = sg_next(src_sg); | |
1044 | src_nents--; | |
1045 | } | |
1046 | ||
1047 | len = min_t(size_t, src_len, dst_len); | |
1048 | if (len == 0) | |
1049 | continue; | |
1050 | ||
1051 | /* take care for the alignment */ | |
1052 | src_width = dst_width = atc_get_xfer_width(src, dst, len); | |
1053 | ||
1054 | ctrla = ATC_SRC_WIDTH(src_width) | | |
1055 | ATC_DST_WIDTH(dst_width); | |
1056 | ||
1057 | /* | |
1058 | * The number of transfers to set up refer to the source width | |
1059 | * that depends on the alignment. | |
1060 | */ | |
1061 | xfer_count = len >> src_width; | |
1062 | if (xfer_count > ATC_BTSIZE_MAX) { | |
1063 | xfer_count = ATC_BTSIZE_MAX; | |
1064 | len = ATC_BTSIZE_MAX << src_width; | |
1065 | } | |
1066 | ||
1067 | /* create the transfer */ | |
1068 | desc = atc_desc_get(atchan); | |
1069 | if (!desc) | |
1070 | goto err_desc_get; | |
1071 | ||
1072 | desc->lli.saddr = src; | |
1073 | desc->lli.daddr = dst; | |
1074 | desc->lli.ctrla = ctrla | xfer_count; | |
1075 | desc->lli.ctrlb = ctrlb; | |
1076 | ||
1077 | desc->txd.cookie = 0; | |
1078 | desc->len = len; | |
1079 | ||
1080 | /* | |
1081 | * Although we only need the transfer width for the first and | |
1082 | * the last descriptor, its easier to set it to all descriptors. | |
1083 | */ | |
1084 | desc->tx_width = src_width; | |
1085 | ||
1086 | atc_desc_chain(&first, &prev, desc); | |
1087 | ||
1088 | /* update the lengths and addresses for the next loop cycle */ | |
1089 | dst_len -= len; | |
1090 | src_len -= len; | |
1091 | dst += len; | |
1092 | src += len; | |
1093 | ||
1094 | total_len += len; | |
1095 | } | |
1096 | ||
1097 | /* First descriptor of the chain embedds additional information */ | |
1098 | first->txd.cookie = -EBUSY; | |
1099 | first->total_len = total_len; | |
1100 | ||
1101 | /* set end-of-link to the last link descriptor of list*/ | |
1102 | set_desc_eol(desc); | |
1103 | ||
1104 | first->txd.flags = flags; /* client is in control of this ack */ | |
1105 | ||
1106 | return &first->txd; | |
1107 | ||
1108 | err_desc_get: | |
1109 | atc_desc_put(atchan, first); | |
1110 | return NULL; | |
1111 | } | |
1112 | ||
53830cc7 NF |
1113 | /** |
1114 | * atc_dma_cyclic_check_values | |
1115 | * Check for too big/unaligned periods and unaligned DMA buffer | |
1116 | */ | |
1117 | static int | |
1118 | atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, | |
0e7264cc | 1119 | size_t period_len) |
53830cc7 NF |
1120 | { |
1121 | if (period_len > (ATC_BTSIZE_MAX << reg_width)) | |
1122 | goto err_out; | |
1123 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1124 | goto err_out; | |
1125 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1126 | goto err_out; | |
53830cc7 NF |
1127 | |
1128 | return 0; | |
1129 | ||
1130 | err_out: | |
1131 | return -EINVAL; | |
1132 | } | |
1133 | ||
1134 | /** | |
d73111c6 | 1135 | * atc_dma_cyclic_fill_desc - Fill one period descriptor |
53830cc7 NF |
1136 | */ |
1137 | static int | |
beeaa103 | 1138 | atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, |
53830cc7 | 1139 | unsigned int period_index, dma_addr_t buf_addr, |
beeaa103 NF |
1140 | unsigned int reg_width, size_t period_len, |
1141 | enum dma_transfer_direction direction) | |
53830cc7 | 1142 | { |
beeaa103 | 1143 | struct at_dma_chan *atchan = to_at_dma_chan(chan); |
beeaa103 NF |
1144 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
1145 | u32 ctrla; | |
53830cc7 NF |
1146 | |
1147 | /* prepare common CRTLA value */ | |
1dd1ea8e NF |
1148 | ctrla = ATC_SCSIZE(sconfig->src_maxburst) |
1149 | | ATC_DCSIZE(sconfig->dst_maxburst) | |
53830cc7 NF |
1150 | | ATC_DST_WIDTH(reg_width) |
1151 | | ATC_SRC_WIDTH(reg_width) | |
1152 | | period_len >> reg_width; | |
1153 | ||
1154 | switch (direction) { | |
db8196df | 1155 | case DMA_MEM_TO_DEV: |
53830cc7 | 1156 | desc->lli.saddr = buf_addr + (period_len * period_index); |
beeaa103 | 1157 | desc->lli.daddr = sconfig->dst_addr; |
53830cc7 | 1158 | desc->lli.ctrla = ctrla; |
ae14d4b5 | 1159 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED |
53830cc7 | 1160 | | ATC_SRC_ADDR_MODE_INCR |
ae14d4b5 | 1161 | | ATC_FC_MEM2PER |
bbe89c8e LD |
1162 | | ATC_SIF(atchan->mem_if) |
1163 | | ATC_DIF(atchan->per_if); | |
bdf6c792 | 1164 | desc->len = period_len; |
53830cc7 NF |
1165 | break; |
1166 | ||
db8196df | 1167 | case DMA_DEV_TO_MEM: |
beeaa103 | 1168 | desc->lli.saddr = sconfig->src_addr; |
53830cc7 NF |
1169 | desc->lli.daddr = buf_addr + (period_len * period_index); |
1170 | desc->lli.ctrla = ctrla; | |
ae14d4b5 | 1171 | desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR |
53830cc7 | 1172 | | ATC_SRC_ADDR_MODE_FIXED |
ae14d4b5 | 1173 | | ATC_FC_PER2MEM |
bbe89c8e LD |
1174 | | ATC_SIF(atchan->per_if) |
1175 | | ATC_DIF(atchan->mem_if); | |
bdf6c792 | 1176 | desc->len = period_len; |
53830cc7 NF |
1177 | break; |
1178 | ||
1179 | default: | |
1180 | return -EINVAL; | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * atc_prep_dma_cyclic - prepare the cyclic DMA transfer | |
1188 | * @chan: the DMA channel to prepare | |
1189 | * @buf_addr: physical DMA address where the buffer starts | |
1190 | * @buf_len: total number of bytes for the entire buffer | |
1191 | * @period_len: number of bytes for each period | |
1192 | * @direction: transfer direction, to or from device | |
ec8b5e48 | 1193 | * @flags: tx descriptor status flags |
53830cc7 NF |
1194 | */ |
1195 | static struct dma_async_tx_descriptor * | |
1196 | atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 1197 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1198 | unsigned long flags) |
53830cc7 NF |
1199 | { |
1200 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1201 | struct at_dma_slave *atslave = chan->private; | |
beeaa103 | 1202 | struct dma_slave_config *sconfig = &atchan->dma_sconfig; |
53830cc7 NF |
1203 | struct at_desc *first = NULL; |
1204 | struct at_desc *prev = NULL; | |
1205 | unsigned long was_cyclic; | |
beeaa103 | 1206 | unsigned int reg_width; |
53830cc7 NF |
1207 | unsigned int periods = buf_len / period_len; |
1208 | unsigned int i; | |
1209 | ||
1210 | dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", | |
db8196df | 1211 | direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", |
53830cc7 NF |
1212 | buf_addr, |
1213 | periods, buf_len, period_len); | |
1214 | ||
1215 | if (unlikely(!atslave || !buf_len || !period_len)) { | |
1216 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); | |
1217 | return NULL; | |
1218 | } | |
1219 | ||
1220 | was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); | |
1221 | if (was_cyclic) { | |
1222 | dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); | |
1223 | return NULL; | |
1224 | } | |
1225 | ||
0e7264cc AS |
1226 | if (unlikely(!is_slave_direction(direction))) |
1227 | goto err_out; | |
1228 | ||
beeaa103 NF |
1229 | if (sconfig->direction == DMA_MEM_TO_DEV) |
1230 | reg_width = convert_buswidth(sconfig->dst_addr_width); | |
1231 | else | |
1232 | reg_width = convert_buswidth(sconfig->src_addr_width); | |
1233 | ||
53830cc7 | 1234 | /* Check for too big/unaligned periods and unaligned DMA buffer */ |
0e7264cc | 1235 | if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len)) |
53830cc7 NF |
1236 | goto err_out; |
1237 | ||
1238 | /* build cyclic linked list */ | |
1239 | for (i = 0; i < periods; i++) { | |
1240 | struct at_desc *desc; | |
1241 | ||
1242 | desc = atc_desc_get(atchan); | |
1243 | if (!desc) | |
1244 | goto err_desc_get; | |
1245 | ||
beeaa103 NF |
1246 | if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, |
1247 | reg_width, period_len, direction)) | |
53830cc7 NF |
1248 | goto err_desc_get; |
1249 | ||
1250 | atc_desc_chain(&first, &prev, desc); | |
1251 | } | |
1252 | ||
1253 | /* lets make a cyclic list */ | |
1254 | prev->lli.dscr = first->txd.phys; | |
1255 | ||
1256 | /* First descriptor of the chain embedds additional information */ | |
1257 | first->txd.cookie = -EBUSY; | |
bdf6c792 | 1258 | first->total_len = buf_len; |
d088c33b | 1259 | first->tx_width = reg_width; |
53830cc7 NF |
1260 | |
1261 | return &first->txd; | |
1262 | ||
1263 | err_desc_get: | |
1264 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
1265 | atc_desc_put(atchan, first); | |
1266 | err_out: | |
1267 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1268 | return NULL; | |
1269 | } | |
1270 | ||
4facfe7f MR |
1271 | static int atc_config(struct dma_chan *chan, |
1272 | struct dma_slave_config *sconfig) | |
beeaa103 NF |
1273 | { |
1274 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1275 | ||
4facfe7f MR |
1276 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
1277 | ||
beeaa103 NF |
1278 | /* Check if it is chan is configured for slave transfers */ |
1279 | if (!chan->private) | |
1280 | return -EINVAL; | |
1281 | ||
1282 | memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); | |
1283 | ||
1284 | convert_burst(&atchan->dma_sconfig.src_maxburst); | |
1285 | convert_burst(&atchan->dma_sconfig.dst_maxburst); | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
4facfe7f MR |
1290 | static int atc_pause(struct dma_chan *chan) |
1291 | { | |
1292 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1293 | struct at_dma *atdma = to_at_dma(chan->device); | |
1294 | int chan_id = atchan->chan_common.chan_id; | |
1295 | unsigned long flags; | |
53830cc7 | 1296 | |
4facfe7f MR |
1297 | LIST_HEAD(list); |
1298 | ||
1299 | dev_vdbg(chan2dev(chan), "%s\n", __func__); | |
1300 | ||
1301 | spin_lock_irqsave(&atchan->lock, flags); | |
1302 | ||
1303 | dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); | |
1304 | set_bit(ATC_IS_PAUSED, &atchan->status); | |
1305 | ||
1306 | spin_unlock_irqrestore(&atchan->lock, flags); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | static int atc_resume(struct dma_chan *chan) | |
808347f6 NF |
1312 | { |
1313 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1314 | struct at_dma *atdma = to_at_dma(chan->device); | |
23b5e3ad | 1315 | int chan_id = atchan->chan_common.chan_id; |
d8cb04b0 | 1316 | unsigned long flags; |
23b5e3ad | 1317 | |
808347f6 NF |
1318 | LIST_HEAD(list); |
1319 | ||
4facfe7f | 1320 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
c3635c78 | 1321 | |
4facfe7f MR |
1322 | if (!atc_chan_is_paused(atchan)) |
1323 | return 0; | |
808347f6 | 1324 | |
4facfe7f | 1325 | spin_lock_irqsave(&atchan->lock, flags); |
808347f6 | 1326 | |
4facfe7f MR |
1327 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); |
1328 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
808347f6 | 1329 | |
4facfe7f | 1330 | spin_unlock_irqrestore(&atchan->lock, flags); |
808347f6 | 1331 | |
4facfe7f MR |
1332 | return 0; |
1333 | } | |
c3635c78 | 1334 | |
4facfe7f MR |
1335 | static int atc_terminate_all(struct dma_chan *chan) |
1336 | { | |
1337 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1338 | struct at_dma *atdma = to_at_dma(chan->device); | |
1339 | int chan_id = atchan->chan_common.chan_id; | |
1340 | struct at_desc *desc, *_desc; | |
1341 | unsigned long flags; | |
23b5e3ad | 1342 | |
4facfe7f | 1343 | LIST_HEAD(list); |
23b5e3ad | 1344 | |
4facfe7f | 1345 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
23b5e3ad | 1346 | |
4facfe7f MR |
1347 | /* |
1348 | * This is only called when something went wrong elsewhere, so | |
1349 | * we don't really care about the data. Just disable the | |
1350 | * channel. We still have to poll the channel enable bit due | |
1351 | * to AHB/HSB limitations. | |
1352 | */ | |
1353 | spin_lock_irqsave(&atchan->lock, flags); | |
23b5e3ad | 1354 | |
4facfe7f MR |
1355 | /* disabling channel: must also remove suspend state */ |
1356 | dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); | |
23b5e3ad | 1357 | |
4facfe7f MR |
1358 | /* confirm that this channel is disabled */ |
1359 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
1360 | cpu_relax(); | |
23b5e3ad | 1361 | |
4facfe7f MR |
1362 | /* active_list entries will end up before queued entries */ |
1363 | list_splice_init(&atchan->queue, &list); | |
1364 | list_splice_init(&atchan->active_list, &list); | |
1365 | ||
1366 | /* Flush all pending and queued descriptors */ | |
1367 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1368 | atc_chain_complete(atchan, desc); | |
1369 | ||
1370 | clear_bit(ATC_IS_PAUSED, &atchan->status); | |
1371 | /* if channel dedicated to cyclic operations, free it */ | |
1372 | clear_bit(ATC_IS_CYCLIC, &atchan->status); | |
1373 | ||
1374 | spin_unlock_irqrestore(&atchan->lock, flags); | |
b0ebeb9c | 1375 | |
c3635c78 | 1376 | return 0; |
808347f6 NF |
1377 | } |
1378 | ||
dc78baa2 | 1379 | /** |
07934481 | 1380 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
1381 | * @chan: DMA channel |
1382 | * @cookie: transaction identifier to check status of | |
07934481 | 1383 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 1384 | * |
07934481 | 1385 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
1386 | * internal state and can be used with dma_async_is_complete() to check |
1387 | * the status of multiple cookies without re-checking hardware state. | |
1388 | */ | |
1389 | static enum dma_status | |
07934481 | 1390 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 1391 | dma_cookie_t cookie, |
07934481 | 1392 | struct dma_tx_state *txstate) |
dc78baa2 NF |
1393 | { |
1394 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1395 | unsigned long flags; |
dc78baa2 | 1396 | enum dma_status ret; |
d48de6f1 | 1397 | int bytes = 0; |
dc78baa2 | 1398 | |
96a2af41 | 1399 | ret = dma_cookie_status(chan, cookie, txstate); |
6d203d1e | 1400 | if (ret == DMA_COMPLETE) |
d48de6f1 ES |
1401 | return ret; |
1402 | /* | |
1403 | * There's no point calculating the residue if there's | |
1404 | * no txstate to store the value. | |
1405 | */ | |
1406 | if (!txstate) | |
1407 | return DMA_ERROR; | |
dc78baa2 | 1408 | |
d48de6f1 | 1409 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 | 1410 | |
d48de6f1 | 1411 | /* Get number of bytes left in the active transactions */ |
bdf6c792 | 1412 | bytes = atc_get_bytes_left(chan, cookie); |
96a2af41 | 1413 | |
d8cb04b0 | 1414 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 | 1415 | |
d48de6f1 ES |
1416 | if (unlikely(bytes < 0)) { |
1417 | dev_vdbg(chan2dev(chan), "get residual bytes error\n"); | |
1418 | return DMA_ERROR; | |
c3dbc60c | 1419 | } else { |
d48de6f1 | 1420 | dma_set_residue(txstate, bytes); |
c3dbc60c | 1421 | } |
23b5e3ad | 1422 | |
d48de6f1 ES |
1423 | dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n", |
1424 | ret, cookie, bytes); | |
dc78baa2 NF |
1425 | |
1426 | return ret; | |
1427 | } | |
1428 | ||
1429 | /** | |
1430 | * atc_issue_pending - try to finish work | |
1431 | * @chan: target DMA channel | |
1432 | */ | |
1433 | static void atc_issue_pending(struct dma_chan *chan) | |
1434 | { | |
1435 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
d8cb04b0 | 1436 | unsigned long flags; |
dc78baa2 NF |
1437 | |
1438 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
1439 | ||
53830cc7 | 1440 | /* Not needed for cyclic transfers */ |
3c477482 | 1441 | if (atc_chan_is_cyclic(atchan)) |
53830cc7 NF |
1442 | return; |
1443 | ||
d8cb04b0 | 1444 | spin_lock_irqsave(&atchan->lock, flags); |
d202f051 | 1445 | atc_advance_work(atchan); |
d8cb04b0 | 1446 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1447 | } |
1448 | ||
1449 | /** | |
1450 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
1451 | * @chan: allocate descriptor resources for this channel | |
1452 | * @client: current client requesting the channel be ready for requests | |
1453 | * | |
1454 | * return - the number of allocated descriptors | |
1455 | */ | |
1456 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
1457 | { | |
1458 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1459 | struct at_dma *atdma = to_at_dma(chan->device); | |
1460 | struct at_desc *desc; | |
808347f6 | 1461 | struct at_dma_slave *atslave; |
d8cb04b0 | 1462 | unsigned long flags; |
dc78baa2 | 1463 | int i; |
808347f6 | 1464 | u32 cfg; |
dc78baa2 NF |
1465 | LIST_HEAD(tmp_list); |
1466 | ||
1467 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
1468 | ||
1469 | /* ASSERT: channel is idle */ | |
1470 | if (atc_chan_is_enabled(atchan)) { | |
1471 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
1472 | return -EIO; | |
1473 | } | |
1474 | ||
808347f6 NF |
1475 | cfg = ATC_DEFAULT_CFG; |
1476 | ||
1477 | atslave = chan->private; | |
1478 | if (atslave) { | |
1479 | /* | |
1480 | * We need controller-specific data to set up slave | |
1481 | * transfers. | |
1482 | */ | |
1483 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
1484 | ||
ea7e7906 | 1485 | /* if cfg configuration specified take it instead of default */ |
808347f6 NF |
1486 | if (atslave->cfg) |
1487 | cfg = atslave->cfg; | |
1488 | } | |
1489 | ||
1490 | /* have we already been set up? | |
1491 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
1492 | if (!list_empty(&atchan->free_list)) |
1493 | return atchan->descs_allocated; | |
1494 | ||
1495 | /* Allocate initial pool of descriptors */ | |
1496 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1497 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
1498 | if (!desc) { | |
1499 | dev_err(atdma->dma_common.dev, | |
1500 | "Only %d initial descriptors\n", i); | |
1501 | break; | |
1502 | } | |
1503 | list_add_tail(&desc->desc_node, &tmp_list); | |
1504 | } | |
1505 | ||
d8cb04b0 | 1506 | spin_lock_irqsave(&atchan->lock, flags); |
dc78baa2 NF |
1507 | atchan->descs_allocated = i; |
1508 | list_splice(&tmp_list, &atchan->free_list); | |
d3ee98cd | 1509 | dma_cookie_init(chan); |
d8cb04b0 | 1510 | spin_unlock_irqrestore(&atchan->lock, flags); |
dc78baa2 NF |
1511 | |
1512 | /* channel parameters */ | |
808347f6 | 1513 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
1514 | |
1515 | dev_dbg(chan2dev(chan), | |
1516 | "alloc_chan_resources: allocated %d descriptors\n", | |
1517 | atchan->descs_allocated); | |
1518 | ||
1519 | return atchan->descs_allocated; | |
1520 | } | |
1521 | ||
1522 | /** | |
1523 | * atc_free_chan_resources - free all channel resources | |
1524 | * @chan: DMA channel | |
1525 | */ | |
1526 | static void atc_free_chan_resources(struct dma_chan *chan) | |
1527 | { | |
1528 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1529 | struct at_dma *atdma = to_at_dma(chan->device); | |
1530 | struct at_desc *desc, *_desc; | |
1531 | LIST_HEAD(list); | |
1532 | ||
1533 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
1534 | atchan->descs_allocated); | |
1535 | ||
1536 | /* ASSERT: channel is idle */ | |
1537 | BUG_ON(!list_empty(&atchan->active_list)); | |
1538 | BUG_ON(!list_empty(&atchan->queue)); | |
1539 | BUG_ON(atc_chan_is_enabled(atchan)); | |
1540 | ||
1541 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
1542 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
1543 | list_del(&desc->desc_node); | |
1544 | /* free link descriptor */ | |
1545 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
1546 | } | |
1547 | list_splice_init(&atchan->free_list, &list); | |
1548 | atchan->descs_allocated = 0; | |
53830cc7 | 1549 | atchan->status = 0; |
dc78baa2 NF |
1550 | |
1551 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
1552 | } | |
1553 | ||
bbe89c8e LD |
1554 | #ifdef CONFIG_OF |
1555 | static bool at_dma_filter(struct dma_chan *chan, void *slave) | |
1556 | { | |
1557 | struct at_dma_slave *atslave = slave; | |
1558 | ||
1559 | if (atslave->dma_dev == chan->device->dev) { | |
1560 | chan->private = atslave; | |
1561 | return true; | |
1562 | } else { | |
1563 | return false; | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1568 | struct of_dma *of_dma) | |
1569 | { | |
1570 | struct dma_chan *chan; | |
1571 | struct at_dma_chan *atchan; | |
1572 | struct at_dma_slave *atslave; | |
1573 | dma_cap_mask_t mask; | |
1574 | unsigned int per_id; | |
1575 | struct platform_device *dmac_pdev; | |
1576 | ||
1577 | if (dma_spec->args_count != 2) | |
1578 | return NULL; | |
1579 | ||
1580 | dmac_pdev = of_find_device_by_node(dma_spec->np); | |
1581 | ||
1582 | dma_cap_zero(mask); | |
1583 | dma_cap_set(DMA_SLAVE, mask); | |
1584 | ||
1585 | atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL); | |
1586 | if (!atslave) | |
1587 | return NULL; | |
62971b29 LD |
1588 | |
1589 | atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW; | |
bbe89c8e LD |
1590 | /* |
1591 | * We can fill both SRC_PER and DST_PER, one of these fields will be | |
1592 | * ignored depending on DMA transfer direction. | |
1593 | */ | |
62971b29 LD |
1594 | per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK; |
1595 | atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id) | |
6c22770f | 1596 | | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id); |
62971b29 LD |
1597 | /* |
1598 | * We have to translate the value we get from the device tree since | |
1599 | * the half FIFO configuration value had to be 0 to keep backward | |
1600 | * compatibility. | |
1601 | */ | |
1602 | switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) { | |
1603 | case AT91_DMA_CFG_FIFOCFG_ALAP: | |
1604 | atslave->cfg |= ATC_FIFOCFG_LARGESTBURST; | |
1605 | break; | |
1606 | case AT91_DMA_CFG_FIFOCFG_ASAP: | |
1607 | atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE; | |
1608 | break; | |
1609 | case AT91_DMA_CFG_FIFOCFG_HALF: | |
1610 | default: | |
1611 | atslave->cfg |= ATC_FIFOCFG_HALFFIFO; | |
1612 | } | |
bbe89c8e LD |
1613 | atslave->dma_dev = &dmac_pdev->dev; |
1614 | ||
1615 | chan = dma_request_channel(mask, at_dma_filter, atslave); | |
1616 | if (!chan) | |
1617 | return NULL; | |
1618 | ||
1619 | atchan = to_at_dma_chan(chan); | |
1620 | atchan->per_if = dma_spec->args[0] & 0xff; | |
1621 | atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff; | |
1622 | ||
1623 | return chan; | |
1624 | } | |
1625 | #else | |
1626 | static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, | |
1627 | struct of_dma *of_dma) | |
1628 | { | |
1629 | return NULL; | |
1630 | } | |
1631 | #endif | |
dc78baa2 NF |
1632 | |
1633 | /*-- Module Management -----------------------------------------------*/ | |
1634 | ||
02f88be9 NF |
1635 | /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ |
1636 | static struct at_dma_platform_data at91sam9rl_config = { | |
1637 | .nr_channels = 2, | |
1638 | }; | |
1639 | static struct at_dma_platform_data at91sam9g45_config = { | |
1640 | .nr_channels = 8, | |
1641 | }; | |
1642 | ||
c5115953 NF |
1643 | #if defined(CONFIG_OF) |
1644 | static const struct of_device_id atmel_dma_dt_ids[] = { | |
1645 | { | |
1646 | .compatible = "atmel,at91sam9rl-dma", | |
02f88be9 | 1647 | .data = &at91sam9rl_config, |
c5115953 NF |
1648 | }, { |
1649 | .compatible = "atmel,at91sam9g45-dma", | |
02f88be9 | 1650 | .data = &at91sam9g45_config, |
dcc81734 NF |
1651 | }, { |
1652 | /* sentinel */ | |
1653 | } | |
c5115953 NF |
1654 | }; |
1655 | ||
1656 | MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); | |
1657 | #endif | |
1658 | ||
0ab88a01 | 1659 | static const struct platform_device_id atdma_devtypes[] = { |
67348450 NF |
1660 | { |
1661 | .name = "at91sam9rl_dma", | |
02f88be9 | 1662 | .driver_data = (unsigned long) &at91sam9rl_config, |
67348450 NF |
1663 | }, { |
1664 | .name = "at91sam9g45_dma", | |
02f88be9 | 1665 | .driver_data = (unsigned long) &at91sam9g45_config, |
67348450 NF |
1666 | }, { |
1667 | /* sentinel */ | |
1668 | } | |
1669 | }; | |
1670 | ||
7fd63ccd | 1671 | static inline const struct at_dma_platform_data * __init at_dma_get_driver_data( |
02f88be9 | 1672 | struct platform_device *pdev) |
c5115953 NF |
1673 | { |
1674 | if (pdev->dev.of_node) { | |
1675 | const struct of_device_id *match; | |
1676 | match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); | |
1677 | if (match == NULL) | |
02f88be9 NF |
1678 | return NULL; |
1679 | return match->data; | |
c5115953 | 1680 | } |
02f88be9 NF |
1681 | return (struct at_dma_platform_data *) |
1682 | platform_get_device_id(pdev)->driver_data; | |
c5115953 NF |
1683 | } |
1684 | ||
dc78baa2 NF |
1685 | /** |
1686 | * at_dma_off - disable DMA controller | |
1687 | * @atdma: the Atmel HDAMC device | |
1688 | */ | |
1689 | static void at_dma_off(struct at_dma *atdma) | |
1690 | { | |
1691 | dma_writel(atdma, EN, 0); | |
1692 | ||
1693 | /* disable all interrupts */ | |
1694 | dma_writel(atdma, EBCIDR, -1L); | |
1695 | ||
1696 | /* confirm that all channels are disabled */ | |
1697 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
1698 | cpu_relax(); | |
1699 | } | |
1700 | ||
1701 | static int __init at_dma_probe(struct platform_device *pdev) | |
1702 | { | |
dc78baa2 NF |
1703 | struct resource *io; |
1704 | struct at_dma *atdma; | |
1705 | size_t size; | |
1706 | int irq; | |
1707 | int err; | |
1708 | int i; | |
7fd63ccd | 1709 | const struct at_dma_platform_data *plat_dat; |
67348450 | 1710 | |
02f88be9 NF |
1711 | /* setup platform data for each SoC */ |
1712 | dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); | |
265567fb | 1713 | dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask); |
5abecfa5 | 1714 | dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask); |
02f88be9 NF |
1715 | dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); |
1716 | dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); | |
265567fb | 1717 | dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask); |
67348450 NF |
1718 | |
1719 | /* get DMA parameters from controller type */ | |
02f88be9 NF |
1720 | plat_dat = at_dma_get_driver_data(pdev); |
1721 | if (!plat_dat) | |
1722 | return -ENODEV; | |
dc78baa2 NF |
1723 | |
1724 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1725 | if (!io) | |
1726 | return -EINVAL; | |
1727 | ||
1728 | irq = platform_get_irq(pdev, 0); | |
1729 | if (irq < 0) | |
1730 | return irq; | |
1731 | ||
1732 | size = sizeof(struct at_dma); | |
02f88be9 | 1733 | size += plat_dat->nr_channels * sizeof(struct at_dma_chan); |
dc78baa2 NF |
1734 | atdma = kzalloc(size, GFP_KERNEL); |
1735 | if (!atdma) | |
1736 | return -ENOMEM; | |
1737 | ||
67348450 | 1738 | /* discover transaction capabilities */ |
02f88be9 NF |
1739 | atdma->dma_common.cap_mask = plat_dat->cap_mask; |
1740 | atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; | |
dc78baa2 | 1741 | |
114df7d6 | 1742 | size = resource_size(io); |
dc78baa2 NF |
1743 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { |
1744 | err = -EBUSY; | |
1745 | goto err_kfree; | |
1746 | } | |
1747 | ||
1748 | atdma->regs = ioremap(io->start, size); | |
1749 | if (!atdma->regs) { | |
1750 | err = -ENOMEM; | |
1751 | goto err_release_r; | |
1752 | } | |
1753 | ||
1754 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1755 | if (IS_ERR(atdma->clk)) { | |
1756 | err = PTR_ERR(atdma->clk); | |
1757 | goto err_clk; | |
1758 | } | |
f784d9c9 BB |
1759 | err = clk_prepare_enable(atdma->clk); |
1760 | if (err) | |
1761 | goto err_clk_prepare; | |
dc78baa2 NF |
1762 | |
1763 | /* force dma off, just in case */ | |
1764 | at_dma_off(atdma); | |
1765 | ||
1766 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1767 | if (err) | |
1768 | goto err_irq; | |
1769 | ||
1770 | platform_set_drvdata(pdev, atdma); | |
1771 | ||
1772 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1773 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1774 | &pdev->dev, sizeof(struct at_desc), | |
1775 | 4 /* word alignment */, 0); | |
1776 | if (!atdma->dma_desc_pool) { | |
1777 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1778 | err = -ENOMEM; | |
1779 | goto err_pool_create; | |
1780 | } | |
1781 | ||
1782 | /* clear any pending interrupt */ | |
1783 | while (dma_readl(atdma, EBCISR)) | |
1784 | cpu_relax(); | |
1785 | ||
1786 | /* initialize channels related values */ | |
1787 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
02f88be9 | 1788 | for (i = 0; i < plat_dat->nr_channels; i++) { |
dc78baa2 NF |
1789 | struct at_dma_chan *atchan = &atdma->chan[i]; |
1790 | ||
bbe89c8e LD |
1791 | atchan->mem_if = AT_DMA_MEM_IF; |
1792 | atchan->per_if = AT_DMA_PER_IF; | |
dc78baa2 | 1793 | atchan->chan_common.device = &atdma->dma_common; |
d3ee98cd | 1794 | dma_cookie_init(&atchan->chan_common); |
dc78baa2 NF |
1795 | list_add_tail(&atchan->chan_common.device_node, |
1796 | &atdma->dma_common.channels); | |
1797 | ||
1798 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1799 | spin_lock_init(&atchan->lock); | |
1800 | atchan->mask = 1 << i; | |
1801 | ||
1802 | INIT_LIST_HEAD(&atchan->active_list); | |
1803 | INIT_LIST_HEAD(&atchan->queue); | |
1804 | INIT_LIST_HEAD(&atchan->free_list); | |
1805 | ||
1806 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1807 | (unsigned long)atchan); | |
bda3a47c | 1808 | atc_enable_chan_irq(atdma, i); |
dc78baa2 NF |
1809 | } |
1810 | ||
1811 | /* set base routines */ | |
1812 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1813 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1814 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1815 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1816 | atdma->dma_common.dev = &pdev->dev; | |
1817 | ||
1818 | /* set prep routines based on capability */ | |
5abecfa5 MR |
1819 | if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask)) |
1820 | atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved; | |
1821 | ||
dc78baa2 NF |
1822 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) |
1823 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1824 | ||
d7db8080 | 1825 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
808347f6 | 1826 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; |
d7db8080 NF |
1827 | /* controller can do slave DMA: can trigger cyclic transfers */ |
1828 | dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); | |
53830cc7 | 1829 | atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; |
4facfe7f MR |
1830 | atdma->dma_common.device_config = atc_config; |
1831 | atdma->dma_common.device_pause = atc_pause; | |
1832 | atdma->dma_common.device_resume = atc_resume; | |
1833 | atdma->dma_common.device_terminate_all = atc_terminate_all; | |
816070ed LD |
1834 | atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS; |
1835 | atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS; | |
1836 | atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1837 | atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
d7db8080 | 1838 | } |
808347f6 | 1839 | |
265567fb TF |
1840 | if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask)) |
1841 | atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg; | |
1842 | ||
dc78baa2 NF |
1843 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1844 | ||
265567fb | 1845 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n", |
dc78baa2 NF |
1846 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", |
1847 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
265567fb | 1848 | dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "", |
02f88be9 | 1849 | plat_dat->nr_channels); |
dc78baa2 NF |
1850 | |
1851 | dma_async_device_register(&atdma->dma_common); | |
1852 | ||
bbe89c8e LD |
1853 | /* |
1854 | * Do not return an error if the dmac node is not present in order to | |
1855 | * not break the existing way of requesting channel with | |
1856 | * dma_request_channel(). | |
1857 | */ | |
1858 | if (pdev->dev.of_node) { | |
1859 | err = of_dma_controller_register(pdev->dev.of_node, | |
1860 | at_dma_xlate, atdma); | |
1861 | if (err) { | |
1862 | dev_err(&pdev->dev, "could not register of_dma_controller\n"); | |
1863 | goto err_of_dma_controller_register; | |
1864 | } | |
1865 | } | |
1866 | ||
dc78baa2 NF |
1867 | return 0; |
1868 | ||
bbe89c8e LD |
1869 | err_of_dma_controller_register: |
1870 | dma_async_device_unregister(&atdma->dma_common); | |
1871 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 | 1872 | err_pool_create: |
dc78baa2 NF |
1873 | free_irq(platform_get_irq(pdev, 0), atdma); |
1874 | err_irq: | |
f784d9c9 BB |
1875 | clk_disable_unprepare(atdma->clk); |
1876 | err_clk_prepare: | |
dc78baa2 NF |
1877 | clk_put(atdma->clk); |
1878 | err_clk: | |
1879 | iounmap(atdma->regs); | |
1880 | atdma->regs = NULL; | |
1881 | err_release_r: | |
1882 | release_mem_region(io->start, size); | |
1883 | err_kfree: | |
1884 | kfree(atdma); | |
1885 | return err; | |
1886 | } | |
1887 | ||
1d1bbd30 | 1888 | static int at_dma_remove(struct platform_device *pdev) |
dc78baa2 NF |
1889 | { |
1890 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1891 | struct dma_chan *chan, *_chan; | |
1892 | struct resource *io; | |
1893 | ||
1894 | at_dma_off(atdma); | |
1895 | dma_async_device_unregister(&atdma->dma_common); | |
1896 | ||
1897 | dma_pool_destroy(atdma->dma_desc_pool); | |
dc78baa2 NF |
1898 | free_irq(platform_get_irq(pdev, 0), atdma); |
1899 | ||
1900 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1901 | device_node) { | |
1902 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1903 | ||
1904 | /* Disable interrupts */ | |
bda3a47c | 1905 | atc_disable_chan_irq(atdma, chan->chan_id); |
dc78baa2 NF |
1906 | |
1907 | tasklet_kill(&atchan->tasklet); | |
1908 | list_del(&chan->device_node); | |
1909 | } | |
1910 | ||
f784d9c9 | 1911 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1912 | clk_put(atdma->clk); |
1913 | ||
1914 | iounmap(atdma->regs); | |
1915 | atdma->regs = NULL; | |
1916 | ||
1917 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
114df7d6 | 1918 | release_mem_region(io->start, resource_size(io)); |
dc78baa2 NF |
1919 | |
1920 | kfree(atdma); | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | static void at_dma_shutdown(struct platform_device *pdev) | |
1926 | { | |
1927 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1928 | ||
1929 | at_dma_off(platform_get_drvdata(pdev)); | |
f784d9c9 | 1930 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1931 | } |
1932 | ||
c0ba5947 NF |
1933 | static int at_dma_prepare(struct device *dev) |
1934 | { | |
1935 | struct platform_device *pdev = to_platform_device(dev); | |
1936 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1937 | struct dma_chan *chan, *_chan; | |
1938 | ||
1939 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1940 | device_node) { | |
1941 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1942 | /* wait for transaction completion (except in cyclic case) */ | |
3c477482 | 1943 | if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1944 | return -EAGAIN; |
1945 | } | |
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | static void atc_suspend_cyclic(struct at_dma_chan *atchan) | |
1950 | { | |
1951 | struct dma_chan *chan = &atchan->chan_common; | |
1952 | ||
1953 | /* Channel should be paused by user | |
1954 | * do it anyway even if it is not done already */ | |
3c477482 | 1955 | if (!atc_chan_is_paused(atchan)) { |
c0ba5947 NF |
1956 | dev_warn(chan2dev(chan), |
1957 | "cyclic channel not paused, should be done by channel user\n"); | |
4facfe7f | 1958 | atc_pause(chan); |
c0ba5947 NF |
1959 | } |
1960 | ||
1961 | /* now preserve additional data for cyclic operations */ | |
1962 | /* next descriptor address in the cyclic list */ | |
1963 | atchan->save_dscr = channel_readl(atchan, DSCR); | |
1964 | ||
1965 | vdbg_dump_regs(atchan); | |
1966 | } | |
1967 | ||
33f82d14 | 1968 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1969 | { |
33f82d14 DW |
1970 | struct platform_device *pdev = to_platform_device(dev); |
1971 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 1972 | struct dma_chan *chan, *_chan; |
dc78baa2 | 1973 | |
c0ba5947 NF |
1974 | /* preserve data */ |
1975 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1976 | device_node) { | |
1977 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1978 | ||
3c477482 | 1979 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
1980 | atc_suspend_cyclic(atchan); |
1981 | atchan->save_cfg = channel_readl(atchan, CFG); | |
1982 | } | |
1983 | atdma->save_imr = dma_readl(atdma, EBCIMR); | |
1984 | ||
1985 | /* disable DMA controller */ | |
1986 | at_dma_off(atdma); | |
f784d9c9 | 1987 | clk_disable_unprepare(atdma->clk); |
dc78baa2 NF |
1988 | return 0; |
1989 | } | |
1990 | ||
c0ba5947 NF |
1991 | static void atc_resume_cyclic(struct at_dma_chan *atchan) |
1992 | { | |
1993 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
1994 | ||
1995 | /* restore channel status for cyclic descriptors list: | |
1996 | * next descriptor in the cyclic list at the time of suspend */ | |
1997 | channel_writel(atchan, SADDR, 0); | |
1998 | channel_writel(atchan, DADDR, 0); | |
1999 | channel_writel(atchan, CTRLA, 0); | |
2000 | channel_writel(atchan, CTRLB, 0); | |
2001 | channel_writel(atchan, DSCR, atchan->save_dscr); | |
2002 | dma_writel(atdma, CHER, atchan->mask); | |
2003 | ||
2004 | /* channel pause status should be removed by channel user | |
2005 | * We cannot take the initiative to do it here */ | |
2006 | ||
2007 | vdbg_dump_regs(atchan); | |
2008 | } | |
2009 | ||
33f82d14 | 2010 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 2011 | { |
33f82d14 DW |
2012 | struct platform_device *pdev = to_platform_device(dev); |
2013 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
c0ba5947 | 2014 | struct dma_chan *chan, *_chan; |
dc78baa2 | 2015 | |
c0ba5947 | 2016 | /* bring back DMA controller */ |
f784d9c9 | 2017 | clk_prepare_enable(atdma->clk); |
dc78baa2 | 2018 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
c0ba5947 NF |
2019 | |
2020 | /* clear any pending interrupt */ | |
2021 | while (dma_readl(atdma, EBCISR)) | |
2022 | cpu_relax(); | |
2023 | ||
2024 | /* restore saved data */ | |
2025 | dma_writel(atdma, EBCIER, atdma->save_imr); | |
2026 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
2027 | device_node) { | |
2028 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
2029 | ||
2030 | channel_writel(atchan, CFG, atchan->save_cfg); | |
3c477482 | 2031 | if (atc_chan_is_cyclic(atchan)) |
c0ba5947 NF |
2032 | atc_resume_cyclic(atchan); |
2033 | } | |
dc78baa2 | 2034 | return 0; |
dc78baa2 NF |
2035 | } |
2036 | ||
47145210 | 2037 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
c0ba5947 | 2038 | .prepare = at_dma_prepare, |
33f82d14 DW |
2039 | .suspend_noirq = at_dma_suspend_noirq, |
2040 | .resume_noirq = at_dma_resume_noirq, | |
2041 | }; | |
2042 | ||
dc78baa2 | 2043 | static struct platform_driver at_dma_driver = { |
1d1bbd30 | 2044 | .remove = at_dma_remove, |
dc78baa2 | 2045 | .shutdown = at_dma_shutdown, |
67348450 | 2046 | .id_table = atdma_devtypes, |
dc78baa2 NF |
2047 | .driver = { |
2048 | .name = "at_hdmac", | |
33f82d14 | 2049 | .pm = &at_dma_dev_pm_ops, |
c5115953 | 2050 | .of_match_table = of_match_ptr(atmel_dma_dt_ids), |
dc78baa2 NF |
2051 | }, |
2052 | }; | |
2053 | ||
2054 | static int __init at_dma_init(void) | |
2055 | { | |
2056 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
2057 | } | |
93d0bec2 | 2058 | subsys_initcall(at_dma_init); |
dc78baa2 NF |
2059 | |
2060 | static void __exit at_dma_exit(void) | |
2061 | { | |
2062 | platform_driver_unregister(&at_dma_driver); | |
2063 | } | |
2064 | module_exit(at_dma_exit); | |
2065 | ||
2066 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
2067 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
2068 | MODULE_LICENSE("GPL"); | |
2069 | MODULE_ALIAS("platform:at_hdmac"); |