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Commit | Line | Data |
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96286b57 FM |
1 | /* |
2 | * BCM2835 DMA engine support | |
3 | * | |
4 | * This driver only supports cyclic DMA transfers | |
5 | * as needed for the I2S module. | |
6 | * | |
7 | * Author: Florian Meier <florian.meier@koalo.de> | |
8 | * Copyright 2013 | |
9 | * | |
10 | * Based on | |
11 | * OMAP DMAengine support by Russell King | |
12 | * | |
13 | * BCM2708 DMA Driver | |
14 | * Copyright (C) 2010 Broadcom | |
15 | * | |
16 | * Raspberry Pi PCM I2S ALSA Driver | |
17 | * Copyright (c) by Phil Poole 2013 | |
18 | * | |
19 | * MARVELL MMP Peripheral DMA Driver | |
20 | * Copyright 2012 Marvell International Ltd. | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or modify | |
23 | * it under the terms of the GNU General Public License as published by | |
24 | * the Free Software Foundation; either version 2 of the License, or | |
25 | * (at your option) any later version. | |
26 | * | |
27 | * This program is distributed in the hope that it will be useful, | |
28 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
29 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 | * GNU General Public License for more details. | |
31 | */ | |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/dma-mapping.h> | |
27bc944c | 34 | #include <linux/dmapool.h> |
96286b57 FM |
35 | #include <linux/err.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/list.h> | |
39 | #include <linux/module.h> | |
6166a91c | 40 | #include <linux/platform_data/dma-bcm2708.h> |
96286b57 FM |
41 | #include <linux/platform_device.h> |
42 | #include <linux/slab.h> | |
43 | #include <linux/io.h> | |
44 | #include <linux/spinlock.h> | |
45 | #include <linux/of.h> | |
46 | #include <linux/of_dma.h> | |
47 | ||
48 | #include "virt-dma.h" | |
49 | ||
e2eca638 MS |
50 | #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 |
51 | #define BCM2835_DMA_CHAN_NAME_SIZE 8 | |
6166a91c | 52 | #define BCM2835_DMA_BULK_MASK BIT(0) |
e2eca638 | 53 | |
96286b57 FM |
54 | struct bcm2835_dmadev { |
55 | struct dma_device ddev; | |
56 | spinlock_t lock; | |
57 | void __iomem *base; | |
58 | struct device_dma_parameters dma_parms; | |
59 | }; | |
60 | ||
61 | struct bcm2835_dma_cb { | |
62 | uint32_t info; | |
63 | uint32_t src; | |
64 | uint32_t dst; | |
65 | uint32_t length; | |
66 | uint32_t stride; | |
67 | uint32_t next; | |
68 | uint32_t pad[2]; | |
69 | }; | |
70 | ||
27bc944c PU |
71 | struct bcm2835_cb_entry { |
72 | struct bcm2835_dma_cb *cb; | |
73 | dma_addr_t paddr; | |
74 | }; | |
75 | ||
96286b57 FM |
76 | struct bcm2835_chan { |
77 | struct virt_dma_chan vc; | |
78 | struct list_head node; | |
79 | ||
80 | struct dma_slave_config cfg; | |
96286b57 FM |
81 | unsigned int dreq; |
82 | ||
83 | int ch; | |
84 | struct bcm2835_desc *desc; | |
27bc944c | 85 | struct dma_pool *cb_pool; |
96286b57 FM |
86 | |
87 | void __iomem *chan_base; | |
88 | int irq_number; | |
e2eca638 | 89 | unsigned int irq_flags; |
40874122 MS |
90 | |
91 | bool is_lite_channel; | |
96286b57 FM |
92 | }; |
93 | ||
94 | struct bcm2835_desc { | |
27bc944c | 95 | struct bcm2835_chan *c; |
96286b57 FM |
96 | struct virt_dma_desc vd; |
97 | enum dma_transfer_direction dir; | |
98 | ||
96286b57 FM |
99 | unsigned int frames; |
100 | size_t size; | |
a4dcdd84 MS |
101 | |
102 | bool cyclic; | |
92153bb5 MS |
103 | |
104 | struct bcm2835_cb_entry cb_list[]; | |
96286b57 FM |
105 | }; |
106 | ||
107 | #define BCM2835_DMA_CS 0x00 | |
108 | #define BCM2835_DMA_ADDR 0x04 | |
e42685d7 | 109 | #define BCM2835_DMA_TI 0x08 |
96286b57 FM |
110 | #define BCM2835_DMA_SOURCE_AD 0x0c |
111 | #define BCM2835_DMA_DEST_AD 0x10 | |
e42685d7 MS |
112 | #define BCM2835_DMA_LEN 0x14 |
113 | #define BCM2835_DMA_STRIDE 0x18 | |
114 | #define BCM2835_DMA_NEXTCB 0x1c | |
115 | #define BCM2835_DMA_DEBUG 0x20 | |
96286b57 FM |
116 | |
117 | /* DMA CS Control and Status bits */ | |
e42685d7 MS |
118 | #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */ |
119 | #define BCM2835_DMA_END BIT(1) /* current CB has ended */ | |
120 | #define BCM2835_DMA_INT BIT(2) /* interrupt status */ | |
121 | #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */ | |
96286b57 FM |
122 | #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ |
123 | #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ | |
e42685d7 MS |
124 | #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last |
125 | * AXI-write to ack | |
126 | */ | |
127 | #define BCM2835_DMA_ERR BIT(8) | |
128 | #define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */ | |
129 | #define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */ | |
130 | /* current value of TI.BCM2835_DMA_WAIT_RESP */ | |
131 | #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28) | |
132 | #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */ | |
96286b57 FM |
133 | #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ |
134 | #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ | |
135 | ||
e42685d7 | 136 | /* Transfer information bits - also bcm2835_cb.info field */ |
96286b57 | 137 | #define BCM2835_DMA_INT_EN BIT(0) |
e42685d7 MS |
138 | #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */ |
139 | #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */ | |
96286b57 | 140 | #define BCM2835_DMA_D_INC BIT(4) |
e42685d7 MS |
141 | #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */ |
142 | #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */ | |
143 | #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */ | |
96286b57 | 144 | #define BCM2835_DMA_S_INC BIT(8) |
e42685d7 MS |
145 | #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ |
146 | #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ | |
147 | #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ | |
148 | #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) | |
149 | #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */ | |
150 | #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */ | |
151 | #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ | |
152 | ||
153 | /* debug register bits */ | |
154 | #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) | |
155 | #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) | |
156 | #define BCM2835_DMA_DEBUG_READ_ERR BIT(2) | |
157 | #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4 | |
158 | #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4 | |
159 | #define BCM2835_DMA_DEBUG_ID_SHIFT 16 | |
160 | #define BCM2835_DMA_DEBUG_ID_BITS 9 | |
161 | #define BCM2835_DMA_DEBUG_STATE_SHIFT 16 | |
162 | #define BCM2835_DMA_DEBUG_STATE_BITS 9 | |
163 | #define BCM2835_DMA_DEBUG_VERSION_SHIFT 25 | |
164 | #define BCM2835_DMA_DEBUG_VERSION_BITS 3 | |
165 | #define BCM2835_DMA_DEBUG_LITE BIT(28) | |
166 | ||
167 | /* shared registers for all dma channels */ | |
168 | #define BCM2835_DMA_INT_STATUS 0xfe0 | |
169 | #define BCM2835_DMA_ENABLE 0xff0 | |
96286b57 FM |
170 | |
171 | #define BCM2835_DMA_DATA_TYPE_S8 1 | |
172 | #define BCM2835_DMA_DATA_TYPE_S16 2 | |
173 | #define BCM2835_DMA_DATA_TYPE_S32 4 | |
174 | #define BCM2835_DMA_DATA_TYPE_S128 16 | |
175 | ||
96286b57 FM |
176 | /* Valid only for channels 0 - 14, 15 has its own base address */ |
177 | #define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ | |
178 | #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) | |
179 | ||
40874122 MS |
180 | /* the max dma length for different channels */ |
181 | #define MAX_DMA_LEN SZ_1G | |
182 | #define MAX_LITE_DMA_LEN (SZ_64K - 4) | |
183 | ||
184 | static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) | |
185 | { | |
186 | /* lite and normal channels have different max frame length */ | |
187 | return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN; | |
188 | } | |
189 | ||
92153bb5 MS |
190 | /* how many frames of max_len size do we need to transfer len bytes */ |
191 | static inline size_t bcm2835_dma_frames_for_length(size_t len, | |
192 | size_t max_len) | |
193 | { | |
194 | return DIV_ROUND_UP(len, max_len); | |
195 | } | |
196 | ||
96286b57 FM |
197 | static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) |
198 | { | |
199 | return container_of(d, struct bcm2835_dmadev, ddev); | |
200 | } | |
201 | ||
202 | static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) | |
203 | { | |
204 | return container_of(c, struct bcm2835_chan, vc.chan); | |
205 | } | |
206 | ||
207 | static inline struct bcm2835_desc *to_bcm2835_dma_desc( | |
208 | struct dma_async_tx_descriptor *t) | |
209 | { | |
210 | return container_of(t, struct bcm2835_desc, vd.tx); | |
211 | } | |
212 | ||
92153bb5 | 213 | static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc) |
96286b57 | 214 | { |
92153bb5 | 215 | size_t i; |
27bc944c PU |
216 | |
217 | for (i = 0; i < desc->frames; i++) | |
218 | dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb, | |
219 | desc->cb_list[i].paddr); | |
220 | ||
96286b57 FM |
221 | kfree(desc); |
222 | } | |
223 | ||
92153bb5 MS |
224 | static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) |
225 | { | |
226 | bcm2835_dma_free_cb_chain( | |
227 | container_of(vd, struct bcm2835_desc, vd)); | |
228 | } | |
229 | ||
230 | static void bcm2835_dma_create_cb_set_length( | |
231 | struct bcm2835_chan *chan, | |
232 | struct bcm2835_dma_cb *control_block, | |
233 | size_t len, | |
234 | size_t period_len, | |
235 | size_t *total_len, | |
236 | u32 finalextrainfo) | |
237 | { | |
40874122 MS |
238 | size_t max_len = bcm2835_dma_max_frame_length(chan); |
239 | ||
240 | /* set the length taking lite-channel limitations into account */ | |
241 | control_block->length = min_t(u32, len, max_len); | |
92153bb5 MS |
242 | |
243 | /* finished if we have no period_length */ | |
244 | if (!period_len) | |
245 | return; | |
246 | ||
247 | /* | |
248 | * period_len means: that we need to generate | |
249 | * transfers that are terminating at every | |
250 | * multiple of period_len - this is typically | |
251 | * used to set the interrupt flag in info | |
252 | * which is required during cyclic transfers | |
253 | */ | |
254 | ||
255 | /* have we filled in period_length yet? */ | |
bc8c767f MR |
256 | if (*total_len + control_block->length < period_len) { |
257 | /* update number of bytes in this period so far */ | |
258 | *total_len += control_block->length; | |
92153bb5 | 259 | return; |
bc8c767f | 260 | } |
92153bb5 MS |
261 | |
262 | /* calculate the length that remains to reach period_length */ | |
263 | control_block->length = period_len - *total_len; | |
264 | ||
265 | /* reset total_length for next period */ | |
266 | *total_len = 0; | |
267 | ||
268 | /* add extrainfo bits in info */ | |
269 | control_block->info |= finalextrainfo; | |
270 | } | |
271 | ||
388cc7a2 MS |
272 | static inline size_t bcm2835_dma_count_frames_for_sg( |
273 | struct bcm2835_chan *c, | |
274 | struct scatterlist *sgl, | |
275 | unsigned int sg_len) | |
276 | { | |
277 | size_t frames = 0; | |
278 | struct scatterlist *sgent; | |
279 | unsigned int i; | |
280 | size_t plength = bcm2835_dma_max_frame_length(c); | |
281 | ||
282 | for_each_sg(sgl, sgent, sg_len, i) | |
283 | frames += bcm2835_dma_frames_for_length( | |
284 | sg_dma_len(sgent), plength); | |
285 | ||
286 | return frames; | |
287 | } | |
288 | ||
92153bb5 MS |
289 | /** |
290 | * bcm2835_dma_create_cb_chain - create a control block and fills data in | |
291 | * | |
292 | * @chan: the @dma_chan for which we run this | |
293 | * @direction: the direction in which we transfer | |
294 | * @cyclic: it is a cyclic transfer | |
295 | * @info: the default info bits to apply per controlblock | |
296 | * @frames: number of controlblocks to allocate | |
297 | * @src: the src address to assign (if the S_INC bit is set | |
298 | * in @info, then it gets incremented) | |
299 | * @dst: the dst address to assign (if the D_INC bit is set | |
300 | * in @info, then it gets incremented) | |
301 | * @buf_len: the full buffer length (may also be 0) | |
302 | * @period_len: the period length when to apply @finalextrainfo | |
303 | * in addition to the last transfer | |
304 | * this will also break some control-blocks early | |
305 | * @finalextrainfo: additional bits in last controlblock | |
306 | * (or when period_len is reached in case of cyclic) | |
307 | * @gfp: the GFP flag to use for allocation | |
308 | */ | |
309 | static struct bcm2835_desc *bcm2835_dma_create_cb_chain( | |
310 | struct dma_chan *chan, enum dma_transfer_direction direction, | |
311 | bool cyclic, u32 info, u32 finalextrainfo, size_t frames, | |
312 | dma_addr_t src, dma_addr_t dst, size_t buf_len, | |
313 | size_t period_len, gfp_t gfp) | |
314 | { | |
315 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
316 | size_t len = buf_len, total_len; | |
317 | size_t frame; | |
318 | struct bcm2835_desc *d; | |
319 | struct bcm2835_cb_entry *cb_entry; | |
320 | struct bcm2835_dma_cb *control_block; | |
321 | ||
d9f094a0 MS |
322 | if (!frames) |
323 | return NULL; | |
324 | ||
92153bb5 MS |
325 | /* allocate and setup the descriptor. */ |
326 | d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry), | |
327 | gfp); | |
328 | if (!d) | |
329 | return NULL; | |
330 | ||
331 | d->c = c; | |
332 | d->dir = direction; | |
333 | d->cyclic = cyclic; | |
334 | ||
335 | /* | |
336 | * Iterate over all frames, create a control block | |
337 | * for each frame and link them together. | |
338 | */ | |
339 | for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) { | |
340 | cb_entry = &d->cb_list[frame]; | |
341 | cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp, | |
342 | &cb_entry->paddr); | |
343 | if (!cb_entry->cb) | |
344 | goto error_cb; | |
345 | ||
346 | /* fill in the control block */ | |
347 | control_block = cb_entry->cb; | |
348 | control_block->info = info; | |
349 | control_block->src = src; | |
350 | control_block->dst = dst; | |
351 | control_block->stride = 0; | |
352 | control_block->next = 0; | |
353 | /* set up length in control_block if requested */ | |
354 | if (buf_len) { | |
355 | /* calculate length honoring period_length */ | |
356 | bcm2835_dma_create_cb_set_length( | |
357 | c, control_block, | |
358 | len, period_len, &total_len, | |
359 | cyclic ? finalextrainfo : 0); | |
360 | ||
361 | /* calculate new remaining length */ | |
362 | len -= control_block->length; | |
363 | } | |
364 | ||
365 | /* link this the last controlblock */ | |
366 | if (frame) | |
367 | d->cb_list[frame - 1].cb->next = cb_entry->paddr; | |
368 | ||
369 | /* update src and dst and length */ | |
370 | if (src && (info & BCM2835_DMA_S_INC)) | |
371 | src += control_block->length; | |
372 | if (dst && (info & BCM2835_DMA_D_INC)) | |
373 | dst += control_block->length; | |
374 | ||
375 | /* Length of total transfer */ | |
376 | d->size += control_block->length; | |
377 | } | |
378 | ||
379 | /* the last frame requires extra flags */ | |
380 | d->cb_list[d->frames - 1].cb->info |= finalextrainfo; | |
381 | ||
382 | /* detect a size missmatch */ | |
383 | if (buf_len && (d->size != buf_len)) | |
384 | goto error_cb; | |
385 | ||
386 | return d; | |
387 | error_cb: | |
388 | bcm2835_dma_free_cb_chain(d); | |
389 | ||
390 | return NULL; | |
391 | } | |
392 | ||
388cc7a2 MS |
393 | static void bcm2835_dma_fill_cb_chain_with_sg( |
394 | struct dma_chan *chan, | |
395 | enum dma_transfer_direction direction, | |
396 | struct bcm2835_cb_entry *cb, | |
397 | struct scatterlist *sgl, | |
398 | unsigned int sg_len) | |
399 | { | |
400 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
4aa819c7 AB |
401 | size_t len, max_len; |
402 | unsigned int i; | |
388cc7a2 MS |
403 | dma_addr_t addr; |
404 | struct scatterlist *sgent; | |
405 | ||
4aa819c7 | 406 | max_len = bcm2835_dma_max_frame_length(c); |
388cc7a2 MS |
407 | for_each_sg(sgl, sgent, sg_len, i) { |
408 | for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); | |
409 | len > 0; | |
410 | addr += cb->cb->length, len -= cb->cb->length, cb++) { | |
411 | if (direction == DMA_DEV_TO_MEM) | |
412 | cb->cb->dst = addr; | |
413 | else | |
414 | cb->cb->src = addr; | |
415 | cb->cb->length = min(len, max_len); | |
416 | } | |
417 | } | |
418 | } | |
419 | ||
96286b57 FM |
420 | static int bcm2835_dma_abort(void __iomem *chan_base) |
421 | { | |
422 | unsigned long cs; | |
423 | long int timeout = 10000; | |
424 | ||
425 | cs = readl(chan_base + BCM2835_DMA_CS); | |
426 | if (!(cs & BCM2835_DMA_ACTIVE)) | |
427 | return 0; | |
428 | ||
429 | /* Write 0 to the active bit - Pause the DMA */ | |
430 | writel(0, chan_base + BCM2835_DMA_CS); | |
431 | ||
432 | /* Wait for any current AXI transfer to complete */ | |
433 | while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { | |
434 | cpu_relax(); | |
435 | cs = readl(chan_base + BCM2835_DMA_CS); | |
436 | } | |
437 | ||
438 | /* We'll un-pause when we set of our next DMA */ | |
439 | if (!timeout) | |
440 | return -ETIMEDOUT; | |
441 | ||
442 | if (!(cs & BCM2835_DMA_ACTIVE)) | |
443 | return 0; | |
444 | ||
445 | /* Terminate the control block chain */ | |
446 | writel(0, chan_base + BCM2835_DMA_NEXTCB); | |
447 | ||
448 | /* Abort the whole DMA */ | |
449 | writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, | |
450 | chan_base + BCM2835_DMA_CS); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static void bcm2835_dma_start_desc(struct bcm2835_chan *c) | |
456 | { | |
457 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
458 | struct bcm2835_desc *d; | |
459 | ||
460 | if (!vd) { | |
461 | c->desc = NULL; | |
462 | return; | |
463 | } | |
464 | ||
465 | list_del(&vd->node); | |
466 | ||
467 | c->desc = d = to_bcm2835_dma_desc(&vd->tx); | |
468 | ||
27bc944c | 469 | writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); |
96286b57 FM |
470 | writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); |
471 | } | |
472 | ||
473 | static irqreturn_t bcm2835_dma_callback(int irq, void *data) | |
474 | { | |
475 | struct bcm2835_chan *c = data; | |
476 | struct bcm2835_desc *d; | |
477 | unsigned long flags; | |
478 | ||
e2eca638 MS |
479 | /* check the shared interrupt */ |
480 | if (c->irq_flags & IRQF_SHARED) { | |
481 | /* check if the interrupt is enabled */ | |
482 | flags = readl(c->chan_base + BCM2835_DMA_CS); | |
483 | /* if not set then we are not the reason for the irq */ | |
484 | if (!(flags & BCM2835_DMA_INT)) | |
485 | return IRQ_NONE; | |
486 | } | |
487 | ||
96286b57 FM |
488 | spin_lock_irqsave(&c->vc.lock, flags); |
489 | ||
490 | /* Acknowledge interrupt */ | |
491 | writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); | |
492 | ||
493 | d = c->desc; | |
494 | ||
495 | if (d) { | |
388cc7a2 MS |
496 | if (d->cyclic) { |
497 | /* call the cyclic callback */ | |
498 | vchan_cyclic_callback(&d->vd); | |
499 | ||
500 | /* Keep the DMA engine running */ | |
501 | writel(BCM2835_DMA_ACTIVE, | |
502 | c->chan_base + BCM2835_DMA_CS); | |
503 | } else { | |
504 | vchan_cookie_complete(&c->desc->vd); | |
505 | bcm2835_dma_start_desc(c); | |
506 | } | |
96286b57 FM |
507 | } |
508 | ||
96286b57 FM |
509 | spin_unlock_irqrestore(&c->vc.lock, flags); |
510 | ||
511 | return IRQ_HANDLED; | |
512 | } | |
513 | ||
514 | static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) | |
515 | { | |
516 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
27bc944c | 517 | struct device *dev = c->vc.chan.device->dev; |
96286b57 | 518 | |
27bc944c PU |
519 | dev_dbg(dev, "Allocating DMA channel %d\n", c->ch); |
520 | ||
521 | c->cb_pool = dma_pool_create(dev_name(dev), dev, | |
522 | sizeof(struct bcm2835_dma_cb), 0, 0); | |
523 | if (!c->cb_pool) { | |
524 | dev_err(dev, "unable to allocate descriptor pool\n"); | |
525 | return -ENOMEM; | |
526 | } | |
96286b57 | 527 | |
e2eca638 MS |
528 | return request_irq(c->irq_number, bcm2835_dma_callback, |
529 | c->irq_flags, "DMA IRQ", c); | |
96286b57 FM |
530 | } |
531 | ||
532 | static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) | |
533 | { | |
534 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
535 | ||
536 | vchan_free_chan_resources(&c->vc); | |
537 | free_irq(c->irq_number, c); | |
27bc944c | 538 | dma_pool_destroy(c->cb_pool); |
96286b57 FM |
539 | |
540 | dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); | |
541 | } | |
542 | ||
543 | static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) | |
544 | { | |
545 | return d->size; | |
546 | } | |
547 | ||
548 | static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) | |
549 | { | |
550 | unsigned int i; | |
551 | size_t size; | |
552 | ||
553 | for (size = i = 0; i < d->frames; i++) { | |
27bc944c | 554 | struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; |
96286b57 FM |
555 | size_t this_size = control_block->length; |
556 | dma_addr_t dma; | |
557 | ||
558 | if (d->dir == DMA_DEV_TO_MEM) | |
559 | dma = control_block->dst; | |
560 | else | |
561 | dma = control_block->src; | |
562 | ||
563 | if (size) | |
564 | size += this_size; | |
565 | else if (addr >= dma && addr < dma + this_size) | |
566 | size += dma + this_size - addr; | |
567 | } | |
568 | ||
569 | return size; | |
570 | } | |
571 | ||
572 | static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, | |
573 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
574 | { | |
575 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
576 | struct virt_dma_desc *vd; | |
577 | enum dma_status ret; | |
578 | unsigned long flags; | |
579 | ||
580 | ret = dma_cookie_status(chan, cookie, txstate); | |
581 | if (ret == DMA_COMPLETE || !txstate) | |
582 | return ret; | |
583 | ||
584 | spin_lock_irqsave(&c->vc.lock, flags); | |
585 | vd = vchan_find_desc(&c->vc, cookie); | |
586 | if (vd) { | |
587 | txstate->residue = | |
588 | bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); | |
589 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
590 | struct bcm2835_desc *d = c->desc; | |
591 | dma_addr_t pos; | |
592 | ||
593 | if (d->dir == DMA_MEM_TO_DEV) | |
594 | pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); | |
595 | else if (d->dir == DMA_DEV_TO_MEM) | |
596 | pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); | |
597 | else | |
598 | pos = 0; | |
599 | ||
600 | txstate->residue = bcm2835_dma_desc_size_pos(d, pos); | |
601 | } else { | |
602 | txstate->residue = 0; | |
603 | } | |
604 | ||
605 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
606 | ||
607 | return ret; | |
608 | } | |
609 | ||
610 | static void bcm2835_dma_issue_pending(struct dma_chan *chan) | |
611 | { | |
612 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
613 | unsigned long flags; | |
614 | ||
96286b57 FM |
615 | spin_lock_irqsave(&c->vc.lock, flags); |
616 | if (vchan_issue_pending(&c->vc) && !c->desc) | |
617 | bcm2835_dma_start_desc(c); | |
618 | ||
619 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
620 | } | |
621 | ||
63637228 | 622 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( |
d9f094a0 MS |
623 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
624 | size_t len, unsigned long flags) | |
625 | { | |
626 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
627 | struct bcm2835_desc *d; | |
628 | u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC; | |
629 | u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP; | |
630 | size_t max_len = bcm2835_dma_max_frame_length(c); | |
631 | size_t frames; | |
632 | ||
633 | /* if src, dst or len is not given return with an error */ | |
634 | if (!src || !dst || !len) | |
635 | return NULL; | |
636 | ||
637 | /* calculate number of frames */ | |
638 | frames = bcm2835_dma_frames_for_length(len, max_len); | |
639 | ||
640 | /* allocate the CB chain - this also fills in the pointers */ | |
641 | d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false, | |
642 | info, extra, frames, | |
643 | src, dst, len, 0, GFP_KERNEL); | |
644 | if (!d) | |
645 | return NULL; | |
646 | ||
647 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
648 | } | |
649 | ||
388cc7a2 MS |
650 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( |
651 | struct dma_chan *chan, | |
652 | struct scatterlist *sgl, unsigned int sg_len, | |
653 | enum dma_transfer_direction direction, | |
654 | unsigned long flags, void *context) | |
655 | { | |
656 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
657 | struct bcm2835_desc *d; | |
658 | dma_addr_t src = 0, dst = 0; | |
659 | u32 info = BCM2835_DMA_WAIT_RESP; | |
660 | u32 extra = BCM2835_DMA_INT_EN; | |
661 | size_t frames; | |
662 | ||
663 | if (!is_slave_direction(direction)) { | |
664 | dev_err(chan->device->dev, | |
665 | "%s: bad direction?\n", __func__); | |
666 | return NULL; | |
667 | } | |
668 | ||
669 | if (c->dreq != 0) | |
670 | info |= BCM2835_DMA_PER_MAP(c->dreq); | |
671 | ||
672 | if (direction == DMA_DEV_TO_MEM) { | |
673 | if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
674 | return NULL; | |
675 | src = c->cfg.src_addr; | |
676 | info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; | |
677 | } else { | |
678 | if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
679 | return NULL; | |
680 | dst = c->cfg.dst_addr; | |
681 | info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; | |
682 | } | |
683 | ||
684 | /* count frames in sg list */ | |
685 | frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len); | |
686 | ||
687 | /* allocate the CB chain */ | |
688 | d = bcm2835_dma_create_cb_chain(chan, direction, false, | |
689 | info, extra, | |
690 | frames, src, dst, 0, 0, | |
691 | GFP_KERNEL); | |
692 | if (!d) | |
693 | return NULL; | |
694 | ||
695 | /* fill in frames with scatterlist pointers */ | |
696 | bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list, | |
697 | sgl, sg_len); | |
698 | ||
699 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
700 | } | |
701 | ||
96286b57 FM |
702 | static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( |
703 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
704 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 705 | unsigned long flags) |
96286b57 FM |
706 | { |
707 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); | |
96286b57 | 708 | struct bcm2835_desc *d; |
92153bb5 MS |
709 | dma_addr_t src, dst; |
710 | u32 info = BCM2835_DMA_WAIT_RESP; | |
711 | u32 extra = BCM2835_DMA_INT_EN; | |
40874122 | 712 | size_t max_len = bcm2835_dma_max_frame_length(c); |
92153bb5 | 713 | size_t frames; |
96286b57 FM |
714 | |
715 | /* Grab configuration */ | |
716 | if (!is_slave_direction(direction)) { | |
717 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
718 | return NULL; | |
719 | } | |
720 | ||
92153bb5 MS |
721 | if (!buf_len) { |
722 | dev_err(chan->device->dev, | |
723 | "%s: bad buffer length (= 0)\n", __func__); | |
96286b57 FM |
724 | return NULL; |
725 | } | |
726 | ||
92153bb5 MS |
727 | /* |
728 | * warn if buf_len is not a multiple of period_len - this may leed | |
729 | * to unexpected latencies for interrupts and thus audiable clicks | |
730 | */ | |
731 | if (buf_len % period_len) | |
732 | dev_warn_once(chan->device->dev, | |
733 | "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n", | |
734 | __func__, buf_len, period_len); | |
96286b57 | 735 | |
92153bb5 MS |
736 | /* Setup DREQ channel */ |
737 | if (c->dreq != 0) | |
738 | info |= BCM2835_DMA_PER_MAP(c->dreq); | |
96286b57 | 739 | |
92153bb5 MS |
740 | if (direction == DMA_DEV_TO_MEM) { |
741 | if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
742 | return NULL; | |
743 | src = c->cfg.src_addr; | |
744 | dst = buf_addr; | |
745 | info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; | |
746 | } else { | |
747 | if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) | |
748 | return NULL; | |
749 | dst = c->cfg.dst_addr; | |
750 | src = buf_addr; | |
751 | info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; | |
96286b57 | 752 | } |
27bc944c | 753 | |
92153bb5 | 754 | /* calculate number of frames */ |
40874122 MS |
755 | frames = /* number of periods */ |
756 | DIV_ROUND_UP(buf_len, period_len) * | |
757 | /* number of frames per period */ | |
758 | bcm2835_dma_frames_for_length(period_len, max_len); | |
96286b57 FM |
759 | |
760 | /* | |
92153bb5 MS |
761 | * allocate the CB chain |
762 | * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine | |
763 | * implementation calls prep_dma_cyclic with interrupts disabled. | |
96286b57 | 764 | */ |
92153bb5 MS |
765 | d = bcm2835_dma_create_cb_chain(chan, direction, true, |
766 | info, extra, | |
767 | frames, src, dst, buf_len, | |
768 | period_len, GFP_NOWAIT); | |
769 | if (!d) | |
770 | return NULL; | |
96286b57 | 771 | |
92153bb5 MS |
772 | /* wrap around into a loop */ |
773 | d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr; | |
96286b57 FM |
774 | |
775 | return vchan_tx_prep(&c->vc, &d->vd, flags); | |
776 | } | |
777 | ||
39159bea MR |
778 | static int bcm2835_dma_slave_config(struct dma_chan *chan, |
779 | struct dma_slave_config *cfg) | |
96286b57 | 780 | { |
39159bea MR |
781 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); |
782 | ||
96286b57 FM |
783 | if ((cfg->direction == DMA_DEV_TO_MEM && |
784 | cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || | |
785 | (cfg->direction == DMA_MEM_TO_DEV && | |
786 | cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || | |
787 | !is_slave_direction(cfg->direction)) { | |
788 | return -EINVAL; | |
789 | } | |
790 | ||
791 | c->cfg = *cfg; | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
39159bea | 796 | static int bcm2835_dma_terminate_all(struct dma_chan *chan) |
96286b57 | 797 | { |
39159bea | 798 | struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); |
96286b57 FM |
799 | struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); |
800 | unsigned long flags; | |
801 | int timeout = 10000; | |
802 | LIST_HEAD(head); | |
803 | ||
804 | spin_lock_irqsave(&c->vc.lock, flags); | |
805 | ||
806 | /* Prevent this channel being scheduled */ | |
807 | spin_lock(&d->lock); | |
808 | list_del_init(&c->node); | |
809 | spin_unlock(&d->lock); | |
810 | ||
811 | /* | |
812 | * Stop DMA activity: we assume the callback will not be called | |
813 | * after bcm_dma_abort() returns (even if it does, it will see | |
814 | * c->desc is NULL and exit.) | |
815 | */ | |
816 | if (c->desc) { | |
f9317829 | 817 | bcm2835_dma_desc_free(&c->desc->vd); |
96286b57 FM |
818 | c->desc = NULL; |
819 | bcm2835_dma_abort(c->chan_base); | |
820 | ||
821 | /* Wait for stopping */ | |
822 | while (--timeout) { | |
823 | if (!(readl(c->chan_base + BCM2835_DMA_CS) & | |
824 | BCM2835_DMA_ACTIVE)) | |
825 | break; | |
826 | ||
827 | cpu_relax(); | |
828 | } | |
829 | ||
830 | if (!timeout) | |
831 | dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); | |
832 | } | |
833 | ||
834 | vchan_get_all_descriptors(&c->vc, &head); | |
835 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
836 | vchan_dma_desc_free_list(&c->vc, &head); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
e2eca638 MS |
841 | static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, |
842 | int irq, unsigned int irq_flags) | |
96286b57 FM |
843 | { |
844 | struct bcm2835_chan *c; | |
845 | ||
846 | c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); | |
847 | if (!c) | |
848 | return -ENOMEM; | |
849 | ||
850 | c->vc.desc_free = bcm2835_dma_desc_free; | |
851 | vchan_init(&c->vc, &d->ddev); | |
852 | INIT_LIST_HEAD(&c->node); | |
853 | ||
96286b57 FM |
854 | c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); |
855 | c->ch = chan_id; | |
856 | c->irq_number = irq; | |
e2eca638 | 857 | c->irq_flags = irq_flags; |
96286b57 | 858 | |
40874122 MS |
859 | /* check in DEBUG register if this is a LITE channel */ |
860 | if (readl(c->chan_base + BCM2835_DMA_DEBUG) & | |
861 | BCM2835_DMA_DEBUG_LITE) | |
862 | c->is_lite_channel = true; | |
863 | ||
96286b57 FM |
864 | return 0; |
865 | } | |
866 | ||
867 | static void bcm2835_dma_free(struct bcm2835_dmadev *od) | |
868 | { | |
869 | struct bcm2835_chan *c, *next; | |
870 | ||
871 | list_for_each_entry_safe(c, next, &od->ddev.channels, | |
872 | vc.chan.device_node) { | |
873 | list_del(&c->vc.chan.device_node); | |
874 | tasklet_kill(&c->vc.task); | |
875 | } | |
876 | } | |
877 | ||
878 | static const struct of_device_id bcm2835_dma_of_match[] = { | |
879 | { .compatible = "brcm,bcm2835-dma", }, | |
880 | {}, | |
881 | }; | |
882 | MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); | |
883 | ||
884 | static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, | |
885 | struct of_dma *ofdma) | |
886 | { | |
887 | struct bcm2835_dmadev *d = ofdma->of_dma_data; | |
888 | struct dma_chan *chan; | |
889 | ||
890 | chan = dma_get_any_slave_channel(&d->ddev); | |
891 | if (!chan) | |
892 | return NULL; | |
893 | ||
894 | /* Set DREQ from param */ | |
895 | to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; | |
896 | ||
897 | return chan; | |
898 | } | |
899 | ||
96286b57 FM |
900 | static int bcm2835_dma_probe(struct platform_device *pdev) |
901 | { | |
902 | struct bcm2835_dmadev *od; | |
903 | struct resource *res; | |
904 | void __iomem *base; | |
905 | int rc; | |
e2eca638 MS |
906 | int i, j; |
907 | int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1]; | |
908 | int irq_flags; | |
96286b57 | 909 | uint32_t chans_available; |
e2eca638 | 910 | char chan_name[BCM2835_DMA_CHAN_NAME_SIZE]; |
96286b57 FM |
911 | |
912 | if (!pdev->dev.dma_mask) | |
913 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
914 | ||
915 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
916 | if (rc) | |
917 | return rc; | |
918 | ||
919 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); | |
920 | if (!od) | |
921 | return -ENOMEM; | |
922 | ||
923 | pdev->dev.dma_parms = &od->dma_parms; | |
924 | dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); | |
925 | ||
926 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
927 | base = devm_ioremap_resource(&pdev->dev, res); | |
928 | if (IS_ERR(base)) | |
929 | return PTR_ERR(base); | |
6166a91c NT |
930 | rc = bcm_dmaman_probe(pdev, base, BCM2835_DMA_BULK_MASK); |
931 | if (rc) | |
932 | dev_err(&pdev->dev, "Failed to initialize the legacy API\n"); | |
96286b57 FM |
933 | |
934 | od->base = base; | |
935 | ||
936 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); | |
7f5ae355 | 937 | dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); |
96286b57 | 938 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
388cc7a2 | 939 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
d9f094a0 | 940 | dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); |
96286b57 FM |
941 | od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; |
942 | od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; | |
943 | od->ddev.device_tx_status = bcm2835_dma_tx_status; | |
944 | od->ddev.device_issue_pending = bcm2835_dma_issue_pending; | |
96286b57 | 945 | od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; |
388cc7a2 | 946 | od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; |
d9f094a0 | 947 | od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy; |
39159bea MR |
948 | od->ddev.device_config = bcm2835_dma_slave_config; |
949 | od->ddev.device_terminate_all = bcm2835_dma_terminate_all; | |
b5743680 MR |
950 | od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); |
951 | od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); | |
d9f094a0 MS |
952 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | |
953 | BIT(DMA_MEM_TO_MEM); | |
0fa5867e | 954 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
96286b57 FM |
955 | od->ddev.dev = &pdev->dev; |
956 | INIT_LIST_HEAD(&od->ddev.channels); | |
957 | spin_lock_init(&od->lock); | |
958 | ||
959 | platform_set_drvdata(pdev, od); | |
960 | ||
961 | /* Request DMA channel mask from device tree */ | |
962 | if (of_property_read_u32(pdev->dev.of_node, | |
963 | "brcm,dma-channel-mask", | |
964 | &chans_available)) { | |
965 | dev_err(&pdev->dev, "Failed to get channel mask\n"); | |
966 | rc = -EINVAL; | |
967 | goto err_no_dma; | |
968 | } | |
969 | ||
6166a91c NT |
970 | /* Channel 0 is used by the legacy API */ |
971 | chans_available &= ~BCM2835_DMA_BULK_MASK; | |
972 | ||
e2eca638 MS |
973 | /* get irqs for each channel that we support */ |
974 | for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { | |
975 | /* skip masked out channels */ | |
976 | if (!(chans_available & (1 << i))) { | |
977 | irq[i] = -1; | |
978 | continue; | |
96286b57 | 979 | } |
e2eca638 MS |
980 | |
981 | /* get the named irq */ | |
982 | snprintf(chan_name, sizeof(chan_name), "dma%i", i); | |
983 | irq[i] = platform_get_irq_byname(pdev, chan_name); | |
984 | if (irq[i] >= 0) | |
985 | continue; | |
986 | ||
987 | /* legacy device tree case handling */ | |
988 | dev_warn_once(&pdev->dev, | |
0eef727a | 989 | "missing interrupt-names property in device tree - legacy interpretation is used\n"); |
e2eca638 MS |
990 | /* |
991 | * in case of channel >= 11 | |
992 | * use the 11th interrupt and that is shared | |
993 | */ | |
994 | irq[i] = platform_get_irq(pdev, i < 11 ? i : 11); | |
995 | } | |
996 | ||
997 | /* get irqs for each channel */ | |
998 | for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { | |
999 | /* skip channels without irq */ | |
1000 | if (irq[i] < 0) | |
1001 | continue; | |
1002 | ||
1003 | /* check if there are other channels that also use this irq */ | |
1004 | irq_flags = 0; | |
1005 | for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++) | |
1006 | if ((i != j) && (irq[j] == irq[i])) { | |
1007 | irq_flags = IRQF_SHARED; | |
1008 | break; | |
1009 | } | |
1010 | ||
1011 | /* initialize the channel */ | |
1012 | rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags); | |
1013 | if (rc) | |
1014 | goto err_no_dma; | |
96286b57 FM |
1015 | } |
1016 | ||
1017 | dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); | |
1018 | ||
1019 | /* Device-tree DMA controller registration */ | |
1020 | rc = of_dma_controller_register(pdev->dev.of_node, | |
1021 | bcm2835_dma_xlate, od); | |
1022 | if (rc) { | |
1023 | dev_err(&pdev->dev, "Failed to register DMA controller\n"); | |
1024 | goto err_no_dma; | |
1025 | } | |
1026 | ||
1027 | rc = dma_async_device_register(&od->ddev); | |
1028 | if (rc) { | |
1029 | dev_err(&pdev->dev, | |
1030 | "Failed to register slave DMA engine device: %d\n", rc); | |
1031 | goto err_no_dma; | |
1032 | } | |
1033 | ||
1034 | dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); | |
1035 | ||
1036 | return 0; | |
1037 | ||
1038 | err_no_dma: | |
1039 | bcm2835_dma_free(od); | |
1040 | return rc; | |
1041 | } | |
1042 | ||
1043 | static int bcm2835_dma_remove(struct platform_device *pdev) | |
1044 | { | |
1045 | struct bcm2835_dmadev *od = platform_get_drvdata(pdev); | |
1046 | ||
6166a91c | 1047 | bcm_dmaman_remove(pdev); |
96286b57 FM |
1048 | dma_async_device_unregister(&od->ddev); |
1049 | bcm2835_dma_free(od); | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static struct platform_driver bcm2835_dma_driver = { | |
1055 | .probe = bcm2835_dma_probe, | |
1056 | .remove = bcm2835_dma_remove, | |
1057 | .driver = { | |
1058 | .name = "bcm2835-dma", | |
96286b57 FM |
1059 | .of_match_table = of_match_ptr(bcm2835_dma_of_match), |
1060 | }, | |
1061 | }; | |
1062 | ||
6166a91c NT |
1063 | static int bcm2835_dma_init(void) |
1064 | { | |
1065 | return platform_driver_register(&bcm2835_dma_driver); | |
1066 | } | |
1067 | ||
1068 | static void bcm2835_dma_exit(void) | |
1069 | { | |
1070 | platform_driver_unregister(&bcm2835_dma_driver); | |
1071 | } | |
1072 | ||
1073 | /* | |
1074 | * Load after serial driver (arch_initcall) so we see the messages if it fails, | |
1075 | * but before drivers (module_init) that need a DMA channel. | |
1076 | */ | |
1077 | subsys_initcall(bcm2835_dma_init); | |
1078 | module_exit(bcm2835_dma_exit); | |
96286b57 FM |
1079 | |
1080 | MODULE_ALIAS("platform:bcm2835-dma"); | |
1081 | MODULE_DESCRIPTION("BCM2835 DMA engine driver"); | |
1082 | MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>"); | |
1083 | MODULE_LICENSE("GPL v2"); |