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61f135b9 LW |
1 | /* |
2 | * driver/dma/coh901318.c | |
3 | * | |
4 | * Copyright (C) 2007-2009 ST-Ericsson | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * DMA driver for COH 901 318 | |
7 | * Author: Per Friden <per.friden@stericsson.com> | |
8 | */ | |
9 | ||
10 | #include <linux/init.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> /* printk() */ | |
13 | #include <linux/fs.h> /* everything... */ | |
b7f080cf | 14 | #include <linux/scatterlist.h> |
61f135b9 LW |
15 | #include <linux/slab.h> /* kmalloc() */ |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/irqreturn.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/uaccess.h> | |
23 | #include <linux/debugfs.h> | |
9f575d97 | 24 | #include <linux/platform_data/dma-coh901318.h> |
faadc6e3 | 25 | #include <linux/of_dma.h> |
61f135b9 | 26 | |
2b9277ad | 27 | #include "coh901318.h" |
d2ebfb33 | 28 | #include "dmaengine.h" |
61f135b9 | 29 | |
03b5357c LW |
30 | #define COH901318_MOD32_MASK (0x1F) |
31 | #define COH901318_WORD_MASK (0xFFFFFFFF) | |
32 | /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */ | |
33 | #define COH901318_INT_STATUS1 (0x0000) | |
34 | #define COH901318_INT_STATUS2 (0x0004) | |
35 | /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */ | |
36 | #define COH901318_TC_INT_STATUS1 (0x0008) | |
37 | #define COH901318_TC_INT_STATUS2 (0x000C) | |
38 | /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */ | |
39 | #define COH901318_TC_INT_CLEAR1 (0x0010) | |
40 | #define COH901318_TC_INT_CLEAR2 (0x0014) | |
41 | /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ | |
42 | #define COH901318_RAW_TC_INT_STATUS1 (0x0018) | |
43 | #define COH901318_RAW_TC_INT_STATUS2 (0x001C) | |
44 | /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */ | |
45 | #define COH901318_BE_INT_STATUS1 (0x0020) | |
46 | #define COH901318_BE_INT_STATUS2 (0x0024) | |
47 | /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */ | |
48 | #define COH901318_BE_INT_CLEAR1 (0x0028) | |
49 | #define COH901318_BE_INT_CLEAR2 (0x002C) | |
50 | /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ | |
51 | #define COH901318_RAW_BE_INT_STATUS1 (0x0030) | |
52 | #define COH901318_RAW_BE_INT_STATUS2 (0x0034) | |
53 | ||
54 | /* | |
55 | * CX_CFG - Channel Configuration Registers 32bit (R/W) | |
56 | */ | |
57 | #define COH901318_CX_CFG (0x0100) | |
58 | #define COH901318_CX_CFG_SPACING (0x04) | |
59 | /* Channel enable activates tha dma job */ | |
60 | #define COH901318_CX_CFG_CH_ENABLE (0x00000001) | |
61 | #define COH901318_CX_CFG_CH_DISABLE (0x00000000) | |
62 | /* Request Mode */ | |
63 | #define COH901318_CX_CFG_RM_MASK (0x00000006) | |
64 | #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1) | |
65 | #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1) | |
66 | #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1) | |
67 | #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1) | |
68 | #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1) | |
69 | /* Linked channel request field. RM must == 11 */ | |
70 | #define COH901318_CX_CFG_LCRF_SHIFT 3 | |
71 | #define COH901318_CX_CFG_LCRF_MASK (0x000001F8) | |
72 | #define COH901318_CX_CFG_LCR_DISABLE (0x00000000) | |
73 | /* Terminal Counter Interrupt Request Mask */ | |
74 | #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200) | |
75 | #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000) | |
76 | /* Bus Error interrupt Mask */ | |
77 | #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400) | |
78 | #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000) | |
79 | ||
80 | /* | |
81 | * CX_STAT - Channel Status Registers 32bit (R/-) | |
82 | */ | |
83 | #define COH901318_CX_STAT (0x0200) | |
84 | #define COH901318_CX_STAT_SPACING (0x04) | |
85 | #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008) | |
86 | #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004) | |
87 | #define COH901318_CX_STAT_ACTIVE (0x00000002) | |
88 | #define COH901318_CX_STAT_ENABLED (0x00000001) | |
89 | ||
90 | /* | |
91 | * CX_CTRL - Channel Control Registers 32bit (R/W) | |
92 | */ | |
93 | #define COH901318_CX_CTRL (0x0400) | |
94 | #define COH901318_CX_CTRL_SPACING (0x10) | |
95 | /* Transfer Count Enable */ | |
96 | #define COH901318_CX_CTRL_TC_ENABLE (0x00001000) | |
97 | #define COH901318_CX_CTRL_TC_DISABLE (0x00000000) | |
98 | /* Transfer Count Value 0 - 4095 */ | |
99 | #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF) | |
100 | /* Burst count */ | |
101 | #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000) | |
102 | #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13) | |
103 | #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13) | |
104 | #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13) | |
105 | #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13) | |
106 | #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13) | |
107 | #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13) | |
108 | #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13) | |
109 | #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13) | |
110 | /* Source bus size */ | |
111 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000) | |
112 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16) | |
113 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16) | |
114 | #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16) | |
115 | /* Source address increment */ | |
116 | #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000) | |
117 | #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000) | |
118 | /* Destination Bus Size */ | |
119 | #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000) | |
120 | #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19) | |
121 | #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19) | |
122 | #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19) | |
123 | /* Destination address increment */ | |
124 | #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000) | |
125 | #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000) | |
126 | /* Master Mode (Master2 is only connected to MSL) */ | |
127 | #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000) | |
128 | #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22) | |
129 | #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22) | |
130 | #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22) | |
131 | #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22) | |
132 | /* Terminal Count flag to PER enable */ | |
133 | #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000) | |
134 | #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000) | |
135 | /* Terminal Count flags to CPU enable */ | |
136 | #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000) | |
137 | #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000) | |
138 | /* Hand shake to peripheral */ | |
139 | #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000) | |
140 | #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000) | |
141 | #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000) | |
142 | #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000) | |
143 | /* DMA mode */ | |
144 | #define COH901318_CX_CTRL_DDMA_MASK (0x30000000) | |
145 | #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28) | |
146 | #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28) | |
147 | #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28) | |
148 | /* Primary Request Data Destination */ | |
149 | #define COH901318_CX_CTRL_PRDD_MASK (0x40000000) | |
150 | #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30) | |
151 | #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30) | |
152 | ||
153 | /* | |
154 | * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W) | |
155 | */ | |
156 | #define COH901318_CX_SRC_ADDR (0x0404) | |
157 | #define COH901318_CX_SRC_ADDR_SPACING (0x10) | |
158 | ||
159 | /* | |
160 | * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W | |
161 | */ | |
162 | #define COH901318_CX_DST_ADDR (0x0408) | |
163 | #define COH901318_CX_DST_ADDR_SPACING (0x10) | |
164 | ||
165 | /* | |
166 | * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W) | |
167 | */ | |
168 | #define COH901318_CX_LNK_ADDR (0x040C) | |
169 | #define COH901318_CX_LNK_ADDR_SPACING (0x10) | |
170 | #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001) | |
171 | ||
172 | /** | |
173 | * struct coh901318_params - parameters for DMAC configuration | |
174 | * @config: DMA config register | |
175 | * @ctrl_lli_last: DMA control register for the last lli in the list | |
176 | * @ctrl_lli: DMA control register for an lli | |
177 | * @ctrl_lli_chained: DMA control register for a chained lli | |
178 | */ | |
179 | struct coh901318_params { | |
180 | u32 config; | |
181 | u32 ctrl_lli_last; | |
182 | u32 ctrl_lli; | |
183 | u32 ctrl_lli_chained; | |
184 | }; | |
185 | ||
186 | /** | |
187 | * struct coh_dma_channel - dma channel base | |
188 | * @name: ascii name of dma channel | |
189 | * @number: channel id number | |
190 | * @desc_nbr_max: number of preallocated descriptors | |
191 | * @priority_high: prio of channel, 0 low otherwise high. | |
192 | * @param: configuration parameters | |
193 | */ | |
194 | struct coh_dma_channel { | |
195 | const char name[32]; | |
196 | const int number; | |
197 | const int desc_nbr_max; | |
198 | const int priority_high; | |
199 | const struct coh901318_params param; | |
200 | }; | |
201 | ||
03b5357c LW |
202 | /** |
203 | * struct powersave - DMA power save structure | |
204 | * @lock: lock protecting data in this struct | |
205 | * @started_channels: bit mask indicating active dma channels | |
206 | */ | |
207 | struct powersave { | |
208 | spinlock_t lock; | |
209 | u64 started_channels; | |
210 | }; | |
211 | ||
24dbcd8a LW |
212 | /* points out all dma slave channels. |
213 | * Syntax is [A1, B1, A2, B2, .... ,-1,-1] | |
214 | * Select all channels from A to B, end of list is marked with -1,-1 | |
215 | */ | |
216 | static int dma_slave_channels[] = { | |
217 | U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, | |
218 | U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1}; | |
219 | ||
220 | /* points out all dma memcpy channels. */ | |
221 | static int dma_memcpy_channels[] = { | |
222 | U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1}; | |
223 | ||
24dbcd8a LW |
224 | #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \ |
225 | COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \ | |
226 | COH901318_CX_CFG_LCR_DISABLE | \ | |
227 | COH901318_CX_CFG_TC_IRQ_ENABLE | \ | |
228 | COH901318_CX_CFG_BE_IRQ_ENABLE) | |
229 | #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \ | |
230 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
231 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
232 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
233 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
234 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
235 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
236 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
237 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | |
238 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
239 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
240 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
241 | COH901318_CX_CTRL_PRDD_SOURCE) | |
242 | #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \ | |
243 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
244 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
245 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
246 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
247 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
248 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
249 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
250 | COH901318_CX_CTRL_TC_IRQ_DISABLE | \ | |
251 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
252 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
253 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
254 | COH901318_CX_CTRL_PRDD_SOURCE) | |
255 | #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \ | |
256 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \ | |
257 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \ | |
258 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \ | |
259 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \ | |
260 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \ | |
261 | COH901318_CX_CTRL_MASTER_MODE_M1RW | \ | |
262 | COH901318_CX_CTRL_TCP_DISABLE | \ | |
263 | COH901318_CX_CTRL_TC_IRQ_ENABLE | \ | |
264 | COH901318_CX_CTRL_HSP_DISABLE | \ | |
265 | COH901318_CX_CTRL_HSS_DISABLE | \ | |
266 | COH901318_CX_CTRL_DDMA_LEGACY | \ | |
267 | COH901318_CX_CTRL_PRDD_SOURCE) | |
268 | ||
f57b7cb4 | 269 | static const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { |
24dbcd8a LW |
270 | { |
271 | .number = U300_DMA_MSL_TX_0, | |
272 | .name = "MSL TX 0", | |
273 | .priority_high = 0, | |
24dbcd8a LW |
274 | }, |
275 | { | |
276 | .number = U300_DMA_MSL_TX_1, | |
277 | .name = "MSL TX 1", | |
278 | .priority_high = 0, | |
24dbcd8a LW |
279 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
280 | COH901318_CX_CFG_LCR_DISABLE | | |
281 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
282 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
283 | .param.ctrl_lli_chained = 0 | | |
284 | COH901318_CX_CTRL_TC_ENABLE | | |
285 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
286 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
287 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
288 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
289 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
290 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
291 | COH901318_CX_CTRL_TCP_DISABLE | | |
292 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
293 | COH901318_CX_CTRL_HSP_ENABLE | | |
294 | COH901318_CX_CTRL_HSS_DISABLE | | |
295 | COH901318_CX_CTRL_DDMA_LEGACY | | |
296 | COH901318_CX_CTRL_PRDD_SOURCE, | |
297 | .param.ctrl_lli = 0 | | |
298 | COH901318_CX_CTRL_TC_ENABLE | | |
299 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
300 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
301 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
302 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
303 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
304 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
305 | COH901318_CX_CTRL_TCP_ENABLE | | |
306 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
307 | COH901318_CX_CTRL_HSP_ENABLE | | |
308 | COH901318_CX_CTRL_HSS_DISABLE | | |
309 | COH901318_CX_CTRL_DDMA_LEGACY | | |
310 | COH901318_CX_CTRL_PRDD_SOURCE, | |
311 | .param.ctrl_lli_last = 0 | | |
312 | COH901318_CX_CTRL_TC_ENABLE | | |
313 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
314 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
315 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
316 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
317 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
318 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
319 | COH901318_CX_CTRL_TCP_ENABLE | | |
320 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
321 | COH901318_CX_CTRL_HSP_ENABLE | | |
322 | COH901318_CX_CTRL_HSS_DISABLE | | |
323 | COH901318_CX_CTRL_DDMA_LEGACY | | |
324 | COH901318_CX_CTRL_PRDD_SOURCE, | |
325 | }, | |
326 | { | |
327 | .number = U300_DMA_MSL_TX_2, | |
328 | .name = "MSL TX 2", | |
329 | .priority_high = 0, | |
24dbcd8a LW |
330 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
331 | COH901318_CX_CFG_LCR_DISABLE | | |
332 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
333 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
334 | .param.ctrl_lli_chained = 0 | | |
335 | COH901318_CX_CTRL_TC_ENABLE | | |
336 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
337 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
338 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
339 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
340 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
341 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
342 | COH901318_CX_CTRL_TCP_DISABLE | | |
343 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
344 | COH901318_CX_CTRL_HSP_ENABLE | | |
345 | COH901318_CX_CTRL_HSS_DISABLE | | |
346 | COH901318_CX_CTRL_DDMA_LEGACY | | |
347 | COH901318_CX_CTRL_PRDD_SOURCE, | |
348 | .param.ctrl_lli = 0 | | |
349 | COH901318_CX_CTRL_TC_ENABLE | | |
350 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
351 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
352 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
353 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
354 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
355 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
356 | COH901318_CX_CTRL_TCP_ENABLE | | |
357 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
358 | COH901318_CX_CTRL_HSP_ENABLE | | |
359 | COH901318_CX_CTRL_HSS_DISABLE | | |
360 | COH901318_CX_CTRL_DDMA_LEGACY | | |
361 | COH901318_CX_CTRL_PRDD_SOURCE, | |
362 | .param.ctrl_lli_last = 0 | | |
363 | COH901318_CX_CTRL_TC_ENABLE | | |
364 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
365 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
366 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
367 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
368 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
369 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
370 | COH901318_CX_CTRL_TCP_ENABLE | | |
371 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
372 | COH901318_CX_CTRL_HSP_ENABLE | | |
373 | COH901318_CX_CTRL_HSS_DISABLE | | |
374 | COH901318_CX_CTRL_DDMA_LEGACY | | |
375 | COH901318_CX_CTRL_PRDD_SOURCE, | |
376 | .desc_nbr_max = 10, | |
377 | }, | |
378 | { | |
379 | .number = U300_DMA_MSL_TX_3, | |
380 | .name = "MSL TX 3", | |
381 | .priority_high = 0, | |
24dbcd8a LW |
382 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
383 | COH901318_CX_CFG_LCR_DISABLE | | |
384 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
385 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
386 | .param.ctrl_lli_chained = 0 | | |
387 | COH901318_CX_CTRL_TC_ENABLE | | |
388 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
389 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
390 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
391 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
392 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
393 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
394 | COH901318_CX_CTRL_TCP_DISABLE | | |
395 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
396 | COH901318_CX_CTRL_HSP_ENABLE | | |
397 | COH901318_CX_CTRL_HSS_DISABLE | | |
398 | COH901318_CX_CTRL_DDMA_LEGACY | | |
399 | COH901318_CX_CTRL_PRDD_SOURCE, | |
400 | .param.ctrl_lli = 0 | | |
401 | COH901318_CX_CTRL_TC_ENABLE | | |
402 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
403 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
404 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
405 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
406 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
407 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
408 | COH901318_CX_CTRL_TCP_ENABLE | | |
409 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
410 | COH901318_CX_CTRL_HSP_ENABLE | | |
411 | COH901318_CX_CTRL_HSS_DISABLE | | |
412 | COH901318_CX_CTRL_DDMA_LEGACY | | |
413 | COH901318_CX_CTRL_PRDD_SOURCE, | |
414 | .param.ctrl_lli_last = 0 | | |
415 | COH901318_CX_CTRL_TC_ENABLE | | |
416 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
417 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
418 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
419 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
420 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
421 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
422 | COH901318_CX_CTRL_TCP_ENABLE | | |
423 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
424 | COH901318_CX_CTRL_HSP_ENABLE | | |
425 | COH901318_CX_CTRL_HSS_DISABLE | | |
426 | COH901318_CX_CTRL_DDMA_LEGACY | | |
427 | COH901318_CX_CTRL_PRDD_SOURCE, | |
428 | }, | |
429 | { | |
430 | .number = U300_DMA_MSL_TX_4, | |
431 | .name = "MSL TX 4", | |
432 | .priority_high = 0, | |
24dbcd8a LW |
433 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
434 | COH901318_CX_CFG_LCR_DISABLE | | |
435 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
436 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
437 | .param.ctrl_lli_chained = 0 | | |
438 | COH901318_CX_CTRL_TC_ENABLE | | |
439 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
440 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
441 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
442 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
443 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
444 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
445 | COH901318_CX_CTRL_TCP_DISABLE | | |
446 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
447 | COH901318_CX_CTRL_HSP_ENABLE | | |
448 | COH901318_CX_CTRL_HSS_DISABLE | | |
449 | COH901318_CX_CTRL_DDMA_LEGACY | | |
450 | COH901318_CX_CTRL_PRDD_SOURCE, | |
451 | .param.ctrl_lli = 0 | | |
452 | COH901318_CX_CTRL_TC_ENABLE | | |
453 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
454 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
455 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
456 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
457 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
458 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
459 | COH901318_CX_CTRL_TCP_ENABLE | | |
460 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
461 | COH901318_CX_CTRL_HSP_ENABLE | | |
462 | COH901318_CX_CTRL_HSS_DISABLE | | |
463 | COH901318_CX_CTRL_DDMA_LEGACY | | |
464 | COH901318_CX_CTRL_PRDD_SOURCE, | |
465 | .param.ctrl_lli_last = 0 | | |
466 | COH901318_CX_CTRL_TC_ENABLE | | |
467 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
468 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
469 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
470 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
471 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
472 | COH901318_CX_CTRL_MASTER_MODE_M1R_M2W | | |
473 | COH901318_CX_CTRL_TCP_ENABLE | | |
474 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
475 | COH901318_CX_CTRL_HSP_ENABLE | | |
476 | COH901318_CX_CTRL_HSS_DISABLE | | |
477 | COH901318_CX_CTRL_DDMA_LEGACY | | |
478 | COH901318_CX_CTRL_PRDD_SOURCE, | |
479 | }, | |
480 | { | |
481 | .number = U300_DMA_MSL_TX_5, | |
482 | .name = "MSL TX 5", | |
483 | .priority_high = 0, | |
24dbcd8a LW |
484 | }, |
485 | { | |
486 | .number = U300_DMA_MSL_TX_6, | |
487 | .name = "MSL TX 6", | |
488 | .priority_high = 0, | |
24dbcd8a LW |
489 | }, |
490 | { | |
491 | .number = U300_DMA_MSL_RX_0, | |
492 | .name = "MSL RX 0", | |
493 | .priority_high = 0, | |
24dbcd8a LW |
494 | }, |
495 | { | |
496 | .number = U300_DMA_MSL_RX_1, | |
497 | .name = "MSL RX 1", | |
498 | .priority_high = 0, | |
24dbcd8a LW |
499 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
500 | COH901318_CX_CFG_LCR_DISABLE | | |
501 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
502 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
503 | .param.ctrl_lli_chained = 0 | | |
504 | COH901318_CX_CTRL_TC_ENABLE | | |
505 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
506 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
507 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
508 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
509 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
510 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
511 | COH901318_CX_CTRL_TCP_DISABLE | | |
512 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
513 | COH901318_CX_CTRL_HSP_ENABLE | | |
514 | COH901318_CX_CTRL_HSS_DISABLE | | |
515 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
516 | COH901318_CX_CTRL_PRDD_DEST, | |
517 | .param.ctrl_lli = 0, | |
518 | .param.ctrl_lli_last = 0 | | |
519 | COH901318_CX_CTRL_TC_ENABLE | | |
520 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
521 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
522 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
523 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
524 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
525 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
526 | COH901318_CX_CTRL_TCP_DISABLE | | |
527 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
528 | COH901318_CX_CTRL_HSP_ENABLE | | |
529 | COH901318_CX_CTRL_HSS_DISABLE | | |
530 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
531 | COH901318_CX_CTRL_PRDD_DEST, | |
532 | }, | |
533 | { | |
534 | .number = U300_DMA_MSL_RX_2, | |
535 | .name = "MSL RX 2", | |
536 | .priority_high = 0, | |
24dbcd8a LW |
537 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
538 | COH901318_CX_CFG_LCR_DISABLE | | |
539 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
540 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
541 | .param.ctrl_lli_chained = 0 | | |
542 | COH901318_CX_CTRL_TC_ENABLE | | |
543 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
544 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
545 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
546 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
547 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
548 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
549 | COH901318_CX_CTRL_TCP_DISABLE | | |
550 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
551 | COH901318_CX_CTRL_HSP_ENABLE | | |
552 | COH901318_CX_CTRL_HSS_DISABLE | | |
553 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
554 | COH901318_CX_CTRL_PRDD_DEST, | |
555 | .param.ctrl_lli = 0 | | |
556 | COH901318_CX_CTRL_TC_ENABLE | | |
557 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
558 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
559 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
560 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
561 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
562 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
563 | COH901318_CX_CTRL_TCP_DISABLE | | |
564 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
565 | COH901318_CX_CTRL_HSP_ENABLE | | |
566 | COH901318_CX_CTRL_HSS_DISABLE | | |
567 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
568 | COH901318_CX_CTRL_PRDD_DEST, | |
569 | .param.ctrl_lli_last = 0 | | |
570 | COH901318_CX_CTRL_TC_ENABLE | | |
571 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
572 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
573 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
574 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
575 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
576 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
577 | COH901318_CX_CTRL_TCP_DISABLE | | |
578 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
579 | COH901318_CX_CTRL_HSP_ENABLE | | |
580 | COH901318_CX_CTRL_HSS_DISABLE | | |
581 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
582 | COH901318_CX_CTRL_PRDD_DEST, | |
583 | }, | |
584 | { | |
585 | .number = U300_DMA_MSL_RX_3, | |
586 | .name = "MSL RX 3", | |
587 | .priority_high = 0, | |
24dbcd8a LW |
588 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
589 | COH901318_CX_CFG_LCR_DISABLE | | |
590 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
591 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
592 | .param.ctrl_lli_chained = 0 | | |
593 | COH901318_CX_CTRL_TC_ENABLE | | |
594 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
595 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
596 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
597 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
598 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
599 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
600 | COH901318_CX_CTRL_TCP_DISABLE | | |
601 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
602 | COH901318_CX_CTRL_HSP_ENABLE | | |
603 | COH901318_CX_CTRL_HSS_DISABLE | | |
604 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
605 | COH901318_CX_CTRL_PRDD_DEST, | |
606 | .param.ctrl_lli = 0 | | |
607 | COH901318_CX_CTRL_TC_ENABLE | | |
608 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
609 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
610 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
611 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
612 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
613 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
614 | COH901318_CX_CTRL_TCP_DISABLE | | |
615 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
616 | COH901318_CX_CTRL_HSP_ENABLE | | |
617 | COH901318_CX_CTRL_HSS_DISABLE | | |
618 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
619 | COH901318_CX_CTRL_PRDD_DEST, | |
620 | .param.ctrl_lli_last = 0 | | |
621 | COH901318_CX_CTRL_TC_ENABLE | | |
622 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
623 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
624 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
625 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
626 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
627 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
628 | COH901318_CX_CTRL_TCP_DISABLE | | |
629 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
630 | COH901318_CX_CTRL_HSP_ENABLE | | |
631 | COH901318_CX_CTRL_HSS_DISABLE | | |
632 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
633 | COH901318_CX_CTRL_PRDD_DEST, | |
634 | }, | |
635 | { | |
636 | .number = U300_DMA_MSL_RX_4, | |
637 | .name = "MSL RX 4", | |
638 | .priority_high = 0, | |
24dbcd8a LW |
639 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
640 | COH901318_CX_CFG_LCR_DISABLE | | |
641 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
642 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
643 | .param.ctrl_lli_chained = 0 | | |
644 | COH901318_CX_CTRL_TC_ENABLE | | |
645 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
646 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
647 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
648 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
649 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
650 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
651 | COH901318_CX_CTRL_TCP_DISABLE | | |
652 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
653 | COH901318_CX_CTRL_HSP_ENABLE | | |
654 | COH901318_CX_CTRL_HSS_DISABLE | | |
655 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
656 | COH901318_CX_CTRL_PRDD_DEST, | |
657 | .param.ctrl_lli = 0 | | |
658 | COH901318_CX_CTRL_TC_ENABLE | | |
659 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
660 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
661 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
662 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
663 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
664 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
665 | COH901318_CX_CTRL_TCP_DISABLE | | |
666 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
667 | COH901318_CX_CTRL_HSP_ENABLE | | |
668 | COH901318_CX_CTRL_HSS_DISABLE | | |
669 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
670 | COH901318_CX_CTRL_PRDD_DEST, | |
671 | .param.ctrl_lli_last = 0 | | |
672 | COH901318_CX_CTRL_TC_ENABLE | | |
673 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
674 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
675 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
676 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
677 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
678 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
679 | COH901318_CX_CTRL_TCP_DISABLE | | |
680 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
681 | COH901318_CX_CTRL_HSP_ENABLE | | |
682 | COH901318_CX_CTRL_HSS_DISABLE | | |
683 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
684 | COH901318_CX_CTRL_PRDD_DEST, | |
685 | }, | |
686 | { | |
687 | .number = U300_DMA_MSL_RX_5, | |
688 | .name = "MSL RX 5", | |
689 | .priority_high = 0, | |
24dbcd8a LW |
690 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
691 | COH901318_CX_CFG_LCR_DISABLE | | |
692 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
693 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
694 | .param.ctrl_lli_chained = 0 | | |
695 | COH901318_CX_CTRL_TC_ENABLE | | |
696 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
697 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
698 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
699 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
700 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
701 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
702 | COH901318_CX_CTRL_TCP_DISABLE | | |
703 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
704 | COH901318_CX_CTRL_HSP_ENABLE | | |
705 | COH901318_CX_CTRL_HSS_DISABLE | | |
706 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
707 | COH901318_CX_CTRL_PRDD_DEST, | |
708 | .param.ctrl_lli = 0 | | |
709 | COH901318_CX_CTRL_TC_ENABLE | | |
710 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
711 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
712 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
713 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
714 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
715 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
716 | COH901318_CX_CTRL_TCP_DISABLE | | |
717 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
718 | COH901318_CX_CTRL_HSP_ENABLE | | |
719 | COH901318_CX_CTRL_HSS_DISABLE | | |
720 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
721 | COH901318_CX_CTRL_PRDD_DEST, | |
722 | .param.ctrl_lli_last = 0 | | |
723 | COH901318_CX_CTRL_TC_ENABLE | | |
724 | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | | |
725 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
726 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
727 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
728 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
729 | COH901318_CX_CTRL_MASTER_MODE_M2R_M1W | | |
730 | COH901318_CX_CTRL_TCP_DISABLE | | |
731 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
732 | COH901318_CX_CTRL_HSP_ENABLE | | |
733 | COH901318_CX_CTRL_HSS_DISABLE | | |
734 | COH901318_CX_CTRL_DDMA_DEMAND_DMA1 | | |
735 | COH901318_CX_CTRL_PRDD_DEST, | |
736 | }, | |
737 | { | |
738 | .number = U300_DMA_MSL_RX_6, | |
739 | .name = "MSL RX 6", | |
740 | .priority_high = 0, | |
24dbcd8a LW |
741 | }, |
742 | /* | |
743 | * Don't set up device address, burst count or size of src | |
744 | * or dst bus for this peripheral - handled by PrimeCell | |
745 | * DMA extension. | |
746 | */ | |
747 | { | |
748 | .number = U300_DMA_MMCSD_RX_TX, | |
749 | .name = "MMCSD RX TX", | |
750 | .priority_high = 0, | |
751 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
752 | COH901318_CX_CFG_LCR_DISABLE | | |
753 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
754 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
755 | .param.ctrl_lli_chained = 0 | | |
756 | COH901318_CX_CTRL_TC_ENABLE | | |
757 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
758 | COH901318_CX_CTRL_TCP_ENABLE | | |
759 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
760 | COH901318_CX_CTRL_HSP_ENABLE | | |
761 | COH901318_CX_CTRL_HSS_DISABLE | | |
762 | COH901318_CX_CTRL_DDMA_LEGACY, | |
763 | .param.ctrl_lli = 0 | | |
764 | COH901318_CX_CTRL_TC_ENABLE | | |
765 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
766 | COH901318_CX_CTRL_TCP_ENABLE | | |
767 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
768 | COH901318_CX_CTRL_HSP_ENABLE | | |
769 | COH901318_CX_CTRL_HSS_DISABLE | | |
770 | COH901318_CX_CTRL_DDMA_LEGACY, | |
771 | .param.ctrl_lli_last = 0 | | |
772 | COH901318_CX_CTRL_TC_ENABLE | | |
773 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
774 | COH901318_CX_CTRL_TCP_DISABLE | | |
775 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
776 | COH901318_CX_CTRL_HSP_ENABLE | | |
777 | COH901318_CX_CTRL_HSS_DISABLE | | |
778 | COH901318_CX_CTRL_DDMA_LEGACY, | |
779 | ||
780 | }, | |
781 | { | |
782 | .number = U300_DMA_MSPRO_TX, | |
783 | .name = "MSPRO TX", | |
784 | .priority_high = 0, | |
785 | }, | |
786 | { | |
787 | .number = U300_DMA_MSPRO_RX, | |
788 | .name = "MSPRO RX", | |
789 | .priority_high = 0, | |
790 | }, | |
791 | /* | |
792 | * Don't set up device address, burst count or size of src | |
793 | * or dst bus for this peripheral - handled by PrimeCell | |
794 | * DMA extension. | |
795 | */ | |
796 | { | |
797 | .number = U300_DMA_UART0_TX, | |
798 | .name = "UART0 TX", | |
799 | .priority_high = 0, | |
800 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
801 | COH901318_CX_CFG_LCR_DISABLE | | |
802 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
803 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
804 | .param.ctrl_lli_chained = 0 | | |
805 | COH901318_CX_CTRL_TC_ENABLE | | |
806 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
807 | COH901318_CX_CTRL_TCP_ENABLE | | |
808 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
809 | COH901318_CX_CTRL_HSP_ENABLE | | |
810 | COH901318_CX_CTRL_HSS_DISABLE | | |
811 | COH901318_CX_CTRL_DDMA_LEGACY, | |
812 | .param.ctrl_lli = 0 | | |
813 | COH901318_CX_CTRL_TC_ENABLE | | |
814 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
815 | COH901318_CX_CTRL_TCP_ENABLE | | |
816 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
817 | COH901318_CX_CTRL_HSP_ENABLE | | |
818 | COH901318_CX_CTRL_HSS_DISABLE | | |
819 | COH901318_CX_CTRL_DDMA_LEGACY, | |
820 | .param.ctrl_lli_last = 0 | | |
821 | COH901318_CX_CTRL_TC_ENABLE | | |
822 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
823 | COH901318_CX_CTRL_TCP_ENABLE | | |
824 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
825 | COH901318_CX_CTRL_HSP_ENABLE | | |
826 | COH901318_CX_CTRL_HSS_DISABLE | | |
827 | COH901318_CX_CTRL_DDMA_LEGACY, | |
828 | }, | |
829 | { | |
830 | .number = U300_DMA_UART0_RX, | |
831 | .name = "UART0 RX", | |
832 | .priority_high = 0, | |
833 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
834 | COH901318_CX_CFG_LCR_DISABLE | | |
835 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
836 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
837 | .param.ctrl_lli_chained = 0 | | |
838 | COH901318_CX_CTRL_TC_ENABLE | | |
839 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
840 | COH901318_CX_CTRL_TCP_ENABLE | | |
841 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
842 | COH901318_CX_CTRL_HSP_ENABLE | | |
843 | COH901318_CX_CTRL_HSS_DISABLE | | |
844 | COH901318_CX_CTRL_DDMA_LEGACY, | |
845 | .param.ctrl_lli = 0 | | |
846 | COH901318_CX_CTRL_TC_ENABLE | | |
847 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
848 | COH901318_CX_CTRL_TCP_ENABLE | | |
849 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
850 | COH901318_CX_CTRL_HSP_ENABLE | | |
851 | COH901318_CX_CTRL_HSS_DISABLE | | |
852 | COH901318_CX_CTRL_DDMA_LEGACY, | |
853 | .param.ctrl_lli_last = 0 | | |
854 | COH901318_CX_CTRL_TC_ENABLE | | |
855 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
856 | COH901318_CX_CTRL_TCP_ENABLE | | |
857 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
858 | COH901318_CX_CTRL_HSP_ENABLE | | |
859 | COH901318_CX_CTRL_HSS_DISABLE | | |
860 | COH901318_CX_CTRL_DDMA_LEGACY, | |
861 | }, | |
862 | { | |
863 | .number = U300_DMA_APEX_TX, | |
864 | .name = "APEX TX", | |
865 | .priority_high = 0, | |
866 | }, | |
867 | { | |
868 | .number = U300_DMA_APEX_RX, | |
869 | .name = "APEX RX", | |
870 | .priority_high = 0, | |
871 | }, | |
872 | { | |
873 | .number = U300_DMA_PCM_I2S0_TX, | |
874 | .name = "PCM I2S0 TX", | |
875 | .priority_high = 1, | |
24dbcd8a LW |
876 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
877 | COH901318_CX_CFG_LCR_DISABLE | | |
878 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
879 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
880 | .param.ctrl_lli_chained = 0 | | |
881 | COH901318_CX_CTRL_TC_ENABLE | | |
882 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
883 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
884 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
885 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
886 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
887 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
888 | COH901318_CX_CTRL_TCP_DISABLE | | |
889 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
890 | COH901318_CX_CTRL_HSP_ENABLE | | |
891 | COH901318_CX_CTRL_HSS_DISABLE | | |
892 | COH901318_CX_CTRL_DDMA_LEGACY | | |
893 | COH901318_CX_CTRL_PRDD_SOURCE, | |
894 | .param.ctrl_lli = 0 | | |
895 | COH901318_CX_CTRL_TC_ENABLE | | |
896 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
897 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
898 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
899 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
900 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
901 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
902 | COH901318_CX_CTRL_TCP_ENABLE | | |
903 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
904 | COH901318_CX_CTRL_HSP_ENABLE | | |
905 | COH901318_CX_CTRL_HSS_DISABLE | | |
906 | COH901318_CX_CTRL_DDMA_LEGACY | | |
907 | COH901318_CX_CTRL_PRDD_SOURCE, | |
908 | .param.ctrl_lli_last = 0 | | |
909 | COH901318_CX_CTRL_TC_ENABLE | | |
910 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
911 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
912 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
913 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
914 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
915 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
916 | COH901318_CX_CTRL_TCP_ENABLE | | |
917 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
918 | COH901318_CX_CTRL_HSP_ENABLE | | |
919 | COH901318_CX_CTRL_HSS_DISABLE | | |
920 | COH901318_CX_CTRL_DDMA_LEGACY | | |
921 | COH901318_CX_CTRL_PRDD_SOURCE, | |
922 | }, | |
923 | { | |
924 | .number = U300_DMA_PCM_I2S0_RX, | |
925 | .name = "PCM I2S0 RX", | |
926 | .priority_high = 1, | |
24dbcd8a LW |
927 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
928 | COH901318_CX_CFG_LCR_DISABLE | | |
929 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
930 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
931 | .param.ctrl_lli_chained = 0 | | |
932 | COH901318_CX_CTRL_TC_ENABLE | | |
933 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
934 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
935 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
936 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
937 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
938 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
939 | COH901318_CX_CTRL_TCP_DISABLE | | |
940 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
941 | COH901318_CX_CTRL_HSP_ENABLE | | |
942 | COH901318_CX_CTRL_HSS_DISABLE | | |
943 | COH901318_CX_CTRL_DDMA_LEGACY | | |
944 | COH901318_CX_CTRL_PRDD_DEST, | |
945 | .param.ctrl_lli = 0 | | |
946 | COH901318_CX_CTRL_TC_ENABLE | | |
947 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
948 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
949 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
950 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
951 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
952 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
953 | COH901318_CX_CTRL_TCP_ENABLE | | |
954 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
955 | COH901318_CX_CTRL_HSP_ENABLE | | |
956 | COH901318_CX_CTRL_HSS_DISABLE | | |
957 | COH901318_CX_CTRL_DDMA_LEGACY | | |
958 | COH901318_CX_CTRL_PRDD_DEST, | |
959 | .param.ctrl_lli_last = 0 | | |
960 | COH901318_CX_CTRL_TC_ENABLE | | |
961 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
962 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
963 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
964 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
965 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
966 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
967 | COH901318_CX_CTRL_TCP_ENABLE | | |
968 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
969 | COH901318_CX_CTRL_HSP_ENABLE | | |
970 | COH901318_CX_CTRL_HSS_DISABLE | | |
971 | COH901318_CX_CTRL_DDMA_LEGACY | | |
972 | COH901318_CX_CTRL_PRDD_DEST, | |
973 | }, | |
974 | { | |
975 | .number = U300_DMA_PCM_I2S1_TX, | |
976 | .name = "PCM I2S1 TX", | |
977 | .priority_high = 1, | |
24dbcd8a LW |
978 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
979 | COH901318_CX_CFG_LCR_DISABLE | | |
980 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
981 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
982 | .param.ctrl_lli_chained = 0 | | |
983 | COH901318_CX_CTRL_TC_ENABLE | | |
984 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
985 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
986 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
987 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
988 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
989 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
990 | COH901318_CX_CTRL_TCP_DISABLE | | |
991 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
992 | COH901318_CX_CTRL_HSP_ENABLE | | |
993 | COH901318_CX_CTRL_HSS_DISABLE | | |
994 | COH901318_CX_CTRL_DDMA_LEGACY | | |
995 | COH901318_CX_CTRL_PRDD_SOURCE, | |
996 | .param.ctrl_lli = 0 | | |
997 | COH901318_CX_CTRL_TC_ENABLE | | |
998 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
999 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1000 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1001 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1002 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1003 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1004 | COH901318_CX_CTRL_TCP_ENABLE | | |
1005 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1006 | COH901318_CX_CTRL_HSP_ENABLE | | |
1007 | COH901318_CX_CTRL_HSS_DISABLE | | |
1008 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1009 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1010 | .param.ctrl_lli_last = 0 | | |
1011 | COH901318_CX_CTRL_TC_ENABLE | | |
1012 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1013 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1014 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | | |
1015 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1016 | COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | | |
1017 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1018 | COH901318_CX_CTRL_TCP_ENABLE | | |
1019 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1020 | COH901318_CX_CTRL_HSP_ENABLE | | |
1021 | COH901318_CX_CTRL_HSS_DISABLE | | |
1022 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1023 | COH901318_CX_CTRL_PRDD_SOURCE, | |
1024 | }, | |
1025 | { | |
1026 | .number = U300_DMA_PCM_I2S1_RX, | |
1027 | .name = "PCM I2S1 RX", | |
1028 | .priority_high = 1, | |
24dbcd8a LW |
1029 | .param.config = COH901318_CX_CFG_CH_DISABLE | |
1030 | COH901318_CX_CFG_LCR_DISABLE | | |
1031 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1032 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1033 | .param.ctrl_lli_chained = 0 | | |
1034 | COH901318_CX_CTRL_TC_ENABLE | | |
1035 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1036 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1037 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1038 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1039 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1040 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1041 | COH901318_CX_CTRL_TCP_DISABLE | | |
1042 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1043 | COH901318_CX_CTRL_HSP_ENABLE | | |
1044 | COH901318_CX_CTRL_HSS_DISABLE | | |
1045 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1046 | COH901318_CX_CTRL_PRDD_DEST, | |
1047 | .param.ctrl_lli = 0 | | |
1048 | COH901318_CX_CTRL_TC_ENABLE | | |
1049 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1050 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1051 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1052 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1053 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1054 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1055 | COH901318_CX_CTRL_TCP_ENABLE | | |
1056 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1057 | COH901318_CX_CTRL_HSP_ENABLE | | |
1058 | COH901318_CX_CTRL_HSS_DISABLE | | |
1059 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1060 | COH901318_CX_CTRL_PRDD_DEST, | |
1061 | .param.ctrl_lli_last = 0 | | |
1062 | COH901318_CX_CTRL_TC_ENABLE | | |
1063 | COH901318_CX_CTRL_BURST_COUNT_16_BYTES | | |
1064 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | | |
1065 | COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE | | |
1066 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | | |
1067 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | | |
1068 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1069 | COH901318_CX_CTRL_TCP_ENABLE | | |
1070 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1071 | COH901318_CX_CTRL_HSP_ENABLE | | |
1072 | COH901318_CX_CTRL_HSS_DISABLE | | |
1073 | COH901318_CX_CTRL_DDMA_LEGACY | | |
1074 | COH901318_CX_CTRL_PRDD_DEST, | |
1075 | }, | |
1076 | { | |
1077 | .number = U300_DMA_XGAM_CDI, | |
1078 | .name = "XGAM CDI", | |
1079 | .priority_high = 0, | |
1080 | }, | |
1081 | { | |
1082 | .number = U300_DMA_XGAM_PDI, | |
1083 | .name = "XGAM PDI", | |
1084 | .priority_high = 0, | |
1085 | }, | |
1086 | /* | |
1087 | * Don't set up device address, burst count or size of src | |
1088 | * or dst bus for this peripheral - handled by PrimeCell | |
1089 | * DMA extension. | |
1090 | */ | |
1091 | { | |
1092 | .number = U300_DMA_SPI_TX, | |
1093 | .name = "SPI TX", | |
1094 | .priority_high = 0, | |
1095 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
1096 | COH901318_CX_CFG_LCR_DISABLE | | |
1097 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1098 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1099 | .param.ctrl_lli_chained = 0 | | |
1100 | COH901318_CX_CTRL_TC_ENABLE | | |
1101 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1102 | COH901318_CX_CTRL_TCP_DISABLE | | |
1103 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1104 | COH901318_CX_CTRL_HSP_ENABLE | | |
1105 | COH901318_CX_CTRL_HSS_DISABLE | | |
1106 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1107 | .param.ctrl_lli = 0 | | |
1108 | COH901318_CX_CTRL_TC_ENABLE | | |
1109 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1110 | COH901318_CX_CTRL_TCP_DISABLE | | |
1111 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1112 | COH901318_CX_CTRL_HSP_ENABLE | | |
1113 | COH901318_CX_CTRL_HSS_DISABLE | | |
1114 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1115 | .param.ctrl_lli_last = 0 | | |
1116 | COH901318_CX_CTRL_TC_ENABLE | | |
1117 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1118 | COH901318_CX_CTRL_TCP_DISABLE | | |
1119 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1120 | COH901318_CX_CTRL_HSP_ENABLE | | |
1121 | COH901318_CX_CTRL_HSS_DISABLE | | |
1122 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1123 | }, | |
1124 | { | |
1125 | .number = U300_DMA_SPI_RX, | |
1126 | .name = "SPI RX", | |
1127 | .priority_high = 0, | |
1128 | .param.config = COH901318_CX_CFG_CH_DISABLE | | |
1129 | COH901318_CX_CFG_LCR_DISABLE | | |
1130 | COH901318_CX_CFG_TC_IRQ_ENABLE | | |
1131 | COH901318_CX_CFG_BE_IRQ_ENABLE, | |
1132 | .param.ctrl_lli_chained = 0 | | |
1133 | COH901318_CX_CTRL_TC_ENABLE | | |
1134 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1135 | COH901318_CX_CTRL_TCP_DISABLE | | |
1136 | COH901318_CX_CTRL_TC_IRQ_DISABLE | | |
1137 | COH901318_CX_CTRL_HSP_ENABLE | | |
1138 | COH901318_CX_CTRL_HSS_DISABLE | | |
1139 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1140 | .param.ctrl_lli = 0 | | |
1141 | COH901318_CX_CTRL_TC_ENABLE | | |
1142 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1143 | COH901318_CX_CTRL_TCP_DISABLE | | |
1144 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1145 | COH901318_CX_CTRL_HSP_ENABLE | | |
1146 | COH901318_CX_CTRL_HSS_DISABLE | | |
1147 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1148 | .param.ctrl_lli_last = 0 | | |
1149 | COH901318_CX_CTRL_TC_ENABLE | | |
1150 | COH901318_CX_CTRL_MASTER_MODE_M1RW | | |
1151 | COH901318_CX_CTRL_TCP_DISABLE | | |
1152 | COH901318_CX_CTRL_TC_IRQ_ENABLE | | |
1153 | COH901318_CX_CTRL_HSP_ENABLE | | |
1154 | COH901318_CX_CTRL_HSS_DISABLE | | |
1155 | COH901318_CX_CTRL_DDMA_LEGACY, | |
1156 | ||
1157 | }, | |
1158 | { | |
1159 | .number = U300_DMA_GENERAL_PURPOSE_0, | |
1160 | .name = "GENERAL 00", | |
1161 | .priority_high = 0, | |
1162 | ||
1163 | .param.config = flags_memcpy_config, | |
1164 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1165 | .param.ctrl_lli = flags_memcpy_lli, | |
1166 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1167 | }, | |
1168 | { | |
1169 | .number = U300_DMA_GENERAL_PURPOSE_1, | |
1170 | .name = "GENERAL 01", | |
1171 | .priority_high = 0, | |
1172 | ||
1173 | .param.config = flags_memcpy_config, | |
1174 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1175 | .param.ctrl_lli = flags_memcpy_lli, | |
1176 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1177 | }, | |
1178 | { | |
1179 | .number = U300_DMA_GENERAL_PURPOSE_2, | |
1180 | .name = "GENERAL 02", | |
1181 | .priority_high = 0, | |
1182 | ||
1183 | .param.config = flags_memcpy_config, | |
1184 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1185 | .param.ctrl_lli = flags_memcpy_lli, | |
1186 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1187 | }, | |
1188 | { | |
1189 | .number = U300_DMA_GENERAL_PURPOSE_3, | |
1190 | .name = "GENERAL 03", | |
1191 | .priority_high = 0, | |
1192 | ||
1193 | .param.config = flags_memcpy_config, | |
1194 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1195 | .param.ctrl_lli = flags_memcpy_lli, | |
1196 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1197 | }, | |
1198 | { | |
1199 | .number = U300_DMA_GENERAL_PURPOSE_4, | |
1200 | .name = "GENERAL 04", | |
1201 | .priority_high = 0, | |
1202 | ||
1203 | .param.config = flags_memcpy_config, | |
1204 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1205 | .param.ctrl_lli = flags_memcpy_lli, | |
1206 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1207 | }, | |
1208 | { | |
1209 | .number = U300_DMA_GENERAL_PURPOSE_5, | |
1210 | .name = "GENERAL 05", | |
1211 | .priority_high = 0, | |
1212 | ||
1213 | .param.config = flags_memcpy_config, | |
1214 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1215 | .param.ctrl_lli = flags_memcpy_lli, | |
1216 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1217 | }, | |
1218 | { | |
1219 | .number = U300_DMA_GENERAL_PURPOSE_6, | |
1220 | .name = "GENERAL 06", | |
1221 | .priority_high = 0, | |
1222 | ||
1223 | .param.config = flags_memcpy_config, | |
1224 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1225 | .param.ctrl_lli = flags_memcpy_lli, | |
1226 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1227 | }, | |
1228 | { | |
1229 | .number = U300_DMA_GENERAL_PURPOSE_7, | |
1230 | .name = "GENERAL 07", | |
1231 | .priority_high = 0, | |
1232 | ||
1233 | .param.config = flags_memcpy_config, | |
1234 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1235 | .param.ctrl_lli = flags_memcpy_lli, | |
1236 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1237 | }, | |
1238 | { | |
1239 | .number = U300_DMA_GENERAL_PURPOSE_8, | |
1240 | .name = "GENERAL 08", | |
1241 | .priority_high = 0, | |
1242 | ||
1243 | .param.config = flags_memcpy_config, | |
1244 | .param.ctrl_lli_chained = flags_memcpy_lli_chained, | |
1245 | .param.ctrl_lli = flags_memcpy_lli, | |
1246 | .param.ctrl_lli_last = flags_memcpy_lli_last, | |
1247 | }, | |
1248 | { | |
1249 | .number = U300_DMA_UART1_TX, | |
1250 | .name = "UART1 TX", | |
1251 | .priority_high = 0, | |
1252 | }, | |
1253 | { | |
1254 | .number = U300_DMA_UART1_RX, | |
1255 | .name = "UART1 RX", | |
1256 | .priority_high = 0, | |
1257 | } | |
1258 | }; | |
1259 | ||
61f135b9 LW |
1260 | #define COHC_2_DEV(cohc) (&cohc->chan.dev->device) |
1261 | ||
1262 | #ifdef VERBOSE_DEBUG | |
1263 | #define COH_DBG(x) ({ if (1) x; 0; }) | |
1264 | #else | |
1265 | #define COH_DBG(x) ({ if (0) x; 0; }) | |
1266 | #endif | |
1267 | ||
1268 | struct coh901318_desc { | |
1269 | struct dma_async_tx_descriptor desc; | |
1270 | struct list_head node; | |
1271 | struct scatterlist *sg; | |
1272 | unsigned int sg_len; | |
cecd87da | 1273 | struct coh901318_lli *lli; |
db8196df | 1274 | enum dma_transfer_direction dir; |
61f135b9 | 1275 | unsigned long flags; |
b89243dd LW |
1276 | u32 head_config; |
1277 | u32 head_ctrl; | |
61f135b9 LW |
1278 | }; |
1279 | ||
1280 | struct coh901318_base { | |
1281 | struct device *dev; | |
1282 | void __iomem *virtbase; | |
7bb45f66 | 1283 | unsigned int irq; |
61f135b9 LW |
1284 | struct coh901318_pool pool; |
1285 | struct powersave pm; | |
1286 | struct dma_device dma_slave; | |
1287 | struct dma_device dma_memcpy; | |
1288 | struct coh901318_chan *chans; | |
61f135b9 LW |
1289 | }; |
1290 | ||
1291 | struct coh901318_chan { | |
1292 | spinlock_t lock; | |
1293 | int allocated; | |
61f135b9 LW |
1294 | int id; |
1295 | int stopped; | |
1296 | ||
1297 | struct work_struct free_work; | |
1298 | struct dma_chan chan; | |
1299 | ||
1300 | struct tasklet_struct tasklet; | |
1301 | ||
1302 | struct list_head active; | |
1303 | struct list_head queue; | |
1304 | struct list_head free; | |
1305 | ||
1306 | unsigned long nbr_active_done; | |
1307 | unsigned long busy; | |
61f135b9 | 1308 | |
9aab4d6f LW |
1309 | u32 addr; |
1310 | u32 ctrl; | |
128f904a | 1311 | |
61f135b9 LW |
1312 | struct coh901318_base *base; |
1313 | }; | |
1314 | ||
1315 | static void coh901318_list_print(struct coh901318_chan *cohc, | |
1316 | struct coh901318_lli *lli) | |
1317 | { | |
848ad121 | 1318 | struct coh901318_lli *l = lli; |
61f135b9 LW |
1319 | int i = 0; |
1320 | ||
848ad121 | 1321 | while (l) { |
6d82e05b VK |
1322 | dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src %pad" |
1323 | ", dst %pad, link %pad virt_link_addr 0x%p\n", | |
3fd38662 VK |
1324 | i, l, l->control, &l->src_addr, &l->dst_addr, |
1325 | &l->link_addr, l->virt_link_addr); | |
61f135b9 | 1326 | i++; |
848ad121 | 1327 | l = l->virt_link_addr; |
61f135b9 LW |
1328 | } |
1329 | } | |
1330 | ||
1331 | #ifdef CONFIG_DEBUG_FS | |
1332 | ||
1333 | #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y) | |
1334 | ||
1335 | static struct coh901318_base *debugfs_dma_base; | |
1336 | static struct dentry *dma_dentry; | |
1337 | ||
66a1a512 | 1338 | static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf, |
61f135b9 LW |
1339 | size_t count, loff_t *f_pos) |
1340 | { | |
1341 | u64 started_channels = debugfs_dma_base->pm.started_channels; | |
1342 | int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; | |
61f135b9 LW |
1343 | char *dev_buf; |
1344 | char *tmp; | |
5d30b427 AV |
1345 | int ret; |
1346 | int i; | |
61f135b9 LW |
1347 | |
1348 | dev_buf = kmalloc(4*1024, GFP_KERNEL); | |
1349 | if (dev_buf == NULL) | |
5d30b427 | 1350 | return -ENOMEM; |
61f135b9 LW |
1351 | tmp = dev_buf; |
1352 | ||
848ad121 | 1353 | tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); |
61f135b9 | 1354 | |
9f0df936 CIK |
1355 | for (i = 0; i < U300_DMA_CHANNELS; i++) { |
1356 | if (started_channels & (1ULL << i)) | |
61f135b9 | 1357 | tmp += sprintf(tmp, "channel %d\n", i); |
9f0df936 | 1358 | } |
61f135b9 LW |
1359 | |
1360 | tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count); | |
61f135b9 | 1361 | |
5d30b427 AV |
1362 | ret = simple_read_from_buffer(buf, count, f_pos, dev_buf, |
1363 | tmp - dev_buf); | |
61f135b9 LW |
1364 | kfree(dev_buf); |
1365 | return ret; | |
61f135b9 LW |
1366 | } |
1367 | ||
1368 | static const struct file_operations coh901318_debugfs_status_operations = { | |
234e3405 | 1369 | .open = simple_open, |
61f135b9 | 1370 | .read = coh901318_debugfs_read, |
6038f373 | 1371 | .llseek = default_llseek, |
61f135b9 LW |
1372 | }; |
1373 | ||
1374 | ||
1375 | static int __init init_coh901318_debugfs(void) | |
1376 | { | |
1377 | ||
1378 | dma_dentry = debugfs_create_dir("dma", NULL); | |
1379 | ||
1380 | (void) debugfs_create_file("status", | |
1381 | S_IFREG | S_IRUGO, | |
1382 | dma_dentry, NULL, | |
1383 | &coh901318_debugfs_status_operations); | |
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | static void __exit exit_coh901318_debugfs(void) | |
1388 | { | |
1389 | debugfs_remove_recursive(dma_dentry); | |
1390 | } | |
1391 | ||
1392 | module_init(init_coh901318_debugfs); | |
1393 | module_exit(exit_coh901318_debugfs); | |
1394 | #else | |
1395 | ||
1396 | #define COH901318_DEBUGFS_ASSIGN(x, y) | |
1397 | ||
1398 | #endif /* CONFIG_DEBUG_FS */ | |
1399 | ||
1400 | static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) | |
1401 | { | |
1402 | return container_of(chan, struct coh901318_chan, chan); | |
1403 | } | |
1404 | ||
61f135b9 LW |
1405 | static inline const struct coh901318_params * |
1406 | cohc_chan_param(struct coh901318_chan *cohc) | |
1407 | { | |
73b31eae | 1408 | return &chan_config[cohc->id].param; |
61f135b9 LW |
1409 | } |
1410 | ||
1411 | static inline const struct coh_dma_channel * | |
1412 | cohc_chan_conf(struct coh901318_chan *cohc) | |
1413 | { | |
73b31eae | 1414 | return &chan_config[cohc->id]; |
61f135b9 LW |
1415 | } |
1416 | ||
1417 | static void enable_powersave(struct coh901318_chan *cohc) | |
1418 | { | |
1419 | unsigned long flags; | |
1420 | struct powersave *pm = &cohc->base->pm; | |
1421 | ||
1422 | spin_lock_irqsave(&pm->lock, flags); | |
1423 | ||
1424 | pm->started_channels &= ~(1ULL << cohc->id); | |
1425 | ||
61f135b9 LW |
1426 | spin_unlock_irqrestore(&pm->lock, flags); |
1427 | } | |
1428 | static void disable_powersave(struct coh901318_chan *cohc) | |
1429 | { | |
1430 | unsigned long flags; | |
1431 | struct powersave *pm = &cohc->base->pm; | |
1432 | ||
1433 | spin_lock_irqsave(&pm->lock, flags); | |
1434 | ||
61f135b9 LW |
1435 | pm->started_channels |= (1ULL << cohc->id); |
1436 | ||
1437 | spin_unlock_irqrestore(&pm->lock, flags); | |
1438 | } | |
1439 | ||
1440 | static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) | |
1441 | { | |
1442 | int channel = cohc->id; | |
1443 | void __iomem *virtbase = cohc->base->virtbase; | |
1444 | ||
1445 | writel(control, | |
1446 | virtbase + COH901318_CX_CTRL + | |
1447 | COH901318_CX_CTRL_SPACING * channel); | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) | |
1452 | { | |
1453 | int channel = cohc->id; | |
1454 | void __iomem *virtbase = cohc->base->virtbase; | |
1455 | ||
1456 | writel(conf, | |
1457 | virtbase + COH901318_CX_CFG + | |
1458 | COH901318_CX_CFG_SPACING*channel); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | ||
1463 | static int coh901318_start(struct coh901318_chan *cohc) | |
1464 | { | |
1465 | u32 val; | |
1466 | int channel = cohc->id; | |
1467 | void __iomem *virtbase = cohc->base->virtbase; | |
1468 | ||
1469 | disable_powersave(cohc); | |
1470 | ||
1471 | val = readl(virtbase + COH901318_CX_CFG + | |
1472 | COH901318_CX_CFG_SPACING * channel); | |
1473 | ||
1474 | /* Enable channel */ | |
1475 | val |= COH901318_CX_CFG_CH_ENABLE; | |
1476 | writel(val, virtbase + COH901318_CX_CFG + | |
1477 | COH901318_CX_CFG_SPACING * channel); | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | static int coh901318_prep_linked_list(struct coh901318_chan *cohc, | |
cecd87da | 1483 | struct coh901318_lli *lli) |
61f135b9 LW |
1484 | { |
1485 | int channel = cohc->id; | |
1486 | void __iomem *virtbase = cohc->base->virtbase; | |
1487 | ||
1488 | BUG_ON(readl(virtbase + COH901318_CX_STAT + | |
1489 | COH901318_CX_STAT_SPACING*channel) & | |
1490 | COH901318_CX_STAT_ACTIVE); | |
1491 | ||
cecd87da | 1492 | writel(lli->src_addr, |
61f135b9 LW |
1493 | virtbase + COH901318_CX_SRC_ADDR + |
1494 | COH901318_CX_SRC_ADDR_SPACING * channel); | |
1495 | ||
cecd87da | 1496 | writel(lli->dst_addr, virtbase + |
61f135b9 LW |
1497 | COH901318_CX_DST_ADDR + |
1498 | COH901318_CX_DST_ADDR_SPACING * channel); | |
1499 | ||
cecd87da | 1500 | writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR + |
61f135b9 LW |
1501 | COH901318_CX_LNK_ADDR_SPACING * channel); |
1502 | ||
cecd87da | 1503 | writel(lli->control, virtbase + COH901318_CX_CTRL + |
61f135b9 LW |
1504 | COH901318_CX_CTRL_SPACING * channel); |
1505 | ||
1506 | return 0; | |
1507 | } | |
61f135b9 LW |
1508 | |
1509 | static struct coh901318_desc * | |
1510 | coh901318_desc_get(struct coh901318_chan *cohc) | |
1511 | { | |
1512 | struct coh901318_desc *desc; | |
1513 | ||
1514 | if (list_empty(&cohc->free)) { | |
1515 | /* alloc new desc because we're out of used ones | |
1516 | * TODO: alloc a pile of descs instead of just one, | |
1517 | * avoid many small allocations. | |
1518 | */ | |
b87108a7 | 1519 | desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); |
61f135b9 LW |
1520 | if (desc == NULL) |
1521 | goto out; | |
1522 | INIT_LIST_HEAD(&desc->node); | |
b87108a7 | 1523 | dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); |
61f135b9 LW |
1524 | } else { |
1525 | /* Reuse an old desc. */ | |
1526 | desc = list_first_entry(&cohc->free, | |
1527 | struct coh901318_desc, | |
1528 | node); | |
1529 | list_del(&desc->node); | |
b87108a7 LW |
1530 | /* Initialize it a bit so it's not insane */ |
1531 | desc->sg = NULL; | |
1532 | desc->sg_len = 0; | |
1533 | desc->desc.callback = NULL; | |
1534 | desc->desc.callback_param = NULL; | |
61f135b9 LW |
1535 | } |
1536 | ||
1537 | out: | |
1538 | return desc; | |
1539 | } | |
1540 | ||
1541 | static void | |
1542 | coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd) | |
1543 | { | |
1544 | list_add_tail(&cohd->node, &cohc->free); | |
1545 | } | |
1546 | ||
1547 | /* call with irq lock held */ | |
1548 | static void | |
1549 | coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) | |
1550 | { | |
1551 | list_add_tail(&desc->node, &cohc->active); | |
61f135b9 LW |
1552 | } |
1553 | ||
1554 | static struct coh901318_desc * | |
1555 | coh901318_first_active_get(struct coh901318_chan *cohc) | |
1556 | { | |
360af35b MY |
1557 | return list_first_entry_or_null(&cohc->active, struct coh901318_desc, |
1558 | node); | |
61f135b9 LW |
1559 | } |
1560 | ||
1561 | static void | |
1562 | coh901318_desc_remove(struct coh901318_desc *cohd) | |
1563 | { | |
1564 | list_del(&cohd->node); | |
1565 | } | |
1566 | ||
1567 | static void | |
1568 | coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc) | |
1569 | { | |
1570 | list_add_tail(&desc->node, &cohc->queue); | |
1571 | } | |
1572 | ||
1573 | static struct coh901318_desc * | |
1574 | coh901318_first_queued(struct coh901318_chan *cohc) | |
1575 | { | |
360af35b MY |
1576 | return list_first_entry_or_null(&cohc->queue, struct coh901318_desc, |
1577 | node); | |
61f135b9 LW |
1578 | } |
1579 | ||
84c8447c LW |
1580 | static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli) |
1581 | { | |
1582 | struct coh901318_lli *lli = in_lli; | |
1583 | u32 bytes = 0; | |
1584 | ||
1585 | while (lli) { | |
1586 | bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK; | |
1587 | lli = lli->virt_link_addr; | |
1588 | } | |
1589 | return bytes; | |
1590 | } | |
1591 | ||
61f135b9 | 1592 | /* |
84c8447c LW |
1593 | * Get the number of bytes left to transfer on this channel, |
1594 | * it is unwise to call this before stopping the channel for | |
1595 | * absolute measures, but for a rough guess you can still call | |
1596 | * it. | |
61f135b9 | 1597 | */ |
07934481 | 1598 | static u32 coh901318_get_bytes_left(struct dma_chan *chan) |
61f135b9 | 1599 | { |
61f135b9 | 1600 | struct coh901318_chan *cohc = to_coh901318_chan(chan); |
84c8447c LW |
1601 | struct coh901318_desc *cohd; |
1602 | struct list_head *pos; | |
1603 | unsigned long flags; | |
1604 | u32 left = 0; | |
1605 | int i = 0; | |
61f135b9 LW |
1606 | |
1607 | spin_lock_irqsave(&cohc->lock, flags); | |
1608 | ||
84c8447c LW |
1609 | /* |
1610 | * If there are many queued jobs, we iterate and add the | |
1611 | * size of them all. We take a special look on the first | |
1612 | * job though, since it is probably active. | |
1613 | */ | |
1614 | list_for_each(pos, &cohc->active) { | |
1615 | /* | |
1616 | * The first job in the list will be working on the | |
1617 | * hardware. The job can be stopped but still active, | |
1618 | * so that the transfer counter is somewhere inside | |
1619 | * the buffer. | |
1620 | */ | |
1621 | cohd = list_entry(pos, struct coh901318_desc, node); | |
1622 | ||
1623 | if (i == 0) { | |
1624 | struct coh901318_lli *lli; | |
1625 | dma_addr_t ladd; | |
1626 | ||
1627 | /* Read current transfer count value */ | |
1628 | left = readl(cohc->base->virtbase + | |
1629 | COH901318_CX_CTRL + | |
1630 | COH901318_CX_CTRL_SPACING * cohc->id) & | |
1631 | COH901318_CX_CTRL_TC_VALUE_MASK; | |
1632 | ||
1633 | /* See if the transfer is linked... */ | |
1634 | ladd = readl(cohc->base->virtbase + | |
1635 | COH901318_CX_LNK_ADDR + | |
1636 | COH901318_CX_LNK_ADDR_SPACING * | |
1637 | cohc->id) & | |
1638 | ~COH901318_CX_LNK_LINK_IMMEDIATE; | |
1639 | /* Single transaction */ | |
1640 | if (!ladd) | |
1641 | continue; | |
1642 | ||
1643 | /* | |
1644 | * Linked transaction, follow the lli, find the | |
1645 | * currently processing lli, and proceed to the next | |
1646 | */ | |
1647 | lli = cohd->lli; | |
1648 | while (lli && lli->link_addr != ladd) | |
1649 | lli = lli->virt_link_addr; | |
1650 | ||
1651 | if (lli) | |
1652 | lli = lli->virt_link_addr; | |
1653 | ||
1654 | /* | |
1655 | * Follow remaining lli links around to count the total | |
1656 | * number of bytes left | |
1657 | */ | |
1658 | left += coh901318_get_bytes_in_lli(lli); | |
1659 | } else { | |
1660 | left += coh901318_get_bytes_in_lli(cohd->lli); | |
1661 | } | |
1662 | i++; | |
1663 | } | |
1664 | ||
1665 | /* Also count bytes in the queued jobs */ | |
1666 | list_for_each(pos, &cohc->queue) { | |
1667 | cohd = list_entry(pos, struct coh901318_desc, node); | |
1668 | left += coh901318_get_bytes_in_lli(cohd->lli); | |
1669 | } | |
61f135b9 LW |
1670 | |
1671 | spin_unlock_irqrestore(&cohc->lock, flags); | |
1672 | ||
84c8447c | 1673 | return left; |
61f135b9 | 1674 | } |
61f135b9 | 1675 | |
c3635c78 LW |
1676 | /* |
1677 | * Pauses a transfer without losing data. Enables power save. | |
1678 | * Use this function in conjunction with coh901318_resume. | |
1679 | */ | |
4d76bbed | 1680 | static int coh901318_pause(struct dma_chan *chan) |
61f135b9 LW |
1681 | { |
1682 | u32 val; | |
1683 | unsigned long flags; | |
1684 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
1685 | int channel = cohc->id; | |
1686 | void __iomem *virtbase = cohc->base->virtbase; | |
1687 | ||
1688 | spin_lock_irqsave(&cohc->lock, flags); | |
1689 | ||
1690 | /* Disable channel in HW */ | |
1691 | val = readl(virtbase + COH901318_CX_CFG + | |
1692 | COH901318_CX_CFG_SPACING * channel); | |
1693 | ||
25985edc | 1694 | /* Stopping infinite transfer */ |
61f135b9 LW |
1695 | if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 && |
1696 | (val & COH901318_CX_CFG_CH_ENABLE)) | |
1697 | cohc->stopped = 1; | |
1698 | ||
1699 | ||
1700 | val &= ~COH901318_CX_CFG_CH_ENABLE; | |
1701 | /* Enable twice, HW bug work around */ | |
1702 | writel(val, virtbase + COH901318_CX_CFG + | |
1703 | COH901318_CX_CFG_SPACING * channel); | |
1704 | writel(val, virtbase + COH901318_CX_CFG + | |
1705 | COH901318_CX_CFG_SPACING * channel); | |
1706 | ||
1707 | /* Spin-wait for it to actually go inactive */ | |
1708 | while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING * | |
1709 | channel) & COH901318_CX_STAT_ACTIVE) | |
1710 | cpu_relax(); | |
1711 | ||
1712 | /* Check if we stopped an active job */ | |
1713 | if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING * | |
1714 | channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0) | |
1715 | cohc->stopped = 1; | |
1716 | ||
1717 | enable_powersave(cohc); | |
1718 | ||
1719 | spin_unlock_irqrestore(&cohc->lock, flags); | |
4d76bbed | 1720 | return 0; |
61f135b9 | 1721 | } |
61f135b9 | 1722 | |
c3635c78 | 1723 | /* Resumes a transfer that has been stopped via 300_dma_stop(..). |
61f135b9 LW |
1724 | Power save is handled. |
1725 | */ | |
4d76bbed | 1726 | static int coh901318_resume(struct dma_chan *chan) |
61f135b9 LW |
1727 | { |
1728 | u32 val; | |
1729 | unsigned long flags; | |
1730 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
1731 | int channel = cohc->id; | |
1732 | ||
1733 | spin_lock_irqsave(&cohc->lock, flags); | |
1734 | ||
1735 | disable_powersave(cohc); | |
1736 | ||
1737 | if (cohc->stopped) { | |
1738 | /* Enable channel in HW */ | |
1739 | val = readl(cohc->base->virtbase + COH901318_CX_CFG + | |
1740 | COH901318_CX_CFG_SPACING * channel); | |
1741 | ||
1742 | val |= COH901318_CX_CFG_CH_ENABLE; | |
1743 | ||
1744 | writel(val, cohc->base->virtbase + COH901318_CX_CFG + | |
1745 | COH901318_CX_CFG_SPACING*channel); | |
1746 | ||
1747 | cohc->stopped = 0; | |
1748 | } | |
1749 | ||
1750 | spin_unlock_irqrestore(&cohc->lock, flags); | |
4d76bbed | 1751 | return 0; |
61f135b9 | 1752 | } |
61f135b9 LW |
1753 | |
1754 | bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) | |
1755 | { | |
c021d835 | 1756 | unsigned long ch_nr = (unsigned long) chan_id; |
61f135b9 LW |
1757 | |
1758 | if (ch_nr == to_coh901318_chan(chan)->id) | |
1759 | return true; | |
1760 | ||
1761 | return false; | |
1762 | } | |
1763 | EXPORT_SYMBOL(coh901318_filter_id); | |
1764 | ||
faadc6e3 LW |
1765 | struct coh901318_filter_args { |
1766 | struct coh901318_base *base; | |
1767 | unsigned int ch_nr; | |
1768 | }; | |
1769 | ||
1770 | static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data) | |
1771 | { | |
1772 | struct coh901318_filter_args *args = data; | |
1773 | ||
1774 | if (&args->base->dma_slave == chan->device && | |
1775 | args->ch_nr == to_coh901318_chan(chan)->id) | |
1776 | return true; | |
1777 | ||
1778 | return false; | |
1779 | } | |
1780 | ||
1781 | static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec, | |
1782 | struct of_dma *ofdma) | |
1783 | { | |
1784 | struct coh901318_filter_args args = { | |
1785 | .base = ofdma->of_dma_data, | |
1786 | .ch_nr = dma_spec->args[0], | |
1787 | }; | |
1788 | dma_cap_mask_t cap; | |
1789 | dma_cap_zero(cap); | |
1790 | dma_cap_set(DMA_SLAVE, cap); | |
1791 | ||
1792 | return dma_request_channel(cap, coh901318_filter_base_and_id, &args); | |
1793 | } | |
61f135b9 LW |
1794 | /* |
1795 | * DMA channel allocation | |
1796 | */ | |
1797 | static int coh901318_config(struct coh901318_chan *cohc, | |
1798 | struct coh901318_params *param) | |
1799 | { | |
1800 | unsigned long flags; | |
1801 | const struct coh901318_params *p; | |
1802 | int channel = cohc->id; | |
1803 | void __iomem *virtbase = cohc->base->virtbase; | |
1804 | ||
1805 | spin_lock_irqsave(&cohc->lock, flags); | |
1806 | ||
1807 | if (param) | |
1808 | p = param; | |
1809 | else | |
73b31eae | 1810 | p = cohc_chan_param(cohc); |
61f135b9 LW |
1811 | |
1812 | /* Clear any pending BE or TC interrupt */ | |
1813 | if (channel < 32) { | |
1814 | writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1); | |
1815 | writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1); | |
1816 | } else { | |
1817 | writel(1 << (channel - 32), virtbase + | |
1818 | COH901318_BE_INT_CLEAR2); | |
1819 | writel(1 << (channel - 32), virtbase + | |
1820 | COH901318_TC_INT_CLEAR2); | |
1821 | } | |
1822 | ||
1823 | coh901318_set_conf(cohc, p->config); | |
1824 | coh901318_set_ctrl(cohc, p->ctrl_lli_last); | |
1825 | ||
1826 | spin_unlock_irqrestore(&cohc->lock, flags); | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | /* must lock when calling this function | |
1832 | * start queued jobs, if any | |
1833 | * TODO: start all queued jobs in one go | |
1834 | * | |
1835 | * Returns descriptor if queued job is started otherwise NULL. | |
1836 | * If the queue is empty NULL is returned. | |
1837 | */ | |
1838 | static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) | |
1839 | { | |
cecd87da | 1840 | struct coh901318_desc *cohd; |
61f135b9 | 1841 | |
cecd87da LW |
1842 | /* |
1843 | * start queued jobs, if any | |
61f135b9 LW |
1844 | * TODO: transmit all queued jobs in one go |
1845 | */ | |
cecd87da | 1846 | cohd = coh901318_first_queued(cohc); |
61f135b9 | 1847 | |
cecd87da | 1848 | if (cohd != NULL) { |
61f135b9 | 1849 | /* Remove from queue */ |
cecd87da | 1850 | coh901318_desc_remove(cohd); |
61f135b9 LW |
1851 | /* initiate DMA job */ |
1852 | cohc->busy = 1; | |
1853 | ||
cecd87da | 1854 | coh901318_desc_submit(cohc, cohd); |
61f135b9 | 1855 | |
b89243dd LW |
1856 | /* Program the transaction head */ |
1857 | coh901318_set_conf(cohc, cohd->head_config); | |
1858 | coh901318_set_ctrl(cohc, cohd->head_ctrl); | |
cecd87da | 1859 | coh901318_prep_linked_list(cohc, cohd->lli); |
61f135b9 | 1860 | |
cecd87da | 1861 | /* start dma job on this channel */ |
61f135b9 LW |
1862 | coh901318_start(cohc); |
1863 | ||
1864 | } | |
1865 | ||
cecd87da | 1866 | return cohd; |
61f135b9 LW |
1867 | } |
1868 | ||
848ad121 LW |
1869 | /* |
1870 | * This tasklet is called from the interrupt handler to | |
1871 | * handle each descriptor (DMA job) that is sent to a channel. | |
1872 | */ | |
61f135b9 LW |
1873 | static void dma_tasklet(unsigned long data) |
1874 | { | |
1875 | struct coh901318_chan *cohc = (struct coh901318_chan *) data; | |
1876 | struct coh901318_desc *cohd_fin; | |
1877 | unsigned long flags; | |
3ab553d9 | 1878 | struct dmaengine_desc_callback cb; |
61f135b9 | 1879 | |
848ad121 LW |
1880 | dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d" |
1881 | " nbr_active_done %ld\n", __func__, | |
1882 | cohc->id, cohc->nbr_active_done); | |
1883 | ||
61f135b9 LW |
1884 | spin_lock_irqsave(&cohc->lock, flags); |
1885 | ||
848ad121 | 1886 | /* get first active descriptor entry from list */ |
61f135b9 LW |
1887 | cohd_fin = coh901318_first_active_get(cohc); |
1888 | ||
61f135b9 LW |
1889 | if (cohd_fin == NULL) |
1890 | goto err; | |
1891 | ||
0b58828c | 1892 | /* locate callback to client */ |
3ab553d9 | 1893 | dmaengine_desc_get_callback(&cohd_fin->desc, &cb); |
61f135b9 | 1894 | |
0b58828c | 1895 | /* sign this job as completed on the channel */ |
f7fbce07 | 1896 | dma_cookie_complete(&cohd_fin->desc); |
61f135b9 | 1897 | |
0b58828c | 1898 | /* release the lli allocation and remove the descriptor */ |
cecd87da | 1899 | coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); |
61f135b9 | 1900 | |
0b58828c LW |
1901 | /* return desc to free-list */ |
1902 | coh901318_desc_remove(cohd_fin); | |
1903 | coh901318_desc_free(cohc, cohd_fin); | |
61f135b9 | 1904 | |
0b58828c | 1905 | spin_unlock_irqrestore(&cohc->lock, flags); |
61f135b9 | 1906 | |
0b58828c | 1907 | /* Call the callback when we're done */ |
3ab553d9 | 1908 | dmaengine_desc_callback_invoke(&cb, NULL); |
61f135b9 | 1909 | |
0b58828c | 1910 | spin_lock_irqsave(&cohc->lock, flags); |
61f135b9 | 1911 | |
848ad121 LW |
1912 | /* |
1913 | * If another interrupt fired while the tasklet was scheduling, | |
1914 | * we don't get called twice, so we have this number of active | |
1915 | * counter that keep track of the number of IRQs expected to | |
1916 | * be handled for this channel. If there happen to be more than | |
1917 | * one IRQ to be ack:ed, we simply schedule this tasklet again. | |
1918 | */ | |
0b58828c | 1919 | cohc->nbr_active_done--; |
61f135b9 | 1920 | if (cohc->nbr_active_done) { |
848ad121 LW |
1921 | dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " |
1922 | "came in while we were scheduling this tasklet\n"); | |
61f135b9 LW |
1923 | if (cohc_chan_conf(cohc)->priority_high) |
1924 | tasklet_hi_schedule(&cohc->tasklet); | |
1925 | else | |
1926 | tasklet_schedule(&cohc->tasklet); | |
1927 | } | |
61f135b9 | 1928 | |
0b58828c | 1929 | spin_unlock_irqrestore(&cohc->lock, flags); |
61f135b9 LW |
1930 | |
1931 | return; | |
1932 | ||
1933 | err: | |
1934 | spin_unlock_irqrestore(&cohc->lock, flags); | |
1935 | dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__); | |
1936 | } | |
1937 | ||
1938 | ||
1939 | /* called from interrupt context */ | |
1940 | static void dma_tc_handle(struct coh901318_chan *cohc) | |
1941 | { | |
cecd87da LW |
1942 | /* |
1943 | * If the channel is not allocated, then we shouldn't have | |
1944 | * any TC interrupts on it. | |
1945 | */ | |
1946 | if (!cohc->allocated) { | |
1947 | dev_err(COHC_2_DEV(cohc), "spurious interrupt from " | |
1948 | "unallocated channel\n"); | |
61f135b9 | 1949 | return; |
cecd87da | 1950 | } |
61f135b9 | 1951 | |
0b58828c | 1952 | spin_lock(&cohc->lock); |
61f135b9 | 1953 | |
cecd87da LW |
1954 | /* |
1955 | * When we reach this point, at least one queue item | |
1956 | * should have been moved over from cohc->queue to | |
1957 | * cohc->active and run to completion, that is why we're | |
1958 | * getting a terminal count interrupt is it not? | |
1959 | * If you get this BUG() the most probable cause is that | |
1960 | * the individual nodes in the lli chain have IRQ enabled, | |
1961 | * so check your platform config for lli chain ctrl. | |
1962 | */ | |
1963 | BUG_ON(list_empty(&cohc->active)); | |
1964 | ||
61f135b9 LW |
1965 | cohc->nbr_active_done++; |
1966 | ||
cecd87da LW |
1967 | /* |
1968 | * This attempt to take a job from cohc->queue, put it | |
1969 | * into cohc->active and start it. | |
1970 | */ | |
0b58828c | 1971 | if (coh901318_queue_start(cohc) == NULL) |
61f135b9 LW |
1972 | cohc->busy = 0; |
1973 | ||
0b58828c LW |
1974 | spin_unlock(&cohc->lock); |
1975 | ||
cecd87da LW |
1976 | /* |
1977 | * This tasklet will remove items from cohc->active | |
1978 | * and thus terminates them. | |
1979 | */ | |
61f135b9 LW |
1980 | if (cohc_chan_conf(cohc)->priority_high) |
1981 | tasklet_hi_schedule(&cohc->tasklet); | |
1982 | else | |
1983 | tasklet_schedule(&cohc->tasklet); | |
1984 | } | |
1985 | ||
1986 | ||
1987 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) | |
1988 | { | |
1989 | u32 status1; | |
1990 | u32 status2; | |
1991 | int i; | |
1992 | int ch; | |
1993 | struct coh901318_base *base = dev_id; | |
1994 | struct coh901318_chan *cohc; | |
1995 | void __iomem *virtbase = base->virtbase; | |
1996 | ||
1997 | status1 = readl(virtbase + COH901318_INT_STATUS1); | |
1998 | status2 = readl(virtbase + COH901318_INT_STATUS2); | |
1999 | ||
2000 | if (unlikely(status1 == 0 && status2 == 0)) { | |
2001 | dev_warn(base->dev, "spurious DMA IRQ from no channel!\n"); | |
2002 | return IRQ_HANDLED; | |
2003 | } | |
2004 | ||
2005 | /* TODO: consider handle IRQ in tasklet here to | |
2006 | * minimize interrupt latency */ | |
2007 | ||
2008 | /* Check the first 32 DMA channels for IRQ */ | |
2009 | while (status1) { | |
2010 | /* Find first bit set, return as a number. */ | |
2011 | i = ffs(status1) - 1; | |
2012 | ch = i; | |
2013 | ||
2014 | cohc = &base->chans[ch]; | |
2015 | spin_lock(&cohc->lock); | |
2016 | ||
2017 | /* Mask off this bit */ | |
2018 | status1 &= ~(1 << i); | |
2019 | /* Check the individual channel bits */ | |
2020 | if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) { | |
2021 | dev_crit(COHC_2_DEV(cohc), | |
2022 | "DMA bus error on channel %d!\n", ch); | |
2023 | BUG_ON(1); | |
2024 | /* Clear BE interrupt */ | |
2025 | __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1); | |
2026 | } else { | |
2027 | /* Caused by TC, really? */ | |
2028 | if (unlikely(!test_bit(i, virtbase + | |
2029 | COH901318_TC_INT_STATUS1))) { | |
2030 | dev_warn(COHC_2_DEV(cohc), | |
2031 | "ignoring interrupt not caused by terminal count on channel %d\n", ch); | |
2032 | /* Clear TC interrupt */ | |
2033 | BUG_ON(1); | |
2034 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); | |
2035 | } else { | |
2036 | /* Enable powersave if transfer has finished */ | |
2037 | if (!(readl(virtbase + COH901318_CX_STAT + | |
2038 | COH901318_CX_STAT_SPACING*ch) & | |
2039 | COH901318_CX_STAT_ENABLED)) { | |
2040 | enable_powersave(cohc); | |
2041 | } | |
2042 | ||
2043 | /* Must clear TC interrupt before calling | |
2044 | * dma_tc_handle | |
bc0b44c3 | 2045 | * in case tc_handle initiate a new dma job |
61f135b9 LW |
2046 | */ |
2047 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); | |
2048 | ||
2049 | dma_tc_handle(cohc); | |
2050 | } | |
2051 | } | |
2052 | spin_unlock(&cohc->lock); | |
2053 | } | |
2054 | ||
2055 | /* Check the remaining 32 DMA channels for IRQ */ | |
2056 | while (status2) { | |
2057 | /* Find first bit set, return as a number. */ | |
2058 | i = ffs(status2) - 1; | |
2059 | ch = i + 32; | |
2060 | cohc = &base->chans[ch]; | |
2061 | spin_lock(&cohc->lock); | |
2062 | ||
2063 | /* Mask off this bit */ | |
2064 | status2 &= ~(1 << i); | |
2065 | /* Check the individual channel bits */ | |
2066 | if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) { | |
2067 | dev_crit(COHC_2_DEV(cohc), | |
2068 | "DMA bus error on channel %d!\n", ch); | |
2069 | /* Clear BE interrupt */ | |
2070 | BUG_ON(1); | |
2071 | __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2); | |
2072 | } else { | |
2073 | /* Caused by TC, really? */ | |
2074 | if (unlikely(!test_bit(i, virtbase + | |
2075 | COH901318_TC_INT_STATUS2))) { | |
2076 | dev_warn(COHC_2_DEV(cohc), | |
2077 | "ignoring interrupt not caused by terminal count on channel %d\n", ch); | |
2078 | /* Clear TC interrupt */ | |
2079 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); | |
2080 | BUG_ON(1); | |
2081 | } else { | |
2082 | /* Enable powersave if transfer has finished */ | |
2083 | if (!(readl(virtbase + COH901318_CX_STAT + | |
2084 | COH901318_CX_STAT_SPACING*ch) & | |
2085 | COH901318_CX_STAT_ENABLED)) { | |
2086 | enable_powersave(cohc); | |
2087 | } | |
2088 | /* Must clear TC interrupt before calling | |
2089 | * dma_tc_handle | |
bc0b44c3 | 2090 | * in case tc_handle initiate a new dma job |
61f135b9 LW |
2091 | */ |
2092 | __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); | |
2093 | ||
2094 | dma_tc_handle(cohc); | |
2095 | } | |
2096 | } | |
2097 | spin_unlock(&cohc->lock); | |
2098 | } | |
2099 | ||
2100 | return IRQ_HANDLED; | |
2101 | } | |
2102 | ||
6782af11 MR |
2103 | static int coh901318_terminate_all(struct dma_chan *chan) |
2104 | { | |
2105 | unsigned long flags; | |
2106 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
2107 | struct coh901318_desc *cohd; | |
2108 | void __iomem *virtbase = cohc->base->virtbase; | |
2109 | ||
2110 | /* The remainder of this function terminates the transfer */ | |
2111 | coh901318_pause(chan); | |
2112 | spin_lock_irqsave(&cohc->lock, flags); | |
2113 | ||
2114 | /* Clear any pending BE or TC interrupt */ | |
2115 | if (cohc->id < 32) { | |
2116 | writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1); | |
2117 | writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1); | |
2118 | } else { | |
2119 | writel(1 << (cohc->id - 32), virtbase + | |
2120 | COH901318_BE_INT_CLEAR2); | |
2121 | writel(1 << (cohc->id - 32), virtbase + | |
2122 | COH901318_TC_INT_CLEAR2); | |
2123 | } | |
2124 | ||
2125 | enable_powersave(cohc); | |
2126 | ||
2127 | while ((cohd = coh901318_first_active_get(cohc))) { | |
2128 | /* release the lli allocation*/ | |
2129 | coh901318_lli_free(&cohc->base->pool, &cohd->lli); | |
2130 | ||
2131 | /* return desc to free-list */ | |
2132 | coh901318_desc_remove(cohd); | |
2133 | coh901318_desc_free(cohc, cohd); | |
2134 | } | |
2135 | ||
2136 | while ((cohd = coh901318_first_queued(cohc))) { | |
2137 | /* release the lli allocation*/ | |
2138 | coh901318_lli_free(&cohc->base->pool, &cohd->lli); | |
2139 | ||
2140 | /* return desc to free-list */ | |
2141 | coh901318_desc_remove(cohd); | |
2142 | coh901318_desc_free(cohc, cohd); | |
2143 | } | |
2144 | ||
2145 | ||
2146 | cohc->nbr_active_done = 0; | |
2147 | cohc->busy = 0; | |
2148 | ||
2149 | spin_unlock_irqrestore(&cohc->lock, flags); | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
61f135b9 LW |
2154 | static int coh901318_alloc_chan_resources(struct dma_chan *chan) |
2155 | { | |
2156 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
84c8447c | 2157 | unsigned long flags; |
61f135b9 LW |
2158 | |
2159 | dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n", | |
2160 | __func__, cohc->id); | |
2161 | ||
2162 | if (chan->client_count > 1) | |
2163 | return -EBUSY; | |
2164 | ||
84c8447c LW |
2165 | spin_lock_irqsave(&cohc->lock, flags); |
2166 | ||
61f135b9 LW |
2167 | coh901318_config(cohc, NULL); |
2168 | ||
2169 | cohc->allocated = 1; | |
d3ee98cd | 2170 | dma_cookie_init(chan); |
61f135b9 | 2171 | |
84c8447c LW |
2172 | spin_unlock_irqrestore(&cohc->lock, flags); |
2173 | ||
61f135b9 LW |
2174 | return 1; |
2175 | } | |
2176 | ||
2177 | static void | |
2178 | coh901318_free_chan_resources(struct dma_chan *chan) | |
2179 | { | |
2180 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
2181 | int channel = cohc->id; | |
2182 | unsigned long flags; | |
2183 | ||
2184 | spin_lock_irqsave(&cohc->lock, flags); | |
2185 | ||
2186 | /* Disable HW */ | |
2187 | writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG + | |
2188 | COH901318_CX_CFG_SPACING*channel); | |
2189 | writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL + | |
2190 | COH901318_CX_CTRL_SPACING*channel); | |
2191 | ||
2192 | cohc->allocated = 0; | |
2193 | ||
2194 | spin_unlock_irqrestore(&cohc->lock, flags); | |
2195 | ||
6782af11 | 2196 | coh901318_terminate_all(chan); |
61f135b9 LW |
2197 | } |
2198 | ||
2199 | ||
2200 | static dma_cookie_t | |
2201 | coh901318_tx_submit(struct dma_async_tx_descriptor *tx) | |
2202 | { | |
2203 | struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc, | |
2204 | desc); | |
2205 | struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); | |
2206 | unsigned long flags; | |
884485e1 | 2207 | dma_cookie_t cookie; |
61f135b9 LW |
2208 | |
2209 | spin_lock_irqsave(&cohc->lock, flags); | |
884485e1 | 2210 | cookie = dma_cookie_assign(tx); |
61f135b9 LW |
2211 | |
2212 | coh901318_desc_queue(cohc, cohd); | |
2213 | ||
2214 | spin_unlock_irqrestore(&cohc->lock, flags); | |
2215 | ||
884485e1 | 2216 | return cookie; |
61f135b9 LW |
2217 | } |
2218 | ||
2219 | static struct dma_async_tx_descriptor * | |
2220 | coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
2221 | size_t size, unsigned long flags) | |
2222 | { | |
cecd87da | 2223 | struct coh901318_lli *lli; |
61f135b9 LW |
2224 | struct coh901318_desc *cohd; |
2225 | unsigned long flg; | |
2226 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
2227 | int lli_len; | |
2228 | u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; | |
b87108a7 | 2229 | int ret; |
61f135b9 LW |
2230 | |
2231 | spin_lock_irqsave(&cohc->lock, flg); | |
2232 | ||
2233 | dev_vdbg(COHC_2_DEV(cohc), | |
6d82e05b | 2234 | "[%s] channel %d src %pad dest %pad size %zu\n", |
3fd38662 | 2235 | __func__, cohc->id, &src, &dest, size); |
61f135b9 LW |
2236 | |
2237 | if (flags & DMA_PREP_INTERRUPT) | |
2238 | /* Trigger interrupt after last lli */ | |
2239 | ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; | |
2240 | ||
2241 | lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT; | |
2242 | if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size) | |
2243 | lli_len++; | |
2244 | ||
cecd87da | 2245 | lli = coh901318_lli_alloc(&cohc->base->pool, lli_len); |
61f135b9 | 2246 | |
cecd87da | 2247 | if (lli == NULL) |
61f135b9 LW |
2248 | goto err; |
2249 | ||
b87108a7 | 2250 | ret = coh901318_lli_fill_memcpy( |
cecd87da | 2251 | &cohc->base->pool, lli, src, size, dest, |
b87108a7 LW |
2252 | cohc_chan_param(cohc)->ctrl_lli_chained, |
2253 | ctrl_last); | |
2254 | if (ret) | |
2255 | goto err; | |
61f135b9 | 2256 | |
cecd87da | 2257 | COH_DBG(coh901318_list_print(cohc, lli)); |
61f135b9 | 2258 | |
b87108a7 LW |
2259 | /* Pick a descriptor to handle this transfer */ |
2260 | cohd = coh901318_desc_get(cohc); | |
cecd87da | 2261 | cohd->lli = lli; |
b87108a7 | 2262 | cohd->flags = flags; |
61f135b9 LW |
2263 | cohd->desc.tx_submit = coh901318_tx_submit; |
2264 | ||
2265 | spin_unlock_irqrestore(&cohc->lock, flg); | |
2266 | ||
2267 | return &cohd->desc; | |
2268 | err: | |
2269 | spin_unlock_irqrestore(&cohc->lock, flg); | |
2270 | return NULL; | |
2271 | } | |
2272 | ||
2273 | static struct dma_async_tx_descriptor * | |
2274 | coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2275 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2276 | unsigned long flags, void *context) |
61f135b9 LW |
2277 | { |
2278 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
cecd87da | 2279 | struct coh901318_lli *lli; |
61f135b9 | 2280 | struct coh901318_desc *cohd; |
516fd430 | 2281 | const struct coh901318_params *params; |
61f135b9 LW |
2282 | struct scatterlist *sg; |
2283 | int len = 0; | |
2284 | int size; | |
2285 | int i; | |
2286 | u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; | |
2287 | u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; | |
2288 | u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; | |
516fd430 | 2289 | u32 config; |
61f135b9 | 2290 | unsigned long flg; |
0b58828c | 2291 | int ret; |
61f135b9 LW |
2292 | |
2293 | if (!sgl) | |
2294 | goto out; | |
fdaf9c4b | 2295 | if (sg_dma_len(sgl) == 0) |
61f135b9 LW |
2296 | goto out; |
2297 | ||
2298 | spin_lock_irqsave(&cohc->lock, flg); | |
2299 | ||
2300 | dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n", | |
2301 | __func__, sg_len, direction); | |
2302 | ||
2303 | if (flags & DMA_PREP_INTERRUPT) | |
2304 | /* Trigger interrupt after last lli */ | |
2305 | ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; | |
2306 | ||
516fd430 LW |
2307 | params = cohc_chan_param(cohc); |
2308 | config = params->config; | |
128f904a LW |
2309 | /* |
2310 | * Add runtime-specific control on top, make | |
2311 | * sure the bits you set per peripheral channel are | |
2312 | * cleared in the default config from the platform. | |
2313 | */ | |
9aab4d6f LW |
2314 | ctrl_chained |= cohc->ctrl; |
2315 | ctrl_last |= cohc->ctrl; | |
2316 | ctrl |= cohc->ctrl; | |
516fd430 | 2317 | |
db8196df | 2318 | if (direction == DMA_MEM_TO_DEV) { |
61f135b9 LW |
2319 | u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | |
2320 | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; | |
2321 | ||
516fd430 | 2322 | config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY; |
61f135b9 LW |
2323 | ctrl_chained |= tx_flags; |
2324 | ctrl_last |= tx_flags; | |
2325 | ctrl |= tx_flags; | |
db8196df | 2326 | } else if (direction == DMA_DEV_TO_MEM) { |
61f135b9 LW |
2327 | u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | |
2328 | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; | |
2329 | ||
516fd430 | 2330 | config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY; |
61f135b9 LW |
2331 | ctrl_chained |= rx_flags; |
2332 | ctrl_last |= rx_flags; | |
2333 | ctrl |= rx_flags; | |
2334 | } else | |
2335 | goto err_direction; | |
2336 | ||
61f135b9 LW |
2337 | /* The dma only supports transmitting packages up to |
2338 | * MAX_DMA_PACKET_SIZE. Calculate to total number of | |
2339 | * dma elemts required to send the entire sg list | |
2340 | */ | |
2341 | for_each_sg(sgl, sg, sg_len, i) { | |
2342 | unsigned int factor; | |
2343 | size = sg_dma_len(sg); | |
2344 | ||
2345 | if (size <= MAX_DMA_PACKET_SIZE) { | |
2346 | len++; | |
2347 | continue; | |
2348 | } | |
2349 | ||
2350 | factor = size >> MAX_DMA_PACKET_SIZE_SHIFT; | |
2351 | if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size) | |
2352 | factor++; | |
2353 | ||
2354 | len += factor; | |
2355 | } | |
2356 | ||
848ad121 | 2357 | pr_debug("Allocate %d lli:s for this transfer\n", len); |
cecd87da | 2358 | lli = coh901318_lli_alloc(&cohc->base->pool, len); |
61f135b9 | 2359 | |
cecd87da | 2360 | if (lli == NULL) |
61f135b9 LW |
2361 | goto err_dma_alloc; |
2362 | ||
cecd87da LW |
2363 | /* initiate allocated lli list */ |
2364 | ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, | |
9aab4d6f | 2365 | cohc->addr, |
0b58828c LW |
2366 | ctrl_chained, |
2367 | ctrl, | |
2368 | ctrl_last, | |
2369 | direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); | |
2370 | if (ret) | |
2371 | goto err_lli_fill; | |
61f135b9 | 2372 | |
128f904a | 2373 | |
cecd87da | 2374 | COH_DBG(coh901318_list_print(cohc, lli)); |
61f135b9 | 2375 | |
b87108a7 LW |
2376 | /* Pick a descriptor to handle this transfer */ |
2377 | cohd = coh901318_desc_get(cohc); | |
b89243dd LW |
2378 | cohd->head_config = config; |
2379 | /* | |
2380 | * Set the default head ctrl for the channel to the one from the | |
2381 | * lli, things may have changed due to odd buffer alignment | |
2382 | * etc. | |
2383 | */ | |
2384 | cohd->head_ctrl = lli->control; | |
b87108a7 LW |
2385 | cohd->dir = direction; |
2386 | cohd->flags = flags; | |
2387 | cohd->desc.tx_submit = coh901318_tx_submit; | |
cecd87da | 2388 | cohd->lli = lli; |
b87108a7 | 2389 | |
61f135b9 LW |
2390 | spin_unlock_irqrestore(&cohc->lock, flg); |
2391 | ||
2392 | return &cohd->desc; | |
0b58828c | 2393 | err_lli_fill: |
61f135b9 LW |
2394 | err_dma_alloc: |
2395 | err_direction: | |
61f135b9 LW |
2396 | spin_unlock_irqrestore(&cohc->lock, flg); |
2397 | out: | |
2398 | return NULL; | |
2399 | } | |
2400 | ||
2401 | static enum dma_status | |
07934481 LW |
2402 | coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
2403 | struct dma_tx_state *txstate) | |
61f135b9 LW |
2404 | { |
2405 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
96a2af41 | 2406 | enum dma_status ret; |
61f135b9 | 2407 | |
96a2af41 | 2408 | ret = dma_cookie_status(chan, cookie, txstate); |
95b0aa3e | 2409 | if (ret == DMA_COMPLETE || !txstate) |
9b562639 AS |
2410 | return ret; |
2411 | ||
96a2af41 | 2412 | dma_set_residue(txstate, coh901318_get_bytes_left(chan)); |
61f135b9 | 2413 | |
07934481 LW |
2414 | if (ret == DMA_IN_PROGRESS && cohc->stopped) |
2415 | ret = DMA_PAUSED; | |
61f135b9 LW |
2416 | |
2417 | return ret; | |
2418 | } | |
2419 | ||
2420 | static void | |
2421 | coh901318_issue_pending(struct dma_chan *chan) | |
2422 | { | |
2423 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
2424 | unsigned long flags; | |
2425 | ||
2426 | spin_lock_irqsave(&cohc->lock, flags); | |
2427 | ||
cecd87da LW |
2428 | /* |
2429 | * Busy means that pending jobs are already being processed, | |
2430 | * and then there is no point in starting the queue: the | |
2431 | * terminal count interrupt on the channel will take the next | |
2432 | * job on the queue and execute it anyway. | |
2433 | */ | |
61f135b9 LW |
2434 | if (!cohc->busy) |
2435 | coh901318_queue_start(cohc); | |
2436 | ||
2437 | spin_unlock_irqrestore(&cohc->lock, flags); | |
2438 | } | |
2439 | ||
128f904a LW |
2440 | /* |
2441 | * Here we wrap in the runtime dma control interface | |
2442 | */ | |
2443 | struct burst_table { | |
2444 | int burst_8bit; | |
2445 | int burst_16bit; | |
2446 | int burst_32bit; | |
2447 | u32 reg; | |
2448 | }; | |
2449 | ||
2450 | static const struct burst_table burst_sizes[] = { | |
2451 | { | |
2452 | .burst_8bit = 64, | |
2453 | .burst_16bit = 32, | |
2454 | .burst_32bit = 16, | |
2455 | .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES, | |
2456 | }, | |
2457 | { | |
2458 | .burst_8bit = 48, | |
2459 | .burst_16bit = 24, | |
2460 | .burst_32bit = 12, | |
2461 | .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES, | |
2462 | }, | |
2463 | { | |
2464 | .burst_8bit = 32, | |
2465 | .burst_16bit = 16, | |
2466 | .burst_32bit = 8, | |
2467 | .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES, | |
2468 | }, | |
2469 | { | |
2470 | .burst_8bit = 16, | |
2471 | .burst_16bit = 8, | |
2472 | .burst_32bit = 4, | |
2473 | .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES, | |
2474 | }, | |
2475 | { | |
2476 | .burst_8bit = 8, | |
2477 | .burst_16bit = 4, | |
2478 | .burst_32bit = 2, | |
2479 | .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES, | |
2480 | }, | |
2481 | { | |
2482 | .burst_8bit = 4, | |
2483 | .burst_16bit = 2, | |
2484 | .burst_32bit = 1, | |
2485 | .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES, | |
2486 | }, | |
2487 | { | |
2488 | .burst_8bit = 2, | |
2489 | .burst_16bit = 1, | |
2490 | .burst_32bit = 0, | |
2491 | .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES, | |
2492 | }, | |
2493 | { | |
2494 | .burst_8bit = 1, | |
2495 | .burst_16bit = 0, | |
2496 | .burst_32bit = 0, | |
2497 | .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE, | |
2498 | }, | |
2499 | }; | |
2500 | ||
4d76bbed AB |
2501 | static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan, |
2502 | struct dma_slave_config *config) | |
128f904a LW |
2503 | { |
2504 | struct coh901318_chan *cohc = to_coh901318_chan(chan); | |
2505 | dma_addr_t addr; | |
2506 | enum dma_slave_buswidth addr_width; | |
2507 | u32 maxburst; | |
9aab4d6f | 2508 | u32 ctrl = 0; |
128f904a LW |
2509 | int i = 0; |
2510 | ||
2511 | /* We only support mem to per or per to mem transfers */ | |
db8196df | 2512 | if (config->direction == DMA_DEV_TO_MEM) { |
128f904a LW |
2513 | addr = config->src_addr; |
2514 | addr_width = config->src_addr_width; | |
2515 | maxburst = config->src_maxburst; | |
db8196df | 2516 | } else if (config->direction == DMA_MEM_TO_DEV) { |
128f904a LW |
2517 | addr = config->dst_addr; |
2518 | addr_width = config->dst_addr_width; | |
2519 | maxburst = config->dst_maxburst; | |
2520 | } else { | |
2521 | dev_err(COHC_2_DEV(cohc), "illegal channel mode\n"); | |
4d76bbed | 2522 | return -EINVAL; |
128f904a LW |
2523 | } |
2524 | ||
2525 | dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n", | |
2526 | addr_width); | |
2527 | switch (addr_width) { | |
2528 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9aab4d6f | 2529 | ctrl |= |
128f904a LW |
2530 | COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS | |
2531 | COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS; | |
2532 | ||
2533 | while (i < ARRAY_SIZE(burst_sizes)) { | |
2534 | if (burst_sizes[i].burst_8bit <= maxburst) | |
2535 | break; | |
2536 | i++; | |
2537 | } | |
2538 | ||
2539 | break; | |
2540 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9aab4d6f | 2541 | ctrl |= |
128f904a LW |
2542 | COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS | |
2543 | COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS; | |
2544 | ||
2545 | while (i < ARRAY_SIZE(burst_sizes)) { | |
2546 | if (burst_sizes[i].burst_16bit <= maxburst) | |
2547 | break; | |
2548 | i++; | |
2549 | } | |
2550 | ||
2551 | break; | |
2552 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2553 | /* Direction doesn't matter here, it's 32/32 bits */ | |
9aab4d6f | 2554 | ctrl |= |
128f904a LW |
2555 | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | |
2556 | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS; | |
2557 | ||
2558 | while (i < ARRAY_SIZE(burst_sizes)) { | |
2559 | if (burst_sizes[i].burst_32bit <= maxburst) | |
2560 | break; | |
2561 | i++; | |
2562 | } | |
2563 | ||
2564 | break; | |
2565 | default: | |
2566 | dev_err(COHC_2_DEV(cohc), | |
2567 | "bad runtimeconfig: alien address width\n"); | |
4d76bbed | 2568 | return -EINVAL; |
128f904a LW |
2569 | } |
2570 | ||
9aab4d6f | 2571 | ctrl |= burst_sizes[i].reg; |
128f904a LW |
2572 | dev_dbg(COHC_2_DEV(cohc), |
2573 | "selected burst size %d bytes for address width %d bytes, maxburst %d\n", | |
2574 | burst_sizes[i].burst_8bit, addr_width, maxburst); | |
2575 | ||
9aab4d6f LW |
2576 | cohc->addr = addr; |
2577 | cohc->ctrl = ctrl; | |
4d76bbed AB |
2578 | |
2579 | return 0; | |
128f904a LW |
2580 | } |
2581 | ||
4d76bbed AB |
2582 | static void coh901318_base_init(struct dma_device *dma, const int *pick_chans, |
2583 | struct coh901318_base *base) | |
61f135b9 LW |
2584 | { |
2585 | int chans_i; | |
2586 | int i = 0; | |
2587 | struct coh901318_chan *cohc; | |
2588 | ||
2589 | INIT_LIST_HEAD(&dma->channels); | |
2590 | ||
2591 | for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { | |
2592 | for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { | |
2593 | cohc = &base->chans[i]; | |
2594 | ||
2595 | cohc->base = base; | |
2596 | cohc->chan.device = dma; | |
2597 | cohc->id = i; | |
2598 | ||
2599 | /* TODO: do we really need this lock if only one | |
2600 | * client is connected to each channel? | |
2601 | */ | |
2602 | ||
2603 | spin_lock_init(&cohc->lock); | |
2604 | ||
61f135b9 LW |
2605 | cohc->nbr_active_done = 0; |
2606 | cohc->busy = 0; | |
2607 | INIT_LIST_HEAD(&cohc->free); | |
2608 | INIT_LIST_HEAD(&cohc->active); | |
2609 | INIT_LIST_HEAD(&cohc->queue); | |
2610 | ||
2611 | tasklet_init(&cohc->tasklet, dma_tasklet, | |
2612 | (unsigned long) cohc); | |
2613 | ||
2614 | list_add_tail(&cohc->chan.device_node, | |
2615 | &dma->channels); | |
2616 | } | |
2617 | } | |
2618 | } | |
2619 | ||
2620 | static int __init coh901318_probe(struct platform_device *pdev) | |
2621 | { | |
2622 | int err = 0; | |
61f135b9 LW |
2623 | struct coh901318_base *base; |
2624 | int irq; | |
2625 | struct resource *io; | |
2626 | ||
2627 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2628 | if (!io) | |
f7ceb362 | 2629 | return -ENODEV; |
61f135b9 LW |
2630 | |
2631 | /* Map DMA controller registers to virtual memory */ | |
f7ceb362 LW |
2632 | if (devm_request_mem_region(&pdev->dev, |
2633 | io->start, | |
2634 | resource_size(io), | |
2635 | pdev->dev.driver->name) == NULL) | |
2636 | return -ENOMEM; | |
61f135b9 | 2637 | |
f7ceb362 LW |
2638 | base = devm_kzalloc(&pdev->dev, |
2639 | ALIGN(sizeof(struct coh901318_base), 4) + | |
73b31eae | 2640 | U300_DMA_CHANNELS * |
f7ceb362 LW |
2641 | sizeof(struct coh901318_chan), |
2642 | GFP_KERNEL); | |
61f135b9 | 2643 | if (!base) |
f7ceb362 | 2644 | return -ENOMEM; |
61f135b9 LW |
2645 | |
2646 | base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4); | |
2647 | ||
f7ceb362 LW |
2648 | base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io)); |
2649 | if (!base->virtbase) | |
2650 | return -ENOMEM; | |
61f135b9 LW |
2651 | |
2652 | base->dev = &pdev->dev; | |
61f135b9 LW |
2653 | spin_lock_init(&base->pm.lock); |
2654 | base->pm.started_channels = 0; | |
2655 | ||
2656 | COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base); | |
2657 | ||
61f135b9 LW |
2658 | irq = platform_get_irq(pdev, 0); |
2659 | if (irq < 0) | |
f7ceb362 LW |
2660 | return irq; |
2661 | ||
05864648 | 2662 | err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0, |
f7ceb362 LW |
2663 | "coh901318", base); |
2664 | if (err) | |
2665 | return err; | |
61f135b9 | 2666 | |
7bb45f66 VK |
2667 | base->irq = irq; |
2668 | ||
61f135b9 LW |
2669 | err = coh901318_pool_create(&base->pool, &pdev->dev, |
2670 | sizeof(struct coh901318_lli), | |
2671 | 32); | |
2672 | if (err) | |
f7ceb362 | 2673 | return err; |
61f135b9 LW |
2674 | |
2675 | /* init channels for device transfers */ | |
73b31eae | 2676 | coh901318_base_init(&base->dma_slave, dma_slave_channels, |
61f135b9 LW |
2677 | base); |
2678 | ||
2679 | dma_cap_zero(base->dma_slave.cap_mask); | |
2680 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
2681 | ||
2682 | base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; | |
2683 | base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; | |
2684 | base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; | |
07934481 | 2685 | base->dma_slave.device_tx_status = coh901318_tx_status; |
61f135b9 | 2686 | base->dma_slave.device_issue_pending = coh901318_issue_pending; |
6782af11 MR |
2687 | base->dma_slave.device_config = coh901318_dma_set_runtimeconfig; |
2688 | base->dma_slave.device_pause = coh901318_pause; | |
2689 | base->dma_slave.device_resume = coh901318_resume; | |
2690 | base->dma_slave.device_terminate_all = coh901318_terminate_all; | |
61f135b9 LW |
2691 | base->dma_slave.dev = &pdev->dev; |
2692 | ||
2693 | err = dma_async_device_register(&base->dma_slave); | |
2694 | ||
2695 | if (err) | |
2696 | goto err_register_slave; | |
2697 | ||
2698 | /* init channels for memcpy */ | |
73b31eae | 2699 | coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels, |
61f135b9 LW |
2700 | base); |
2701 | ||
2702 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2703 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
2704 | ||
2705 | base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; | |
2706 | base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; | |
2707 | base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; | |
07934481 | 2708 | base->dma_memcpy.device_tx_status = coh901318_tx_status; |
61f135b9 | 2709 | base->dma_memcpy.device_issue_pending = coh901318_issue_pending; |
6782af11 MR |
2710 | base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig; |
2711 | base->dma_memcpy.device_pause = coh901318_pause; | |
2712 | base->dma_memcpy.device_resume = coh901318_resume; | |
2713 | base->dma_memcpy.device_terminate_all = coh901318_terminate_all; | |
61f135b9 | 2714 | base->dma_memcpy.dev = &pdev->dev; |
516fd430 LW |
2715 | /* |
2716 | * This controller can only access address at even 32bit boundaries, | |
2717 | * i.e. 2^2 | |
2718 | */ | |
77a68e56 | 2719 | base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES; |
61f135b9 LW |
2720 | err = dma_async_device_register(&base->dma_memcpy); |
2721 | ||
2722 | if (err) | |
2723 | goto err_register_memcpy; | |
2724 | ||
faadc6e3 LW |
2725 | err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate, |
2726 | base); | |
2727 | if (err) | |
2728 | goto err_register_of_dma; | |
2729 | ||
f7ceb362 | 2730 | platform_set_drvdata(pdev, base); |
c021d835 VK |
2731 | dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%p\n", |
2732 | base->virtbase); | |
61f135b9 LW |
2733 | |
2734 | return err; | |
2735 | ||
faadc6e3 LW |
2736 | err_register_of_dma: |
2737 | dma_async_device_unregister(&base->dma_memcpy); | |
61f135b9 LW |
2738 | err_register_memcpy: |
2739 | dma_async_device_unregister(&base->dma_slave); | |
2740 | err_register_slave: | |
2741 | coh901318_pool_destroy(&base->pool); | |
61f135b9 LW |
2742 | return err; |
2743 | } | |
85abae17 VK |
2744 | static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans) |
2745 | { | |
2746 | int chans_i; | |
2747 | int i = 0; | |
2748 | struct coh901318_chan *cohc; | |
2749 | ||
2750 | for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { | |
2751 | for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { | |
2752 | cohc = &base->chans[i]; | |
2753 | ||
2754 | tasklet_kill(&cohc->tasklet); | |
2755 | } | |
2756 | } | |
2757 | ||
2758 | } | |
61f135b9 | 2759 | |
1d1bbd30 | 2760 | static int coh901318_remove(struct platform_device *pdev) |
61f135b9 LW |
2761 | { |
2762 | struct coh901318_base *base = platform_get_drvdata(pdev); | |
2763 | ||
7bb45f66 VK |
2764 | devm_free_irq(&pdev->dev, base->irq, base); |
2765 | ||
85abae17 VK |
2766 | coh901318_base_remove(base, dma_slave_channels); |
2767 | coh901318_base_remove(base, dma_memcpy_channels); | |
2768 | ||
faadc6e3 | 2769 | of_dma_controller_free(pdev->dev.of_node); |
61f135b9 LW |
2770 | dma_async_device_unregister(&base->dma_memcpy); |
2771 | dma_async_device_unregister(&base->dma_slave); | |
2772 | coh901318_pool_destroy(&base->pool); | |
61f135b9 LW |
2773 | return 0; |
2774 | } | |
2775 | ||
faadc6e3 LW |
2776 | static const struct of_device_id coh901318_dt_match[] = { |
2777 | { .compatible = "stericsson,coh901318" }, | |
2778 | {}, | |
2779 | }; | |
61f135b9 LW |
2780 | |
2781 | static struct platform_driver coh901318_driver = { | |
1d1bbd30 | 2782 | .remove = coh901318_remove, |
61f135b9 LW |
2783 | .driver = { |
2784 | .name = "coh901318", | |
faadc6e3 | 2785 | .of_match_table = coh901318_dt_match, |
61f135b9 LW |
2786 | }, |
2787 | }; | |
2788 | ||
f57b7cb4 | 2789 | static int __init coh901318_init(void) |
61f135b9 LW |
2790 | { |
2791 | return platform_driver_probe(&coh901318_driver, coh901318_probe); | |
2792 | } | |
a0eb221a | 2793 | subsys_initcall(coh901318_init); |
61f135b9 | 2794 | |
f57b7cb4 | 2795 | static void __exit coh901318_exit(void) |
61f135b9 LW |
2796 | { |
2797 | platform_driver_unregister(&coh901318_driver); | |
2798 | } | |
2799 | module_exit(coh901318_exit); | |
2800 | ||
2801 | MODULE_LICENSE("GPL"); | |
2802 | MODULE_AUTHOR("Per Friden"); |