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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * This code implements the DMA subsystem. It provides a HW-neutral interface | |
24 | * for other kernel code to use asynchronous memory copy capabilities, | |
25 | * if present, and allows different HW DMA drivers to register as providing | |
26 | * this capability. | |
27 | * | |
28 | * Due to the fact we are accelerating what is already a relatively fast | |
29 | * operation, the code goes to great lengths to avoid additional overhead, | |
30 | * such as locking. | |
31 | * | |
32 | * LOCKING: | |
33 | * | |
aa1e6f1a DW |
34 | * The subsystem keeps a global list of dma_device structs it is protected by a |
35 | * mutex, dma_list_mutex. | |
c13c8260 | 36 | * |
f27c580c DW |
37 | * A subsystem can get access to a channel by calling dmaengine_get() followed |
38 | * by dma_find_channel(), or if it has need for an exclusive channel it can call | |
39 | * dma_request_channel(). Once a channel is allocated a reference is taken | |
40 | * against its corresponding driver to disable removal. | |
41 | * | |
c13c8260 CL |
42 | * Each device has a channels list, which runs unlocked but is never modified |
43 | * once the device is registered, it's just setup by the driver. | |
44 | * | |
f27c580c | 45 | * See Documentation/dmaengine.txt for more details |
c13c8260 CL |
46 | */ |
47 | ||
63433250 JP |
48 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
49 | ||
b7f080cf | 50 | #include <linux/dma-mapping.h> |
c13c8260 CL |
51 | #include <linux/init.h> |
52 | #include <linux/module.h> | |
7405f74b | 53 | #include <linux/mm.h> |
c13c8260 CL |
54 | #include <linux/device.h> |
55 | #include <linux/dmaengine.h> | |
56 | #include <linux/hardirq.h> | |
57 | #include <linux/spinlock.h> | |
58 | #include <linux/percpu.h> | |
59 | #include <linux/rcupdate.h> | |
60 | #include <linux/mutex.h> | |
7405f74b | 61 | #include <linux/jiffies.h> |
2ba05622 | 62 | #include <linux/rculist.h> |
864498aa | 63 | #include <linux/idr.h> |
5a0e3ad6 | 64 | #include <linux/slab.h> |
c13c8260 CL |
65 | |
66 | static DEFINE_MUTEX(dma_list_mutex); | |
21ef4b8b | 67 | static DEFINE_IDR(dma_idr); |
c13c8260 | 68 | static LIST_HEAD(dma_device_list); |
6f49a57a | 69 | static long dmaengine_ref_count; |
c13c8260 CL |
70 | |
71 | /* --- sysfs implementation --- */ | |
72 | ||
41d5e59c DW |
73 | /** |
74 | * dev_to_dma_chan - convert a device pointer to the its sysfs container object | |
75 | * @dev - device node | |
76 | * | |
77 | * Must be called under dma_list_mutex | |
78 | */ | |
79 | static struct dma_chan *dev_to_dma_chan(struct device *dev) | |
80 | { | |
81 | struct dma_chan_dev *chan_dev; | |
82 | ||
83 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
84 | return chan_dev->chan; | |
85 | } | |
86 | ||
891f78ea | 87 | static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf) |
c13c8260 | 88 | { |
41d5e59c | 89 | struct dma_chan *chan; |
c13c8260 CL |
90 | unsigned long count = 0; |
91 | int i; | |
41d5e59c | 92 | int err; |
c13c8260 | 93 | |
41d5e59c DW |
94 | mutex_lock(&dma_list_mutex); |
95 | chan = dev_to_dma_chan(dev); | |
96 | if (chan) { | |
97 | for_each_possible_cpu(i) | |
98 | count += per_cpu_ptr(chan->local, i)->memcpy_count; | |
99 | err = sprintf(buf, "%lu\n", count); | |
100 | } else | |
101 | err = -ENODEV; | |
102 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 103 | |
41d5e59c | 104 | return err; |
c13c8260 CL |
105 | } |
106 | ||
891f78ea TJ |
107 | static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr, |
108 | char *buf) | |
c13c8260 | 109 | { |
41d5e59c | 110 | struct dma_chan *chan; |
c13c8260 CL |
111 | unsigned long count = 0; |
112 | int i; | |
41d5e59c | 113 | int err; |
c13c8260 | 114 | |
41d5e59c DW |
115 | mutex_lock(&dma_list_mutex); |
116 | chan = dev_to_dma_chan(dev); | |
117 | if (chan) { | |
118 | for_each_possible_cpu(i) | |
119 | count += per_cpu_ptr(chan->local, i)->bytes_transferred; | |
120 | err = sprintf(buf, "%lu\n", count); | |
121 | } else | |
122 | err = -ENODEV; | |
123 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 124 | |
41d5e59c | 125 | return err; |
c13c8260 CL |
126 | } |
127 | ||
891f78ea | 128 | static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf) |
c13c8260 | 129 | { |
41d5e59c DW |
130 | struct dma_chan *chan; |
131 | int err; | |
c13c8260 | 132 | |
41d5e59c DW |
133 | mutex_lock(&dma_list_mutex); |
134 | chan = dev_to_dma_chan(dev); | |
135 | if (chan) | |
136 | err = sprintf(buf, "%d\n", chan->client_count); | |
137 | else | |
138 | err = -ENODEV; | |
139 | mutex_unlock(&dma_list_mutex); | |
140 | ||
141 | return err; | |
c13c8260 CL |
142 | } |
143 | ||
891f78ea | 144 | static struct device_attribute dma_attrs[] = { |
c13c8260 CL |
145 | __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL), |
146 | __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL), | |
147 | __ATTR(in_use, S_IRUGO, show_in_use, NULL), | |
148 | __ATTR_NULL | |
149 | }; | |
150 | ||
41d5e59c DW |
151 | static void chan_dev_release(struct device *dev) |
152 | { | |
153 | struct dma_chan_dev *chan_dev; | |
154 | ||
155 | chan_dev = container_of(dev, typeof(*chan_dev), device); | |
864498aa DW |
156 | if (atomic_dec_and_test(chan_dev->idr_ref)) { |
157 | mutex_lock(&dma_list_mutex); | |
158 | idr_remove(&dma_idr, chan_dev->dev_id); | |
159 | mutex_unlock(&dma_list_mutex); | |
160 | kfree(chan_dev->idr_ref); | |
161 | } | |
41d5e59c DW |
162 | kfree(chan_dev); |
163 | } | |
164 | ||
c13c8260 | 165 | static struct class dma_devclass = { |
891f78ea TJ |
166 | .name = "dma", |
167 | .dev_attrs = dma_attrs, | |
41d5e59c | 168 | .dev_release = chan_dev_release, |
c13c8260 CL |
169 | }; |
170 | ||
171 | /* --- client and device registration --- */ | |
172 | ||
59b5ec21 DW |
173 | #define dma_device_satisfies_mask(device, mask) \ |
174 | __dma_device_satisfies_mask((device), &(mask)) | |
d379b01e | 175 | static int |
59b5ec21 | 176 | __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want) |
d379b01e DW |
177 | { |
178 | dma_cap_mask_t has; | |
179 | ||
59b5ec21 | 180 | bitmap_and(has.bits, want->bits, device->cap_mask.bits, |
d379b01e DW |
181 | DMA_TX_TYPE_END); |
182 | return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END); | |
183 | } | |
184 | ||
6f49a57a DW |
185 | static struct module *dma_chan_to_owner(struct dma_chan *chan) |
186 | { | |
187 | return chan->device->dev->driver->owner; | |
188 | } | |
189 | ||
190 | /** | |
191 | * balance_ref_count - catch up the channel reference count | |
192 | * @chan - channel to balance ->client_count versus dmaengine_ref_count | |
193 | * | |
194 | * balance_ref_count must be called under dma_list_mutex | |
195 | */ | |
196 | static void balance_ref_count(struct dma_chan *chan) | |
197 | { | |
198 | struct module *owner = dma_chan_to_owner(chan); | |
199 | ||
200 | while (chan->client_count < dmaengine_ref_count) { | |
201 | __module_get(owner); | |
202 | chan->client_count++; | |
203 | } | |
204 | } | |
205 | ||
206 | /** | |
207 | * dma_chan_get - try to grab a dma channel's parent driver module | |
208 | * @chan - channel to grab | |
209 | * | |
210 | * Must be called under dma_list_mutex | |
211 | */ | |
212 | static int dma_chan_get(struct dma_chan *chan) | |
213 | { | |
214 | int err = -ENODEV; | |
215 | struct module *owner = dma_chan_to_owner(chan); | |
216 | ||
217 | if (chan->client_count) { | |
218 | __module_get(owner); | |
219 | err = 0; | |
220 | } else if (try_module_get(owner)) | |
221 | err = 0; | |
222 | ||
223 | if (err == 0) | |
224 | chan->client_count++; | |
225 | ||
226 | /* allocate upon first client reference */ | |
227 | if (chan->client_count == 1 && err == 0) { | |
aa1e6f1a | 228 | int desc_cnt = chan->device->device_alloc_chan_resources(chan); |
6f49a57a DW |
229 | |
230 | if (desc_cnt < 0) { | |
231 | err = desc_cnt; | |
232 | chan->client_count = 0; | |
233 | module_put(owner); | |
59b5ec21 | 234 | } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) |
6f49a57a DW |
235 | balance_ref_count(chan); |
236 | } | |
237 | ||
238 | return err; | |
239 | } | |
240 | ||
241 | /** | |
242 | * dma_chan_put - drop a reference to a dma channel's parent driver module | |
243 | * @chan - channel to release | |
244 | * | |
245 | * Must be called under dma_list_mutex | |
246 | */ | |
247 | static void dma_chan_put(struct dma_chan *chan) | |
248 | { | |
249 | if (!chan->client_count) | |
250 | return; /* this channel failed alloc_chan_resources */ | |
251 | chan->client_count--; | |
252 | module_put(dma_chan_to_owner(chan)); | |
253 | if (chan->client_count == 0) | |
254 | chan->device->device_free_chan_resources(chan); | |
255 | } | |
256 | ||
7405f74b DW |
257 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) |
258 | { | |
259 | enum dma_status status; | |
260 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); | |
261 | ||
262 | dma_async_issue_pending(chan); | |
263 | do { | |
264 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); | |
265 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
63433250 | 266 | pr_err("%s: timeout!\n", __func__); |
7405f74b DW |
267 | return DMA_ERROR; |
268 | } | |
269 | } while (status == DMA_IN_PROGRESS); | |
270 | ||
271 | return status; | |
272 | } | |
273 | EXPORT_SYMBOL(dma_sync_wait); | |
274 | ||
bec08513 DW |
275 | /** |
276 | * dma_cap_mask_all - enable iteration over all operation types | |
277 | */ | |
278 | static dma_cap_mask_t dma_cap_mask_all; | |
279 | ||
280 | /** | |
281 | * dma_chan_tbl_ent - tracks channel allocations per core/operation | |
282 | * @chan - associated channel for this entry | |
283 | */ | |
284 | struct dma_chan_tbl_ent { | |
285 | struct dma_chan *chan; | |
286 | }; | |
287 | ||
288 | /** | |
289 | * channel_table - percpu lookup table for memory-to-memory offload providers | |
290 | */ | |
a29d8b8e | 291 | static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END]; |
bec08513 DW |
292 | |
293 | static int __init dma_channel_table_init(void) | |
294 | { | |
295 | enum dma_transaction_type cap; | |
296 | int err = 0; | |
297 | ||
298 | bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END); | |
299 | ||
59b5ec21 DW |
300 | /* 'interrupt', 'private', and 'slave' are channel capabilities, |
301 | * but are not associated with an operation so they do not need | |
302 | * an entry in the channel_table | |
bec08513 DW |
303 | */ |
304 | clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits); | |
59b5ec21 | 305 | clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits); |
bec08513 DW |
306 | clear_bit(DMA_SLAVE, dma_cap_mask_all.bits); |
307 | ||
308 | for_each_dma_cap_mask(cap, dma_cap_mask_all) { | |
309 | channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent); | |
310 | if (!channel_table[cap]) { | |
311 | err = -ENOMEM; | |
312 | break; | |
313 | } | |
314 | } | |
315 | ||
316 | if (err) { | |
63433250 | 317 | pr_err("initialization failure\n"); |
bec08513 DW |
318 | for_each_dma_cap_mask(cap, dma_cap_mask_all) |
319 | if (channel_table[cap]) | |
320 | free_percpu(channel_table[cap]); | |
321 | } | |
322 | ||
323 | return err; | |
324 | } | |
652afc27 | 325 | arch_initcall(dma_channel_table_init); |
bec08513 DW |
326 | |
327 | /** | |
328 | * dma_find_channel - find a channel to carry out the operation | |
329 | * @tx_type: transaction type | |
330 | */ | |
331 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | |
332 | { | |
e7dcaa47 | 333 | return this_cpu_read(channel_table[tx_type]->chan); |
bec08513 DW |
334 | } |
335 | EXPORT_SYMBOL(dma_find_channel); | |
336 | ||
a2bd1140 DJ |
337 | /* |
338 | * net_dma_find_channel - find a channel for net_dma | |
339 | * net_dma has alignment requirements | |
340 | */ | |
341 | struct dma_chan *net_dma_find_channel(void) | |
342 | { | |
343 | struct dma_chan *chan = dma_find_channel(DMA_MEMCPY); | |
344 | if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1)) | |
345 | return NULL; | |
346 | ||
347 | return chan; | |
348 | } | |
349 | EXPORT_SYMBOL(net_dma_find_channel); | |
350 | ||
2ba05622 DW |
351 | /** |
352 | * dma_issue_pending_all - flush all pending operations across all channels | |
353 | */ | |
354 | void dma_issue_pending_all(void) | |
355 | { | |
356 | struct dma_device *device; | |
357 | struct dma_chan *chan; | |
358 | ||
2ba05622 | 359 | rcu_read_lock(); |
59b5ec21 DW |
360 | list_for_each_entry_rcu(device, &dma_device_list, global_node) { |
361 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
362 | continue; | |
2ba05622 DW |
363 | list_for_each_entry(chan, &device->channels, device_node) |
364 | if (chan->client_count) | |
365 | device->device_issue_pending(chan); | |
59b5ec21 | 366 | } |
2ba05622 DW |
367 | rcu_read_unlock(); |
368 | } | |
369 | EXPORT_SYMBOL(dma_issue_pending_all); | |
370 | ||
bec08513 DW |
371 | /** |
372 | * nth_chan - returns the nth channel of the given capability | |
373 | * @cap: capability to match | |
374 | * @n: nth channel desired | |
375 | * | |
376 | * Defaults to returning the channel with the desired capability and the | |
377 | * lowest reference count when 'n' cannot be satisfied. Must be called | |
378 | * under dma_list_mutex. | |
379 | */ | |
380 | static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n) | |
381 | { | |
382 | struct dma_device *device; | |
383 | struct dma_chan *chan; | |
384 | struct dma_chan *ret = NULL; | |
385 | struct dma_chan *min = NULL; | |
386 | ||
387 | list_for_each_entry(device, &dma_device_list, global_node) { | |
59b5ec21 DW |
388 | if (!dma_has_cap(cap, device->cap_mask) || |
389 | dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
bec08513 DW |
390 | continue; |
391 | list_for_each_entry(chan, &device->channels, device_node) { | |
392 | if (!chan->client_count) | |
393 | continue; | |
394 | if (!min) | |
395 | min = chan; | |
396 | else if (chan->table_count < min->table_count) | |
397 | min = chan; | |
398 | ||
399 | if (n-- == 0) { | |
400 | ret = chan; | |
401 | break; /* done */ | |
402 | } | |
403 | } | |
404 | if (ret) | |
405 | break; /* done */ | |
406 | } | |
407 | ||
408 | if (!ret) | |
409 | ret = min; | |
410 | ||
411 | if (ret) | |
412 | ret->table_count++; | |
413 | ||
414 | return ret; | |
415 | } | |
416 | ||
417 | /** | |
418 | * dma_channel_rebalance - redistribute the available channels | |
419 | * | |
420 | * Optimize for cpu isolation (each cpu gets a dedicated channel for an | |
421 | * operation type) in the SMP case, and operation isolation (avoid | |
422 | * multi-tasking channels) in the non-SMP case. Must be called under | |
423 | * dma_list_mutex. | |
424 | */ | |
425 | static void dma_channel_rebalance(void) | |
426 | { | |
427 | struct dma_chan *chan; | |
428 | struct dma_device *device; | |
429 | int cpu; | |
430 | int cap; | |
431 | int n; | |
432 | ||
433 | /* undo the last distribution */ | |
434 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
435 | for_each_possible_cpu(cpu) | |
436 | per_cpu_ptr(channel_table[cap], cpu)->chan = NULL; | |
437 | ||
59b5ec21 DW |
438 | list_for_each_entry(device, &dma_device_list, global_node) { |
439 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
440 | continue; | |
bec08513 DW |
441 | list_for_each_entry(chan, &device->channels, device_node) |
442 | chan->table_count = 0; | |
59b5ec21 | 443 | } |
bec08513 DW |
444 | |
445 | /* don't populate the channel_table if no clients are available */ | |
446 | if (!dmaengine_ref_count) | |
447 | return; | |
448 | ||
449 | /* redistribute available channels */ | |
450 | n = 0; | |
451 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
452 | for_each_online_cpu(cpu) { | |
453 | if (num_possible_cpus() > 1) | |
454 | chan = nth_chan(cap, n++); | |
455 | else | |
456 | chan = nth_chan(cap, -1); | |
457 | ||
458 | per_cpu_ptr(channel_table[cap], cpu)->chan = chan; | |
459 | } | |
460 | } | |
461 | ||
e2346677 DW |
462 | static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev, |
463 | dma_filter_fn fn, void *fn_param) | |
59b5ec21 DW |
464 | { |
465 | struct dma_chan *chan; | |
59b5ec21 DW |
466 | |
467 | if (!__dma_device_satisfies_mask(dev, mask)) { | |
468 | pr_debug("%s: wrong capabilities\n", __func__); | |
469 | return NULL; | |
470 | } | |
471 | /* devices with multiple channels need special handling as we need to | |
472 | * ensure that all channels are either private or public. | |
473 | */ | |
474 | if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask)) | |
475 | list_for_each_entry(chan, &dev->channels, device_node) { | |
476 | /* some channels are already publicly allocated */ | |
477 | if (chan->client_count) | |
478 | return NULL; | |
479 | } | |
480 | ||
481 | list_for_each_entry(chan, &dev->channels, device_node) { | |
482 | if (chan->client_count) { | |
483 | pr_debug("%s: %s busy\n", | |
41d5e59c | 484 | __func__, dma_chan_name(chan)); |
59b5ec21 DW |
485 | continue; |
486 | } | |
e2346677 DW |
487 | if (fn && !fn(chan, fn_param)) { |
488 | pr_debug("%s: %s filter said false\n", | |
489 | __func__, dma_chan_name(chan)); | |
490 | continue; | |
491 | } | |
492 | return chan; | |
59b5ec21 DW |
493 | } |
494 | ||
e2346677 | 495 | return NULL; |
59b5ec21 DW |
496 | } |
497 | ||
498 | /** | |
499 | * dma_request_channel - try to allocate an exclusive channel | |
500 | * @mask: capabilities that the channel must satisfy | |
501 | * @fn: optional callback to disposition available channels | |
502 | * @fn_param: opaque parameter to pass to dma_filter_fn | |
503 | */ | |
504 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param) | |
505 | { | |
506 | struct dma_device *device, *_d; | |
507 | struct dma_chan *chan = NULL; | |
59b5ec21 DW |
508 | int err; |
509 | ||
510 | /* Find a channel */ | |
511 | mutex_lock(&dma_list_mutex); | |
512 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { | |
e2346677 DW |
513 | chan = private_candidate(mask, device, fn, fn_param); |
514 | if (chan) { | |
59b5ec21 DW |
515 | /* Found a suitable channel, try to grab, prep, and |
516 | * return it. We first set DMA_PRIVATE to disable | |
517 | * balance_ref_count as this channel will not be | |
518 | * published in the general-purpose allocator | |
519 | */ | |
520 | dma_cap_set(DMA_PRIVATE, device->cap_mask); | |
0f571515 | 521 | device->privatecnt++; |
59b5ec21 DW |
522 | err = dma_chan_get(chan); |
523 | ||
524 | if (err == -ENODEV) { | |
63433250 JP |
525 | pr_debug("%s: %s module removed\n", |
526 | __func__, dma_chan_name(chan)); | |
59b5ec21 DW |
527 | list_del_rcu(&device->global_node); |
528 | } else if (err) | |
d8b53489 | 529 | pr_debug("%s: failed to get %s: (%d)\n", |
63433250 | 530 | __func__, dma_chan_name(chan), err); |
59b5ec21 DW |
531 | else |
532 | break; | |
0f571515 AN |
533 | if (--device->privatecnt == 0) |
534 | dma_cap_clear(DMA_PRIVATE, device->cap_mask); | |
e2346677 DW |
535 | chan = NULL; |
536 | } | |
59b5ec21 DW |
537 | } |
538 | mutex_unlock(&dma_list_mutex); | |
539 | ||
63433250 JP |
540 | pr_debug("%s: %s (%s)\n", |
541 | __func__, | |
542 | chan ? "success" : "fail", | |
41d5e59c | 543 | chan ? dma_chan_name(chan) : NULL); |
59b5ec21 DW |
544 | |
545 | return chan; | |
546 | } | |
547 | EXPORT_SYMBOL_GPL(__dma_request_channel); | |
548 | ||
549 | void dma_release_channel(struct dma_chan *chan) | |
550 | { | |
551 | mutex_lock(&dma_list_mutex); | |
552 | WARN_ONCE(chan->client_count != 1, | |
553 | "chan reference count %d != 1\n", chan->client_count); | |
554 | dma_chan_put(chan); | |
0f571515 AN |
555 | /* drop PRIVATE cap enabled by __dma_request_channel() */ |
556 | if (--chan->device->privatecnt == 0) | |
557 | dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask); | |
59b5ec21 DW |
558 | mutex_unlock(&dma_list_mutex); |
559 | } | |
560 | EXPORT_SYMBOL_GPL(dma_release_channel); | |
561 | ||
d379b01e | 562 | /** |
209b84a8 | 563 | * dmaengine_get - register interest in dma_channels |
d379b01e | 564 | */ |
209b84a8 | 565 | void dmaengine_get(void) |
d379b01e | 566 | { |
6f49a57a DW |
567 | struct dma_device *device, *_d; |
568 | struct dma_chan *chan; | |
569 | int err; | |
570 | ||
c13c8260 | 571 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
572 | dmaengine_ref_count++; |
573 | ||
574 | /* try to grab channels */ | |
59b5ec21 DW |
575 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { |
576 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
577 | continue; | |
6f49a57a DW |
578 | list_for_each_entry(chan, &device->channels, device_node) { |
579 | err = dma_chan_get(chan); | |
580 | if (err == -ENODEV) { | |
581 | /* module removed before we could use it */ | |
2ba05622 | 582 | list_del_rcu(&device->global_node); |
6f49a57a DW |
583 | break; |
584 | } else if (err) | |
0eb5a358 | 585 | pr_debug("%s: failed to get %s: (%d)\n", |
63433250 | 586 | __func__, dma_chan_name(chan), err); |
6f49a57a | 587 | } |
59b5ec21 | 588 | } |
6f49a57a | 589 | |
bec08513 DW |
590 | /* if this is the first reference and there were channels |
591 | * waiting we need to rebalance to get those channels | |
592 | * incorporated into the channel table | |
593 | */ | |
594 | if (dmaengine_ref_count == 1) | |
595 | dma_channel_rebalance(); | |
c13c8260 | 596 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 597 | } |
209b84a8 | 598 | EXPORT_SYMBOL(dmaengine_get); |
c13c8260 CL |
599 | |
600 | /** | |
209b84a8 | 601 | * dmaengine_put - let dma drivers be removed when ref_count == 0 |
c13c8260 | 602 | */ |
209b84a8 | 603 | void dmaengine_put(void) |
c13c8260 | 604 | { |
d379b01e | 605 | struct dma_device *device; |
c13c8260 CL |
606 | struct dma_chan *chan; |
607 | ||
c13c8260 | 608 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
609 | dmaengine_ref_count--; |
610 | BUG_ON(dmaengine_ref_count < 0); | |
611 | /* drop channel references */ | |
59b5ec21 DW |
612 | list_for_each_entry(device, &dma_device_list, global_node) { |
613 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
614 | continue; | |
6f49a57a DW |
615 | list_for_each_entry(chan, &device->channels, device_node) |
616 | dma_chan_put(chan); | |
59b5ec21 | 617 | } |
c13c8260 | 618 | mutex_unlock(&dma_list_mutex); |
c13c8260 | 619 | } |
209b84a8 | 620 | EXPORT_SYMBOL(dmaengine_put); |
c13c8260 | 621 | |
138f4c35 DW |
622 | static bool device_has_all_tx_types(struct dma_device *device) |
623 | { | |
624 | /* A device that satisfies this test has channels that will never cause | |
625 | * an async_tx channel switch event as all possible operation types can | |
626 | * be handled. | |
627 | */ | |
628 | #ifdef CONFIG_ASYNC_TX_DMA | |
629 | if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask)) | |
630 | return false; | |
631 | #endif | |
632 | ||
633 | #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE) | |
634 | if (!dma_has_cap(DMA_MEMCPY, device->cap_mask)) | |
635 | return false; | |
636 | #endif | |
637 | ||
638 | #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE) | |
639 | if (!dma_has_cap(DMA_MEMSET, device->cap_mask)) | |
640 | return false; | |
641 | #endif | |
642 | ||
643 | #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE) | |
644 | if (!dma_has_cap(DMA_XOR, device->cap_mask)) | |
645 | return false; | |
7b3cc2b1 DW |
646 | |
647 | #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
4499a24d DW |
648 | if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask)) |
649 | return false; | |
138f4c35 | 650 | #endif |
7b3cc2b1 | 651 | #endif |
138f4c35 DW |
652 | |
653 | #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE) | |
654 | if (!dma_has_cap(DMA_PQ, device->cap_mask)) | |
655 | return false; | |
7b3cc2b1 DW |
656 | |
657 | #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA | |
4499a24d DW |
658 | if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask)) |
659 | return false; | |
138f4c35 | 660 | #endif |
7b3cc2b1 | 661 | #endif |
138f4c35 DW |
662 | |
663 | return true; | |
664 | } | |
665 | ||
257b17ca DW |
666 | static int get_dma_id(struct dma_device *device) |
667 | { | |
668 | int rc; | |
669 | ||
670 | idr_retry: | |
671 | if (!idr_pre_get(&dma_idr, GFP_KERNEL)) | |
672 | return -ENOMEM; | |
673 | mutex_lock(&dma_list_mutex); | |
674 | rc = idr_get_new(&dma_idr, NULL, &device->dev_id); | |
675 | mutex_unlock(&dma_list_mutex); | |
676 | if (rc == -EAGAIN) | |
677 | goto idr_retry; | |
678 | else if (rc != 0) | |
679 | return rc; | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
c13c8260 | 684 | /** |
6508871e | 685 | * dma_async_device_register - registers DMA devices found |
c13c8260 CL |
686 | * @device: &dma_device |
687 | */ | |
688 | int dma_async_device_register(struct dma_device *device) | |
689 | { | |
ff487fb7 | 690 | int chancnt = 0, rc; |
c13c8260 | 691 | struct dma_chan* chan; |
864498aa | 692 | atomic_t *idr_ref; |
c13c8260 CL |
693 | |
694 | if (!device) | |
695 | return -ENODEV; | |
696 | ||
7405f74b DW |
697 | /* validate device routines */ |
698 | BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) && | |
699 | !device->device_prep_dma_memcpy); | |
700 | BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) && | |
701 | !device->device_prep_dma_xor); | |
099f53cb DW |
702 | BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) && |
703 | !device->device_prep_dma_xor_val); | |
b2f46fd8 DW |
704 | BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) && |
705 | !device->device_prep_dma_pq); | |
706 | BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) && | |
707 | !device->device_prep_dma_pq_val); | |
7405f74b DW |
708 | BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) && |
709 | !device->device_prep_dma_memset); | |
9b941c66 | 710 | BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) && |
7405f74b | 711 | !device->device_prep_dma_interrupt); |
a86ee03c IS |
712 | BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) && |
713 | !device->device_prep_dma_sg); | |
782bc950 SH |
714 | BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) && |
715 | !device->device_prep_dma_cyclic); | |
dc0ee643 | 716 | BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && |
c3635c78 | 717 | !device->device_control); |
b14dab79 JB |
718 | BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && |
719 | !device->device_prep_interleaved_dma); | |
7405f74b DW |
720 | |
721 | BUG_ON(!device->device_alloc_chan_resources); | |
722 | BUG_ON(!device->device_free_chan_resources); | |
07934481 | 723 | BUG_ON(!device->device_tx_status); |
7405f74b DW |
724 | BUG_ON(!device->device_issue_pending); |
725 | BUG_ON(!device->dev); | |
726 | ||
138f4c35 | 727 | /* note: this only matters in the |
5fc6d897 | 728 | * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case |
138f4c35 DW |
729 | */ |
730 | if (device_has_all_tx_types(device)) | |
731 | dma_cap_set(DMA_ASYNC_TX, device->cap_mask); | |
732 | ||
864498aa DW |
733 | idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL); |
734 | if (!idr_ref) | |
735 | return -ENOMEM; | |
257b17ca DW |
736 | rc = get_dma_id(device); |
737 | if (rc != 0) { | |
738 | kfree(idr_ref); | |
864498aa | 739 | return rc; |
257b17ca DW |
740 | } |
741 | ||
742 | atomic_set(idr_ref, 0); | |
c13c8260 CL |
743 | |
744 | /* represent channels in sysfs. Probably want devs too */ | |
745 | list_for_each_entry(chan, &device->channels, device_node) { | |
257b17ca | 746 | rc = -ENOMEM; |
c13c8260 CL |
747 | chan->local = alloc_percpu(typeof(*chan->local)); |
748 | if (chan->local == NULL) | |
257b17ca | 749 | goto err_out; |
41d5e59c DW |
750 | chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); |
751 | if (chan->dev == NULL) { | |
752 | free_percpu(chan->local); | |
257b17ca DW |
753 | chan->local = NULL; |
754 | goto err_out; | |
41d5e59c | 755 | } |
c13c8260 CL |
756 | |
757 | chan->chan_id = chancnt++; | |
41d5e59c DW |
758 | chan->dev->device.class = &dma_devclass; |
759 | chan->dev->device.parent = device->dev; | |
760 | chan->dev->chan = chan; | |
864498aa DW |
761 | chan->dev->idr_ref = idr_ref; |
762 | chan->dev->dev_id = device->dev_id; | |
763 | atomic_inc(idr_ref); | |
41d5e59c | 764 | dev_set_name(&chan->dev->device, "dma%dchan%d", |
06190d84 | 765 | device->dev_id, chan->chan_id); |
c13c8260 | 766 | |
41d5e59c | 767 | rc = device_register(&chan->dev->device); |
ff487fb7 | 768 | if (rc) { |
ff487fb7 JG |
769 | free_percpu(chan->local); |
770 | chan->local = NULL; | |
257b17ca DW |
771 | kfree(chan->dev); |
772 | atomic_dec(idr_ref); | |
ff487fb7 JG |
773 | goto err_out; |
774 | } | |
7cc5bf9a | 775 | chan->client_count = 0; |
c13c8260 | 776 | } |
59b5ec21 | 777 | device->chancnt = chancnt; |
c13c8260 CL |
778 | |
779 | mutex_lock(&dma_list_mutex); | |
59b5ec21 DW |
780 | /* take references on public channels */ |
781 | if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask)) | |
6f49a57a DW |
782 | list_for_each_entry(chan, &device->channels, device_node) { |
783 | /* if clients are already waiting for channels we need | |
784 | * to take references on their behalf | |
785 | */ | |
786 | if (dma_chan_get(chan) == -ENODEV) { | |
787 | /* note we can only get here for the first | |
788 | * channel as the remaining channels are | |
789 | * guaranteed to get a reference | |
790 | */ | |
791 | rc = -ENODEV; | |
792 | mutex_unlock(&dma_list_mutex); | |
793 | goto err_out; | |
794 | } | |
795 | } | |
2ba05622 | 796 | list_add_tail_rcu(&device->global_node, &dma_device_list); |
0f571515 AN |
797 | if (dma_has_cap(DMA_PRIVATE, device->cap_mask)) |
798 | device->privatecnt++; /* Always private */ | |
bec08513 | 799 | dma_channel_rebalance(); |
c13c8260 CL |
800 | mutex_unlock(&dma_list_mutex); |
801 | ||
c13c8260 | 802 | return 0; |
ff487fb7 JG |
803 | |
804 | err_out: | |
257b17ca DW |
805 | /* if we never registered a channel just release the idr */ |
806 | if (atomic_read(idr_ref) == 0) { | |
807 | mutex_lock(&dma_list_mutex); | |
808 | idr_remove(&dma_idr, device->dev_id); | |
809 | mutex_unlock(&dma_list_mutex); | |
810 | kfree(idr_ref); | |
811 | return rc; | |
812 | } | |
813 | ||
ff487fb7 JG |
814 | list_for_each_entry(chan, &device->channels, device_node) { |
815 | if (chan->local == NULL) | |
816 | continue; | |
41d5e59c DW |
817 | mutex_lock(&dma_list_mutex); |
818 | chan->dev->chan = NULL; | |
819 | mutex_unlock(&dma_list_mutex); | |
820 | device_unregister(&chan->dev->device); | |
ff487fb7 JG |
821 | free_percpu(chan->local); |
822 | } | |
823 | return rc; | |
c13c8260 | 824 | } |
765e3d8a | 825 | EXPORT_SYMBOL(dma_async_device_register); |
c13c8260 | 826 | |
6508871e | 827 | /** |
6f49a57a | 828 | * dma_async_device_unregister - unregister a DMA device |
6508871e | 829 | * @device: &dma_device |
f27c580c DW |
830 | * |
831 | * This routine is called by dma driver exit routines, dmaengine holds module | |
832 | * references to prevent it being called while channels are in use. | |
6508871e RD |
833 | */ |
834 | void dma_async_device_unregister(struct dma_device *device) | |
c13c8260 CL |
835 | { |
836 | struct dma_chan *chan; | |
c13c8260 CL |
837 | |
838 | mutex_lock(&dma_list_mutex); | |
2ba05622 | 839 | list_del_rcu(&device->global_node); |
bec08513 | 840 | dma_channel_rebalance(); |
c13c8260 CL |
841 | mutex_unlock(&dma_list_mutex); |
842 | ||
843 | list_for_each_entry(chan, &device->channels, device_node) { | |
6f49a57a DW |
844 | WARN_ONCE(chan->client_count, |
845 | "%s called while %d clients hold a reference\n", | |
846 | __func__, chan->client_count); | |
41d5e59c DW |
847 | mutex_lock(&dma_list_mutex); |
848 | chan->dev->chan = NULL; | |
849 | mutex_unlock(&dma_list_mutex); | |
850 | device_unregister(&chan->dev->device); | |
adef4772 | 851 | free_percpu(chan->local); |
c13c8260 | 852 | } |
c13c8260 | 853 | } |
765e3d8a | 854 | EXPORT_SYMBOL(dma_async_device_unregister); |
c13c8260 | 855 | |
7405f74b DW |
856 | /** |
857 | * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses | |
858 | * @chan: DMA channel to offload copy to | |
859 | * @dest: destination address (virtual) | |
860 | * @src: source address (virtual) | |
861 | * @len: length | |
862 | * | |
863 | * Both @dest and @src must be mappable to a bus address according to the | |
864 | * DMA mapping API rules for streaming mappings. | |
865 | * Both @dest and @src must stay memory resident (kernel memory or locked | |
866 | * user space pages). | |
867 | */ | |
868 | dma_cookie_t | |
869 | dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest, | |
870 | void *src, size_t len) | |
871 | { | |
872 | struct dma_device *dev = chan->device; | |
873 | struct dma_async_tx_descriptor *tx; | |
0036731c | 874 | dma_addr_t dma_dest, dma_src; |
7405f74b | 875 | dma_cookie_t cookie; |
4f005dbe | 876 | unsigned long flags; |
7405f74b | 877 | |
0036731c DW |
878 | dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE); |
879 | dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE); | |
4f005dbe MS |
880 | flags = DMA_CTRL_ACK | |
881 | DMA_COMPL_SRC_UNMAP_SINGLE | | |
882 | DMA_COMPL_DEST_UNMAP_SINGLE; | |
883 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags); | |
0036731c DW |
884 | |
885 | if (!tx) { | |
886 | dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
887 | dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 888 | return -ENOMEM; |
0036731c | 889 | } |
7405f74b | 890 | |
7405f74b | 891 | tx->callback = NULL; |
7405f74b DW |
892 | cookie = tx->tx_submit(tx); |
893 | ||
e7dcaa47 CL |
894 | preempt_disable(); |
895 | __this_cpu_add(chan->local->bytes_transferred, len); | |
896 | __this_cpu_inc(chan->local->memcpy_count); | |
897 | preempt_enable(); | |
7405f74b DW |
898 | |
899 | return cookie; | |
900 | } | |
901 | EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf); | |
902 | ||
903 | /** | |
904 | * dma_async_memcpy_buf_to_pg - offloaded copy from address to page | |
905 | * @chan: DMA channel to offload copy to | |
906 | * @page: destination page | |
907 | * @offset: offset in page to copy to | |
908 | * @kdata: source address (virtual) | |
909 | * @len: length | |
910 | * | |
911 | * Both @page/@offset and @kdata must be mappable to a bus address according | |
912 | * to the DMA mapping API rules for streaming mappings. | |
913 | * Both @page/@offset and @kdata must stay memory resident (kernel memory or | |
914 | * locked user space pages) | |
915 | */ | |
916 | dma_cookie_t | |
917 | dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page, | |
918 | unsigned int offset, void *kdata, size_t len) | |
919 | { | |
920 | struct dma_device *dev = chan->device; | |
921 | struct dma_async_tx_descriptor *tx; | |
0036731c | 922 | dma_addr_t dma_dest, dma_src; |
7405f74b | 923 | dma_cookie_t cookie; |
4f005dbe | 924 | unsigned long flags; |
7405f74b | 925 | |
0036731c DW |
926 | dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE); |
927 | dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE); | |
4f005dbe MS |
928 | flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE; |
929 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags); | |
0036731c DW |
930 | |
931 | if (!tx) { | |
932 | dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
933 | dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 934 | return -ENOMEM; |
0036731c | 935 | } |
7405f74b | 936 | |
7405f74b | 937 | tx->callback = NULL; |
7405f74b DW |
938 | cookie = tx->tx_submit(tx); |
939 | ||
e7dcaa47 CL |
940 | preempt_disable(); |
941 | __this_cpu_add(chan->local->bytes_transferred, len); | |
942 | __this_cpu_inc(chan->local->memcpy_count); | |
943 | preempt_enable(); | |
7405f74b DW |
944 | |
945 | return cookie; | |
946 | } | |
947 | EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg); | |
948 | ||
949 | /** | |
950 | * dma_async_memcpy_pg_to_pg - offloaded copy from page to page | |
951 | * @chan: DMA channel to offload copy to | |
952 | * @dest_pg: destination page | |
953 | * @dest_off: offset in page to copy to | |
954 | * @src_pg: source page | |
955 | * @src_off: offset in page to copy from | |
956 | * @len: length | |
957 | * | |
958 | * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus | |
959 | * address according to the DMA mapping API rules for streaming mappings. | |
960 | * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident | |
961 | * (kernel memory or locked user space pages). | |
962 | */ | |
963 | dma_cookie_t | |
964 | dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg, | |
965 | unsigned int dest_off, struct page *src_pg, unsigned int src_off, | |
966 | size_t len) | |
967 | { | |
968 | struct dma_device *dev = chan->device; | |
969 | struct dma_async_tx_descriptor *tx; | |
0036731c | 970 | dma_addr_t dma_dest, dma_src; |
7405f74b | 971 | dma_cookie_t cookie; |
4f005dbe | 972 | unsigned long flags; |
7405f74b | 973 | |
0036731c DW |
974 | dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE); |
975 | dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len, | |
976 | DMA_FROM_DEVICE); | |
4f005dbe MS |
977 | flags = DMA_CTRL_ACK; |
978 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags); | |
0036731c DW |
979 | |
980 | if (!tx) { | |
981 | dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
982 | dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 983 | return -ENOMEM; |
0036731c | 984 | } |
7405f74b | 985 | |
7405f74b | 986 | tx->callback = NULL; |
7405f74b DW |
987 | cookie = tx->tx_submit(tx); |
988 | ||
e7dcaa47 CL |
989 | preempt_disable(); |
990 | __this_cpu_add(chan->local->bytes_transferred, len); | |
991 | __this_cpu_inc(chan->local->memcpy_count); | |
992 | preempt_enable(); | |
7405f74b DW |
993 | |
994 | return cookie; | |
995 | } | |
996 | EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg); | |
997 | ||
998 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
999 | struct dma_chan *chan) | |
1000 | { | |
1001 | tx->chan = chan; | |
5fc6d897 | 1002 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
7405f74b | 1003 | spin_lock_init(&tx->lock); |
caa20d97 | 1004 | #endif |
7405f74b DW |
1005 | } |
1006 | EXPORT_SYMBOL(dma_async_tx_descriptor_init); | |
1007 | ||
07f2211e DW |
1008 | /* dma_wait_for_async_tx - spin wait for a transaction to complete |
1009 | * @tx: in-flight transaction to wait on | |
07f2211e DW |
1010 | */ |
1011 | enum dma_status | |
1012 | dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
1013 | { | |
95475e57 | 1014 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); |
07f2211e DW |
1015 | |
1016 | if (!tx) | |
1017 | return DMA_SUCCESS; | |
1018 | ||
95475e57 DW |
1019 | while (tx->cookie == -EBUSY) { |
1020 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
1021 | pr_err("%s timeout waiting for descriptor submission\n", | |
63433250 | 1022 | __func__); |
95475e57 DW |
1023 | return DMA_ERROR; |
1024 | } | |
1025 | cpu_relax(); | |
1026 | } | |
1027 | return dma_sync_wait(tx->chan, tx->cookie); | |
07f2211e DW |
1028 | } |
1029 | EXPORT_SYMBOL_GPL(dma_wait_for_async_tx); | |
1030 | ||
1031 | /* dma_run_dependencies - helper routine for dma drivers to process | |
1032 | * (start) dependent operations on their target channel | |
1033 | * @tx: transaction with dependencies | |
1034 | */ | |
1035 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx) | |
1036 | { | |
caa20d97 | 1037 | struct dma_async_tx_descriptor *dep = txd_next(tx); |
07f2211e DW |
1038 | struct dma_async_tx_descriptor *dep_next; |
1039 | struct dma_chan *chan; | |
1040 | ||
1041 | if (!dep) | |
1042 | return; | |
1043 | ||
dd59b853 | 1044 | /* we'll submit tx->next now, so clear the link */ |
caa20d97 | 1045 | txd_clear_next(tx); |
07f2211e DW |
1046 | chan = dep->chan; |
1047 | ||
1048 | /* keep submitting up until a channel switch is detected | |
1049 | * in that case we will be called again as a result of | |
1050 | * processing the interrupt from async_tx_channel_switch | |
1051 | */ | |
1052 | for (; dep; dep = dep_next) { | |
caa20d97 DW |
1053 | txd_lock(dep); |
1054 | txd_clear_parent(dep); | |
1055 | dep_next = txd_next(dep); | |
07f2211e | 1056 | if (dep_next && dep_next->chan == chan) |
caa20d97 | 1057 | txd_clear_next(dep); /* ->next will be submitted */ |
07f2211e DW |
1058 | else |
1059 | dep_next = NULL; /* submit current dep and terminate */ | |
caa20d97 | 1060 | txd_unlock(dep); |
07f2211e DW |
1061 | |
1062 | dep->tx_submit(dep); | |
1063 | } | |
1064 | ||
1065 | chan->device->device_issue_pending(chan); | |
1066 | } | |
1067 | EXPORT_SYMBOL_GPL(dma_run_dependencies); | |
1068 | ||
c13c8260 CL |
1069 | static int __init dma_bus_init(void) |
1070 | { | |
c13c8260 CL |
1071 | return class_register(&dma_devclass); |
1072 | } | |
652afc27 | 1073 | arch_initcall(dma_bus_init); |
c13c8260 | 1074 | |
bec08513 | 1075 |