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dmaengine: add interface of dma_get_slave_channel
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CommitLineData
c13c8260
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1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21
22/*
23 * This code implements the DMA subsystem. It provides a HW-neutral interface
24 * for other kernel code to use asynchronous memory copy capabilities,
25 * if present, and allows different HW DMA drivers to register as providing
26 * this capability.
27 *
28 * Due to the fact we are accelerating what is already a relatively fast
29 * operation, the code goes to great lengths to avoid additional overhead,
30 * such as locking.
31 *
32 * LOCKING:
33 *
aa1e6f1a
DW
34 * The subsystem keeps a global list of dma_device structs it is protected by a
35 * mutex, dma_list_mutex.
c13c8260 36 *
f27c580c
DW
37 * A subsystem can get access to a channel by calling dmaengine_get() followed
38 * by dma_find_channel(), or if it has need for an exclusive channel it can call
39 * dma_request_channel(). Once a channel is allocated a reference is taken
40 * against its corresponding driver to disable removal.
41 *
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42 * Each device has a channels list, which runs unlocked but is never modified
43 * once the device is registered, it's just setup by the driver.
44 *
f27c580c 45 * See Documentation/dmaengine.txt for more details
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46 */
47
63433250
JP
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
b7f080cf 50#include <linux/dma-mapping.h>
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51#include <linux/init.h>
52#include <linux/module.h>
7405f74b 53#include <linux/mm.h>
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54#include <linux/device.h>
55#include <linux/dmaengine.h>
56#include <linux/hardirq.h>
57#include <linux/spinlock.h>
58#include <linux/percpu.h>
59#include <linux/rcupdate.h>
60#include <linux/mutex.h>
7405f74b 61#include <linux/jiffies.h>
2ba05622 62#include <linux/rculist.h>
864498aa 63#include <linux/idr.h>
5a0e3ad6 64#include <linux/slab.h>
4e82f5dd
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65#include <linux/acpi.h>
66#include <linux/acpi_dma.h>
9a6cecc8 67#include <linux/of_dma.h>
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68
69static DEFINE_MUTEX(dma_list_mutex);
21ef4b8b 70static DEFINE_IDR(dma_idr);
c13c8260 71static LIST_HEAD(dma_device_list);
6f49a57a 72static long dmaengine_ref_count;
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73
74/* --- sysfs implementation --- */
75
41d5e59c
DW
76/**
77 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
78 * @dev - device node
79 *
80 * Must be called under dma_list_mutex
81 */
82static struct dma_chan *dev_to_dma_chan(struct device *dev)
83{
84 struct dma_chan_dev *chan_dev;
85
86 chan_dev = container_of(dev, typeof(*chan_dev), device);
87 return chan_dev->chan;
88}
89
891f78ea 90static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 91{
41d5e59c 92 struct dma_chan *chan;
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93 unsigned long count = 0;
94 int i;
41d5e59c 95 int err;
c13c8260 96
41d5e59c
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97 mutex_lock(&dma_list_mutex);
98 chan = dev_to_dma_chan(dev);
99 if (chan) {
100 for_each_possible_cpu(i)
101 count += per_cpu_ptr(chan->local, i)->memcpy_count;
102 err = sprintf(buf, "%lu\n", count);
103 } else
104 err = -ENODEV;
105 mutex_unlock(&dma_list_mutex);
c13c8260 106
41d5e59c 107 return err;
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108}
109
891f78ea
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110static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
111 char *buf)
c13c8260 112{
41d5e59c 113 struct dma_chan *chan;
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114 unsigned long count = 0;
115 int i;
41d5e59c 116 int err;
c13c8260 117
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118 mutex_lock(&dma_list_mutex);
119 chan = dev_to_dma_chan(dev);
120 if (chan) {
121 for_each_possible_cpu(i)
122 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
123 err = sprintf(buf, "%lu\n", count);
124 } else
125 err = -ENODEV;
126 mutex_unlock(&dma_list_mutex);
c13c8260 127
41d5e59c 128 return err;
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129}
130
891f78ea 131static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 132{
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133 struct dma_chan *chan;
134 int err;
c13c8260 135
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136 mutex_lock(&dma_list_mutex);
137 chan = dev_to_dma_chan(dev);
138 if (chan)
139 err = sprintf(buf, "%d\n", chan->client_count);
140 else
141 err = -ENODEV;
142 mutex_unlock(&dma_list_mutex);
143
144 return err;
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145}
146
891f78ea 147static struct device_attribute dma_attrs[] = {
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148 __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
149 __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
150 __ATTR(in_use, S_IRUGO, show_in_use, NULL),
151 __ATTR_NULL
152};
153
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154static void chan_dev_release(struct device *dev)
155{
156 struct dma_chan_dev *chan_dev;
157
158 chan_dev = container_of(dev, typeof(*chan_dev), device);
864498aa
DW
159 if (atomic_dec_and_test(chan_dev->idr_ref)) {
160 mutex_lock(&dma_list_mutex);
161 idr_remove(&dma_idr, chan_dev->dev_id);
162 mutex_unlock(&dma_list_mutex);
163 kfree(chan_dev->idr_ref);
164 }
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165 kfree(chan_dev);
166}
167
c13c8260 168static struct class dma_devclass = {
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169 .name = "dma",
170 .dev_attrs = dma_attrs,
41d5e59c 171 .dev_release = chan_dev_release,
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172};
173
174/* --- client and device registration --- */
175
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176#define dma_device_satisfies_mask(device, mask) \
177 __dma_device_satisfies_mask((device), &(mask))
d379b01e 178static int
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179__dma_device_satisfies_mask(struct dma_device *device,
180 const dma_cap_mask_t *want)
d379b01e
DW
181{
182 dma_cap_mask_t has;
183
59b5ec21 184 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
d379b01e
DW
185 DMA_TX_TYPE_END);
186 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
187}
188
6f49a57a
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189static struct module *dma_chan_to_owner(struct dma_chan *chan)
190{
191 return chan->device->dev->driver->owner;
192}
193
194/**
195 * balance_ref_count - catch up the channel reference count
196 * @chan - channel to balance ->client_count versus dmaengine_ref_count
197 *
198 * balance_ref_count must be called under dma_list_mutex
199 */
200static void balance_ref_count(struct dma_chan *chan)
201{
202 struct module *owner = dma_chan_to_owner(chan);
203
204 while (chan->client_count < dmaengine_ref_count) {
205 __module_get(owner);
206 chan->client_count++;
207 }
208}
209
210/**
211 * dma_chan_get - try to grab a dma channel's parent driver module
212 * @chan - channel to grab
213 *
214 * Must be called under dma_list_mutex
215 */
216static int dma_chan_get(struct dma_chan *chan)
217{
218 int err = -ENODEV;
219 struct module *owner = dma_chan_to_owner(chan);
220
221 if (chan->client_count) {
222 __module_get(owner);
223 err = 0;
224 } else if (try_module_get(owner))
225 err = 0;
226
227 if (err == 0)
228 chan->client_count++;
229
230 /* allocate upon first client reference */
231 if (chan->client_count == 1 && err == 0) {
aa1e6f1a 232 int desc_cnt = chan->device->device_alloc_chan_resources(chan);
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DW
233
234 if (desc_cnt < 0) {
235 err = desc_cnt;
236 chan->client_count = 0;
237 module_put(owner);
59b5ec21 238 } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
6f49a57a
DW
239 balance_ref_count(chan);
240 }
241
242 return err;
243}
244
245/**
246 * dma_chan_put - drop a reference to a dma channel's parent driver module
247 * @chan - channel to release
248 *
249 * Must be called under dma_list_mutex
250 */
251static void dma_chan_put(struct dma_chan *chan)
252{
253 if (!chan->client_count)
254 return; /* this channel failed alloc_chan_resources */
255 chan->client_count--;
256 module_put(dma_chan_to_owner(chan));
257 if (chan->client_count == 0)
258 chan->device->device_free_chan_resources(chan);
259}
260
7405f74b
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261enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
262{
263 enum dma_status status;
264 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
265
266 dma_async_issue_pending(chan);
267 do {
268 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
269 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
63433250 270 pr_err("%s: timeout!\n", __func__);
7405f74b
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271 return DMA_ERROR;
272 }
2cbe7feb
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273 if (status != DMA_IN_PROGRESS)
274 break;
275 cpu_relax();
276 } while (1);
7405f74b
DW
277
278 return status;
279}
280EXPORT_SYMBOL(dma_sync_wait);
281
bec08513
DW
282/**
283 * dma_cap_mask_all - enable iteration over all operation types
284 */
285static dma_cap_mask_t dma_cap_mask_all;
286
287/**
288 * dma_chan_tbl_ent - tracks channel allocations per core/operation
289 * @chan - associated channel for this entry
290 */
291struct dma_chan_tbl_ent {
292 struct dma_chan *chan;
293};
294
295/**
296 * channel_table - percpu lookup table for memory-to-memory offload providers
297 */
a29d8b8e 298static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
bec08513
DW
299
300static int __init dma_channel_table_init(void)
301{
302 enum dma_transaction_type cap;
303 int err = 0;
304
305 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
306
59b5ec21
DW
307 /* 'interrupt', 'private', and 'slave' are channel capabilities,
308 * but are not associated with an operation so they do not need
309 * an entry in the channel_table
bec08513
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310 */
311 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 312 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
bec08513
DW
313 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
314
315 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
316 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
317 if (!channel_table[cap]) {
318 err = -ENOMEM;
319 break;
320 }
321 }
322
323 if (err) {
63433250 324 pr_err("initialization failure\n");
bec08513
DW
325 for_each_dma_cap_mask(cap, dma_cap_mask_all)
326 if (channel_table[cap])
327 free_percpu(channel_table[cap]);
328 }
329
330 return err;
331}
652afc27 332arch_initcall(dma_channel_table_init);
bec08513
DW
333
334/**
335 * dma_find_channel - find a channel to carry out the operation
336 * @tx_type: transaction type
337 */
338struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
339{
e7dcaa47 340 return this_cpu_read(channel_table[tx_type]->chan);
bec08513
DW
341}
342EXPORT_SYMBOL(dma_find_channel);
343
a2bd1140
DJ
344/*
345 * net_dma_find_channel - find a channel for net_dma
346 * net_dma has alignment requirements
347 */
348struct dma_chan *net_dma_find_channel(void)
349{
350 struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
351 if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
352 return NULL;
353
354 return chan;
355}
356EXPORT_SYMBOL(net_dma_find_channel);
357
2ba05622
DW
358/**
359 * dma_issue_pending_all - flush all pending operations across all channels
360 */
361void dma_issue_pending_all(void)
362{
363 struct dma_device *device;
364 struct dma_chan *chan;
365
2ba05622 366 rcu_read_lock();
59b5ec21
DW
367 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
368 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
369 continue;
2ba05622
DW
370 list_for_each_entry(chan, &device->channels, device_node)
371 if (chan->client_count)
372 device->device_issue_pending(chan);
59b5ec21 373 }
2ba05622
DW
374 rcu_read_unlock();
375}
376EXPORT_SYMBOL(dma_issue_pending_all);
377
bec08513
DW
378/**
379 * nth_chan - returns the nth channel of the given capability
380 * @cap: capability to match
381 * @n: nth channel desired
382 *
383 * Defaults to returning the channel with the desired capability and the
384 * lowest reference count when 'n' cannot be satisfied. Must be called
385 * under dma_list_mutex.
386 */
387static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
388{
389 struct dma_device *device;
390 struct dma_chan *chan;
391 struct dma_chan *ret = NULL;
392 struct dma_chan *min = NULL;
393
394 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
395 if (!dma_has_cap(cap, device->cap_mask) ||
396 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
397 continue;
398 list_for_each_entry(chan, &device->channels, device_node) {
399 if (!chan->client_count)
400 continue;
401 if (!min)
402 min = chan;
403 else if (chan->table_count < min->table_count)
404 min = chan;
405
406 if (n-- == 0) {
407 ret = chan;
408 break; /* done */
409 }
410 }
411 if (ret)
412 break; /* done */
413 }
414
415 if (!ret)
416 ret = min;
417
418 if (ret)
419 ret->table_count++;
420
421 return ret;
422}
423
424/**
425 * dma_channel_rebalance - redistribute the available channels
426 *
427 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
428 * operation type) in the SMP case, and operation isolation (avoid
429 * multi-tasking channels) in the non-SMP case. Must be called under
430 * dma_list_mutex.
431 */
432static void dma_channel_rebalance(void)
433{
434 struct dma_chan *chan;
435 struct dma_device *device;
436 int cpu;
437 int cap;
438 int n;
439
440 /* undo the last distribution */
441 for_each_dma_cap_mask(cap, dma_cap_mask_all)
442 for_each_possible_cpu(cpu)
443 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
444
59b5ec21
DW
445 list_for_each_entry(device, &dma_device_list, global_node) {
446 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
447 continue;
bec08513
DW
448 list_for_each_entry(chan, &device->channels, device_node)
449 chan->table_count = 0;
59b5ec21 450 }
bec08513
DW
451
452 /* don't populate the channel_table if no clients are available */
453 if (!dmaengine_ref_count)
454 return;
455
456 /* redistribute available channels */
457 n = 0;
458 for_each_dma_cap_mask(cap, dma_cap_mask_all)
459 for_each_online_cpu(cpu) {
460 if (num_possible_cpus() > 1)
461 chan = nth_chan(cap, n++);
462 else
463 chan = nth_chan(cap, -1);
464
465 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
466 }
467}
468
a53e28da
LPC
469static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
470 struct dma_device *dev,
e2346677 471 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
472{
473 struct dma_chan *chan;
59b5ec21
DW
474
475 if (!__dma_device_satisfies_mask(dev, mask)) {
476 pr_debug("%s: wrong capabilities\n", __func__);
477 return NULL;
478 }
479 /* devices with multiple channels need special handling as we need to
480 * ensure that all channels are either private or public.
481 */
482 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
483 list_for_each_entry(chan, &dev->channels, device_node) {
484 /* some channels are already publicly allocated */
485 if (chan->client_count)
486 return NULL;
487 }
488
489 list_for_each_entry(chan, &dev->channels, device_node) {
490 if (chan->client_count) {
491 pr_debug("%s: %s busy\n",
41d5e59c 492 __func__, dma_chan_name(chan));
59b5ec21
DW
493 continue;
494 }
e2346677
DW
495 if (fn && !fn(chan, fn_param)) {
496 pr_debug("%s: %s filter said false\n",
497 __func__, dma_chan_name(chan));
498 continue;
499 }
500 return chan;
59b5ec21
DW
501 }
502
e2346677 503 return NULL;
59b5ec21
DW
504}
505
7bb587f4
ZG
506/**
507 * dma_request_channel - try to get specific channel exclusively
508 * @chan: target channel
509 */
510struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
511{
512 int err = -EBUSY;
513
514 /* lock against __dma_request_channel */
515 mutex_lock(&dma_list_mutex);
516
517 if (chan->client_count == 0)
518 err = dma_chan_get(chan);
519 else
520 chan = NULL;
521
522 mutex_unlock(&dma_list_mutex);
523
524 if (err)
525 pr_debug("%s: failed to get %s: (%d)\n",
526 __func__, dma_chan_name(chan), err);
527
528 return chan;
529}
530EXPORT_SYMBOL_GPL(dma_get_slave_channel);
531
59b5ec21
DW
532/**
533 * dma_request_channel - try to allocate an exclusive channel
534 * @mask: capabilities that the channel must satisfy
535 * @fn: optional callback to disposition available channels
536 * @fn_param: opaque parameter to pass to dma_filter_fn
537 */
a53e28da
LPC
538struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
539 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
540{
541 struct dma_device *device, *_d;
542 struct dma_chan *chan = NULL;
59b5ec21
DW
543 int err;
544
545 /* Find a channel */
546 mutex_lock(&dma_list_mutex);
547 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
e2346677
DW
548 chan = private_candidate(mask, device, fn, fn_param);
549 if (chan) {
59b5ec21
DW
550 /* Found a suitable channel, try to grab, prep, and
551 * return it. We first set DMA_PRIVATE to disable
552 * balance_ref_count as this channel will not be
553 * published in the general-purpose allocator
554 */
555 dma_cap_set(DMA_PRIVATE, device->cap_mask);
0f571515 556 device->privatecnt++;
59b5ec21
DW
557 err = dma_chan_get(chan);
558
559 if (err == -ENODEV) {
63433250
JP
560 pr_debug("%s: %s module removed\n",
561 __func__, dma_chan_name(chan));
59b5ec21
DW
562 list_del_rcu(&device->global_node);
563 } else if (err)
d8b53489 564 pr_debug("%s: failed to get %s: (%d)\n",
63433250 565 __func__, dma_chan_name(chan), err);
59b5ec21
DW
566 else
567 break;
0f571515
AN
568 if (--device->privatecnt == 0)
569 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
e2346677
DW
570 chan = NULL;
571 }
59b5ec21
DW
572 }
573 mutex_unlock(&dma_list_mutex);
574
63433250
JP
575 pr_debug("%s: %s (%s)\n",
576 __func__,
577 chan ? "success" : "fail",
41d5e59c 578 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
579
580 return chan;
581}
582EXPORT_SYMBOL_GPL(__dma_request_channel);
583
9a6cecc8
JH
584/**
585 * dma_request_slave_channel - try to allocate an exclusive slave channel
586 * @dev: pointer to client device structure
587 * @name: slave channel name
588 */
bef29ec5 589struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name)
9a6cecc8
JH
590{
591 /* If device-tree is present get slave info from here */
592 if (dev->of_node)
593 return of_dma_request_slave_channel(dev->of_node, name);
594
4e82f5dd
AS
595 /* If device was enumerated by ACPI get slave info from here */
596 if (ACPI_HANDLE(dev))
597 return acpi_dma_request_slave_chan_by_name(dev, name);
598
9a6cecc8
JH
599 return NULL;
600}
601EXPORT_SYMBOL_GPL(dma_request_slave_channel);
602
59b5ec21
DW
603void dma_release_channel(struct dma_chan *chan)
604{
605 mutex_lock(&dma_list_mutex);
606 WARN_ONCE(chan->client_count != 1,
607 "chan reference count %d != 1\n", chan->client_count);
608 dma_chan_put(chan);
0f571515
AN
609 /* drop PRIVATE cap enabled by __dma_request_channel() */
610 if (--chan->device->privatecnt == 0)
611 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
59b5ec21
DW
612 mutex_unlock(&dma_list_mutex);
613}
614EXPORT_SYMBOL_GPL(dma_release_channel);
615
d379b01e 616/**
209b84a8 617 * dmaengine_get - register interest in dma_channels
d379b01e 618 */
209b84a8 619void dmaengine_get(void)
d379b01e 620{
6f49a57a
DW
621 struct dma_device *device, *_d;
622 struct dma_chan *chan;
623 int err;
624
c13c8260 625 mutex_lock(&dma_list_mutex);
6f49a57a
DW
626 dmaengine_ref_count++;
627
628 /* try to grab channels */
59b5ec21
DW
629 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
630 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
631 continue;
6f49a57a
DW
632 list_for_each_entry(chan, &device->channels, device_node) {
633 err = dma_chan_get(chan);
634 if (err == -ENODEV) {
635 /* module removed before we could use it */
2ba05622 636 list_del_rcu(&device->global_node);
6f49a57a
DW
637 break;
638 } else if (err)
0eb5a358 639 pr_debug("%s: failed to get %s: (%d)\n",
63433250 640 __func__, dma_chan_name(chan), err);
6f49a57a 641 }
59b5ec21 642 }
6f49a57a 643
bec08513
DW
644 /* if this is the first reference and there were channels
645 * waiting we need to rebalance to get those channels
646 * incorporated into the channel table
647 */
648 if (dmaengine_ref_count == 1)
649 dma_channel_rebalance();
c13c8260 650 mutex_unlock(&dma_list_mutex);
c13c8260 651}
209b84a8 652EXPORT_SYMBOL(dmaengine_get);
c13c8260
CL
653
654/**
209b84a8 655 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 656 */
209b84a8 657void dmaengine_put(void)
c13c8260 658{
d379b01e 659 struct dma_device *device;
c13c8260
CL
660 struct dma_chan *chan;
661
c13c8260 662 mutex_lock(&dma_list_mutex);
6f49a57a
DW
663 dmaengine_ref_count--;
664 BUG_ON(dmaengine_ref_count < 0);
665 /* drop channel references */
59b5ec21
DW
666 list_for_each_entry(device, &dma_device_list, global_node) {
667 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
668 continue;
6f49a57a
DW
669 list_for_each_entry(chan, &device->channels, device_node)
670 dma_chan_put(chan);
59b5ec21 671 }
c13c8260 672 mutex_unlock(&dma_list_mutex);
c13c8260 673}
209b84a8 674EXPORT_SYMBOL(dmaengine_put);
c13c8260 675
138f4c35
DW
676static bool device_has_all_tx_types(struct dma_device *device)
677{
678 /* A device that satisfies this test has channels that will never cause
679 * an async_tx channel switch event as all possible operation types can
680 * be handled.
681 */
682 #ifdef CONFIG_ASYNC_TX_DMA
683 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
684 return false;
685 #endif
686
687 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
688 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
689 return false;
690 #endif
691
138f4c35
DW
692 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
693 if (!dma_has_cap(DMA_XOR, device->cap_mask))
694 return false;
7b3cc2b1
DW
695
696 #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
4499a24d
DW
697 if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
698 return false;
138f4c35 699 #endif
7b3cc2b1 700 #endif
138f4c35
DW
701
702 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
703 if (!dma_has_cap(DMA_PQ, device->cap_mask))
704 return false;
7b3cc2b1
DW
705
706 #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
4499a24d
DW
707 if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
708 return false;
138f4c35 709 #endif
7b3cc2b1 710 #endif
138f4c35
DW
711
712 return true;
713}
714
257b17ca
DW
715static int get_dma_id(struct dma_device *device)
716{
717 int rc;
718
257b17ca 719 mutex_lock(&dma_list_mutex);
257b17ca 720
69ee266b
TH
721 rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
722 if (rc >= 0)
723 device->dev_id = rc;
724
725 mutex_unlock(&dma_list_mutex);
726 return rc < 0 ? rc : 0;
257b17ca
DW
727}
728
c13c8260 729/**
6508871e 730 * dma_async_device_register - registers DMA devices found
c13c8260
CL
731 * @device: &dma_device
732 */
733int dma_async_device_register(struct dma_device *device)
734{
ff487fb7 735 int chancnt = 0, rc;
c13c8260 736 struct dma_chan* chan;
864498aa 737 atomic_t *idr_ref;
c13c8260
CL
738
739 if (!device)
740 return -ENODEV;
741
7405f74b
DW
742 /* validate device routines */
743 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
744 !device->device_prep_dma_memcpy);
745 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
746 !device->device_prep_dma_xor);
099f53cb
DW
747 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
748 !device->device_prep_dma_xor_val);
b2f46fd8
DW
749 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
750 !device->device_prep_dma_pq);
751 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
752 !device->device_prep_dma_pq_val);
9b941c66 753 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 754 !device->device_prep_dma_interrupt);
a86ee03c
IS
755 BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
756 !device->device_prep_dma_sg);
782bc950
SH
757 BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
758 !device->device_prep_dma_cyclic);
dc0ee643 759 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
c3635c78 760 !device->device_control);
b14dab79
JB
761 BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
762 !device->device_prep_interleaved_dma);
7405f74b
DW
763
764 BUG_ON(!device->device_alloc_chan_resources);
765 BUG_ON(!device->device_free_chan_resources);
07934481 766 BUG_ON(!device->device_tx_status);
7405f74b
DW
767 BUG_ON(!device->device_issue_pending);
768 BUG_ON(!device->dev);
769
138f4c35 770 /* note: this only matters in the
5fc6d897 771 * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
138f4c35
DW
772 */
773 if (device_has_all_tx_types(device))
774 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
775
864498aa
DW
776 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
777 if (!idr_ref)
778 return -ENOMEM;
257b17ca
DW
779 rc = get_dma_id(device);
780 if (rc != 0) {
781 kfree(idr_ref);
864498aa 782 return rc;
257b17ca
DW
783 }
784
785 atomic_set(idr_ref, 0);
c13c8260
CL
786
787 /* represent channels in sysfs. Probably want devs too */
788 list_for_each_entry(chan, &device->channels, device_node) {
257b17ca 789 rc = -ENOMEM;
c13c8260
CL
790 chan->local = alloc_percpu(typeof(*chan->local));
791 if (chan->local == NULL)
257b17ca 792 goto err_out;
41d5e59c
DW
793 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
794 if (chan->dev == NULL) {
795 free_percpu(chan->local);
257b17ca
DW
796 chan->local = NULL;
797 goto err_out;
41d5e59c 798 }
c13c8260
CL
799
800 chan->chan_id = chancnt++;
41d5e59c
DW
801 chan->dev->device.class = &dma_devclass;
802 chan->dev->device.parent = device->dev;
803 chan->dev->chan = chan;
864498aa
DW
804 chan->dev->idr_ref = idr_ref;
805 chan->dev->dev_id = device->dev_id;
806 atomic_inc(idr_ref);
41d5e59c 807 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 808 device->dev_id, chan->chan_id);
c13c8260 809
41d5e59c 810 rc = device_register(&chan->dev->device);
ff487fb7 811 if (rc) {
ff487fb7
JG
812 free_percpu(chan->local);
813 chan->local = NULL;
257b17ca
DW
814 kfree(chan->dev);
815 atomic_dec(idr_ref);
ff487fb7
JG
816 goto err_out;
817 }
7cc5bf9a 818 chan->client_count = 0;
c13c8260 819 }
59b5ec21 820 device->chancnt = chancnt;
c13c8260
CL
821
822 mutex_lock(&dma_list_mutex);
59b5ec21
DW
823 /* take references on public channels */
824 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
825 list_for_each_entry(chan, &device->channels, device_node) {
826 /* if clients are already waiting for channels we need
827 * to take references on their behalf
828 */
829 if (dma_chan_get(chan) == -ENODEV) {
830 /* note we can only get here for the first
831 * channel as the remaining channels are
832 * guaranteed to get a reference
833 */
834 rc = -ENODEV;
835 mutex_unlock(&dma_list_mutex);
836 goto err_out;
837 }
838 }
2ba05622 839 list_add_tail_rcu(&device->global_node, &dma_device_list);
0f571515
AN
840 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
841 device->privatecnt++; /* Always private */
bec08513 842 dma_channel_rebalance();
c13c8260
CL
843 mutex_unlock(&dma_list_mutex);
844
c13c8260 845 return 0;
ff487fb7
JG
846
847err_out:
257b17ca
DW
848 /* if we never registered a channel just release the idr */
849 if (atomic_read(idr_ref) == 0) {
850 mutex_lock(&dma_list_mutex);
851 idr_remove(&dma_idr, device->dev_id);
852 mutex_unlock(&dma_list_mutex);
853 kfree(idr_ref);
854 return rc;
855 }
856
ff487fb7
JG
857 list_for_each_entry(chan, &device->channels, device_node) {
858 if (chan->local == NULL)
859 continue;
41d5e59c
DW
860 mutex_lock(&dma_list_mutex);
861 chan->dev->chan = NULL;
862 mutex_unlock(&dma_list_mutex);
863 device_unregister(&chan->dev->device);
ff487fb7
JG
864 free_percpu(chan->local);
865 }
866 return rc;
c13c8260 867}
765e3d8a 868EXPORT_SYMBOL(dma_async_device_register);
c13c8260 869
6508871e 870/**
6f49a57a 871 * dma_async_device_unregister - unregister a DMA device
6508871e 872 * @device: &dma_device
f27c580c
DW
873 *
874 * This routine is called by dma driver exit routines, dmaengine holds module
875 * references to prevent it being called while channels are in use.
6508871e
RD
876 */
877void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
878{
879 struct dma_chan *chan;
c13c8260
CL
880
881 mutex_lock(&dma_list_mutex);
2ba05622 882 list_del_rcu(&device->global_node);
bec08513 883 dma_channel_rebalance();
c13c8260
CL
884 mutex_unlock(&dma_list_mutex);
885
886 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
887 WARN_ONCE(chan->client_count,
888 "%s called while %d clients hold a reference\n",
889 __func__, chan->client_count);
41d5e59c
DW
890 mutex_lock(&dma_list_mutex);
891 chan->dev->chan = NULL;
892 mutex_unlock(&dma_list_mutex);
893 device_unregister(&chan->dev->device);
adef4772 894 free_percpu(chan->local);
c13c8260 895 }
c13c8260 896}
765e3d8a 897EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 898
7405f74b
DW
899/**
900 * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
901 * @chan: DMA channel to offload copy to
902 * @dest: destination address (virtual)
903 * @src: source address (virtual)
904 * @len: length
905 *
906 * Both @dest and @src must be mappable to a bus address according to the
907 * DMA mapping API rules for streaming mappings.
908 * Both @dest and @src must stay memory resident (kernel memory or locked
909 * user space pages).
910 */
911dma_cookie_t
912dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
913 void *src, size_t len)
914{
915 struct dma_device *dev = chan->device;
916 struct dma_async_tx_descriptor *tx;
0036731c 917 dma_addr_t dma_dest, dma_src;
7405f74b 918 dma_cookie_t cookie;
4f005dbe 919 unsigned long flags;
7405f74b 920
0036731c
DW
921 dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
922 dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
4f005dbe
MS
923 flags = DMA_CTRL_ACK |
924 DMA_COMPL_SRC_UNMAP_SINGLE |
925 DMA_COMPL_DEST_UNMAP_SINGLE;
926 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
927
928 if (!tx) {
929 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
930 dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 931 return -ENOMEM;
0036731c 932 }
7405f74b 933
7405f74b 934 tx->callback = NULL;
7405f74b
DW
935 cookie = tx->tx_submit(tx);
936
e7dcaa47
CL
937 preempt_disable();
938 __this_cpu_add(chan->local->bytes_transferred, len);
939 __this_cpu_inc(chan->local->memcpy_count);
940 preempt_enable();
7405f74b
DW
941
942 return cookie;
943}
944EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
945
946/**
947 * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
948 * @chan: DMA channel to offload copy to
949 * @page: destination page
950 * @offset: offset in page to copy to
951 * @kdata: source address (virtual)
952 * @len: length
953 *
954 * Both @page/@offset and @kdata must be mappable to a bus address according
955 * to the DMA mapping API rules for streaming mappings.
956 * Both @page/@offset and @kdata must stay memory resident (kernel memory or
957 * locked user space pages)
958 */
959dma_cookie_t
960dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
961 unsigned int offset, void *kdata, size_t len)
962{
963 struct dma_device *dev = chan->device;
964 struct dma_async_tx_descriptor *tx;
0036731c 965 dma_addr_t dma_dest, dma_src;
7405f74b 966 dma_cookie_t cookie;
4f005dbe 967 unsigned long flags;
7405f74b 968
0036731c
DW
969 dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
970 dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
4f005dbe
MS
971 flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
972 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
973
974 if (!tx) {
975 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
976 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 977 return -ENOMEM;
0036731c 978 }
7405f74b 979
7405f74b 980 tx->callback = NULL;
7405f74b
DW
981 cookie = tx->tx_submit(tx);
982
e7dcaa47
CL
983 preempt_disable();
984 __this_cpu_add(chan->local->bytes_transferred, len);
985 __this_cpu_inc(chan->local->memcpy_count);
986 preempt_enable();
7405f74b
DW
987
988 return cookie;
989}
990EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
991
992/**
993 * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
994 * @chan: DMA channel to offload copy to
995 * @dest_pg: destination page
996 * @dest_off: offset in page to copy to
997 * @src_pg: source page
998 * @src_off: offset in page to copy from
999 * @len: length
1000 *
1001 * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
1002 * address according to the DMA mapping API rules for streaming mappings.
1003 * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
1004 * (kernel memory or locked user space pages).
1005 */
1006dma_cookie_t
1007dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
1008 unsigned int dest_off, struct page *src_pg, unsigned int src_off,
1009 size_t len)
1010{
1011 struct dma_device *dev = chan->device;
1012 struct dma_async_tx_descriptor *tx;
0036731c 1013 dma_addr_t dma_dest, dma_src;
7405f74b 1014 dma_cookie_t cookie;
4f005dbe 1015 unsigned long flags;
7405f74b 1016
0036731c
DW
1017 dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
1018 dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
1019 DMA_FROM_DEVICE);
4f005dbe
MS
1020 flags = DMA_CTRL_ACK;
1021 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
0036731c
DW
1022
1023 if (!tx) {
1024 dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
1025 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 1026 return -ENOMEM;
0036731c 1027 }
7405f74b 1028
7405f74b 1029 tx->callback = NULL;
7405f74b
DW
1030 cookie = tx->tx_submit(tx);
1031
e7dcaa47
CL
1032 preempt_disable();
1033 __this_cpu_add(chan->local->bytes_transferred, len);
1034 __this_cpu_inc(chan->local->memcpy_count);
1035 preempt_enable();
7405f74b
DW
1036
1037 return cookie;
1038}
1039EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
1040
1041void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1042 struct dma_chan *chan)
1043{
1044 tx->chan = chan;
5fc6d897 1045 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
7405f74b 1046 spin_lock_init(&tx->lock);
caa20d97 1047 #endif
7405f74b
DW
1048}
1049EXPORT_SYMBOL(dma_async_tx_descriptor_init);
1050
07f2211e
DW
1051/* dma_wait_for_async_tx - spin wait for a transaction to complete
1052 * @tx: in-flight transaction to wait on
07f2211e
DW
1053 */
1054enum dma_status
1055dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1056{
95475e57 1057 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
07f2211e
DW
1058
1059 if (!tx)
1060 return DMA_SUCCESS;
1061
95475e57
DW
1062 while (tx->cookie == -EBUSY) {
1063 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
1064 pr_err("%s timeout waiting for descriptor submission\n",
63433250 1065 __func__);
95475e57
DW
1066 return DMA_ERROR;
1067 }
1068 cpu_relax();
1069 }
1070 return dma_sync_wait(tx->chan, tx->cookie);
07f2211e
DW
1071}
1072EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1073
1074/* dma_run_dependencies - helper routine for dma drivers to process
1075 * (start) dependent operations on their target channel
1076 * @tx: transaction with dependencies
1077 */
1078void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1079{
caa20d97 1080 struct dma_async_tx_descriptor *dep = txd_next(tx);
07f2211e
DW
1081 struct dma_async_tx_descriptor *dep_next;
1082 struct dma_chan *chan;
1083
1084 if (!dep)
1085 return;
1086
dd59b853 1087 /* we'll submit tx->next now, so clear the link */
caa20d97 1088 txd_clear_next(tx);
07f2211e
DW
1089 chan = dep->chan;
1090
1091 /* keep submitting up until a channel switch is detected
1092 * in that case we will be called again as a result of
1093 * processing the interrupt from async_tx_channel_switch
1094 */
1095 for (; dep; dep = dep_next) {
caa20d97
DW
1096 txd_lock(dep);
1097 txd_clear_parent(dep);
1098 dep_next = txd_next(dep);
07f2211e 1099 if (dep_next && dep_next->chan == chan)
caa20d97 1100 txd_clear_next(dep); /* ->next will be submitted */
07f2211e
DW
1101 else
1102 dep_next = NULL; /* submit current dep and terminate */
caa20d97 1103 txd_unlock(dep);
07f2211e
DW
1104
1105 dep->tx_submit(dep);
1106 }
1107
1108 chan->device->device_issue_pending(chan);
1109}
1110EXPORT_SYMBOL_GPL(dma_run_dependencies);
1111
c13c8260
CL
1112static int __init dma_bus_init(void)
1113{
c13c8260
CL
1114 return class_register(&dma_devclass);
1115}
652afc27 1116arch_initcall(dma_bus_init);
c13c8260 1117
bec08513 1118