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CommitLineData
c13c8260
CL
1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
c13c8260
CL
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
16 */
17
18/*
19 * This code implements the DMA subsystem. It provides a HW-neutral interface
20 * for other kernel code to use asynchronous memory copy capabilities,
21 * if present, and allows different HW DMA drivers to register as providing
22 * this capability.
23 *
24 * Due to the fact we are accelerating what is already a relatively fast
25 * operation, the code goes to great lengths to avoid additional overhead,
26 * such as locking.
27 *
28 * LOCKING:
29 *
aa1e6f1a
DW
30 * The subsystem keeps a global list of dma_device structs it is protected by a
31 * mutex, dma_list_mutex.
c13c8260 32 *
f27c580c
DW
33 * A subsystem can get access to a channel by calling dmaengine_get() followed
34 * by dma_find_channel(), or if it has need for an exclusive channel it can call
35 * dma_request_channel(). Once a channel is allocated a reference is taken
36 * against its corresponding driver to disable removal.
37 *
c13c8260
CL
38 * Each device has a channels list, which runs unlocked but is never modified
39 * once the device is registered, it's just setup by the driver.
40 *
f27c580c 41 * See Documentation/dmaengine.txt for more details
c13c8260
CL
42 */
43
63433250
JP
44#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
45
a8135d0d 46#include <linux/platform_device.h>
b7f080cf 47#include <linux/dma-mapping.h>
c13c8260
CL
48#include <linux/init.h>
49#include <linux/module.h>
7405f74b 50#include <linux/mm.h>
c13c8260
CL
51#include <linux/device.h>
52#include <linux/dmaengine.h>
53#include <linux/hardirq.h>
54#include <linux/spinlock.h>
55#include <linux/percpu.h>
56#include <linux/rcupdate.h>
57#include <linux/mutex.h>
7405f74b 58#include <linux/jiffies.h>
2ba05622 59#include <linux/rculist.h>
864498aa 60#include <linux/idr.h>
5a0e3ad6 61#include <linux/slab.h>
4e82f5dd
AS
62#include <linux/acpi.h>
63#include <linux/acpi_dma.h>
9a6cecc8 64#include <linux/of_dma.h>
45c463ae 65#include <linux/mempool.h>
c13c8260
CL
66
67static DEFINE_MUTEX(dma_list_mutex);
21ef4b8b 68static DEFINE_IDR(dma_idr);
c13c8260 69static LIST_HEAD(dma_device_list);
6f49a57a 70static long dmaengine_ref_count;
c13c8260
CL
71
72/* --- sysfs implementation --- */
73
41d5e59c
DW
74/**
75 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
76 * @dev - device node
77 *
78 * Must be called under dma_list_mutex
79 */
80static struct dma_chan *dev_to_dma_chan(struct device *dev)
81{
82 struct dma_chan_dev *chan_dev;
83
84 chan_dev = container_of(dev, typeof(*chan_dev), device);
85 return chan_dev->chan;
86}
87
58b267d3
GKH
88static ssize_t memcpy_count_show(struct device *dev,
89 struct device_attribute *attr, char *buf)
c13c8260 90{
41d5e59c 91 struct dma_chan *chan;
c13c8260
CL
92 unsigned long count = 0;
93 int i;
41d5e59c 94 int err;
c13c8260 95
41d5e59c
DW
96 mutex_lock(&dma_list_mutex);
97 chan = dev_to_dma_chan(dev);
98 if (chan) {
99 for_each_possible_cpu(i)
100 count += per_cpu_ptr(chan->local, i)->memcpy_count;
101 err = sprintf(buf, "%lu\n", count);
102 } else
103 err = -ENODEV;
104 mutex_unlock(&dma_list_mutex);
c13c8260 105
41d5e59c 106 return err;
c13c8260 107}
58b267d3 108static DEVICE_ATTR_RO(memcpy_count);
c13c8260 109
58b267d3
GKH
110static ssize_t bytes_transferred_show(struct device *dev,
111 struct device_attribute *attr, char *buf)
c13c8260 112{
41d5e59c 113 struct dma_chan *chan;
c13c8260
CL
114 unsigned long count = 0;
115 int i;
41d5e59c 116 int err;
c13c8260 117
41d5e59c
DW
118 mutex_lock(&dma_list_mutex);
119 chan = dev_to_dma_chan(dev);
120 if (chan) {
121 for_each_possible_cpu(i)
122 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
123 err = sprintf(buf, "%lu\n", count);
124 } else
125 err = -ENODEV;
126 mutex_unlock(&dma_list_mutex);
c13c8260 127
41d5e59c 128 return err;
c13c8260 129}
58b267d3 130static DEVICE_ATTR_RO(bytes_transferred);
c13c8260 131
58b267d3
GKH
132static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
133 char *buf)
c13c8260 134{
41d5e59c
DW
135 struct dma_chan *chan;
136 int err;
c13c8260 137
41d5e59c
DW
138 mutex_lock(&dma_list_mutex);
139 chan = dev_to_dma_chan(dev);
140 if (chan)
141 err = sprintf(buf, "%d\n", chan->client_count);
142 else
143 err = -ENODEV;
144 mutex_unlock(&dma_list_mutex);
145
146 return err;
c13c8260 147}
58b267d3 148static DEVICE_ATTR_RO(in_use);
c13c8260 149
58b267d3
GKH
150static struct attribute *dma_dev_attrs[] = {
151 &dev_attr_memcpy_count.attr,
152 &dev_attr_bytes_transferred.attr,
153 &dev_attr_in_use.attr,
154 NULL,
c13c8260 155};
58b267d3 156ATTRIBUTE_GROUPS(dma_dev);
c13c8260 157
41d5e59c
DW
158static void chan_dev_release(struct device *dev)
159{
160 struct dma_chan_dev *chan_dev;
161
162 chan_dev = container_of(dev, typeof(*chan_dev), device);
864498aa
DW
163 if (atomic_dec_and_test(chan_dev->idr_ref)) {
164 mutex_lock(&dma_list_mutex);
165 idr_remove(&dma_idr, chan_dev->dev_id);
166 mutex_unlock(&dma_list_mutex);
167 kfree(chan_dev->idr_ref);
168 }
41d5e59c
DW
169 kfree(chan_dev);
170}
171
c13c8260 172static struct class dma_devclass = {
891f78ea 173 .name = "dma",
58b267d3 174 .dev_groups = dma_dev_groups,
41d5e59c 175 .dev_release = chan_dev_release,
c13c8260
CL
176};
177
178/* --- client and device registration --- */
179
59b5ec21
DW
180#define dma_device_satisfies_mask(device, mask) \
181 __dma_device_satisfies_mask((device), &(mask))
d379b01e 182static int
a53e28da
LPC
183__dma_device_satisfies_mask(struct dma_device *device,
184 const dma_cap_mask_t *want)
d379b01e
DW
185{
186 dma_cap_mask_t has;
187
59b5ec21 188 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
d379b01e
DW
189 DMA_TX_TYPE_END);
190 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
191}
192
6f49a57a
DW
193static struct module *dma_chan_to_owner(struct dma_chan *chan)
194{
195 return chan->device->dev->driver->owner;
196}
197
198/**
199 * balance_ref_count - catch up the channel reference count
200 * @chan - channel to balance ->client_count versus dmaengine_ref_count
201 *
202 * balance_ref_count must be called under dma_list_mutex
203 */
204static void balance_ref_count(struct dma_chan *chan)
205{
206 struct module *owner = dma_chan_to_owner(chan);
207
208 while (chan->client_count < dmaengine_ref_count) {
209 __module_get(owner);
210 chan->client_count++;
211 }
212}
213
214/**
215 * dma_chan_get - try to grab a dma channel's parent driver module
216 * @chan - channel to grab
217 *
218 * Must be called under dma_list_mutex
219 */
220static int dma_chan_get(struct dma_chan *chan)
221{
6f49a57a 222 struct module *owner = dma_chan_to_owner(chan);
d2f4f99d 223 int ret;
6f49a57a 224
d2f4f99d 225 /* The channel is already in use, update client count */
6f49a57a
DW
226 if (chan->client_count) {
227 __module_get(owner);
d2f4f99d
MR
228 goto out;
229 }
6f49a57a 230
d2f4f99d
MR
231 if (!try_module_get(owner))
232 return -ENODEV;
6f49a57a
DW
233
234 /* allocate upon first client reference */
c4b54a64
MR
235 if (chan->device->device_alloc_chan_resources) {
236 ret = chan->device->device_alloc_chan_resources(chan);
237 if (ret < 0)
238 goto err_out;
239 }
6f49a57a 240
d2f4f99d
MR
241 if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
242 balance_ref_count(chan);
243
244out:
245 chan->client_count++;
246 return 0;
247
248err_out:
249 module_put(owner);
250 return ret;
6f49a57a
DW
251}
252
253/**
254 * dma_chan_put - drop a reference to a dma channel's parent driver module
255 * @chan - channel to release
256 *
257 * Must be called under dma_list_mutex
258 */
259static void dma_chan_put(struct dma_chan *chan)
260{
c4b54a64 261 /* This channel is not in use, bail out */
6f49a57a 262 if (!chan->client_count)
c4b54a64
MR
263 return;
264
6f49a57a
DW
265 chan->client_count--;
266 module_put(dma_chan_to_owner(chan));
c4b54a64
MR
267
268 /* This channel is not in use anymore, free it */
b36f09c3
LPC
269 if (!chan->client_count && chan->device->device_free_chan_resources) {
270 /* Make sure all operations have completed */
271 dmaengine_synchronize(chan);
6f49a57a 272 chan->device->device_free_chan_resources(chan);
b36f09c3 273 }
56f13c0d
PU
274
275 /* If the channel is used via a DMA request router, free the mapping */
276 if (chan->router && chan->router->route_free) {
277 chan->router->route_free(chan->router->dev, chan->route_data);
278 chan->router = NULL;
279 chan->route_data = NULL;
280 }
6f49a57a
DW
281}
282
7405f74b
DW
283enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
284{
285 enum dma_status status;
286 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
287
288 dma_async_issue_pending(chan);
289 do {
290 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
291 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
ef859312 292 dev_err(chan->device->dev, "%s: timeout!\n", __func__);
7405f74b
DW
293 return DMA_ERROR;
294 }
2cbe7feb
BZ
295 if (status != DMA_IN_PROGRESS)
296 break;
297 cpu_relax();
298 } while (1);
7405f74b
DW
299
300 return status;
301}
302EXPORT_SYMBOL(dma_sync_wait);
303
bec08513
DW
304/**
305 * dma_cap_mask_all - enable iteration over all operation types
306 */
307static dma_cap_mask_t dma_cap_mask_all;
308
309/**
310 * dma_chan_tbl_ent - tracks channel allocations per core/operation
311 * @chan - associated channel for this entry
312 */
313struct dma_chan_tbl_ent {
314 struct dma_chan *chan;
315};
316
317/**
318 * channel_table - percpu lookup table for memory-to-memory offload providers
319 */
a29d8b8e 320static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
bec08513
DW
321
322static int __init dma_channel_table_init(void)
323{
324 enum dma_transaction_type cap;
325 int err = 0;
326
327 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
328
59b5ec21
DW
329 /* 'interrupt', 'private', and 'slave' are channel capabilities,
330 * but are not associated with an operation so they do not need
331 * an entry in the channel_table
bec08513
DW
332 */
333 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 334 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
bec08513
DW
335 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
336
337 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
338 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
339 if (!channel_table[cap]) {
340 err = -ENOMEM;
341 break;
342 }
343 }
344
345 if (err) {
63433250 346 pr_err("initialization failure\n");
bec08513 347 for_each_dma_cap_mask(cap, dma_cap_mask_all)
a9507ca3 348 free_percpu(channel_table[cap]);
bec08513
DW
349 }
350
351 return err;
352}
652afc27 353arch_initcall(dma_channel_table_init);
bec08513
DW
354
355/**
356 * dma_find_channel - find a channel to carry out the operation
357 * @tx_type: transaction type
358 */
359struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
360{
e7dcaa47 361 return this_cpu_read(channel_table[tx_type]->chan);
bec08513
DW
362}
363EXPORT_SYMBOL(dma_find_channel);
a2bd1140 364
2ba05622
DW
365/**
366 * dma_issue_pending_all - flush all pending operations across all channels
367 */
368void dma_issue_pending_all(void)
369{
370 struct dma_device *device;
371 struct dma_chan *chan;
372
2ba05622 373 rcu_read_lock();
59b5ec21
DW
374 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
375 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
376 continue;
2ba05622
DW
377 list_for_each_entry(chan, &device->channels, device_node)
378 if (chan->client_count)
379 device->device_issue_pending(chan);
59b5ec21 380 }
2ba05622
DW
381 rcu_read_unlock();
382}
383EXPORT_SYMBOL(dma_issue_pending_all);
384
bec08513 385/**
c4d27c4d
BG
386 * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
387 */
388static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
389{
390 int node = dev_to_node(chan->device->dev);
391 return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
392}
393
394/**
395 * min_chan - returns the channel with min count and in the same numa-node as the cpu
bec08513 396 * @cap: capability to match
c4d27c4d 397 * @cpu: cpu index which the channel should be close to
bec08513 398 *
c4d27c4d
BG
399 * If some channels are close to the given cpu, the one with the lowest
400 * reference count is returned. Otherwise, cpu is ignored and only the
401 * reference count is taken into account.
402 * Must be called under dma_list_mutex.
bec08513 403 */
c4d27c4d 404static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
bec08513
DW
405{
406 struct dma_device *device;
407 struct dma_chan *chan;
bec08513 408 struct dma_chan *min = NULL;
c4d27c4d 409 struct dma_chan *localmin = NULL;
bec08513
DW
410
411 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
412 if (!dma_has_cap(cap, device->cap_mask) ||
413 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
414 continue;
415 list_for_each_entry(chan, &device->channels, device_node) {
416 if (!chan->client_count)
417 continue;
c4d27c4d 418 if (!min || chan->table_count < min->table_count)
bec08513
DW
419 min = chan;
420
c4d27c4d
BG
421 if (dma_chan_is_local(chan, cpu))
422 if (!localmin ||
423 chan->table_count < localmin->table_count)
424 localmin = chan;
bec08513 425 }
bec08513
DW
426 }
427
c4d27c4d 428 chan = localmin ? localmin : min;
bec08513 429
c4d27c4d
BG
430 if (chan)
431 chan->table_count++;
bec08513 432
c4d27c4d 433 return chan;
bec08513
DW
434}
435
436/**
437 * dma_channel_rebalance - redistribute the available channels
438 *
439 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
440 * operation type) in the SMP case, and operation isolation (avoid
441 * multi-tasking channels) in the non-SMP case. Must be called under
442 * dma_list_mutex.
443 */
444static void dma_channel_rebalance(void)
445{
446 struct dma_chan *chan;
447 struct dma_device *device;
448 int cpu;
449 int cap;
bec08513
DW
450
451 /* undo the last distribution */
452 for_each_dma_cap_mask(cap, dma_cap_mask_all)
453 for_each_possible_cpu(cpu)
454 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
455
59b5ec21
DW
456 list_for_each_entry(device, &dma_device_list, global_node) {
457 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
458 continue;
bec08513
DW
459 list_for_each_entry(chan, &device->channels, device_node)
460 chan->table_count = 0;
59b5ec21 461 }
bec08513
DW
462
463 /* don't populate the channel_table if no clients are available */
464 if (!dmaengine_ref_count)
465 return;
466
467 /* redistribute available channels */
bec08513
DW
468 for_each_dma_cap_mask(cap, dma_cap_mask_all)
469 for_each_online_cpu(cpu) {
c4d27c4d 470 chan = min_chan(cap, cpu);
bec08513
DW
471 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
472 }
473}
474
0d5484b1
LP
475int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
476{
477 struct dma_device *device;
478
479 if (!chan || !caps)
480 return -EINVAL;
481
482 device = chan->device;
483
484 /* check if the channel supports slave transactions */
485 if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
486 return -ENXIO;
487
488 /*
489 * Check whether it reports it uses the generic slave
490 * capabilities, if not, that means it doesn't support any
491 * kind of slave capabilities reporting.
492 */
493 if (!device->directions)
494 return -ENXIO;
495
496 caps->src_addr_widths = device->src_addr_widths;
497 caps->dst_addr_widths = device->dst_addr_widths;
498 caps->directions = device->directions;
6d5bbed3 499 caps->max_burst = device->max_burst;
0d5484b1 500 caps->residue_granularity = device->residue_granularity;
9eeacd3a 501 caps->descriptor_reuse = device->descriptor_reuse;
0d5484b1 502
88d04643
KK
503 /*
504 * Some devices implement only pause (e.g. to get residuum) but no
505 * resume. However cmd_pause is advertised as pause AND resume.
506 */
507 caps->cmd_pause = !!(device->device_pause && device->device_resume);
0d5484b1
LP
508 caps->cmd_terminate = !!device->device_terminate_all;
509
510 return 0;
511}
512EXPORT_SYMBOL_GPL(dma_get_slave_caps);
513
a53e28da
LPC
514static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
515 struct dma_device *dev,
e2346677 516 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
517{
518 struct dma_chan *chan;
59b5ec21 519
26b64256 520 if (mask && !__dma_device_satisfies_mask(dev, mask)) {
ef859312 521 dev_dbg(dev->dev, "%s: wrong capabilities\n", __func__);
59b5ec21
DW
522 return NULL;
523 }
524 /* devices with multiple channels need special handling as we need to
525 * ensure that all channels are either private or public.
526 */
527 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
528 list_for_each_entry(chan, &dev->channels, device_node) {
529 /* some channels are already publicly allocated */
530 if (chan->client_count)
531 return NULL;
532 }
533
534 list_for_each_entry(chan, &dev->channels, device_node) {
535 if (chan->client_count) {
ef859312 536 dev_dbg(dev->dev, "%s: %s busy\n",
41d5e59c 537 __func__, dma_chan_name(chan));
59b5ec21
DW
538 continue;
539 }
e2346677 540 if (fn && !fn(chan, fn_param)) {
ef859312 541 dev_dbg(dev->dev, "%s: %s filter said false\n",
e2346677
DW
542 __func__, dma_chan_name(chan));
543 continue;
544 }
545 return chan;
59b5ec21
DW
546 }
547
e2346677 548 return NULL;
59b5ec21
DW
549}
550
7bd903c5
PU
551static struct dma_chan *find_candidate(struct dma_device *device,
552 const dma_cap_mask_t *mask,
553 dma_filter_fn fn, void *fn_param)
554{
555 struct dma_chan *chan = private_candidate(mask, device, fn, fn_param);
556 int err;
557
558 if (chan) {
559 /* Found a suitable channel, try to grab, prep, and return it.
560 * We first set DMA_PRIVATE to disable balance_ref_count as this
561 * channel will not be published in the general-purpose
562 * allocator
563 */
564 dma_cap_set(DMA_PRIVATE, device->cap_mask);
565 device->privatecnt++;
566 err = dma_chan_get(chan);
567
568 if (err) {
569 if (err == -ENODEV) {
ef859312
JN
570 dev_dbg(device->dev, "%s: %s module removed\n",
571 __func__, dma_chan_name(chan));
7bd903c5
PU
572 list_del_rcu(&device->global_node);
573 } else
ef859312
JN
574 dev_dbg(device->dev,
575 "%s: failed to get %s: (%d)\n",
7bd903c5
PU
576 __func__, dma_chan_name(chan), err);
577
578 if (--device->privatecnt == 0)
579 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
580
581 chan = ERR_PTR(err);
582 }
583 }
584
585 return chan ? chan : ERR_PTR(-EPROBE_DEFER);
586}
587
59b5ec21 588/**
19d643d6 589 * dma_get_slave_channel - try to get specific channel exclusively
7bb587f4
ZG
590 * @chan: target channel
591 */
592struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
593{
594 int err = -EBUSY;
595
596 /* lock against __dma_request_channel */
597 mutex_lock(&dma_list_mutex);
598
d9a6c8f5 599 if (chan->client_count == 0) {
214fc4e4
PU
600 struct dma_device *device = chan->device;
601
602 dma_cap_set(DMA_PRIVATE, device->cap_mask);
603 device->privatecnt++;
7bb587f4 604 err = dma_chan_get(chan);
214fc4e4 605 if (err) {
ef859312
JN
606 dev_dbg(chan->device->dev,
607 "%s: failed to get %s: (%d)\n",
d9a6c8f5 608 __func__, dma_chan_name(chan), err);
214fc4e4
PU
609 chan = NULL;
610 if (--device->privatecnt == 0)
611 dma_cap_clear(DMA_PRIVATE, device->cap_mask);
612 }
d9a6c8f5 613 } else
7bb587f4
ZG
614 chan = NULL;
615
616 mutex_unlock(&dma_list_mutex);
617
7bb587f4
ZG
618
619 return chan;
620}
621EXPORT_SYMBOL_GPL(dma_get_slave_channel);
622
8010dad5
SW
623struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
624{
625 dma_cap_mask_t mask;
626 struct dma_chan *chan;
8010dad5
SW
627
628 dma_cap_zero(mask);
629 dma_cap_set(DMA_SLAVE, mask);
630
631 /* lock against __dma_request_channel */
632 mutex_lock(&dma_list_mutex);
633
7bd903c5 634 chan = find_candidate(device, &mask, NULL, NULL);
8010dad5
SW
635
636 mutex_unlock(&dma_list_mutex);
637
7bd903c5 638 return IS_ERR(chan) ? NULL : chan;
8010dad5
SW
639}
640EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
641
59b5ec21 642/**
6b9019a7 643 * __dma_request_channel - try to allocate an exclusive channel
59b5ec21
DW
644 * @mask: capabilities that the channel must satisfy
645 * @fn: optional callback to disposition available channels
646 * @fn_param: opaque parameter to pass to dma_filter_fn
0ad7c000
SW
647 *
648 * Returns pointer to appropriate DMA channel on success or NULL.
59b5ec21 649 */
a53e28da
LPC
650struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
651 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
652{
653 struct dma_device *device, *_d;
654 struct dma_chan *chan = NULL;
59b5ec21
DW
655
656 /* Find a channel */
657 mutex_lock(&dma_list_mutex);
658 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
7bd903c5
PU
659 chan = find_candidate(device, mask, fn, fn_param);
660 if (!IS_ERR(chan))
661 break;
59b5ec21 662
7bd903c5 663 chan = NULL;
59b5ec21
DW
664 }
665 mutex_unlock(&dma_list_mutex);
666
ef859312 667 dev_dbg(chan->device->dev, "%s: %s (%s)\n",
63433250
JP
668 __func__,
669 chan ? "success" : "fail",
41d5e59c 670 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
671
672 return chan;
673}
674EXPORT_SYMBOL_GPL(__dma_request_channel);
675
a8135d0d
PU
676static const struct dma_slave_map *dma_filter_match(struct dma_device *device,
677 const char *name,
678 struct device *dev)
679{
680 int i;
681
682 if (!device->filter.mapcnt)
683 return NULL;
684
685 for (i = 0; i < device->filter.mapcnt; i++) {
686 const struct dma_slave_map *map = &device->filter.map[i];
687
688 if (!strcmp(map->devname, dev_name(dev)) &&
689 !strcmp(map->slave, name))
690 return map;
691 }
692
693 return NULL;
694}
695
9a6cecc8 696/**
a8135d0d 697 * dma_request_chan - try to allocate an exclusive slave channel
9a6cecc8
JH
698 * @dev: pointer to client device structure
699 * @name: slave channel name
0ad7c000
SW
700 *
701 * Returns pointer to appropriate DMA channel on success or an error pointer.
9a6cecc8 702 */
a8135d0d 703struct dma_chan *dma_request_chan(struct device *dev, const char *name)
9a6cecc8 704{
a8135d0d
PU
705 struct dma_device *d, *_d;
706 struct dma_chan *chan = NULL;
707
9a6cecc8
JH
708 /* If device-tree is present get slave info from here */
709 if (dev->of_node)
a8135d0d 710 chan = of_dma_request_slave_channel(dev->of_node, name);
9a6cecc8 711
4e82f5dd 712 /* If device was enumerated by ACPI get slave info from here */
a8135d0d
PU
713 if (has_acpi_companion(dev) && !chan)
714 chan = acpi_dma_request_slave_chan_by_name(dev, name);
715
716 if (chan) {
717 /* Valid channel found or requester need to be deferred */
718 if (!IS_ERR(chan) || PTR_ERR(chan) == -EPROBE_DEFER)
719 return chan;
720 }
721
722 /* Try to find the channel via the DMA filter map(s) */
723 mutex_lock(&dma_list_mutex);
724 list_for_each_entry_safe(d, _d, &dma_device_list, global_node) {
725 dma_cap_mask_t mask;
726 const struct dma_slave_map *map = dma_filter_match(d, name, dev);
4e82f5dd 727
a8135d0d
PU
728 if (!map)
729 continue;
730
731 dma_cap_zero(mask);
732 dma_cap_set(DMA_SLAVE, mask);
4e82f5dd 733
a8135d0d
PU
734 chan = find_candidate(d, &mask, d->filter.fn, map->param);
735 if (!IS_ERR(chan))
736 break;
737 }
738 mutex_unlock(&dma_list_mutex);
739
740 return chan ? chan : ERR_PTR(-EPROBE_DEFER);
0ad7c000 741}
a8135d0d 742EXPORT_SYMBOL_GPL(dma_request_chan);
0ad7c000
SW
743
744/**
745 * dma_request_slave_channel - try to allocate an exclusive slave channel
746 * @dev: pointer to client device structure
747 * @name: slave channel name
748 *
749 * Returns pointer to appropriate DMA channel on success or NULL.
750 */
751struct dma_chan *dma_request_slave_channel(struct device *dev,
752 const char *name)
753{
a8135d0d 754 struct dma_chan *ch = dma_request_chan(dev, name);
0ad7c000
SW
755 if (IS_ERR(ch))
756 return NULL;
05aa1a77 757
0ad7c000 758 return ch;
9a6cecc8
JH
759}
760EXPORT_SYMBOL_GPL(dma_request_slave_channel);
761
a8135d0d
PU
762/**
763 * dma_request_chan_by_mask - allocate a channel satisfying certain capabilities
764 * @mask: capabilities that the channel must satisfy
765 *
766 * Returns pointer to appropriate DMA channel on success or an error pointer.
767 */
768struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask)
769{
770 struct dma_chan *chan;
771
772 if (!mask)
773 return ERR_PTR(-ENODEV);
774
775 chan = __dma_request_channel(mask, NULL, NULL);
776 if (!chan)
777 chan = ERR_PTR(-ENODEV);
778
779 return chan;
780}
781EXPORT_SYMBOL_GPL(dma_request_chan_by_mask);
782
59b5ec21
DW
783void dma_release_channel(struct dma_chan *chan)
784{
785 mutex_lock(&dma_list_mutex);
786 WARN_ONCE(chan->client_count != 1,
787 "chan reference count %d != 1\n", chan->client_count);
788 dma_chan_put(chan);
0f571515
AN
789 /* drop PRIVATE cap enabled by __dma_request_channel() */
790 if (--chan->device->privatecnt == 0)
791 dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
59b5ec21
DW
792 mutex_unlock(&dma_list_mutex);
793}
794EXPORT_SYMBOL_GPL(dma_release_channel);
795
d379b01e 796/**
209b84a8 797 * dmaengine_get - register interest in dma_channels
d379b01e 798 */
209b84a8 799void dmaengine_get(void)
d379b01e 800{
6f49a57a
DW
801 struct dma_device *device, *_d;
802 struct dma_chan *chan;
803 int err;
804
c13c8260 805 mutex_lock(&dma_list_mutex);
6f49a57a
DW
806 dmaengine_ref_count++;
807
808 /* try to grab channels */
59b5ec21
DW
809 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
810 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
811 continue;
6f49a57a
DW
812 list_for_each_entry(chan, &device->channels, device_node) {
813 err = dma_chan_get(chan);
814 if (err == -ENODEV) {
815 /* module removed before we could use it */
2ba05622 816 list_del_rcu(&device->global_node);
6f49a57a
DW
817 break;
818 } else if (err)
ef859312
JN
819 dev_dbg(chan->device->dev,
820 "%s: failed to get %s: (%d)\n",
821 __func__, dma_chan_name(chan), err);
6f49a57a 822 }
59b5ec21 823 }
6f49a57a 824
bec08513
DW
825 /* if this is the first reference and there were channels
826 * waiting we need to rebalance to get those channels
827 * incorporated into the channel table
828 */
829 if (dmaengine_ref_count == 1)
830 dma_channel_rebalance();
c13c8260 831 mutex_unlock(&dma_list_mutex);
c13c8260 832}
209b84a8 833EXPORT_SYMBOL(dmaengine_get);
c13c8260
CL
834
835/**
209b84a8 836 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 837 */
209b84a8 838void dmaengine_put(void)
c13c8260 839{
d379b01e 840 struct dma_device *device;
c13c8260
CL
841 struct dma_chan *chan;
842
c13c8260 843 mutex_lock(&dma_list_mutex);
6f49a57a
DW
844 dmaengine_ref_count--;
845 BUG_ON(dmaengine_ref_count < 0);
846 /* drop channel references */
59b5ec21
DW
847 list_for_each_entry(device, &dma_device_list, global_node) {
848 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
849 continue;
6f49a57a
DW
850 list_for_each_entry(chan, &device->channels, device_node)
851 dma_chan_put(chan);
59b5ec21 852 }
c13c8260 853 mutex_unlock(&dma_list_mutex);
c13c8260 854}
209b84a8 855EXPORT_SYMBOL(dmaengine_put);
c13c8260 856
138f4c35
DW
857static bool device_has_all_tx_types(struct dma_device *device)
858{
859 /* A device that satisfies this test has channels that will never cause
860 * an async_tx channel switch event as all possible operation types can
861 * be handled.
862 */
863 #ifdef CONFIG_ASYNC_TX_DMA
864 if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
865 return false;
866 #endif
867
868 #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
869 if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
870 return false;
871 #endif
872
138f4c35
DW
873 #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
874 if (!dma_has_cap(DMA_XOR, device->cap_mask))
875 return false;
7b3cc2b1
DW
876
877 #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
4499a24d
DW
878 if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
879 return false;
138f4c35 880 #endif
7b3cc2b1 881 #endif
138f4c35
DW
882
883 #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
884 if (!dma_has_cap(DMA_PQ, device->cap_mask))
885 return false;
7b3cc2b1
DW
886
887 #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
4499a24d
DW
888 if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
889 return false;
138f4c35 890 #endif
7b3cc2b1 891 #endif
138f4c35
DW
892
893 return true;
894}
895
257b17ca
DW
896static int get_dma_id(struct dma_device *device)
897{
898 int rc;
899
257b17ca 900 mutex_lock(&dma_list_mutex);
257b17ca 901
69ee266b
TH
902 rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
903 if (rc >= 0)
904 device->dev_id = rc;
905
906 mutex_unlock(&dma_list_mutex);
907 return rc < 0 ? rc : 0;
257b17ca
DW
908}
909
c13c8260 910/**
6508871e 911 * dma_async_device_register - registers DMA devices found
c13c8260
CL
912 * @device: &dma_device
913 */
914int dma_async_device_register(struct dma_device *device)
915{
ff487fb7 916 int chancnt = 0, rc;
c13c8260 917 struct dma_chan* chan;
864498aa 918 atomic_t *idr_ref;
c13c8260
CL
919
920 if (!device)
921 return -ENODEV;
922
7405f74b
DW
923 /* validate device routines */
924 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
925 !device->device_prep_dma_memcpy);
926 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
927 !device->device_prep_dma_xor);
099f53cb
DW
928 BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
929 !device->device_prep_dma_xor_val);
b2f46fd8
DW
930 BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
931 !device->device_prep_dma_pq);
932 BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
933 !device->device_prep_dma_pq_val);
4983a501
MR
934 BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
935 !device->device_prep_dma_memset);
9b941c66 936 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 937 !device->device_prep_dma_interrupt);
a86ee03c
IS
938 BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
939 !device->device_prep_dma_sg);
782bc950
SH
940 BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
941 !device->device_prep_dma_cyclic);
b14dab79
JB
942 BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
943 !device->device_prep_interleaved_dma);
7405f74b 944
07934481 945 BUG_ON(!device->device_tx_status);
7405f74b
DW
946 BUG_ON(!device->device_issue_pending);
947 BUG_ON(!device->dev);
948
138f4c35 949 /* note: this only matters in the
5fc6d897 950 * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
138f4c35
DW
951 */
952 if (device_has_all_tx_types(device))
953 dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
954
864498aa
DW
955 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
956 if (!idr_ref)
957 return -ENOMEM;
257b17ca
DW
958 rc = get_dma_id(device);
959 if (rc != 0) {
960 kfree(idr_ref);
864498aa 961 return rc;
257b17ca
DW
962 }
963
964 atomic_set(idr_ref, 0);
c13c8260
CL
965
966 /* represent channels in sysfs. Probably want devs too */
967 list_for_each_entry(chan, &device->channels, device_node) {
257b17ca 968 rc = -ENOMEM;
c13c8260
CL
969 chan->local = alloc_percpu(typeof(*chan->local));
970 if (chan->local == NULL)
257b17ca 971 goto err_out;
41d5e59c
DW
972 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
973 if (chan->dev == NULL) {
974 free_percpu(chan->local);
257b17ca
DW
975 chan->local = NULL;
976 goto err_out;
41d5e59c 977 }
c13c8260
CL
978
979 chan->chan_id = chancnt++;
41d5e59c
DW
980 chan->dev->device.class = &dma_devclass;
981 chan->dev->device.parent = device->dev;
982 chan->dev->chan = chan;
864498aa
DW
983 chan->dev->idr_ref = idr_ref;
984 chan->dev->dev_id = device->dev_id;
985 atomic_inc(idr_ref);
41d5e59c 986 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 987 device->dev_id, chan->chan_id);
c13c8260 988
41d5e59c 989 rc = device_register(&chan->dev->device);
ff487fb7 990 if (rc) {
ff487fb7
JG
991 free_percpu(chan->local);
992 chan->local = NULL;
257b17ca
DW
993 kfree(chan->dev);
994 atomic_dec(idr_ref);
ff487fb7
JG
995 goto err_out;
996 }
7cc5bf9a 997 chan->client_count = 0;
c13c8260 998 }
59b5ec21 999 device->chancnt = chancnt;
c13c8260
CL
1000
1001 mutex_lock(&dma_list_mutex);
59b5ec21
DW
1002 /* take references on public channels */
1003 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
1004 list_for_each_entry(chan, &device->channels, device_node) {
1005 /* if clients are already waiting for channels we need
1006 * to take references on their behalf
1007 */
1008 if (dma_chan_get(chan) == -ENODEV) {
1009 /* note we can only get here for the first
1010 * channel as the remaining channels are
1011 * guaranteed to get a reference
1012 */
1013 rc = -ENODEV;
1014 mutex_unlock(&dma_list_mutex);
1015 goto err_out;
1016 }
1017 }
2ba05622 1018 list_add_tail_rcu(&device->global_node, &dma_device_list);
0f571515
AN
1019 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
1020 device->privatecnt++; /* Always private */
bec08513 1021 dma_channel_rebalance();
c13c8260
CL
1022 mutex_unlock(&dma_list_mutex);
1023
c13c8260 1024 return 0;
ff487fb7
JG
1025
1026err_out:
257b17ca
DW
1027 /* if we never registered a channel just release the idr */
1028 if (atomic_read(idr_ref) == 0) {
1029 mutex_lock(&dma_list_mutex);
1030 idr_remove(&dma_idr, device->dev_id);
1031 mutex_unlock(&dma_list_mutex);
1032 kfree(idr_ref);
1033 return rc;
1034 }
1035
ff487fb7
JG
1036 list_for_each_entry(chan, &device->channels, device_node) {
1037 if (chan->local == NULL)
1038 continue;
41d5e59c
DW
1039 mutex_lock(&dma_list_mutex);
1040 chan->dev->chan = NULL;
1041 mutex_unlock(&dma_list_mutex);
1042 device_unregister(&chan->dev->device);
ff487fb7
JG
1043 free_percpu(chan->local);
1044 }
1045 return rc;
c13c8260 1046}
765e3d8a 1047EXPORT_SYMBOL(dma_async_device_register);
c13c8260 1048
6508871e 1049/**
6f49a57a 1050 * dma_async_device_unregister - unregister a DMA device
6508871e 1051 * @device: &dma_device
f27c580c
DW
1052 *
1053 * This routine is called by dma driver exit routines, dmaengine holds module
1054 * references to prevent it being called while channels are in use.
6508871e
RD
1055 */
1056void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
1057{
1058 struct dma_chan *chan;
c13c8260
CL
1059
1060 mutex_lock(&dma_list_mutex);
2ba05622 1061 list_del_rcu(&device->global_node);
bec08513 1062 dma_channel_rebalance();
c13c8260
CL
1063 mutex_unlock(&dma_list_mutex);
1064
1065 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
1066 WARN_ONCE(chan->client_count,
1067 "%s called while %d clients hold a reference\n",
1068 __func__, chan->client_count);
41d5e59c
DW
1069 mutex_lock(&dma_list_mutex);
1070 chan->dev->chan = NULL;
1071 mutex_unlock(&dma_list_mutex);
1072 device_unregister(&chan->dev->device);
adef4772 1073 free_percpu(chan->local);
c13c8260 1074 }
c13c8260 1075}
765e3d8a 1076EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 1077
45c463ae
DW
1078struct dmaengine_unmap_pool {
1079 struct kmem_cache *cache;
1080 const char *name;
1081 mempool_t *pool;
1082 size_t size;
1083};
7405f74b 1084
45c463ae
DW
1085#define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
1086static struct dmaengine_unmap_pool unmap_pool[] = {
1087 __UNMAP_POOL(2),
3cc377b9 1088 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
45c463ae
DW
1089 __UNMAP_POOL(16),
1090 __UNMAP_POOL(128),
1091 __UNMAP_POOL(256),
1092 #endif
1093};
0036731c 1094
45c463ae
DW
1095static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
1096{
1097 int order = get_count_order(nr);
1098
1099 switch (order) {
1100 case 0 ... 1:
1101 return &unmap_pool[0];
1102 case 2 ... 4:
1103 return &unmap_pool[1];
1104 case 5 ... 7:
1105 return &unmap_pool[2];
1106 case 8:
1107 return &unmap_pool[3];
1108 default:
1109 BUG();
1110 return NULL;
0036731c 1111 }
45c463ae 1112}
7405f74b 1113
45c463ae
DW
1114static void dmaengine_unmap(struct kref *kref)
1115{
1116 struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
1117 struct device *dev = unmap->dev;
1118 int cnt, i;
1119
1120 cnt = unmap->to_cnt;
1121 for (i = 0; i < cnt; i++)
1122 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1123 DMA_TO_DEVICE);
1124 cnt += unmap->from_cnt;
1125 for (; i < cnt; i++)
1126 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1127 DMA_FROM_DEVICE);
1128 cnt += unmap->bidi_cnt;
7476bd79
DW
1129 for (; i < cnt; i++) {
1130 if (unmap->addr[i] == 0)
1131 continue;
45c463ae
DW
1132 dma_unmap_page(dev, unmap->addr[i], unmap->len,
1133 DMA_BIDIRECTIONAL);
7476bd79 1134 }
c1f43dd9 1135 cnt = unmap->map_cnt;
45c463ae
DW
1136 mempool_free(unmap, __get_unmap_pool(cnt)->pool);
1137}
7405f74b 1138
45c463ae
DW
1139void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
1140{
1141 if (unmap)
1142 kref_put(&unmap->kref, dmaengine_unmap);
1143}
1144EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
7405f74b 1145
45c463ae
DW
1146static void dmaengine_destroy_unmap_pool(void)
1147{
1148 int i;
1149
1150 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1151 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1152
240eb916 1153 mempool_destroy(p->pool);
45c463ae 1154 p->pool = NULL;
240eb916 1155 kmem_cache_destroy(p->cache);
45c463ae
DW
1156 p->cache = NULL;
1157 }
7405f74b 1158}
7405f74b 1159
45c463ae 1160static int __init dmaengine_init_unmap_pool(void)
7405f74b 1161{
45c463ae 1162 int i;
7405f74b 1163
45c463ae
DW
1164 for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
1165 struct dmaengine_unmap_pool *p = &unmap_pool[i];
1166 size_t size;
0036731c 1167
45c463ae
DW
1168 size = sizeof(struct dmaengine_unmap_data) +
1169 sizeof(dma_addr_t) * p->size;
1170
1171 p->cache = kmem_cache_create(p->name, size, 0,
1172 SLAB_HWCACHE_ALIGN, NULL);
1173 if (!p->cache)
1174 break;
1175 p->pool = mempool_create_slab_pool(1, p->cache);
1176 if (!p->pool)
1177 break;
0036731c 1178 }
7405f74b 1179
45c463ae
DW
1180 if (i == ARRAY_SIZE(unmap_pool))
1181 return 0;
7405f74b 1182
45c463ae
DW
1183 dmaengine_destroy_unmap_pool();
1184 return -ENOMEM;
1185}
7405f74b 1186
89716462 1187struct dmaengine_unmap_data *
45c463ae
DW
1188dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
1189{
1190 struct dmaengine_unmap_data *unmap;
1191
1192 unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
1193 if (!unmap)
1194 return NULL;
1195
1196 memset(unmap, 0, sizeof(*unmap));
1197 kref_init(&unmap->kref);
1198 unmap->dev = dev;
c1f43dd9 1199 unmap->map_cnt = nr;
45c463ae
DW
1200
1201 return unmap;
7405f74b 1202}
89716462 1203EXPORT_SYMBOL(dmaengine_get_unmap_data);
7405f74b 1204
7405f74b
DW
1205void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1206 struct dma_chan *chan)
1207{
1208 tx->chan = chan;
5fc6d897 1209 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
7405f74b 1210 spin_lock_init(&tx->lock);
caa20d97 1211 #endif
7405f74b
DW
1212}
1213EXPORT_SYMBOL(dma_async_tx_descriptor_init);
1214
07f2211e
DW
1215/* dma_wait_for_async_tx - spin wait for a transaction to complete
1216 * @tx: in-flight transaction to wait on
07f2211e
DW
1217 */
1218enum dma_status
1219dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1220{
95475e57 1221 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
07f2211e
DW
1222
1223 if (!tx)
adfedd9a 1224 return DMA_COMPLETE;
07f2211e 1225
95475e57
DW
1226 while (tx->cookie == -EBUSY) {
1227 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
ef859312
JN
1228 dev_err(tx->chan->device->dev,
1229 "%s timeout waiting for descriptor submission\n",
1230 __func__);
95475e57
DW
1231 return DMA_ERROR;
1232 }
1233 cpu_relax();
1234 }
1235 return dma_sync_wait(tx->chan, tx->cookie);
07f2211e
DW
1236}
1237EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
1238
1239/* dma_run_dependencies - helper routine for dma drivers to process
1240 * (start) dependent operations on their target channel
1241 * @tx: transaction with dependencies
1242 */
1243void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
1244{
caa20d97 1245 struct dma_async_tx_descriptor *dep = txd_next(tx);
07f2211e
DW
1246 struct dma_async_tx_descriptor *dep_next;
1247 struct dma_chan *chan;
1248
1249 if (!dep)
1250 return;
1251
dd59b853 1252 /* we'll submit tx->next now, so clear the link */
caa20d97 1253 txd_clear_next(tx);
07f2211e
DW
1254 chan = dep->chan;
1255
1256 /* keep submitting up until a channel switch is detected
1257 * in that case we will be called again as a result of
1258 * processing the interrupt from async_tx_channel_switch
1259 */
1260 for (; dep; dep = dep_next) {
caa20d97
DW
1261 txd_lock(dep);
1262 txd_clear_parent(dep);
1263 dep_next = txd_next(dep);
07f2211e 1264 if (dep_next && dep_next->chan == chan)
caa20d97 1265 txd_clear_next(dep); /* ->next will be submitted */
07f2211e
DW
1266 else
1267 dep_next = NULL; /* submit current dep and terminate */
caa20d97 1268 txd_unlock(dep);
07f2211e
DW
1269
1270 dep->tx_submit(dep);
1271 }
1272
1273 chan->device->device_issue_pending(chan);
1274}
1275EXPORT_SYMBOL_GPL(dma_run_dependencies);
1276
c13c8260
CL
1277static int __init dma_bus_init(void)
1278{
45c463ae
DW
1279 int err = dmaengine_init_unmap_pool();
1280
1281 if (err)
1282 return err;
c13c8260
CL
1283 return class_register(&dma_devclass);
1284}
652afc27 1285arch_initcall(dma_bus_init);
c13c8260 1286
bec08513 1287