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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * This code implements the DMA subsystem. It provides a HW-neutral interface | |
24 | * for other kernel code to use asynchronous memory copy capabilities, | |
25 | * if present, and allows different HW DMA drivers to register as providing | |
26 | * this capability. | |
27 | * | |
28 | * Due to the fact we are accelerating what is already a relatively fast | |
29 | * operation, the code goes to great lengths to avoid additional overhead, | |
30 | * such as locking. | |
31 | * | |
32 | * LOCKING: | |
33 | * | |
34 | * The subsystem keeps two global lists, dma_device_list and dma_client_list. | |
35 | * Both of these are protected by a mutex, dma_list_mutex. | |
36 | * | |
37 | * Each device has a channels list, which runs unlocked but is never modified | |
38 | * once the device is registered, it's just setup by the driver. | |
39 | * | |
d379b01e DW |
40 | * Each client is responsible for keeping track of the channels it uses. See |
41 | * the definition of dma_event_callback in dmaengine.h. | |
c13c8260 CL |
42 | * |
43 | * Each device has a kref, which is initialized to 1 when the device is | |
891f78ea | 44 | * registered. A kref_get is done for each device registered. When the |
8a5703f8 | 45 | * device is released, the corresponding kref_put is done in the release |
c13c8260 | 46 | * method. Every time one of the device's channels is allocated to a client, |
8a5703f8 | 47 | * a kref_get occurs. When the channel is freed, the corresponding kref_put |
c13c8260 | 48 | * happens. The device's release function does a completion, so |
891f78ea | 49 | * unregister_device does a remove event, device_unregister, a kref_put |
c13c8260 CL |
50 | * for the first reference, then waits on the completion for all other |
51 | * references to finish. | |
52 | * | |
53 | * Each channel has an open-coded implementation of Rusty Russell's "bigref," | |
d379b01e DW |
54 | * with a kref and a per_cpu local_t. A dma_chan_get is called when a client |
55 | * signals that it wants to use a channel, and dma_chan_put is called when | |
8a5703f8 | 56 | * a channel is removed or a client using it is unregistered. A client can |
d379b01e DW |
57 | * take extra references per outstanding transaction, as is the case with |
58 | * the NET DMA client. The release function does a kref_put on the device. | |
59 | * -ChrisL, DanW | |
c13c8260 CL |
60 | */ |
61 | ||
62 | #include <linux/init.h> | |
63 | #include <linux/module.h> | |
7405f74b | 64 | #include <linux/mm.h> |
c13c8260 CL |
65 | #include <linux/device.h> |
66 | #include <linux/dmaengine.h> | |
67 | #include <linux/hardirq.h> | |
68 | #include <linux/spinlock.h> | |
69 | #include <linux/percpu.h> | |
70 | #include <linux/rcupdate.h> | |
71 | #include <linux/mutex.h> | |
7405f74b | 72 | #include <linux/jiffies.h> |
2ba05622 | 73 | #include <linux/rculist.h> |
c13c8260 CL |
74 | |
75 | static DEFINE_MUTEX(dma_list_mutex); | |
76 | static LIST_HEAD(dma_device_list); | |
77 | static LIST_HEAD(dma_client_list); | |
6f49a57a | 78 | static long dmaengine_ref_count; |
c13c8260 CL |
79 | |
80 | /* --- sysfs implementation --- */ | |
81 | ||
891f78ea | 82 | static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf) |
c13c8260 | 83 | { |
891f78ea | 84 | struct dma_chan *chan = to_dma_chan(dev); |
c13c8260 CL |
85 | unsigned long count = 0; |
86 | int i; | |
87 | ||
17f3ae08 | 88 | for_each_possible_cpu(i) |
c13c8260 CL |
89 | count += per_cpu_ptr(chan->local, i)->memcpy_count; |
90 | ||
91 | return sprintf(buf, "%lu\n", count); | |
92 | } | |
93 | ||
891f78ea TJ |
94 | static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr, |
95 | char *buf) | |
c13c8260 | 96 | { |
891f78ea | 97 | struct dma_chan *chan = to_dma_chan(dev); |
c13c8260 CL |
98 | unsigned long count = 0; |
99 | int i; | |
100 | ||
17f3ae08 | 101 | for_each_possible_cpu(i) |
c13c8260 CL |
102 | count += per_cpu_ptr(chan->local, i)->bytes_transferred; |
103 | ||
104 | return sprintf(buf, "%lu\n", count); | |
105 | } | |
106 | ||
891f78ea | 107 | static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf) |
c13c8260 | 108 | { |
891f78ea | 109 | struct dma_chan *chan = to_dma_chan(dev); |
c13c8260 | 110 | |
6f49a57a | 111 | return sprintf(buf, "%d\n", chan->client_count); |
c13c8260 CL |
112 | } |
113 | ||
891f78ea | 114 | static struct device_attribute dma_attrs[] = { |
c13c8260 CL |
115 | __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL), |
116 | __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL), | |
117 | __ATTR(in_use, S_IRUGO, show_in_use, NULL), | |
118 | __ATTR_NULL | |
119 | }; | |
120 | ||
121 | static void dma_async_device_cleanup(struct kref *kref); | |
122 | ||
891f78ea | 123 | static void dma_dev_release(struct device *dev) |
c13c8260 | 124 | { |
891f78ea | 125 | struct dma_chan *chan = to_dma_chan(dev); |
c13c8260 CL |
126 | kref_put(&chan->device->refcount, dma_async_device_cleanup); |
127 | } | |
128 | ||
129 | static struct class dma_devclass = { | |
891f78ea TJ |
130 | .name = "dma", |
131 | .dev_attrs = dma_attrs, | |
132 | .dev_release = dma_dev_release, | |
c13c8260 CL |
133 | }; |
134 | ||
135 | /* --- client and device registration --- */ | |
136 | ||
d379b01e DW |
137 | #define dma_chan_satisfies_mask(chan, mask) \ |
138 | __dma_chan_satisfies_mask((chan), &(mask)) | |
139 | static int | |
140 | __dma_chan_satisfies_mask(struct dma_chan *chan, dma_cap_mask_t *want) | |
141 | { | |
142 | dma_cap_mask_t has; | |
143 | ||
144 | bitmap_and(has.bits, want->bits, chan->device->cap_mask.bits, | |
145 | DMA_TX_TYPE_END); | |
146 | return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END); | |
147 | } | |
148 | ||
6f49a57a DW |
149 | static struct module *dma_chan_to_owner(struct dma_chan *chan) |
150 | { | |
151 | return chan->device->dev->driver->owner; | |
152 | } | |
153 | ||
154 | /** | |
155 | * balance_ref_count - catch up the channel reference count | |
156 | * @chan - channel to balance ->client_count versus dmaengine_ref_count | |
157 | * | |
158 | * balance_ref_count must be called under dma_list_mutex | |
159 | */ | |
160 | static void balance_ref_count(struct dma_chan *chan) | |
161 | { | |
162 | struct module *owner = dma_chan_to_owner(chan); | |
163 | ||
164 | while (chan->client_count < dmaengine_ref_count) { | |
165 | __module_get(owner); | |
166 | chan->client_count++; | |
167 | } | |
168 | } | |
169 | ||
170 | /** | |
171 | * dma_chan_get - try to grab a dma channel's parent driver module | |
172 | * @chan - channel to grab | |
173 | * | |
174 | * Must be called under dma_list_mutex | |
175 | */ | |
176 | static int dma_chan_get(struct dma_chan *chan) | |
177 | { | |
178 | int err = -ENODEV; | |
179 | struct module *owner = dma_chan_to_owner(chan); | |
180 | ||
181 | if (chan->client_count) { | |
182 | __module_get(owner); | |
183 | err = 0; | |
184 | } else if (try_module_get(owner)) | |
185 | err = 0; | |
186 | ||
187 | if (err == 0) | |
188 | chan->client_count++; | |
189 | ||
190 | /* allocate upon first client reference */ | |
191 | if (chan->client_count == 1 && err == 0) { | |
192 | int desc_cnt = chan->device->device_alloc_chan_resources(chan, NULL); | |
193 | ||
194 | if (desc_cnt < 0) { | |
195 | err = desc_cnt; | |
196 | chan->client_count = 0; | |
197 | module_put(owner); | |
198 | } else | |
199 | balance_ref_count(chan); | |
200 | } | |
201 | ||
202 | return err; | |
203 | } | |
204 | ||
205 | /** | |
206 | * dma_chan_put - drop a reference to a dma channel's parent driver module | |
207 | * @chan - channel to release | |
208 | * | |
209 | * Must be called under dma_list_mutex | |
210 | */ | |
211 | static void dma_chan_put(struct dma_chan *chan) | |
212 | { | |
213 | if (!chan->client_count) | |
214 | return; /* this channel failed alloc_chan_resources */ | |
215 | chan->client_count--; | |
216 | module_put(dma_chan_to_owner(chan)); | |
217 | if (chan->client_count == 0) | |
218 | chan->device->device_free_chan_resources(chan); | |
219 | } | |
220 | ||
c13c8260 | 221 | /** |
d379b01e | 222 | * dma_client_chan_alloc - try to allocate channels to a client |
c13c8260 CL |
223 | * @client: &dma_client |
224 | * | |
225 | * Called with dma_list_mutex held. | |
226 | */ | |
d379b01e | 227 | static void dma_client_chan_alloc(struct dma_client *client) |
c13c8260 CL |
228 | { |
229 | struct dma_device *device; | |
230 | struct dma_chan *chan; | |
d379b01e | 231 | enum dma_state_client ack; |
c13c8260 | 232 | |
d379b01e | 233 | /* Find a channel */ |
dc0ee643 HS |
234 | list_for_each_entry(device, &dma_device_list, global_node) { |
235 | /* Does the client require a specific DMA controller? */ | |
236 | if (client->slave && client->slave->dma_dev | |
237 | && client->slave->dma_dev != device->dev) | |
238 | continue; | |
239 | ||
c13c8260 | 240 | list_for_each_entry(chan, &device->channels, device_node) { |
d379b01e | 241 | if (!dma_chan_satisfies_mask(chan, client->cap_mask)) |
c13c8260 | 242 | continue; |
6f49a57a DW |
243 | if (!chan->client_count) |
244 | continue; | |
245 | ack = client->event_callback(client, chan, | |
246 | DMA_RESOURCE_AVAILABLE); | |
c13c8260 | 247 | |
6f49a57a DW |
248 | /* we are done once this client rejects |
249 | * an available resource | |
250 | */ | |
251 | if (ack == DMA_NAK) | |
252 | return; | |
c13c8260 | 253 | } |
dc0ee643 | 254 | } |
c13c8260 CL |
255 | } |
256 | ||
7405f74b DW |
257 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) |
258 | { | |
259 | enum dma_status status; | |
260 | unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000); | |
261 | ||
262 | dma_async_issue_pending(chan); | |
263 | do { | |
264 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); | |
265 | if (time_after_eq(jiffies, dma_sync_wait_timeout)) { | |
266 | printk(KERN_ERR "dma_sync_wait_timeout!\n"); | |
267 | return DMA_ERROR; | |
268 | } | |
269 | } while (status == DMA_IN_PROGRESS); | |
270 | ||
271 | return status; | |
272 | } | |
273 | EXPORT_SYMBOL(dma_sync_wait); | |
274 | ||
c13c8260 | 275 | /** |
6508871e RD |
276 | * dma_chan_cleanup - release a DMA channel's resources |
277 | * @kref: kernel reference structure that contains the DMA channel device | |
c13c8260 CL |
278 | */ |
279 | void dma_chan_cleanup(struct kref *kref) | |
280 | { | |
281 | struct dma_chan *chan = container_of(kref, struct dma_chan, refcount); | |
c13c8260 CL |
282 | kref_put(&chan->device->refcount, dma_async_device_cleanup); |
283 | } | |
765e3d8a | 284 | EXPORT_SYMBOL(dma_chan_cleanup); |
c13c8260 CL |
285 | |
286 | static void dma_chan_free_rcu(struct rcu_head *rcu) | |
287 | { | |
288 | struct dma_chan *chan = container_of(rcu, struct dma_chan, rcu); | |
6f49a57a | 289 | |
c13c8260 CL |
290 | kref_put(&chan->refcount, dma_chan_cleanup); |
291 | } | |
292 | ||
d379b01e | 293 | static void dma_chan_release(struct dma_chan *chan) |
c13c8260 | 294 | { |
c13c8260 CL |
295 | call_rcu(&chan->rcu, dma_chan_free_rcu); |
296 | } | |
297 | ||
bec08513 DW |
298 | /** |
299 | * dma_cap_mask_all - enable iteration over all operation types | |
300 | */ | |
301 | static dma_cap_mask_t dma_cap_mask_all; | |
302 | ||
303 | /** | |
304 | * dma_chan_tbl_ent - tracks channel allocations per core/operation | |
305 | * @chan - associated channel for this entry | |
306 | */ | |
307 | struct dma_chan_tbl_ent { | |
308 | struct dma_chan *chan; | |
309 | }; | |
310 | ||
311 | /** | |
312 | * channel_table - percpu lookup table for memory-to-memory offload providers | |
313 | */ | |
314 | static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END]; | |
315 | ||
316 | static int __init dma_channel_table_init(void) | |
317 | { | |
318 | enum dma_transaction_type cap; | |
319 | int err = 0; | |
320 | ||
321 | bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END); | |
322 | ||
323 | /* 'interrupt' and 'slave' are channel capabilities, but are not | |
324 | * associated with an operation so they do not need an entry in the | |
325 | * channel_table | |
326 | */ | |
327 | clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits); | |
328 | clear_bit(DMA_SLAVE, dma_cap_mask_all.bits); | |
329 | ||
330 | for_each_dma_cap_mask(cap, dma_cap_mask_all) { | |
331 | channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent); | |
332 | if (!channel_table[cap]) { | |
333 | err = -ENOMEM; | |
334 | break; | |
335 | } | |
336 | } | |
337 | ||
338 | if (err) { | |
339 | pr_err("dmaengine: initialization failure\n"); | |
340 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
341 | if (channel_table[cap]) | |
342 | free_percpu(channel_table[cap]); | |
343 | } | |
344 | ||
345 | return err; | |
346 | } | |
347 | subsys_initcall(dma_channel_table_init); | |
348 | ||
349 | /** | |
350 | * dma_find_channel - find a channel to carry out the operation | |
351 | * @tx_type: transaction type | |
352 | */ | |
353 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | |
354 | { | |
355 | struct dma_chan *chan; | |
356 | int cpu; | |
357 | ||
358 | WARN_ONCE(dmaengine_ref_count == 0, | |
359 | "client called %s without a reference", __func__); | |
360 | ||
361 | cpu = get_cpu(); | |
362 | chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan; | |
363 | put_cpu(); | |
364 | ||
365 | return chan; | |
366 | } | |
367 | EXPORT_SYMBOL(dma_find_channel); | |
368 | ||
2ba05622 DW |
369 | /** |
370 | * dma_issue_pending_all - flush all pending operations across all channels | |
371 | */ | |
372 | void dma_issue_pending_all(void) | |
373 | { | |
374 | struct dma_device *device; | |
375 | struct dma_chan *chan; | |
376 | ||
377 | WARN_ONCE(dmaengine_ref_count == 0, | |
378 | "client called %s without a reference", __func__); | |
379 | ||
380 | rcu_read_lock(); | |
381 | list_for_each_entry_rcu(device, &dma_device_list, global_node) | |
382 | list_for_each_entry(chan, &device->channels, device_node) | |
383 | if (chan->client_count) | |
384 | device->device_issue_pending(chan); | |
385 | rcu_read_unlock(); | |
386 | } | |
387 | EXPORT_SYMBOL(dma_issue_pending_all); | |
388 | ||
bec08513 DW |
389 | /** |
390 | * nth_chan - returns the nth channel of the given capability | |
391 | * @cap: capability to match | |
392 | * @n: nth channel desired | |
393 | * | |
394 | * Defaults to returning the channel with the desired capability and the | |
395 | * lowest reference count when 'n' cannot be satisfied. Must be called | |
396 | * under dma_list_mutex. | |
397 | */ | |
398 | static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n) | |
399 | { | |
400 | struct dma_device *device; | |
401 | struct dma_chan *chan; | |
402 | struct dma_chan *ret = NULL; | |
403 | struct dma_chan *min = NULL; | |
404 | ||
405 | list_for_each_entry(device, &dma_device_list, global_node) { | |
406 | if (!dma_has_cap(cap, device->cap_mask)) | |
407 | continue; | |
408 | list_for_each_entry(chan, &device->channels, device_node) { | |
409 | if (!chan->client_count) | |
410 | continue; | |
411 | if (!min) | |
412 | min = chan; | |
413 | else if (chan->table_count < min->table_count) | |
414 | min = chan; | |
415 | ||
416 | if (n-- == 0) { | |
417 | ret = chan; | |
418 | break; /* done */ | |
419 | } | |
420 | } | |
421 | if (ret) | |
422 | break; /* done */ | |
423 | } | |
424 | ||
425 | if (!ret) | |
426 | ret = min; | |
427 | ||
428 | if (ret) | |
429 | ret->table_count++; | |
430 | ||
431 | return ret; | |
432 | } | |
433 | ||
434 | /** | |
435 | * dma_channel_rebalance - redistribute the available channels | |
436 | * | |
437 | * Optimize for cpu isolation (each cpu gets a dedicated channel for an | |
438 | * operation type) in the SMP case, and operation isolation (avoid | |
439 | * multi-tasking channels) in the non-SMP case. Must be called under | |
440 | * dma_list_mutex. | |
441 | */ | |
442 | static void dma_channel_rebalance(void) | |
443 | { | |
444 | struct dma_chan *chan; | |
445 | struct dma_device *device; | |
446 | int cpu; | |
447 | int cap; | |
448 | int n; | |
449 | ||
450 | /* undo the last distribution */ | |
451 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
452 | for_each_possible_cpu(cpu) | |
453 | per_cpu_ptr(channel_table[cap], cpu)->chan = NULL; | |
454 | ||
455 | list_for_each_entry(device, &dma_device_list, global_node) | |
456 | list_for_each_entry(chan, &device->channels, device_node) | |
457 | chan->table_count = 0; | |
458 | ||
459 | /* don't populate the channel_table if no clients are available */ | |
460 | if (!dmaengine_ref_count) | |
461 | return; | |
462 | ||
463 | /* redistribute available channels */ | |
464 | n = 0; | |
465 | for_each_dma_cap_mask(cap, dma_cap_mask_all) | |
466 | for_each_online_cpu(cpu) { | |
467 | if (num_possible_cpus() > 1) | |
468 | chan = nth_chan(cap, n++); | |
469 | else | |
470 | chan = nth_chan(cap, -1); | |
471 | ||
472 | per_cpu_ptr(channel_table[cap], cpu)->chan = chan; | |
473 | } | |
474 | } | |
475 | ||
c13c8260 | 476 | /** |
d379b01e | 477 | * dma_chans_notify_available - broadcast available channels to the clients |
c13c8260 | 478 | */ |
d379b01e | 479 | static void dma_clients_notify_available(void) |
c13c8260 CL |
480 | { |
481 | struct dma_client *client; | |
c13c8260 CL |
482 | |
483 | mutex_lock(&dma_list_mutex); | |
484 | ||
d379b01e DW |
485 | list_for_each_entry(client, &dma_client_list, global_node) |
486 | dma_client_chan_alloc(client); | |
c13c8260 CL |
487 | |
488 | mutex_unlock(&dma_list_mutex); | |
489 | } | |
490 | ||
d379b01e DW |
491 | /** |
492 | * dma_async_client_register - register a &dma_client | |
493 | * @client: ptr to a client structure with valid 'event_callback' and 'cap_mask' | |
494 | */ | |
495 | void dma_async_client_register(struct dma_client *client) | |
496 | { | |
6f49a57a DW |
497 | struct dma_device *device, *_d; |
498 | struct dma_chan *chan; | |
499 | int err; | |
500 | ||
dc0ee643 HS |
501 | /* validate client data */ |
502 | BUG_ON(dma_has_cap(DMA_SLAVE, client->cap_mask) && | |
503 | !client->slave); | |
504 | ||
c13c8260 | 505 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
506 | dmaengine_ref_count++; |
507 | ||
508 | /* try to grab channels */ | |
509 | list_for_each_entry_safe(device, _d, &dma_device_list, global_node) | |
510 | list_for_each_entry(chan, &device->channels, device_node) { | |
511 | err = dma_chan_get(chan); | |
512 | if (err == -ENODEV) { | |
513 | /* module removed before we could use it */ | |
2ba05622 | 514 | list_del_rcu(&device->global_node); |
6f49a57a DW |
515 | break; |
516 | } else if (err) | |
517 | pr_err("dmaengine: failed to get %s: (%d)\n", | |
518 | dev_name(&chan->dev), err); | |
519 | } | |
520 | ||
bec08513 DW |
521 | /* if this is the first reference and there were channels |
522 | * waiting we need to rebalance to get those channels | |
523 | * incorporated into the channel table | |
524 | */ | |
525 | if (dmaengine_ref_count == 1) | |
526 | dma_channel_rebalance(); | |
c13c8260 CL |
527 | list_add_tail(&client->global_node, &dma_client_list); |
528 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 529 | } |
765e3d8a | 530 | EXPORT_SYMBOL(dma_async_client_register); |
c13c8260 CL |
531 | |
532 | /** | |
533 | * dma_async_client_unregister - unregister a client and free the &dma_client | |
6508871e | 534 | * @client: &dma_client to free |
c13c8260 CL |
535 | * |
536 | * Force frees any allocated DMA channels, frees the &dma_client memory | |
537 | */ | |
538 | void dma_async_client_unregister(struct dma_client *client) | |
539 | { | |
d379b01e | 540 | struct dma_device *device; |
c13c8260 CL |
541 | struct dma_chan *chan; |
542 | ||
543 | if (!client) | |
544 | return; | |
545 | ||
c13c8260 | 546 | mutex_lock(&dma_list_mutex); |
6f49a57a DW |
547 | dmaengine_ref_count--; |
548 | BUG_ON(dmaengine_ref_count < 0); | |
549 | /* drop channel references */ | |
d379b01e | 550 | list_for_each_entry(device, &dma_device_list, global_node) |
6f49a57a DW |
551 | list_for_each_entry(chan, &device->channels, device_node) |
552 | dma_chan_put(chan); | |
d379b01e | 553 | |
c13c8260 CL |
554 | list_del(&client->global_node); |
555 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 556 | } |
765e3d8a | 557 | EXPORT_SYMBOL(dma_async_client_unregister); |
c13c8260 CL |
558 | |
559 | /** | |
d379b01e DW |
560 | * dma_async_client_chan_request - send all available channels to the |
561 | * client that satisfy the capability mask | |
562 | * @client - requester | |
c13c8260 | 563 | */ |
d379b01e | 564 | void dma_async_client_chan_request(struct dma_client *client) |
c13c8260 | 565 | { |
d379b01e DW |
566 | mutex_lock(&dma_list_mutex); |
567 | dma_client_chan_alloc(client); | |
568 | mutex_unlock(&dma_list_mutex); | |
c13c8260 | 569 | } |
765e3d8a | 570 | EXPORT_SYMBOL(dma_async_client_chan_request); |
c13c8260 CL |
571 | |
572 | /** | |
6508871e | 573 | * dma_async_device_register - registers DMA devices found |
c13c8260 CL |
574 | * @device: &dma_device |
575 | */ | |
576 | int dma_async_device_register(struct dma_device *device) | |
577 | { | |
578 | static int id; | |
ff487fb7 | 579 | int chancnt = 0, rc; |
c13c8260 CL |
580 | struct dma_chan* chan; |
581 | ||
582 | if (!device) | |
583 | return -ENODEV; | |
584 | ||
7405f74b DW |
585 | /* validate device routines */ |
586 | BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) && | |
587 | !device->device_prep_dma_memcpy); | |
588 | BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) && | |
589 | !device->device_prep_dma_xor); | |
590 | BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) && | |
591 | !device->device_prep_dma_zero_sum); | |
592 | BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) && | |
593 | !device->device_prep_dma_memset); | |
9b941c66 | 594 | BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) && |
7405f74b | 595 | !device->device_prep_dma_interrupt); |
dc0ee643 HS |
596 | BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && |
597 | !device->device_prep_slave_sg); | |
598 | BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && | |
599 | !device->device_terminate_all); | |
7405f74b DW |
600 | |
601 | BUG_ON(!device->device_alloc_chan_resources); | |
602 | BUG_ON(!device->device_free_chan_resources); | |
7405f74b DW |
603 | BUG_ON(!device->device_is_tx_complete); |
604 | BUG_ON(!device->device_issue_pending); | |
605 | BUG_ON(!device->dev); | |
606 | ||
c13c8260 CL |
607 | init_completion(&device->done); |
608 | kref_init(&device->refcount); | |
b0b42b16 DW |
609 | |
610 | mutex_lock(&dma_list_mutex); | |
c13c8260 | 611 | device->dev_id = id++; |
b0b42b16 | 612 | mutex_unlock(&dma_list_mutex); |
c13c8260 CL |
613 | |
614 | /* represent channels in sysfs. Probably want devs too */ | |
615 | list_for_each_entry(chan, &device->channels, device_node) { | |
616 | chan->local = alloc_percpu(typeof(*chan->local)); | |
617 | if (chan->local == NULL) | |
618 | continue; | |
619 | ||
620 | chan->chan_id = chancnt++; | |
891f78ea | 621 | chan->dev.class = &dma_devclass; |
1099dc79 | 622 | chan->dev.parent = device->dev; |
06190d84 KS |
623 | dev_set_name(&chan->dev, "dma%dchan%d", |
624 | device->dev_id, chan->chan_id); | |
c13c8260 | 625 | |
891f78ea | 626 | rc = device_register(&chan->dev); |
ff487fb7 JG |
627 | if (rc) { |
628 | chancnt--; | |
629 | free_percpu(chan->local); | |
630 | chan->local = NULL; | |
631 | goto err_out; | |
632 | } | |
633 | ||
348badf1 HS |
634 | /* One for the channel, one of the class device */ |
635 | kref_get(&device->refcount); | |
c13c8260 | 636 | kref_get(&device->refcount); |
d379b01e | 637 | kref_init(&chan->refcount); |
7cc5bf9a | 638 | chan->client_count = 0; |
d379b01e DW |
639 | chan->slow_ref = 0; |
640 | INIT_RCU_HEAD(&chan->rcu); | |
c13c8260 CL |
641 | } |
642 | ||
643 | mutex_lock(&dma_list_mutex); | |
6f49a57a DW |
644 | if (dmaengine_ref_count) |
645 | list_for_each_entry(chan, &device->channels, device_node) { | |
646 | /* if clients are already waiting for channels we need | |
647 | * to take references on their behalf | |
648 | */ | |
649 | if (dma_chan_get(chan) == -ENODEV) { | |
650 | /* note we can only get here for the first | |
651 | * channel as the remaining channels are | |
652 | * guaranteed to get a reference | |
653 | */ | |
654 | rc = -ENODEV; | |
655 | mutex_unlock(&dma_list_mutex); | |
656 | goto err_out; | |
657 | } | |
658 | } | |
2ba05622 | 659 | list_add_tail_rcu(&device->global_node, &dma_device_list); |
bec08513 | 660 | dma_channel_rebalance(); |
c13c8260 CL |
661 | mutex_unlock(&dma_list_mutex); |
662 | ||
d379b01e | 663 | dma_clients_notify_available(); |
c13c8260 CL |
664 | |
665 | return 0; | |
ff487fb7 JG |
666 | |
667 | err_out: | |
668 | list_for_each_entry(chan, &device->channels, device_node) { | |
669 | if (chan->local == NULL) | |
670 | continue; | |
671 | kref_put(&device->refcount, dma_async_device_cleanup); | |
891f78ea | 672 | device_unregister(&chan->dev); |
ff487fb7 JG |
673 | chancnt--; |
674 | free_percpu(chan->local); | |
675 | } | |
676 | return rc; | |
c13c8260 | 677 | } |
765e3d8a | 678 | EXPORT_SYMBOL(dma_async_device_register); |
c13c8260 CL |
679 | |
680 | /** | |
6508871e RD |
681 | * dma_async_device_cleanup - function called when all references are released |
682 | * @kref: kernel reference object | |
c13c8260 CL |
683 | */ |
684 | static void dma_async_device_cleanup(struct kref *kref) | |
685 | { | |
686 | struct dma_device *device; | |
687 | ||
688 | device = container_of(kref, struct dma_device, refcount); | |
689 | complete(&device->done); | |
690 | } | |
691 | ||
6508871e | 692 | /** |
6f49a57a | 693 | * dma_async_device_unregister - unregister a DMA device |
6508871e RD |
694 | * @device: &dma_device |
695 | */ | |
696 | void dma_async_device_unregister(struct dma_device *device) | |
c13c8260 CL |
697 | { |
698 | struct dma_chan *chan; | |
c13c8260 CL |
699 | |
700 | mutex_lock(&dma_list_mutex); | |
2ba05622 | 701 | list_del_rcu(&device->global_node); |
bec08513 | 702 | dma_channel_rebalance(); |
c13c8260 CL |
703 | mutex_unlock(&dma_list_mutex); |
704 | ||
705 | list_for_each_entry(chan, &device->channels, device_node) { | |
6f49a57a DW |
706 | WARN_ONCE(chan->client_count, |
707 | "%s called while %d clients hold a reference\n", | |
708 | __func__, chan->client_count); | |
891f78ea | 709 | device_unregister(&chan->dev); |
d379b01e | 710 | dma_chan_release(chan); |
c13c8260 | 711 | } |
c13c8260 CL |
712 | |
713 | kref_put(&device->refcount, dma_async_device_cleanup); | |
714 | wait_for_completion(&device->done); | |
715 | } | |
765e3d8a | 716 | EXPORT_SYMBOL(dma_async_device_unregister); |
c13c8260 | 717 | |
7405f74b DW |
718 | /** |
719 | * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses | |
720 | * @chan: DMA channel to offload copy to | |
721 | * @dest: destination address (virtual) | |
722 | * @src: source address (virtual) | |
723 | * @len: length | |
724 | * | |
725 | * Both @dest and @src must be mappable to a bus address according to the | |
726 | * DMA mapping API rules for streaming mappings. | |
727 | * Both @dest and @src must stay memory resident (kernel memory or locked | |
728 | * user space pages). | |
729 | */ | |
730 | dma_cookie_t | |
731 | dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest, | |
732 | void *src, size_t len) | |
733 | { | |
734 | struct dma_device *dev = chan->device; | |
735 | struct dma_async_tx_descriptor *tx; | |
0036731c | 736 | dma_addr_t dma_dest, dma_src; |
7405f74b DW |
737 | dma_cookie_t cookie; |
738 | int cpu; | |
739 | ||
0036731c DW |
740 | dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE); |
741 | dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE); | |
636bdeaa DW |
742 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, |
743 | DMA_CTRL_ACK); | |
0036731c DW |
744 | |
745 | if (!tx) { | |
746 | dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
747 | dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 748 | return -ENOMEM; |
0036731c | 749 | } |
7405f74b | 750 | |
7405f74b | 751 | tx->callback = NULL; |
7405f74b DW |
752 | cookie = tx->tx_submit(tx); |
753 | ||
754 | cpu = get_cpu(); | |
755 | per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; | |
756 | per_cpu_ptr(chan->local, cpu)->memcpy_count++; | |
757 | put_cpu(); | |
758 | ||
759 | return cookie; | |
760 | } | |
761 | EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf); | |
762 | ||
763 | /** | |
764 | * dma_async_memcpy_buf_to_pg - offloaded copy from address to page | |
765 | * @chan: DMA channel to offload copy to | |
766 | * @page: destination page | |
767 | * @offset: offset in page to copy to | |
768 | * @kdata: source address (virtual) | |
769 | * @len: length | |
770 | * | |
771 | * Both @page/@offset and @kdata must be mappable to a bus address according | |
772 | * to the DMA mapping API rules for streaming mappings. | |
773 | * Both @page/@offset and @kdata must stay memory resident (kernel memory or | |
774 | * locked user space pages) | |
775 | */ | |
776 | dma_cookie_t | |
777 | dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page, | |
778 | unsigned int offset, void *kdata, size_t len) | |
779 | { | |
780 | struct dma_device *dev = chan->device; | |
781 | struct dma_async_tx_descriptor *tx; | |
0036731c | 782 | dma_addr_t dma_dest, dma_src; |
7405f74b DW |
783 | dma_cookie_t cookie; |
784 | int cpu; | |
785 | ||
0036731c DW |
786 | dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE); |
787 | dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE); | |
636bdeaa DW |
788 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, |
789 | DMA_CTRL_ACK); | |
0036731c DW |
790 | |
791 | if (!tx) { | |
792 | dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
793 | dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 794 | return -ENOMEM; |
0036731c | 795 | } |
7405f74b | 796 | |
7405f74b | 797 | tx->callback = NULL; |
7405f74b DW |
798 | cookie = tx->tx_submit(tx); |
799 | ||
800 | cpu = get_cpu(); | |
801 | per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; | |
802 | per_cpu_ptr(chan->local, cpu)->memcpy_count++; | |
803 | put_cpu(); | |
804 | ||
805 | return cookie; | |
806 | } | |
807 | EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg); | |
808 | ||
809 | /** | |
810 | * dma_async_memcpy_pg_to_pg - offloaded copy from page to page | |
811 | * @chan: DMA channel to offload copy to | |
812 | * @dest_pg: destination page | |
813 | * @dest_off: offset in page to copy to | |
814 | * @src_pg: source page | |
815 | * @src_off: offset in page to copy from | |
816 | * @len: length | |
817 | * | |
818 | * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus | |
819 | * address according to the DMA mapping API rules for streaming mappings. | |
820 | * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident | |
821 | * (kernel memory or locked user space pages). | |
822 | */ | |
823 | dma_cookie_t | |
824 | dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg, | |
825 | unsigned int dest_off, struct page *src_pg, unsigned int src_off, | |
826 | size_t len) | |
827 | { | |
828 | struct dma_device *dev = chan->device; | |
829 | struct dma_async_tx_descriptor *tx; | |
0036731c | 830 | dma_addr_t dma_dest, dma_src; |
7405f74b DW |
831 | dma_cookie_t cookie; |
832 | int cpu; | |
833 | ||
0036731c DW |
834 | dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE); |
835 | dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len, | |
836 | DMA_FROM_DEVICE); | |
636bdeaa DW |
837 | tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, |
838 | DMA_CTRL_ACK); | |
0036731c DW |
839 | |
840 | if (!tx) { | |
841 | dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE); | |
842 | dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE); | |
7405f74b | 843 | return -ENOMEM; |
0036731c | 844 | } |
7405f74b | 845 | |
7405f74b | 846 | tx->callback = NULL; |
7405f74b DW |
847 | cookie = tx->tx_submit(tx); |
848 | ||
849 | cpu = get_cpu(); | |
850 | per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; | |
851 | per_cpu_ptr(chan->local, cpu)->memcpy_count++; | |
852 | put_cpu(); | |
853 | ||
854 | return cookie; | |
855 | } | |
856 | EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg); | |
857 | ||
858 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
859 | struct dma_chan *chan) | |
860 | { | |
861 | tx->chan = chan; | |
862 | spin_lock_init(&tx->lock); | |
7405f74b DW |
863 | } |
864 | EXPORT_SYMBOL(dma_async_tx_descriptor_init); | |
865 | ||
07f2211e DW |
866 | /* dma_wait_for_async_tx - spin wait for a transaction to complete |
867 | * @tx: in-flight transaction to wait on | |
868 | * | |
869 | * This routine assumes that tx was obtained from a call to async_memcpy, | |
870 | * async_xor, async_memset, etc which ensures that tx is "in-flight" (prepped | |
871 | * and submitted). Walking the parent chain is only meant to cover for DMA | |
872 | * drivers that do not implement the DMA_INTERRUPT capability and may race with | |
873 | * the driver's descriptor cleanup routine. | |
874 | */ | |
875 | enum dma_status | |
876 | dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
877 | { | |
878 | enum dma_status status; | |
879 | struct dma_async_tx_descriptor *iter; | |
880 | struct dma_async_tx_descriptor *parent; | |
881 | ||
882 | if (!tx) | |
883 | return DMA_SUCCESS; | |
884 | ||
885 | WARN_ONCE(tx->parent, "%s: speculatively walking dependency chain for" | |
886 | " %s\n", __func__, dev_name(&tx->chan->dev)); | |
887 | ||
888 | /* poll through the dependency chain, return when tx is complete */ | |
889 | do { | |
890 | iter = tx; | |
891 | ||
892 | /* find the root of the unsubmitted dependency chain */ | |
893 | do { | |
894 | parent = iter->parent; | |
895 | if (!parent) | |
896 | break; | |
897 | else | |
898 | iter = parent; | |
899 | } while (parent); | |
900 | ||
901 | /* there is a small window for ->parent == NULL and | |
902 | * ->cookie == -EBUSY | |
903 | */ | |
904 | while (iter->cookie == -EBUSY) | |
905 | cpu_relax(); | |
906 | ||
907 | status = dma_sync_wait(iter->chan, iter->cookie); | |
908 | } while (status == DMA_IN_PROGRESS || (iter != tx)); | |
909 | ||
910 | return status; | |
911 | } | |
912 | EXPORT_SYMBOL_GPL(dma_wait_for_async_tx); | |
913 | ||
914 | /* dma_run_dependencies - helper routine for dma drivers to process | |
915 | * (start) dependent operations on their target channel | |
916 | * @tx: transaction with dependencies | |
917 | */ | |
918 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx) | |
919 | { | |
920 | struct dma_async_tx_descriptor *dep = tx->next; | |
921 | struct dma_async_tx_descriptor *dep_next; | |
922 | struct dma_chan *chan; | |
923 | ||
924 | if (!dep) | |
925 | return; | |
926 | ||
927 | chan = dep->chan; | |
928 | ||
929 | /* keep submitting up until a channel switch is detected | |
930 | * in that case we will be called again as a result of | |
931 | * processing the interrupt from async_tx_channel_switch | |
932 | */ | |
933 | for (; dep; dep = dep_next) { | |
934 | spin_lock_bh(&dep->lock); | |
935 | dep->parent = NULL; | |
936 | dep_next = dep->next; | |
937 | if (dep_next && dep_next->chan == chan) | |
938 | dep->next = NULL; /* ->next will be submitted */ | |
939 | else | |
940 | dep_next = NULL; /* submit current dep and terminate */ | |
941 | spin_unlock_bh(&dep->lock); | |
942 | ||
943 | dep->tx_submit(dep); | |
944 | } | |
945 | ||
946 | chan->device->device_issue_pending(chan); | |
947 | } | |
948 | EXPORT_SYMBOL_GPL(dma_run_dependencies); | |
949 | ||
c13c8260 CL |
950 | static int __init dma_bus_init(void) |
951 | { | |
952 | mutex_init(&dma_list_mutex); | |
953 | return class_register(&dma_devclass); | |
954 | } | |
c13c8260 CL |
955 | subsys_initcall(dma_bus_init); |
956 | ||
bec08513 | 957 |