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CommitLineData
4a776f0a
HS
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
851b7e16 5 * Copyright (C) 2013 Intel Corporation
4a776f0a
HS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
872f05c6
DW
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
4a776f0a 13#include <linux/delay.h>
b7f080cf 14#include <linux/dma-mapping.h>
4a776f0a 15#include <linux/dmaengine.h>
981ed70d 16#include <linux/freezer.h>
4a776f0a
HS
17#include <linux/init.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/random.h>
5a0e3ad6 22#include <linux/slab.h>
4a776f0a
HS
23#include <linux/wait.h>
24
25static unsigned int test_buf_size = 16384;
a6c268d0 26module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
4a776f0a
HS
27MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
28
06190d84 29static char test_channel[20];
a6c268d0
AS
30module_param_string(channel, test_channel, sizeof(test_channel),
31 S_IRUGO | S_IWUSR);
4a776f0a
HS
32MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
33
a85159fe 34static char test_device[32];
a6c268d0
AS
35module_param_string(device, test_device, sizeof(test_device),
36 S_IRUGO | S_IWUSR);
4a776f0a
HS
37MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
38
39static unsigned int threads_per_chan = 1;
a6c268d0 40module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
4a776f0a
HS
41MODULE_PARM_DESC(threads_per_chan,
42 "Number of threads to start per channel (default: 1)");
43
44static unsigned int max_channels;
a6c268d0 45module_param(max_channels, uint, S_IRUGO | S_IWUSR);
33df8ca0 46MODULE_PARM_DESC(max_channels,
4a776f0a
HS
47 "Maximum number of channels to use (default: all)");
48
0a2ff57d 49static unsigned int iterations;
a6c268d0 50module_param(iterations, uint, S_IRUGO | S_IWUSR);
0a2ff57d
NF
51MODULE_PARM_DESC(iterations,
52 "Iterations before stopping test (default: infinite)");
53
b54d5cb9 54static unsigned int xor_sources = 3;
a6c268d0 55module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
b54d5cb9
DW
56MODULE_PARM_DESC(xor_sources,
57 "Number of xor source buffers (default: 3)");
58
58691d64 59static unsigned int pq_sources = 3;
a6c268d0 60module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
58691d64
DW
61MODULE_PARM_DESC(pq_sources,
62 "Number of p+q source buffers (default: 3)");
63
d42efe6b 64static int timeout = 3000;
a6c268d0 65module_param(timeout, uint, S_IRUGO | S_IWUSR);
85ee7a1d
JP
66MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
67 "Pass -1 for infinite timeout");
d42efe6b 68
e3b9c347
DW
69static bool noverify;
70module_param(noverify, bool, S_IRUGO | S_IWUSR);
71MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
4a776f0a 72
50137a7d
DW
73static bool verbose;
74module_param(verbose, bool, S_IRUGO | S_IWUSR);
75MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
4a776f0a 76
e03e93a9 77/**
15b8a8ea 78 * struct dmatest_params - test parameters.
e03e93a9
AS
79 * @buf_size: size of the memcpy test buffer
80 * @channel: bus ID of the channel to test
81 * @device: bus ID of the DMA Engine to test
82 * @threads_per_chan: number of threads to start per channel
83 * @max_channels: maximum number of channels to use
84 * @iterations: iterations before stopping test
85 * @xor_sources: number of xor source buffers
86 * @pq_sources: number of p+q source buffers
87 * @timeout: transfer timeout in msec, -1 for infinite timeout
88 */
15b8a8ea 89struct dmatest_params {
e03e93a9
AS
90 unsigned int buf_size;
91 char channel[20];
a85159fe 92 char device[32];
e03e93a9
AS
93 unsigned int threads_per_chan;
94 unsigned int max_channels;
95 unsigned int iterations;
96 unsigned int xor_sources;
97 unsigned int pq_sources;
98 int timeout;
e3b9c347 99 bool noverify;
15b8a8ea
AS
100};
101
102/**
103 * struct dmatest_info - test information.
104 * @params: test parameters
851b7e16 105 * @lock: access protection to the fields of this structure
15b8a8ea 106 */
a310d037 107static struct dmatest_info {
15b8a8ea
AS
108 /* Test parameters */
109 struct dmatest_params params;
838cc704
AS
110
111 /* Internal state */
112 struct list_head channels;
113 unsigned int nr_channels;
851b7e16 114 struct mutex lock;
a310d037
DW
115 bool did_init;
116} test_info = {
117 .channels = LIST_HEAD_INIT(test_info.channels),
118 .lock = __MUTEX_INITIALIZER(test_info.lock),
119};
851b7e16 120
a310d037
DW
121static int dmatest_run_set(const char *val, const struct kernel_param *kp);
122static int dmatest_run_get(char *val, const struct kernel_param *kp);
9c27847d 123static const struct kernel_param_ops run_ops = {
a310d037
DW
124 .set = dmatest_run_set,
125 .get = dmatest_run_get,
e03e93a9 126};
a310d037
DW
127static bool dmatest_run;
128module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
129MODULE_PARM_DESC(run, "Run the test (default: false)");
e03e93a9 130
a310d037
DW
131/* Maximum amount of mismatched bytes in buffer to print */
132#define MAX_ERROR_COUNT 32
133
134/*
135 * Initialization patterns. All bytes in the source buffer has bit 7
136 * set, all bytes in the destination buffer has bit 7 cleared.
137 *
138 * Bit 6 is set for all bytes which are to be copied by the DMA
139 * engine. Bit 5 is set for all bytes which are to be overwritten by
140 * the DMA engine.
141 *
142 * The remaining bits are the inverse of a counter which increments by
143 * one for each byte address.
144 */
145#define PATTERN_SRC 0x80
146#define PATTERN_DST 0x00
147#define PATTERN_COPY 0x40
148#define PATTERN_OVERWRITE 0x20
149#define PATTERN_COUNT_MASK 0x1f
851b7e16 150
a310d037
DW
151struct dmatest_thread {
152 struct list_head node;
153 struct dmatest_info *info;
154 struct task_struct *task;
155 struct dma_chan *chan;
156 u8 **srcs;
157 u8 **dsts;
158 enum dma_transaction_type type;
159 bool done;
160};
95019c8c 161
a310d037
DW
162struct dmatest_chan {
163 struct list_head node;
164 struct dma_chan *chan;
165 struct list_head threads;
e03e93a9
AS
166};
167
2d88ce76
DW
168static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
169static bool wait;
170
171static bool is_threaded_test_run(struct dmatest_info *info)
172{
173 struct dmatest_chan *dtc;
174
175 list_for_each_entry(dtc, &info->channels, node) {
176 struct dmatest_thread *thread;
177
178 list_for_each_entry(thread, &dtc->threads, node) {
179 if (!thread->done)
180 return true;
181 }
182 }
183
184 return false;
185}
186
187static int dmatest_wait_get(char *val, const struct kernel_param *kp)
188{
189 struct dmatest_info *info = &test_info;
190 struct dmatest_params *params = &info->params;
191
192 if (params->iterations)
193 wait_event(thread_wait, !is_threaded_test_run(info));
194 wait = true;
195 return param_get_bool(val, kp);
196}
197
9c27847d 198static const struct kernel_param_ops wait_ops = {
2d88ce76
DW
199 .get = dmatest_wait_get,
200 .set = param_set_bool,
201};
202module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
203MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
e03e93a9 204
15b8a8ea 205static bool dmatest_match_channel(struct dmatest_params *params,
e03e93a9 206 struct dma_chan *chan)
4a776f0a 207{
15b8a8ea 208 if (params->channel[0] == '\0')
4a776f0a 209 return true;
15b8a8ea 210 return strcmp(dma_chan_name(chan), params->channel) == 0;
4a776f0a
HS
211}
212
15b8a8ea 213static bool dmatest_match_device(struct dmatest_params *params,
e03e93a9 214 struct dma_device *device)
4a776f0a 215{
15b8a8ea 216 if (params->device[0] == '\0')
4a776f0a 217 return true;
15b8a8ea 218 return strcmp(dev_name(device->dev), params->device) == 0;
4a776f0a
HS
219}
220
221static unsigned long dmatest_random(void)
222{
223 unsigned long buf;
224
be9fa5a4 225 prandom_bytes(&buf, sizeof(buf));
4a776f0a
HS
226 return buf;
227}
228
e03e93a9
AS
229static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
230 unsigned int buf_size)
4a776f0a
HS
231{
232 unsigned int i;
b54d5cb9
DW
233 u8 *buf;
234
235 for (; (buf = *bufs); bufs++) {
236 for (i = 0; i < start; i++)
237 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
238 for ( ; i < start + len; i++)
239 buf[i] = PATTERN_SRC | PATTERN_COPY
c019894e 240 | (~i & PATTERN_COUNT_MASK);
e03e93a9 241 for ( ; i < buf_size; i++)
b54d5cb9
DW
242 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
243 buf++;
244 }
4a776f0a
HS
245}
246
e03e93a9
AS
247static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
248 unsigned int buf_size)
4a776f0a
HS
249{
250 unsigned int i;
b54d5cb9
DW
251 u8 *buf;
252
253 for (; (buf = *bufs); bufs++) {
254 for (i = 0; i < start; i++)
255 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
256 for ( ; i < start + len; i++)
257 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
258 | (~i & PATTERN_COUNT_MASK);
e03e93a9 259 for ( ; i < buf_size; i++)
b54d5cb9
DW
260 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
261 }
4a776f0a
HS
262}
263
7b610178
DW
264static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
265 unsigned int counter, bool is_srcbuf)
266{
267 u8 diff = actual ^ pattern;
268 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
269 const char *thread_name = current->comm;
270
271 if (is_srcbuf)
272 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
273 thread_name, index, expected, actual);
274 else if ((pattern & PATTERN_COPY)
275 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
276 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
277 thread_name, index, expected, actual);
278 else if (diff & PATTERN_SRC)
279 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
280 thread_name, index, expected, actual);
281 else
282 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
283 thread_name, index, expected, actual);
284}
285
286static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
287 unsigned int end, unsigned int counter, u8 pattern,
288 bool is_srcbuf)
4a776f0a
HS
289{
290 unsigned int i;
291 unsigned int error_count = 0;
292 u8 actual;
b54d5cb9
DW
293 u8 expected;
294 u8 *buf;
295 unsigned int counter_orig = counter;
296
297 for (; (buf = *bufs); bufs++) {
298 counter = counter_orig;
299 for (i = start; i < end; i++) {
300 actual = buf[i];
301 expected = pattern | (~counter & PATTERN_COUNT_MASK);
302 if (actual != expected) {
7b610178
DW
303 if (error_count < MAX_ERROR_COUNT)
304 dmatest_mismatch(actual, pattern, i,
305 counter, is_srcbuf);
b54d5cb9
DW
306 error_count++;
307 }
308 counter++;
4a776f0a 309 }
4a776f0a
HS
310 }
311
74b5c07a 312 if (error_count > MAX_ERROR_COUNT)
7b610178 313 pr_warn("%s: %u errors suppressed\n",
74b5c07a 314 current->comm, error_count - MAX_ERROR_COUNT);
4a776f0a
HS
315
316 return error_count;
317}
318
adfa543e
TH
319/* poor man's completion - we want to use wait_event_freezable() on it */
320struct dmatest_done {
321 bool done;
322 wait_queue_head_t *wait;
323};
324
325static void dmatest_callback(void *arg)
e44e0aa3 326{
adfa543e
TH
327 struct dmatest_done *done = arg;
328
329 done->done = true;
330 wake_up_all(done->wait);
e44e0aa3
DW
331}
332
8be9e32b
AM
333static unsigned int min_odd(unsigned int x, unsigned int y)
334{
335 unsigned int val = min(x, y);
336
337 return val % 2 ? val : val - 1;
338}
339
872f05c6
DW
340static void result(const char *err, unsigned int n, unsigned int src_off,
341 unsigned int dst_off, unsigned int len, unsigned long data)
d86b2f29 342{
2acec150 343 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
872f05c6 344 current->comm, n, err, src_off, dst_off, len, data);
d86b2f29
AS
345}
346
872f05c6
DW
347static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
348 unsigned int dst_off, unsigned int len,
349 unsigned long data)
95019c8c 350{
2acec150 351 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
a835bb85 352 current->comm, n, err, src_off, dst_off, len, data);
95019c8c
AS
353}
354
a835bb85
AS
355#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
356 if (verbose) \
357 result(err, n, src_off, dst_off, len, data); \
358 else \
359 dbg_result(err, n, src_off, dst_off, len, data);\
50137a7d 360})
95019c8c 361
86727443 362static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
d86b2f29 363{
86727443 364 unsigned long long per_sec = 1000000;
d86b2f29 365
86727443
DW
366 if (runtime <= 0)
367 return 0;
95019c8c 368
86727443
DW
369 /* drop precision until runtime is 32-bits */
370 while (runtime > UINT_MAX) {
371 runtime >>= 1;
372 per_sec <<= 1;
95019c8c
AS
373 }
374
86727443
DW
375 per_sec *= val;
376 do_div(per_sec, runtime);
377 return per_sec;
95019c8c
AS
378}
379
86727443 380static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
95019c8c 381{
86727443 382 return dmatest_persec(runtime, len >> 10);
95019c8c
AS
383}
384
4a776f0a
HS
385/*
386 * This function repeatedly tests DMA transfers of various lengths and
b54d5cb9
DW
387 * offsets for a given operation type until it is told to exit by
388 * kthread_stop(). There may be multiple threads running this function
389 * in parallel for a single channel, and there may be multiple channels
390 * being tested in parallel.
4a776f0a
HS
391 *
392 * Before each test, the source and destination buffer is initialized
393 * with a known pattern. This pattern is different depending on
394 * whether it's in an area which is supposed to be copied or
395 * overwritten, and different in the source and destination buffers.
396 * So if the DMA engine doesn't copy exactly what we tell it to copy,
397 * we'll notice.
398 */
399static int dmatest_func(void *data)
400{
adfa543e 401 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
4a776f0a 402 struct dmatest_thread *thread = data;
adfa543e 403 struct dmatest_done done = { .wait = &done_wait };
e03e93a9 404 struct dmatest_info *info;
15b8a8ea 405 struct dmatest_params *params;
4a776f0a 406 struct dma_chan *chan;
8be9e32b 407 struct dma_device *dev;
4a776f0a
HS
408 unsigned int error_count;
409 unsigned int failed_tests = 0;
410 unsigned int total_tests = 0;
411 dma_cookie_t cookie;
412 enum dma_status status;
b54d5cb9 413 enum dma_ctrl_flags flags;
945b5af3 414 u8 *pq_coefs = NULL;
4a776f0a 415 int ret;
b54d5cb9
DW
416 int src_cnt;
417 int dst_cnt;
418 int i;
86727443
DW
419 ktime_t ktime;
420 s64 runtime = 0;
421 unsigned long long total_len = 0;
4a776f0a 422
adfa543e 423 set_freezable();
4a776f0a
HS
424
425 ret = -ENOMEM;
4a776f0a
HS
426
427 smp_rmb();
e03e93a9 428 info = thread->info;
15b8a8ea 429 params = &info->params;
4a776f0a 430 chan = thread->chan;
8be9e32b 431 dev = chan->device;
b54d5cb9
DW
432 if (thread->type == DMA_MEMCPY)
433 src_cnt = dst_cnt = 1;
434 else if (thread->type == DMA_XOR) {
8be9e32b 435 /* force odd to ensure dst = src */
15b8a8ea 436 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
b54d5cb9 437 dst_cnt = 1;
58691d64 438 } else if (thread->type == DMA_PQ) {
8be9e32b 439 /* force odd to ensure dst = src */
15b8a8ea 440 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
58691d64 441 dst_cnt = 2;
945b5af3 442
15b8a8ea 443 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
945b5af3
AS
444 if (!pq_coefs)
445 goto err_thread_type;
446
94de648d 447 for (i = 0; i < src_cnt; i++)
58691d64 448 pq_coefs[i] = 1;
b54d5cb9 449 } else
945b5af3 450 goto err_thread_type;
b54d5cb9
DW
451
452 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
453 if (!thread->srcs)
454 goto err_srcs;
455 for (i = 0; i < src_cnt; i++) {
15b8a8ea 456 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
b54d5cb9
DW
457 if (!thread->srcs[i])
458 goto err_srcbuf;
459 }
460 thread->srcs[i] = NULL;
461
462 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
463 if (!thread->dsts)
464 goto err_dsts;
465 for (i = 0; i < dst_cnt; i++) {
15b8a8ea 466 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
b54d5cb9
DW
467 if (!thread->dsts[i])
468 goto err_dstbuf;
469 }
470 thread->dsts[i] = NULL;
471
e44e0aa3
DW
472 set_user_nice(current, 10);
473
b203bd3f 474 /*
d1cab34c 475 * src and dst buffers are freed by ourselves below
b203bd3f 476 */
0776ae7b 477 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
4a776f0a 478
86727443 479 ktime = ktime_get();
0a2ff57d 480 while (!kthread_should_stop()
15b8a8ea 481 && !(params->iterations && total_tests >= params->iterations)) {
b54d5cb9 482 struct dma_async_tx_descriptor *tx = NULL;
4076e755
DW
483 struct dmaengine_unmap_data *um;
484 dma_addr_t srcs[src_cnt];
485 dma_addr_t *dsts;
ede23a58 486 unsigned int src_off, dst_off, len;
83544ae9 487 u8 align = 0;
d86be86e 488
4a776f0a
HS
489 total_tests++;
490
83544ae9
DW
491 /* honor alignment restrictions */
492 if (thread->type == DMA_MEMCPY)
493 align = dev->copy_align;
494 else if (thread->type == DMA_XOR)
495 align = dev->xor_align;
496 else if (thread->type == DMA_PQ)
497 align = dev->pq_align;
498
15b8a8ea 499 if (1 << align > params->buf_size) {
cfe4f275 500 pr_err("%u-byte buffer too small for %d-byte alignment\n",
15b8a8ea 501 params->buf_size, 1 << align);
cfe4f275
GL
502 break;
503 }
504
ede23a58 505 if (params->noverify)
e3b9c347 506 len = params->buf_size;
ede23a58
AS
507 else
508 len = dmatest_random() % params->buf_size + 1;
509
510 len = (len >> align) << align;
511 if (!len)
512 len = 1 << align;
513
514 total_len += len;
515
516 if (params->noverify) {
e3b9c347
DW
517 src_off = 0;
518 dst_off = 0;
519 } else {
e3b9c347
DW
520 src_off = dmatest_random() % (params->buf_size - len + 1);
521 dst_off = dmatest_random() % (params->buf_size - len + 1);
522
523 src_off = (src_off >> align) << align;
524 dst_off = (dst_off >> align) << align;
525
526 dmatest_init_srcs(thread->srcs, src_off, len,
527 params->buf_size);
528 dmatest_init_dsts(thread->dsts, dst_off, len,
529 params->buf_size);
530 }
531
4076e755
DW
532 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
533 GFP_KERNEL);
534 if (!um) {
535 failed_tests++;
536 result("unmap data NULL", total_tests,
537 src_off, dst_off, len, ret);
538 continue;
539 }
4a776f0a 540
4076e755 541 um->len = params->buf_size;
b54d5cb9 542 for (i = 0; i < src_cnt; i++) {
745c00da 543 void *buf = thread->srcs[i];
4076e755 544 struct page *pg = virt_to_page(buf);
745c00da 545 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
4076e755
DW
546
547 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
548 um->len, DMA_TO_DEVICE);
549 srcs[i] = um->addr[i] + src_off;
550 ret = dma_mapping_error(dev->dev, um->addr[i]);
afde3be1 551 if (ret) {
4076e755 552 dmaengine_unmap_put(um);
872f05c6
DW
553 result("src mapping error", total_tests,
554 src_off, dst_off, len, ret);
afde3be1
AS
555 failed_tests++;
556 continue;
557 }
4076e755 558 um->to_cnt++;
b54d5cb9 559 }
d86be86e 560 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
4076e755 561 dsts = &um->addr[src_cnt];
b54d5cb9 562 for (i = 0; i < dst_cnt; i++) {
745c00da 563 void *buf = thread->dsts[i];
4076e755 564 struct page *pg = virt_to_page(buf);
745c00da 565 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
4076e755
DW
566
567 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
568 DMA_BIDIRECTIONAL);
569 ret = dma_mapping_error(dev->dev, dsts[i]);
afde3be1 570 if (ret) {
4076e755 571 dmaengine_unmap_put(um);
872f05c6
DW
572 result("dst mapping error", total_tests,
573 src_off, dst_off, len, ret);
afde3be1
AS
574 failed_tests++;
575 continue;
576 }
4076e755 577 um->bidi_cnt++;
b54d5cb9
DW
578 }
579
580 if (thread->type == DMA_MEMCPY)
581 tx = dev->device_prep_dma_memcpy(chan,
4076e755
DW
582 dsts[0] + dst_off,
583 srcs[0], len, flags);
b54d5cb9
DW
584 else if (thread->type == DMA_XOR)
585 tx = dev->device_prep_dma_xor(chan,
4076e755
DW
586 dsts[0] + dst_off,
587 srcs, src_cnt,
b54d5cb9 588 len, flags);
58691d64
DW
589 else if (thread->type == DMA_PQ) {
590 dma_addr_t dma_pq[dst_cnt];
591
592 for (i = 0; i < dst_cnt; i++)
4076e755
DW
593 dma_pq[i] = dsts[i] + dst_off;
594 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
94de648d 595 src_cnt, pq_coefs,
58691d64
DW
596 len, flags);
597 }
d86be86e 598
d86be86e 599 if (!tx) {
4076e755 600 dmaengine_unmap_put(um);
872f05c6
DW
601 result("prep error", total_tests, src_off,
602 dst_off, len, ret);
d86be86e
AN
603 msleep(100);
604 failed_tests++;
605 continue;
606 }
e44e0aa3 607
adfa543e 608 done.done = false;
e44e0aa3 609 tx->callback = dmatest_callback;
adfa543e 610 tx->callback_param = &done;
d86be86e
AN
611 cookie = tx->tx_submit(tx);
612
4a776f0a 613 if (dma_submit_error(cookie)) {
4076e755 614 dmaengine_unmap_put(um);
872f05c6
DW
615 result("submit error", total_tests, src_off,
616 dst_off, len, ret);
4a776f0a
HS
617 msleep(100);
618 failed_tests++;
619 continue;
620 }
b54d5cb9 621 dma_async_issue_pending(chan);
4a776f0a 622
bcc567e3 623 wait_event_freezable_timeout(done_wait, done.done,
15b8a8ea 624 msecs_to_jiffies(params->timeout));
981ed70d 625
e44e0aa3 626 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
4a776f0a 627
adfa543e
TH
628 if (!done.done) {
629 /*
630 * We're leaving the timed out dma operation with
631 * dangling pointer to done_wait. To make this
632 * correct, we'll need to allocate wait_done for
633 * each test iteration and perform "who's gonna
634 * free it this time?" dancing. For now, just
635 * leave it dangling.
636 */
4076e755 637 dmaengine_unmap_put(um);
872f05c6
DW
638 result("test timed out", total_tests, src_off, dst_off,
639 len, 0);
e44e0aa3
DW
640 failed_tests++;
641 continue;
19e9f99f 642 } else if (status != DMA_COMPLETE) {
4076e755 643 dmaengine_unmap_put(um);
872f05c6
DW
644 result(status == DMA_ERROR ?
645 "completion error status" :
646 "completion busy status", total_tests, src_off,
647 dst_off, len, ret);
4a776f0a
HS
648 failed_tests++;
649 continue;
650 }
e44e0aa3 651
4076e755 652 dmaengine_unmap_put(um);
4a776f0a 653
e3b9c347 654 if (params->noverify) {
50137a7d
DW
655 verbose_result("test passed", total_tests, src_off,
656 dst_off, len, 0);
e3b9c347
DW
657 continue;
658 }
4a776f0a 659
872f05c6 660 pr_debug("%s: verifying source buffer...\n", current->comm);
e3b9c347 661 error_count = dmatest_verify(thread->srcs, 0, src_off,
4a776f0a 662 0, PATTERN_SRC, true);
7b610178
DW
663 error_count += dmatest_verify(thread->srcs, src_off,
664 src_off + len, src_off,
665 PATTERN_SRC | PATTERN_COPY, true);
666 error_count += dmatest_verify(thread->srcs, src_off + len,
667 params->buf_size, src_off + len,
668 PATTERN_SRC, true);
669
872f05c6 670 pr_debug("%s: verifying dest buffer...\n", current->comm);
7b610178 671 error_count += dmatest_verify(thread->dsts, 0, dst_off,
4a776f0a 672 0, PATTERN_DST, false);
7b610178
DW
673 error_count += dmatest_verify(thread->dsts, dst_off,
674 dst_off + len, src_off,
675 PATTERN_SRC | PATTERN_COPY, false);
676 error_count += dmatest_verify(thread->dsts, dst_off + len,
677 params->buf_size, dst_off + len,
678 PATTERN_DST, false);
4a776f0a
HS
679
680 if (error_count) {
872f05c6
DW
681 result("data error", total_tests, src_off, dst_off,
682 len, error_count);
4a776f0a
HS
683 failed_tests++;
684 } else {
50137a7d
DW
685 verbose_result("test passed", total_tests, src_off,
686 dst_off, len, 0);
4a776f0a
HS
687 }
688 }
86727443 689 runtime = ktime_us_delta(ktime_get(), ktime);
4a776f0a
HS
690
691 ret = 0;
8e1f50d7 692err_dstbuf:
b54d5cb9
DW
693 for (i = 0; thread->dsts[i]; i++)
694 kfree(thread->dsts[i]);
b54d5cb9
DW
695 kfree(thread->dsts);
696err_dsts:
8e1f50d7 697err_srcbuf:
b54d5cb9
DW
698 for (i = 0; thread->srcs[i]; i++)
699 kfree(thread->srcs[i]);
b54d5cb9
DW
700 kfree(thread->srcs);
701err_srcs:
945b5af3
AS
702 kfree(pq_coefs);
703err_thread_type:
86727443
DW
704 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
705 current->comm, total_tests, failed_tests,
706 dmatest_persec(runtime, total_tests),
707 dmatest_KBs(runtime, total_len), ret);
0a2ff57d 708
9704efaa 709 /* terminate all transfers on specified channels */
5e034f7b
SH
710 if (ret)
711 dmaengine_terminate_all(chan);
712
3e5ccd86 713 thread->done = true;
2d88ce76 714 wake_up(&thread_wait);
0a2ff57d 715
4a776f0a
HS
716 return ret;
717}
718
719static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
720{
721 struct dmatest_thread *thread;
722 struct dmatest_thread *_thread;
723 int ret;
724
725 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
726 ret = kthread_stop(thread->task);
0adff800
DW
727 pr_debug("thread %s exited with status %d\n",
728 thread->task->comm, ret);
4a776f0a 729 list_del(&thread->node);
2d88ce76 730 put_task_struct(thread->task);
4a776f0a
HS
731 kfree(thread);
732 }
9704efaa
VK
733
734 /* terminate all transfers on specified channels */
944ea4dd 735 dmaengine_terminate_all(dtc->chan);
9704efaa 736
4a776f0a
HS
737 kfree(dtc);
738}
739
e03e93a9
AS
740static int dmatest_add_threads(struct dmatest_info *info,
741 struct dmatest_chan *dtc, enum dma_transaction_type type)
4a776f0a 742{
15b8a8ea 743 struct dmatest_params *params = &info->params;
b54d5cb9
DW
744 struct dmatest_thread *thread;
745 struct dma_chan *chan = dtc->chan;
746 char *op;
747 unsigned int i;
4a776f0a 748
b54d5cb9
DW
749 if (type == DMA_MEMCPY)
750 op = "copy";
751 else if (type == DMA_XOR)
752 op = "xor";
58691d64
DW
753 else if (type == DMA_PQ)
754 op = "pq";
b54d5cb9
DW
755 else
756 return -EINVAL;
4a776f0a 757
15b8a8ea 758 for (i = 0; i < params->threads_per_chan; i++) {
4a776f0a
HS
759 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
760 if (!thread) {
0adff800
DW
761 pr_warn("No memory for %s-%s%u\n",
762 dma_chan_name(chan), op, i);
4a776f0a
HS
763 break;
764 }
e03e93a9 765 thread->info = info;
4a776f0a 766 thread->chan = dtc->chan;
b54d5cb9 767 thread->type = type;
4a776f0a 768 smp_wmb();
2d88ce76 769 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
b54d5cb9 770 dma_chan_name(chan), op, i);
4a776f0a 771 if (IS_ERR(thread->task)) {
2d88ce76 772 pr_warn("Failed to create thread %s-%s%u\n",
0adff800 773 dma_chan_name(chan), op, i);
4a776f0a
HS
774 kfree(thread);
775 break;
776 }
777
778 /* srcbuf and dstbuf are allocated by the thread itself */
2d88ce76 779 get_task_struct(thread->task);
4a776f0a 780 list_add_tail(&thread->node, &dtc->threads);
2d88ce76 781 wake_up_process(thread->task);
4a776f0a
HS
782 }
783
b54d5cb9
DW
784 return i;
785}
786
e03e93a9
AS
787static int dmatest_add_channel(struct dmatest_info *info,
788 struct dma_chan *chan)
b54d5cb9
DW
789{
790 struct dmatest_chan *dtc;
791 struct dma_device *dma_dev = chan->device;
792 unsigned int thread_count = 0;
b9033e68 793 int cnt;
b54d5cb9
DW
794
795 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
796 if (!dtc) {
0adff800 797 pr_warn("No memory for %s\n", dma_chan_name(chan));
b54d5cb9
DW
798 return -ENOMEM;
799 }
800
801 dtc->chan = chan;
802 INIT_LIST_HEAD(&dtc->threads);
803
804 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
e03e93a9 805 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
f1aef8b6 806 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9
DW
807 }
808 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
e03e93a9 809 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
f1aef8b6 810 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9 811 }
58691d64 812 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
e03e93a9 813 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
d07a74a5 814 thread_count += cnt > 0 ? cnt : 0;
58691d64 815 }
b54d5cb9 816
0adff800 817 pr_info("Started %u threads using %s\n",
b54d5cb9 818 thread_count, dma_chan_name(chan));
4a776f0a 819
838cc704
AS
820 list_add_tail(&dtc->node, &info->channels);
821 info->nr_channels++;
4a776f0a 822
33df8ca0 823 return 0;
4a776f0a
HS
824}
825
7dd60251 826static bool filter(struct dma_chan *chan, void *param)
4a776f0a 827{
15b8a8ea 828 struct dmatest_params *params = param;
e03e93a9 829
15b8a8ea
AS
830 if (!dmatest_match_channel(params, chan) ||
831 !dmatest_match_device(params, chan->device))
7dd60251 832 return false;
33df8ca0 833 else
7dd60251 834 return true;
4a776f0a
HS
835}
836
a9e55495
DW
837static void request_channels(struct dmatest_info *info,
838 enum dma_transaction_type type)
4a776f0a 839{
33df8ca0 840 dma_cap_mask_t mask;
33df8ca0
DW
841
842 dma_cap_zero(mask);
a9e55495 843 dma_cap_set(type, mask);
33df8ca0 844 for (;;) {
a9e55495
DW
845 struct dmatest_params *params = &info->params;
846 struct dma_chan *chan;
847
15b8a8ea 848 chan = dma_request_channel(mask, filter, params);
33df8ca0 849 if (chan) {
a9e55495 850 if (dmatest_add_channel(info, chan)) {
33df8ca0
DW
851 dma_release_channel(chan);
852 break; /* add_channel failed, punt */
853 }
854 } else
855 break; /* no more channels available */
15b8a8ea
AS
856 if (params->max_channels &&
857 info->nr_channels >= params->max_channels)
33df8ca0
DW
858 break; /* we have all we need */
859 }
4a776f0a 860}
4a776f0a 861
a9e55495 862static void run_threaded_test(struct dmatest_info *info)
851b7e16 863{
a9e55495 864 struct dmatest_params *params = &info->params;
851b7e16 865
a9e55495
DW
866 /* Copy test parameters */
867 params->buf_size = test_buf_size;
868 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
869 strlcpy(params->device, strim(test_device), sizeof(params->device));
870 params->threads_per_chan = threads_per_chan;
871 params->max_channels = max_channels;
872 params->iterations = iterations;
873 params->xor_sources = xor_sources;
874 params->pq_sources = pq_sources;
875 params->timeout = timeout;
e3b9c347 876 params->noverify = noverify;
a9e55495
DW
877
878 request_channels(info, DMA_MEMCPY);
879 request_channels(info, DMA_XOR);
880 request_channels(info, DMA_PQ);
851b7e16 881}
851b7e16 882
a310d037 883static void stop_threaded_test(struct dmatest_info *info)
4a776f0a 884{
33df8ca0 885 struct dmatest_chan *dtc, *_dtc;
7cbd4877 886 struct dma_chan *chan;
33df8ca0 887
838cc704 888 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
33df8ca0 889 list_del(&dtc->node);
7cbd4877 890 chan = dtc->chan;
33df8ca0 891 dmatest_cleanup_channel(dtc);
0adff800 892 pr_debug("dropped channel %s\n", dma_chan_name(chan));
7cbd4877 893 dma_release_channel(chan);
33df8ca0 894 }
838cc704
AS
895
896 info->nr_channels = 0;
4a776f0a 897}
e03e93a9 898
a9e55495 899static void restart_threaded_test(struct dmatest_info *info, bool run)
851b7e16 900{
a310d037
DW
901 /* we might be called early to set run=, defer running until all
902 * parameters have been evaluated
903 */
904 if (!info->did_init)
a9e55495 905 return;
851b7e16
AS
906
907 /* Stop any running test first */
a310d037 908 stop_threaded_test(info);
851b7e16
AS
909
910 /* Run test with new parameters */
a9e55495 911 run_threaded_test(info);
851b7e16
AS
912}
913
a310d037 914static int dmatest_run_get(char *val, const struct kernel_param *kp)
851b7e16 915{
a310d037 916 struct dmatest_info *info = &test_info;
851b7e16
AS
917
918 mutex_lock(&info->lock);
a310d037
DW
919 if (is_threaded_test_run(info)) {
920 dmatest_run = true;
3e5ccd86 921 } else {
a310d037
DW
922 stop_threaded_test(info);
923 dmatest_run = false;
3e5ccd86 924 }
851b7e16 925 mutex_unlock(&info->lock);
851b7e16 926
a310d037 927 return param_get_bool(val, kp);
851b7e16
AS
928}
929
a310d037 930static int dmatest_run_set(const char *val, const struct kernel_param *kp)
95019c8c 931{
a310d037
DW
932 struct dmatest_info *info = &test_info;
933 int ret;
95019c8c 934
a310d037
DW
935 mutex_lock(&info->lock);
936 ret = param_set_bool(val, kp);
937 if (ret) {
851b7e16 938 mutex_unlock(&info->lock);
a310d037 939 return ret;
95019c8c
AS
940 }
941
a310d037
DW
942 if (is_threaded_test_run(info))
943 ret = -EBUSY;
944 else if (dmatest_run)
a9e55495 945 restart_threaded_test(info, dmatest_run);
851b7e16 946
a310d037 947 mutex_unlock(&info->lock);
851b7e16 948
a310d037 949 return ret;
851b7e16
AS
950}
951
e03e93a9
AS
952static int __init dmatest_init(void)
953{
954 struct dmatest_info *info = &test_info;
2d88ce76 955 struct dmatest_params *params = &info->params;
e03e93a9 956
a310d037
DW
957 if (dmatest_run) {
958 mutex_lock(&info->lock);
a9e55495 959 run_threaded_test(info);
a310d037
DW
960 mutex_unlock(&info->lock);
961 }
838cc704 962
2d88ce76
DW
963 if (params->iterations && wait)
964 wait_event(thread_wait, !is_threaded_test_run(info));
95019c8c 965
a310d037
DW
966 /* module parameters are stable, inittime tests are started,
967 * let userspace take over 'run' control
968 */
969 info->did_init = true;
851b7e16 970
851b7e16 971 return 0;
e03e93a9
AS
972}
973/* when compiled-in wait for drivers to load first */
974late_initcall(dmatest_init);
975
976static void __exit dmatest_exit(void)
977{
978 struct dmatest_info *info = &test_info;
979
a310d037 980 mutex_lock(&info->lock);
e03e93a9 981 stop_threaded_test(info);
a310d037 982 mutex_unlock(&info->lock);
e03e93a9 983}
4a776f0a
HS
984module_exit(dmatest_exit);
985
e05503ef 986MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4a776f0a 987MODULE_LICENSE("GPL v2");