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Commit | Line | Data |
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4a776f0a HS |
1 | /* |
2 | * DMA Engine test module | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
851b7e16 | 5 | * Copyright (C) 2013 Intel Corporation |
4a776f0a HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
872f05c6 DW |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
4a776f0a | 13 | #include <linux/delay.h> |
b7f080cf | 14 | #include <linux/dma-mapping.h> |
4a776f0a | 15 | #include <linux/dmaengine.h> |
981ed70d | 16 | #include <linux/freezer.h> |
4a776f0a HS |
17 | #include <linux/init.h> |
18 | #include <linux/kthread.h> | |
0881e7bd | 19 | #include <linux/sched/task.h> |
4a776f0a HS |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/random.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
4a776f0a HS |
24 | #include <linux/wait.h> |
25 | ||
26 | static unsigned int test_buf_size = 16384; | |
a6c268d0 | 27 | module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
28 | MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); |
29 | ||
06190d84 | 30 | static char test_channel[20]; |
a6c268d0 AS |
31 | module_param_string(channel, test_channel, sizeof(test_channel), |
32 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
33 | MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); |
34 | ||
a85159fe | 35 | static char test_device[32]; |
a6c268d0 AS |
36 | module_param_string(device, test_device, sizeof(test_device), |
37 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
38 | MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); |
39 | ||
40 | static unsigned int threads_per_chan = 1; | |
a6c268d0 | 41 | module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
42 | MODULE_PARM_DESC(threads_per_chan, |
43 | "Number of threads to start per channel (default: 1)"); | |
44 | ||
45 | static unsigned int max_channels; | |
a6c268d0 | 46 | module_param(max_channels, uint, S_IRUGO | S_IWUSR); |
33df8ca0 | 47 | MODULE_PARM_DESC(max_channels, |
4a776f0a HS |
48 | "Maximum number of channels to use (default: all)"); |
49 | ||
0a2ff57d | 50 | static unsigned int iterations; |
a6c268d0 | 51 | module_param(iterations, uint, S_IRUGO | S_IWUSR); |
0a2ff57d NF |
52 | MODULE_PARM_DESC(iterations, |
53 | "Iterations before stopping test (default: infinite)"); | |
54 | ||
d8646724 | 55 | static unsigned int dmatest; |
a0d4cb44 KA |
56 | module_param(dmatest, uint, S_IRUGO | S_IWUSR); |
57 | MODULE_PARM_DESC(dmatest, | |
c678fa66 | 58 | "dmatest 0-memcpy 1-memset (default: 0)"); |
a0d4cb44 | 59 | |
b54d5cb9 | 60 | static unsigned int xor_sources = 3; |
a6c268d0 | 61 | module_param(xor_sources, uint, S_IRUGO | S_IWUSR); |
b54d5cb9 DW |
62 | MODULE_PARM_DESC(xor_sources, |
63 | "Number of xor source buffers (default: 3)"); | |
64 | ||
58691d64 | 65 | static unsigned int pq_sources = 3; |
a6c268d0 | 66 | module_param(pq_sources, uint, S_IRUGO | S_IWUSR); |
58691d64 DW |
67 | MODULE_PARM_DESC(pq_sources, |
68 | "Number of p+q source buffers (default: 3)"); | |
69 | ||
d42efe6b | 70 | static int timeout = 3000; |
a6c268d0 | 71 | module_param(timeout, uint, S_IRUGO | S_IWUSR); |
85ee7a1d JP |
72 | MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " |
73 | "Pass -1 for infinite timeout"); | |
d42efe6b | 74 | |
e3b9c347 DW |
75 | static bool noverify; |
76 | module_param(noverify, bool, S_IRUGO | S_IWUSR); | |
77 | MODULE_PARM_DESC(noverify, "Disable random data setup and verification"); | |
4a776f0a | 78 | |
50137a7d DW |
79 | static bool verbose; |
80 | module_param(verbose, bool, S_IRUGO | S_IWUSR); | |
81 | MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); | |
4a776f0a | 82 | |
e03e93a9 | 83 | /** |
15b8a8ea | 84 | * struct dmatest_params - test parameters. |
e03e93a9 AS |
85 | * @buf_size: size of the memcpy test buffer |
86 | * @channel: bus ID of the channel to test | |
87 | * @device: bus ID of the DMA Engine to test | |
88 | * @threads_per_chan: number of threads to start per channel | |
89 | * @max_channels: maximum number of channels to use | |
90 | * @iterations: iterations before stopping test | |
91 | * @xor_sources: number of xor source buffers | |
92 | * @pq_sources: number of p+q source buffers | |
93 | * @timeout: transfer timeout in msec, -1 for infinite timeout | |
94 | */ | |
15b8a8ea | 95 | struct dmatest_params { |
e03e93a9 AS |
96 | unsigned int buf_size; |
97 | char channel[20]; | |
a85159fe | 98 | char device[32]; |
e03e93a9 AS |
99 | unsigned int threads_per_chan; |
100 | unsigned int max_channels; | |
101 | unsigned int iterations; | |
102 | unsigned int xor_sources; | |
103 | unsigned int pq_sources; | |
104 | int timeout; | |
e3b9c347 | 105 | bool noverify; |
15b8a8ea AS |
106 | }; |
107 | ||
108 | /** | |
109 | * struct dmatest_info - test information. | |
110 | * @params: test parameters | |
851b7e16 | 111 | * @lock: access protection to the fields of this structure |
15b8a8ea | 112 | */ |
a310d037 | 113 | static struct dmatest_info { |
15b8a8ea AS |
114 | /* Test parameters */ |
115 | struct dmatest_params params; | |
838cc704 AS |
116 | |
117 | /* Internal state */ | |
118 | struct list_head channels; | |
119 | unsigned int nr_channels; | |
851b7e16 | 120 | struct mutex lock; |
a310d037 DW |
121 | bool did_init; |
122 | } test_info = { | |
123 | .channels = LIST_HEAD_INIT(test_info.channels), | |
124 | .lock = __MUTEX_INITIALIZER(test_info.lock), | |
125 | }; | |
851b7e16 | 126 | |
a310d037 DW |
127 | static int dmatest_run_set(const char *val, const struct kernel_param *kp); |
128 | static int dmatest_run_get(char *val, const struct kernel_param *kp); | |
9c27847d | 129 | static const struct kernel_param_ops run_ops = { |
a310d037 DW |
130 | .set = dmatest_run_set, |
131 | .get = dmatest_run_get, | |
e03e93a9 | 132 | }; |
a310d037 DW |
133 | static bool dmatest_run; |
134 | module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); | |
135 | MODULE_PARM_DESC(run, "Run the test (default: false)"); | |
e03e93a9 | 136 | |
a310d037 DW |
137 | /* Maximum amount of mismatched bytes in buffer to print */ |
138 | #define MAX_ERROR_COUNT 32 | |
139 | ||
140 | /* | |
141 | * Initialization patterns. All bytes in the source buffer has bit 7 | |
142 | * set, all bytes in the destination buffer has bit 7 cleared. | |
143 | * | |
144 | * Bit 6 is set for all bytes which are to be copied by the DMA | |
145 | * engine. Bit 5 is set for all bytes which are to be overwritten by | |
146 | * the DMA engine. | |
147 | * | |
148 | * The remaining bits are the inverse of a counter which increments by | |
149 | * one for each byte address. | |
150 | */ | |
151 | #define PATTERN_SRC 0x80 | |
152 | #define PATTERN_DST 0x00 | |
153 | #define PATTERN_COPY 0x40 | |
154 | #define PATTERN_OVERWRITE 0x20 | |
155 | #define PATTERN_COUNT_MASK 0x1f | |
61b5f54d | 156 | #define PATTERN_MEMSET_IDX 0x01 |
851b7e16 | 157 | |
6f6a23a2 AW |
158 | /* poor man's completion - we want to use wait_event_freezable() on it */ |
159 | struct dmatest_done { | |
160 | bool done; | |
161 | wait_queue_head_t *wait; | |
162 | }; | |
163 | ||
a310d037 DW |
164 | struct dmatest_thread { |
165 | struct list_head node; | |
166 | struct dmatest_info *info; | |
167 | struct task_struct *task; | |
168 | struct dma_chan *chan; | |
169 | u8 **srcs; | |
d6481608 | 170 | u8 **usrcs; |
a310d037 | 171 | u8 **dsts; |
d6481608 | 172 | u8 **udsts; |
a310d037 | 173 | enum dma_transaction_type type; |
6f6a23a2 AW |
174 | wait_queue_head_t done_wait; |
175 | struct dmatest_done test_done; | |
a310d037 DW |
176 | bool done; |
177 | }; | |
95019c8c | 178 | |
a310d037 DW |
179 | struct dmatest_chan { |
180 | struct list_head node; | |
181 | struct dma_chan *chan; | |
182 | struct list_head threads; | |
e03e93a9 AS |
183 | }; |
184 | ||
2d88ce76 DW |
185 | static DECLARE_WAIT_QUEUE_HEAD(thread_wait); |
186 | static bool wait; | |
187 | ||
188 | static bool is_threaded_test_run(struct dmatest_info *info) | |
189 | { | |
190 | struct dmatest_chan *dtc; | |
191 | ||
192 | list_for_each_entry(dtc, &info->channels, node) { | |
193 | struct dmatest_thread *thread; | |
194 | ||
195 | list_for_each_entry(thread, &dtc->threads, node) { | |
196 | if (!thread->done) | |
197 | return true; | |
198 | } | |
199 | } | |
200 | ||
201 | return false; | |
202 | } | |
203 | ||
204 | static int dmatest_wait_get(char *val, const struct kernel_param *kp) | |
205 | { | |
206 | struct dmatest_info *info = &test_info; | |
207 | struct dmatest_params *params = &info->params; | |
208 | ||
209 | if (params->iterations) | |
210 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
211 | wait = true; | |
212 | return param_get_bool(val, kp); | |
213 | } | |
214 | ||
9c27847d | 215 | static const struct kernel_param_ops wait_ops = { |
2d88ce76 DW |
216 | .get = dmatest_wait_get, |
217 | .set = param_set_bool, | |
218 | }; | |
219 | module_param_cb(wait, &wait_ops, &wait, S_IRUGO); | |
220 | MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); | |
e03e93a9 | 221 | |
15b8a8ea | 222 | static bool dmatest_match_channel(struct dmatest_params *params, |
e03e93a9 | 223 | struct dma_chan *chan) |
4a776f0a | 224 | { |
15b8a8ea | 225 | if (params->channel[0] == '\0') |
4a776f0a | 226 | return true; |
15b8a8ea | 227 | return strcmp(dma_chan_name(chan), params->channel) == 0; |
4a776f0a HS |
228 | } |
229 | ||
15b8a8ea | 230 | static bool dmatest_match_device(struct dmatest_params *params, |
e03e93a9 | 231 | struct dma_device *device) |
4a776f0a | 232 | { |
15b8a8ea | 233 | if (params->device[0] == '\0') |
4a776f0a | 234 | return true; |
15b8a8ea | 235 | return strcmp(dev_name(device->dev), params->device) == 0; |
4a776f0a HS |
236 | } |
237 | ||
238 | static unsigned long dmatest_random(void) | |
239 | { | |
240 | unsigned long buf; | |
241 | ||
be9fa5a4 | 242 | prandom_bytes(&buf, sizeof(buf)); |
4a776f0a HS |
243 | return buf; |
244 | } | |
245 | ||
61b5f54d SK |
246 | static inline u8 gen_inv_idx(u8 index, bool is_memset) |
247 | { | |
248 | u8 val = is_memset ? PATTERN_MEMSET_IDX : index; | |
249 | ||
250 | return ~val & PATTERN_COUNT_MASK; | |
251 | } | |
252 | ||
253 | static inline u8 gen_src_value(u8 index, bool is_memset) | |
254 | { | |
255 | return PATTERN_SRC | gen_inv_idx(index, is_memset); | |
256 | } | |
257 | ||
258 | static inline u8 gen_dst_value(u8 index, bool is_memset) | |
259 | { | |
260 | return PATTERN_DST | gen_inv_idx(index, is_memset); | |
261 | } | |
262 | ||
e03e93a9 | 263 | static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 264 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
265 | { |
266 | unsigned int i; | |
b54d5cb9 DW |
267 | u8 *buf; |
268 | ||
269 | for (; (buf = *bufs); bufs++) { | |
270 | for (i = 0; i < start; i++) | |
61b5f54d | 271 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 | 272 | for ( ; i < start + len; i++) |
61b5f54d | 273 | buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY; |
e03e93a9 | 274 | for ( ; i < buf_size; i++) |
61b5f54d | 275 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 DW |
276 | buf++; |
277 | } | |
4a776f0a HS |
278 | } |
279 | ||
e03e93a9 | 280 | static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 281 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
282 | { |
283 | unsigned int i; | |
b54d5cb9 DW |
284 | u8 *buf; |
285 | ||
286 | for (; (buf = *bufs); bufs++) { | |
287 | for (i = 0; i < start; i++) | |
61b5f54d | 288 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 289 | for ( ; i < start + len; i++) |
61b5f54d SK |
290 | buf[i] = gen_dst_value(i, is_memset) | |
291 | PATTERN_OVERWRITE; | |
e03e93a9 | 292 | for ( ; i < buf_size; i++) |
61b5f54d | 293 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 294 | } |
4a776f0a HS |
295 | } |
296 | ||
7b610178 | 297 | static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, |
61b5f54d | 298 | unsigned int counter, bool is_srcbuf, bool is_memset) |
7b610178 DW |
299 | { |
300 | u8 diff = actual ^ pattern; | |
61b5f54d | 301 | u8 expected = pattern | gen_inv_idx(counter, is_memset); |
7b610178 DW |
302 | const char *thread_name = current->comm; |
303 | ||
304 | if (is_srcbuf) | |
305 | pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", | |
306 | thread_name, index, expected, actual); | |
307 | else if ((pattern & PATTERN_COPY) | |
308 | && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) | |
309 | pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", | |
310 | thread_name, index, expected, actual); | |
311 | else if (diff & PATTERN_SRC) | |
312 | pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", | |
313 | thread_name, index, expected, actual); | |
314 | else | |
315 | pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", | |
316 | thread_name, index, expected, actual); | |
317 | } | |
318 | ||
319 | static unsigned int dmatest_verify(u8 **bufs, unsigned int start, | |
320 | unsigned int end, unsigned int counter, u8 pattern, | |
61b5f54d | 321 | bool is_srcbuf, bool is_memset) |
4a776f0a HS |
322 | { |
323 | unsigned int i; | |
324 | unsigned int error_count = 0; | |
325 | u8 actual; | |
b54d5cb9 DW |
326 | u8 expected; |
327 | u8 *buf; | |
328 | unsigned int counter_orig = counter; | |
329 | ||
330 | for (; (buf = *bufs); bufs++) { | |
331 | counter = counter_orig; | |
332 | for (i = start; i < end; i++) { | |
333 | actual = buf[i]; | |
61b5f54d | 334 | expected = pattern | gen_inv_idx(counter, is_memset); |
b54d5cb9 | 335 | if (actual != expected) { |
7b610178 DW |
336 | if (error_count < MAX_ERROR_COUNT) |
337 | dmatest_mismatch(actual, pattern, i, | |
61b5f54d SK |
338 | counter, is_srcbuf, |
339 | is_memset); | |
b54d5cb9 DW |
340 | error_count++; |
341 | } | |
342 | counter++; | |
4a776f0a | 343 | } |
4a776f0a HS |
344 | } |
345 | ||
74b5c07a | 346 | if (error_count > MAX_ERROR_COUNT) |
7b610178 | 347 | pr_warn("%s: %u errors suppressed\n", |
74b5c07a | 348 | current->comm, error_count - MAX_ERROR_COUNT); |
4a776f0a HS |
349 | |
350 | return error_count; | |
351 | } | |
352 | ||
adfa543e TH |
353 | |
354 | static void dmatest_callback(void *arg) | |
e44e0aa3 | 355 | { |
adfa543e | 356 | struct dmatest_done *done = arg; |
6f6a23a2 | 357 | struct dmatest_thread *thread = |
240efe4a | 358 | container_of(done, struct dmatest_thread, test_done); |
6f6a23a2 AW |
359 | if (!thread->done) { |
360 | done->done = true; | |
361 | wake_up_all(done->wait); | |
362 | } else { | |
363 | /* | |
364 | * If thread->done, it means that this callback occurred | |
365 | * after the parent thread has cleaned up. This can | |
366 | * happen in the case that driver doesn't implement | |
367 | * the terminate_all() functionality and a dma operation | |
368 | * did not occur within the timeout period | |
369 | */ | |
370 | WARN(1, "dmatest: Kernel memory may be corrupted!!\n"); | |
371 | } | |
e44e0aa3 DW |
372 | } |
373 | ||
8be9e32b AM |
374 | static unsigned int min_odd(unsigned int x, unsigned int y) |
375 | { | |
376 | unsigned int val = min(x, y); | |
377 | ||
378 | return val % 2 ? val : val - 1; | |
379 | } | |
380 | ||
872f05c6 DW |
381 | static void result(const char *err, unsigned int n, unsigned int src_off, |
382 | unsigned int dst_off, unsigned int len, unsigned long data) | |
d86b2f29 | 383 | { |
2acec150 | 384 | pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
872f05c6 | 385 | current->comm, n, err, src_off, dst_off, len, data); |
d86b2f29 AS |
386 | } |
387 | ||
872f05c6 DW |
388 | static void dbg_result(const char *err, unsigned int n, unsigned int src_off, |
389 | unsigned int dst_off, unsigned int len, | |
390 | unsigned long data) | |
95019c8c | 391 | { |
2acec150 | 392 | pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
a835bb85 | 393 | current->comm, n, err, src_off, dst_off, len, data); |
95019c8c AS |
394 | } |
395 | ||
a835bb85 AS |
396 | #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ |
397 | if (verbose) \ | |
398 | result(err, n, src_off, dst_off, len, data); \ | |
399 | else \ | |
400 | dbg_result(err, n, src_off, dst_off, len, data);\ | |
50137a7d | 401 | }) |
95019c8c | 402 | |
86727443 | 403 | static unsigned long long dmatest_persec(s64 runtime, unsigned int val) |
d86b2f29 | 404 | { |
86727443 | 405 | unsigned long long per_sec = 1000000; |
d86b2f29 | 406 | |
86727443 DW |
407 | if (runtime <= 0) |
408 | return 0; | |
95019c8c | 409 | |
86727443 DW |
410 | /* drop precision until runtime is 32-bits */ |
411 | while (runtime > UINT_MAX) { | |
412 | runtime >>= 1; | |
413 | per_sec <<= 1; | |
95019c8c AS |
414 | } |
415 | ||
86727443 DW |
416 | per_sec *= val; |
417 | do_div(per_sec, runtime); | |
418 | return per_sec; | |
95019c8c AS |
419 | } |
420 | ||
86727443 | 421 | static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) |
95019c8c | 422 | { |
86727443 | 423 | return dmatest_persec(runtime, len >> 10); |
95019c8c AS |
424 | } |
425 | ||
4a776f0a HS |
426 | /* |
427 | * This function repeatedly tests DMA transfers of various lengths and | |
b54d5cb9 DW |
428 | * offsets for a given operation type until it is told to exit by |
429 | * kthread_stop(). There may be multiple threads running this function | |
430 | * in parallel for a single channel, and there may be multiple channels | |
431 | * being tested in parallel. | |
4a776f0a HS |
432 | * |
433 | * Before each test, the source and destination buffer is initialized | |
434 | * with a known pattern. This pattern is different depending on | |
435 | * whether it's in an area which is supposed to be copied or | |
436 | * overwritten, and different in the source and destination buffers. | |
437 | * So if the DMA engine doesn't copy exactly what we tell it to copy, | |
438 | * we'll notice. | |
439 | */ | |
440 | static int dmatest_func(void *data) | |
441 | { | |
442 | struct dmatest_thread *thread = data; | |
6f6a23a2 | 443 | struct dmatest_done *done = &thread->test_done; |
e03e93a9 | 444 | struct dmatest_info *info; |
15b8a8ea | 445 | struct dmatest_params *params; |
4a776f0a | 446 | struct dma_chan *chan; |
8be9e32b | 447 | struct dma_device *dev; |
4a776f0a HS |
448 | unsigned int error_count; |
449 | unsigned int failed_tests = 0; | |
450 | unsigned int total_tests = 0; | |
451 | dma_cookie_t cookie; | |
452 | enum dma_status status; | |
b54d5cb9 | 453 | enum dma_ctrl_flags flags; |
945b5af3 | 454 | u8 *pq_coefs = NULL; |
4a776f0a | 455 | int ret; |
b54d5cb9 DW |
456 | int src_cnt; |
457 | int dst_cnt; | |
458 | int i; | |
e9405ef0 | 459 | ktime_t ktime, start, diff; |
8b0e1953 TG |
460 | ktime_t filltime = 0; |
461 | ktime_t comparetime = 0; | |
86727443 DW |
462 | s64 runtime = 0; |
463 | unsigned long long total_len = 0; | |
d6481608 | 464 | u8 align = 0; |
61b5f54d | 465 | bool is_memset = false; |
4a776f0a | 466 | |
adfa543e | 467 | set_freezable(); |
4a776f0a HS |
468 | |
469 | ret = -ENOMEM; | |
4a776f0a HS |
470 | |
471 | smp_rmb(); | |
e03e93a9 | 472 | info = thread->info; |
15b8a8ea | 473 | params = &info->params; |
4a776f0a | 474 | chan = thread->chan; |
8be9e32b | 475 | dev = chan->device; |
d6481608 DJ |
476 | if (thread->type == DMA_MEMCPY) { |
477 | align = dev->copy_align; | |
b54d5cb9 | 478 | src_cnt = dst_cnt = 1; |
61b5f54d SK |
479 | } else if (thread->type == DMA_MEMSET) { |
480 | align = dev->fill_align; | |
481 | src_cnt = dst_cnt = 1; | |
482 | is_memset = true; | |
d6481608 | 483 | } else if (thread->type == DMA_XOR) { |
8be9e32b | 484 | /* force odd to ensure dst = src */ |
15b8a8ea | 485 | src_cnt = min_odd(params->xor_sources | 1, dev->max_xor); |
b54d5cb9 | 486 | dst_cnt = 1; |
d6481608 | 487 | align = dev->xor_align; |
58691d64 | 488 | } else if (thread->type == DMA_PQ) { |
8be9e32b | 489 | /* force odd to ensure dst = src */ |
15b8a8ea | 490 | src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); |
58691d64 | 491 | dst_cnt = 2; |
d6481608 | 492 | align = dev->pq_align; |
945b5af3 | 493 | |
31d18257 | 494 | pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL); |
945b5af3 AS |
495 | if (!pq_coefs) |
496 | goto err_thread_type; | |
497 | ||
94de648d | 498 | for (i = 0; i < src_cnt; i++) |
58691d64 | 499 | pq_coefs[i] = 1; |
b54d5cb9 | 500 | } else |
945b5af3 | 501 | goto err_thread_type; |
b54d5cb9 | 502 | |
31d18257 | 503 | thread->srcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL); |
b54d5cb9 DW |
504 | if (!thread->srcs) |
505 | goto err_srcs; | |
d6481608 DJ |
506 | |
507 | thread->usrcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
508 | if (!thread->usrcs) | |
509 | goto err_usrcs; | |
510 | ||
b54d5cb9 | 511 | for (i = 0; i < src_cnt; i++) { |
d6481608 DJ |
512 | thread->usrcs[i] = kmalloc(params->buf_size + align, |
513 | GFP_KERNEL); | |
514 | if (!thread->usrcs[i]) | |
b54d5cb9 | 515 | goto err_srcbuf; |
d6481608 DJ |
516 | |
517 | /* align srcs to alignment restriction */ | |
518 | if (align) | |
519 | thread->srcs[i] = PTR_ALIGN(thread->usrcs[i], align); | |
520 | else | |
521 | thread->srcs[i] = thread->usrcs[i]; | |
b54d5cb9 DW |
522 | } |
523 | thread->srcs[i] = NULL; | |
524 | ||
31d18257 | 525 | thread->dsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL); |
b54d5cb9 DW |
526 | if (!thread->dsts) |
527 | goto err_dsts; | |
d6481608 DJ |
528 | |
529 | thread->udsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
530 | if (!thread->udsts) | |
531 | goto err_udsts; | |
532 | ||
b54d5cb9 | 533 | for (i = 0; i < dst_cnt; i++) { |
d6481608 DJ |
534 | thread->udsts[i] = kmalloc(params->buf_size + align, |
535 | GFP_KERNEL); | |
536 | if (!thread->udsts[i]) | |
b54d5cb9 | 537 | goto err_dstbuf; |
d6481608 DJ |
538 | |
539 | /* align dsts to alignment restriction */ | |
540 | if (align) | |
541 | thread->dsts[i] = PTR_ALIGN(thread->udsts[i], align); | |
542 | else | |
543 | thread->dsts[i] = thread->udsts[i]; | |
b54d5cb9 DW |
544 | } |
545 | thread->dsts[i] = NULL; | |
546 | ||
e44e0aa3 DW |
547 | set_user_nice(current, 10); |
548 | ||
b203bd3f | 549 | /* |
d1cab34c | 550 | * src and dst buffers are freed by ourselves below |
b203bd3f | 551 | */ |
0776ae7b | 552 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
4a776f0a | 553 | |
86727443 | 554 | ktime = ktime_get(); |
0a2ff57d | 555 | while (!kthread_should_stop() |
15b8a8ea | 556 | && !(params->iterations && total_tests >= params->iterations)) { |
b54d5cb9 | 557 | struct dma_async_tx_descriptor *tx = NULL; |
4076e755 DW |
558 | struct dmaengine_unmap_data *um; |
559 | dma_addr_t srcs[src_cnt]; | |
560 | dma_addr_t *dsts; | |
ede23a58 | 561 | unsigned int src_off, dst_off, len; |
d86be86e | 562 | |
4a776f0a HS |
563 | total_tests++; |
564 | ||
fbfb8e1d SR |
565 | /* Check if buffer count fits into map count variable (u8) */ |
566 | if ((src_cnt + dst_cnt) >= 255) { | |
567 | pr_err("too many buffers (%d of 255 supported)\n", | |
568 | src_cnt + dst_cnt); | |
569 | break; | |
570 | } | |
571 | ||
15b8a8ea | 572 | if (1 << align > params->buf_size) { |
cfe4f275 | 573 | pr_err("%u-byte buffer too small for %d-byte alignment\n", |
15b8a8ea | 574 | params->buf_size, 1 << align); |
cfe4f275 GL |
575 | break; |
576 | } | |
577 | ||
ede23a58 | 578 | if (params->noverify) |
e3b9c347 | 579 | len = params->buf_size; |
ede23a58 AS |
580 | else |
581 | len = dmatest_random() % params->buf_size + 1; | |
582 | ||
583 | len = (len >> align) << align; | |
584 | if (!len) | |
585 | len = 1 << align; | |
586 | ||
587 | total_len += len; | |
588 | ||
589 | if (params->noverify) { | |
e3b9c347 DW |
590 | src_off = 0; |
591 | dst_off = 0; | |
592 | } else { | |
e9405ef0 | 593 | start = ktime_get(); |
e3b9c347 DW |
594 | src_off = dmatest_random() % (params->buf_size - len + 1); |
595 | dst_off = dmatest_random() % (params->buf_size - len + 1); | |
596 | ||
597 | src_off = (src_off >> align) << align; | |
598 | dst_off = (dst_off >> align) << align; | |
599 | ||
600 | dmatest_init_srcs(thread->srcs, src_off, len, | |
61b5f54d | 601 | params->buf_size, is_memset); |
e3b9c347 | 602 | dmatest_init_dsts(thread->dsts, dst_off, len, |
61b5f54d | 603 | params->buf_size, is_memset); |
e9405ef0 SK |
604 | |
605 | diff = ktime_sub(ktime_get(), start); | |
606 | filltime = ktime_add(filltime, diff); | |
e3b9c347 DW |
607 | } |
608 | ||
31d18257 | 609 | um = dmaengine_get_unmap_data(dev->dev, src_cnt + dst_cnt, |
4076e755 DW |
610 | GFP_KERNEL); |
611 | if (!um) { | |
612 | failed_tests++; | |
613 | result("unmap data NULL", total_tests, | |
614 | src_off, dst_off, len, ret); | |
615 | continue; | |
616 | } | |
4a776f0a | 617 | |
4076e755 | 618 | um->len = params->buf_size; |
b54d5cb9 | 619 | for (i = 0; i < src_cnt; i++) { |
745c00da | 620 | void *buf = thread->srcs[i]; |
4076e755 | 621 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 622 | unsigned long pg_off = offset_in_page(buf); |
4076e755 DW |
623 | |
624 | um->addr[i] = dma_map_page(dev->dev, pg, pg_off, | |
625 | um->len, DMA_TO_DEVICE); | |
626 | srcs[i] = um->addr[i] + src_off; | |
627 | ret = dma_mapping_error(dev->dev, um->addr[i]); | |
afde3be1 | 628 | if (ret) { |
872f05c6 DW |
629 | result("src mapping error", total_tests, |
630 | src_off, dst_off, len, ret); | |
633b7552 | 631 | goto error_unmap_continue; |
afde3be1 | 632 | } |
4076e755 | 633 | um->to_cnt++; |
b54d5cb9 | 634 | } |
d86be86e | 635 | /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ |
4076e755 | 636 | dsts = &um->addr[src_cnt]; |
b54d5cb9 | 637 | for (i = 0; i < dst_cnt; i++) { |
745c00da | 638 | void *buf = thread->dsts[i]; |
4076e755 | 639 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 640 | unsigned long pg_off = offset_in_page(buf); |
4076e755 DW |
641 | |
642 | dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, | |
643 | DMA_BIDIRECTIONAL); | |
644 | ret = dma_mapping_error(dev->dev, dsts[i]); | |
afde3be1 | 645 | if (ret) { |
872f05c6 DW |
646 | result("dst mapping error", total_tests, |
647 | src_off, dst_off, len, ret); | |
633b7552 | 648 | goto error_unmap_continue; |
afde3be1 | 649 | } |
4076e755 | 650 | um->bidi_cnt++; |
b54d5cb9 DW |
651 | } |
652 | ||
653 | if (thread->type == DMA_MEMCPY) | |
654 | tx = dev->device_prep_dma_memcpy(chan, | |
4076e755 DW |
655 | dsts[0] + dst_off, |
656 | srcs[0], len, flags); | |
61b5f54d SK |
657 | else if (thread->type == DMA_MEMSET) |
658 | tx = dev->device_prep_dma_memset(chan, | |
659 | dsts[0] + dst_off, | |
660 | *(thread->srcs[0] + src_off), | |
661 | len, flags); | |
b54d5cb9 DW |
662 | else if (thread->type == DMA_XOR) |
663 | tx = dev->device_prep_dma_xor(chan, | |
4076e755 DW |
664 | dsts[0] + dst_off, |
665 | srcs, src_cnt, | |
b54d5cb9 | 666 | len, flags); |
58691d64 DW |
667 | else if (thread->type == DMA_PQ) { |
668 | dma_addr_t dma_pq[dst_cnt]; | |
669 | ||
670 | for (i = 0; i < dst_cnt; i++) | |
4076e755 DW |
671 | dma_pq[i] = dsts[i] + dst_off; |
672 | tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, | |
94de648d | 673 | src_cnt, pq_coefs, |
58691d64 DW |
674 | len, flags); |
675 | } | |
d86be86e | 676 | |
d86be86e | 677 | if (!tx) { |
872f05c6 DW |
678 | result("prep error", total_tests, src_off, |
679 | dst_off, len, ret); | |
d86be86e | 680 | msleep(100); |
633b7552 | 681 | goto error_unmap_continue; |
d86be86e | 682 | } |
e44e0aa3 | 683 | |
6f6a23a2 | 684 | done->done = false; |
e44e0aa3 | 685 | tx->callback = dmatest_callback; |
6f6a23a2 | 686 | tx->callback_param = done; |
d86be86e AN |
687 | cookie = tx->tx_submit(tx); |
688 | ||
4a776f0a | 689 | if (dma_submit_error(cookie)) { |
872f05c6 DW |
690 | result("submit error", total_tests, src_off, |
691 | dst_off, len, ret); | |
4a776f0a | 692 | msleep(100); |
633b7552 | 693 | goto error_unmap_continue; |
4a776f0a | 694 | } |
b54d5cb9 | 695 | dma_async_issue_pending(chan); |
4a776f0a | 696 | |
6f6a23a2 | 697 | wait_event_freezable_timeout(thread->done_wait, done->done, |
15b8a8ea | 698 | msecs_to_jiffies(params->timeout)); |
981ed70d | 699 | |
e44e0aa3 | 700 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); |
4a776f0a | 701 | |
6f6a23a2 | 702 | if (!done->done) { |
4076e755 | 703 | dmaengine_unmap_put(um); |
872f05c6 DW |
704 | result("test timed out", total_tests, src_off, dst_off, |
705 | len, 0); | |
633b7552 | 706 | goto error_unmap_continue; |
19e9f99f | 707 | } else if (status != DMA_COMPLETE) { |
4076e755 | 708 | dmaengine_unmap_put(um); |
872f05c6 DW |
709 | result(status == DMA_ERROR ? |
710 | "completion error status" : | |
711 | "completion busy status", total_tests, src_off, | |
712 | dst_off, len, ret); | |
633b7552 | 713 | goto error_unmap_continue; |
4a776f0a | 714 | } |
e44e0aa3 | 715 | |
4076e755 | 716 | dmaengine_unmap_put(um); |
4a776f0a | 717 | |
e3b9c347 | 718 | if (params->noverify) { |
50137a7d DW |
719 | verbose_result("test passed", total_tests, src_off, |
720 | dst_off, len, 0); | |
e3b9c347 DW |
721 | continue; |
722 | } | |
4a776f0a | 723 | |
e9405ef0 | 724 | start = ktime_get(); |
872f05c6 | 725 | pr_debug("%s: verifying source buffer...\n", current->comm); |
e3b9c347 | 726 | error_count = dmatest_verify(thread->srcs, 0, src_off, |
61b5f54d | 727 | 0, PATTERN_SRC, true, is_memset); |
7b610178 DW |
728 | error_count += dmatest_verify(thread->srcs, src_off, |
729 | src_off + len, src_off, | |
61b5f54d | 730 | PATTERN_SRC | PATTERN_COPY, true, is_memset); |
7b610178 DW |
731 | error_count += dmatest_verify(thread->srcs, src_off + len, |
732 | params->buf_size, src_off + len, | |
61b5f54d | 733 | PATTERN_SRC, true, is_memset); |
7b610178 | 734 | |
872f05c6 | 735 | pr_debug("%s: verifying dest buffer...\n", current->comm); |
7b610178 | 736 | error_count += dmatest_verify(thread->dsts, 0, dst_off, |
61b5f54d SK |
737 | 0, PATTERN_DST, false, is_memset); |
738 | ||
7b610178 DW |
739 | error_count += dmatest_verify(thread->dsts, dst_off, |
740 | dst_off + len, src_off, | |
61b5f54d SK |
741 | PATTERN_SRC | PATTERN_COPY, false, is_memset); |
742 | ||
7b610178 DW |
743 | error_count += dmatest_verify(thread->dsts, dst_off + len, |
744 | params->buf_size, dst_off + len, | |
61b5f54d | 745 | PATTERN_DST, false, is_memset); |
4a776f0a | 746 | |
e9405ef0 SK |
747 | diff = ktime_sub(ktime_get(), start); |
748 | comparetime = ktime_add(comparetime, diff); | |
749 | ||
4a776f0a | 750 | if (error_count) { |
872f05c6 DW |
751 | result("data error", total_tests, src_off, dst_off, |
752 | len, error_count); | |
4a776f0a HS |
753 | failed_tests++; |
754 | } else { | |
50137a7d DW |
755 | verbose_result("test passed", total_tests, src_off, |
756 | dst_off, len, 0); | |
4a776f0a | 757 | } |
633b7552 AS |
758 | |
759 | continue; | |
760 | ||
761 | error_unmap_continue: | |
762 | dmaengine_unmap_put(um); | |
763 | failed_tests++; | |
4a776f0a | 764 | } |
e9405ef0 SK |
765 | ktime = ktime_sub(ktime_get(), ktime); |
766 | ktime = ktime_sub(ktime, comparetime); | |
767 | ktime = ktime_sub(ktime, filltime); | |
768 | runtime = ktime_to_us(ktime); | |
4a776f0a HS |
769 | |
770 | ret = 0; | |
8e1f50d7 | 771 | err_dstbuf: |
d6481608 DJ |
772 | for (i = 0; thread->udsts[i]; i++) |
773 | kfree(thread->udsts[i]); | |
774 | kfree(thread->udsts); | |
775 | err_udsts: | |
b54d5cb9 DW |
776 | kfree(thread->dsts); |
777 | err_dsts: | |
8e1f50d7 | 778 | err_srcbuf: |
d6481608 DJ |
779 | for (i = 0; thread->usrcs[i]; i++) |
780 | kfree(thread->usrcs[i]); | |
781 | kfree(thread->usrcs); | |
782 | err_usrcs: | |
b54d5cb9 DW |
783 | kfree(thread->srcs); |
784 | err_srcs: | |
945b5af3 AS |
785 | kfree(pq_coefs); |
786 | err_thread_type: | |
86727443 DW |
787 | pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n", |
788 | current->comm, total_tests, failed_tests, | |
789 | dmatest_persec(runtime, total_tests), | |
790 | dmatest_KBs(runtime, total_len), ret); | |
0a2ff57d | 791 | |
9704efaa | 792 | /* terminate all transfers on specified channels */ |
6f6a23a2 | 793 | if (ret || failed_tests) |
5e034f7b SH |
794 | dmaengine_terminate_all(chan); |
795 | ||
3e5ccd86 | 796 | thread->done = true; |
2d88ce76 | 797 | wake_up(&thread_wait); |
0a2ff57d | 798 | |
4a776f0a HS |
799 | return ret; |
800 | } | |
801 | ||
802 | static void dmatest_cleanup_channel(struct dmatest_chan *dtc) | |
803 | { | |
804 | struct dmatest_thread *thread; | |
805 | struct dmatest_thread *_thread; | |
806 | int ret; | |
807 | ||
808 | list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { | |
809 | ret = kthread_stop(thread->task); | |
0adff800 DW |
810 | pr_debug("thread %s exited with status %d\n", |
811 | thread->task->comm, ret); | |
4a776f0a | 812 | list_del(&thread->node); |
2d88ce76 | 813 | put_task_struct(thread->task); |
4a776f0a HS |
814 | kfree(thread); |
815 | } | |
9704efaa VK |
816 | |
817 | /* terminate all transfers on specified channels */ | |
944ea4dd | 818 | dmaengine_terminate_all(dtc->chan); |
9704efaa | 819 | |
4a776f0a HS |
820 | kfree(dtc); |
821 | } | |
822 | ||
e03e93a9 AS |
823 | static int dmatest_add_threads(struct dmatest_info *info, |
824 | struct dmatest_chan *dtc, enum dma_transaction_type type) | |
4a776f0a | 825 | { |
15b8a8ea | 826 | struct dmatest_params *params = &info->params; |
b54d5cb9 DW |
827 | struct dmatest_thread *thread; |
828 | struct dma_chan *chan = dtc->chan; | |
829 | char *op; | |
830 | unsigned int i; | |
4a776f0a | 831 | |
b54d5cb9 DW |
832 | if (type == DMA_MEMCPY) |
833 | op = "copy"; | |
61b5f54d SK |
834 | else if (type == DMA_MEMSET) |
835 | op = "set"; | |
b54d5cb9 DW |
836 | else if (type == DMA_XOR) |
837 | op = "xor"; | |
58691d64 DW |
838 | else if (type == DMA_PQ) |
839 | op = "pq"; | |
b54d5cb9 DW |
840 | else |
841 | return -EINVAL; | |
4a776f0a | 842 | |
15b8a8ea | 843 | for (i = 0; i < params->threads_per_chan; i++) { |
4a776f0a HS |
844 | thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); |
845 | if (!thread) { | |
0adff800 DW |
846 | pr_warn("No memory for %s-%s%u\n", |
847 | dma_chan_name(chan), op, i); | |
4a776f0a HS |
848 | break; |
849 | } | |
e03e93a9 | 850 | thread->info = info; |
4a776f0a | 851 | thread->chan = dtc->chan; |
b54d5cb9 | 852 | thread->type = type; |
6f6a23a2 AW |
853 | thread->test_done.wait = &thread->done_wait; |
854 | init_waitqueue_head(&thread->done_wait); | |
4a776f0a | 855 | smp_wmb(); |
2d88ce76 | 856 | thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", |
b54d5cb9 | 857 | dma_chan_name(chan), op, i); |
4a776f0a | 858 | if (IS_ERR(thread->task)) { |
2d88ce76 | 859 | pr_warn("Failed to create thread %s-%s%u\n", |
0adff800 | 860 | dma_chan_name(chan), op, i); |
4a776f0a HS |
861 | kfree(thread); |
862 | break; | |
863 | } | |
864 | ||
865 | /* srcbuf and dstbuf are allocated by the thread itself */ | |
2d88ce76 | 866 | get_task_struct(thread->task); |
4a776f0a | 867 | list_add_tail(&thread->node, &dtc->threads); |
2d88ce76 | 868 | wake_up_process(thread->task); |
4a776f0a HS |
869 | } |
870 | ||
b54d5cb9 DW |
871 | return i; |
872 | } | |
873 | ||
e03e93a9 AS |
874 | static int dmatest_add_channel(struct dmatest_info *info, |
875 | struct dma_chan *chan) | |
b54d5cb9 DW |
876 | { |
877 | struct dmatest_chan *dtc; | |
878 | struct dma_device *dma_dev = chan->device; | |
879 | unsigned int thread_count = 0; | |
b9033e68 | 880 | int cnt; |
b54d5cb9 DW |
881 | |
882 | dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); | |
883 | if (!dtc) { | |
0adff800 | 884 | pr_warn("No memory for %s\n", dma_chan_name(chan)); |
b54d5cb9 DW |
885 | return -ENOMEM; |
886 | } | |
887 | ||
888 | dtc->chan = chan; | |
889 | INIT_LIST_HEAD(&dtc->threads); | |
890 | ||
891 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
a0d4cb44 KA |
892 | if (dmatest == 0) { |
893 | cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); | |
894 | thread_count += cnt > 0 ? cnt : 0; | |
895 | } | |
b54d5cb9 | 896 | } |
a0d4cb44 | 897 | |
61b5f54d | 898 | if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { |
a0d4cb44 | 899 | if (dmatest == 1) { |
c678fa66 | 900 | cnt = dmatest_add_threads(info, dtc, DMA_MEMSET); |
a0d4cb44 KA |
901 | thread_count += cnt > 0 ? cnt : 0; |
902 | } | |
903 | } | |
904 | ||
b54d5cb9 | 905 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
e03e93a9 | 906 | cnt = dmatest_add_threads(info, dtc, DMA_XOR); |
f1aef8b6 | 907 | thread_count += cnt > 0 ? cnt : 0; |
b54d5cb9 | 908 | } |
58691d64 | 909 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
e03e93a9 | 910 | cnt = dmatest_add_threads(info, dtc, DMA_PQ); |
d07a74a5 | 911 | thread_count += cnt > 0 ? cnt : 0; |
58691d64 | 912 | } |
b54d5cb9 | 913 | |
0adff800 | 914 | pr_info("Started %u threads using %s\n", |
b54d5cb9 | 915 | thread_count, dma_chan_name(chan)); |
4a776f0a | 916 | |
838cc704 AS |
917 | list_add_tail(&dtc->node, &info->channels); |
918 | info->nr_channels++; | |
4a776f0a | 919 | |
33df8ca0 | 920 | return 0; |
4a776f0a HS |
921 | } |
922 | ||
7dd60251 | 923 | static bool filter(struct dma_chan *chan, void *param) |
4a776f0a | 924 | { |
15b8a8ea | 925 | struct dmatest_params *params = param; |
e03e93a9 | 926 | |
15b8a8ea AS |
927 | if (!dmatest_match_channel(params, chan) || |
928 | !dmatest_match_device(params, chan->device)) | |
7dd60251 | 929 | return false; |
33df8ca0 | 930 | else |
7dd60251 | 931 | return true; |
4a776f0a HS |
932 | } |
933 | ||
a9e55495 DW |
934 | static void request_channels(struct dmatest_info *info, |
935 | enum dma_transaction_type type) | |
4a776f0a | 936 | { |
33df8ca0 | 937 | dma_cap_mask_t mask; |
33df8ca0 DW |
938 | |
939 | dma_cap_zero(mask); | |
a9e55495 | 940 | dma_cap_set(type, mask); |
33df8ca0 | 941 | for (;;) { |
a9e55495 DW |
942 | struct dmatest_params *params = &info->params; |
943 | struct dma_chan *chan; | |
944 | ||
15b8a8ea | 945 | chan = dma_request_channel(mask, filter, params); |
33df8ca0 | 946 | if (chan) { |
a9e55495 | 947 | if (dmatest_add_channel(info, chan)) { |
33df8ca0 DW |
948 | dma_release_channel(chan); |
949 | break; /* add_channel failed, punt */ | |
950 | } | |
951 | } else | |
952 | break; /* no more channels available */ | |
15b8a8ea AS |
953 | if (params->max_channels && |
954 | info->nr_channels >= params->max_channels) | |
33df8ca0 DW |
955 | break; /* we have all we need */ |
956 | } | |
4a776f0a | 957 | } |
4a776f0a | 958 | |
a9e55495 | 959 | static void run_threaded_test(struct dmatest_info *info) |
851b7e16 | 960 | { |
a9e55495 | 961 | struct dmatest_params *params = &info->params; |
851b7e16 | 962 | |
a9e55495 DW |
963 | /* Copy test parameters */ |
964 | params->buf_size = test_buf_size; | |
965 | strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); | |
966 | strlcpy(params->device, strim(test_device), sizeof(params->device)); | |
967 | params->threads_per_chan = threads_per_chan; | |
968 | params->max_channels = max_channels; | |
969 | params->iterations = iterations; | |
970 | params->xor_sources = xor_sources; | |
971 | params->pq_sources = pq_sources; | |
972 | params->timeout = timeout; | |
e3b9c347 | 973 | params->noverify = noverify; |
a9e55495 DW |
974 | |
975 | request_channels(info, DMA_MEMCPY); | |
61b5f54d | 976 | request_channels(info, DMA_MEMSET); |
a9e55495 DW |
977 | request_channels(info, DMA_XOR); |
978 | request_channels(info, DMA_PQ); | |
851b7e16 | 979 | } |
851b7e16 | 980 | |
a310d037 | 981 | static void stop_threaded_test(struct dmatest_info *info) |
4a776f0a | 982 | { |
33df8ca0 | 983 | struct dmatest_chan *dtc, *_dtc; |
7cbd4877 | 984 | struct dma_chan *chan; |
33df8ca0 | 985 | |
838cc704 | 986 | list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { |
33df8ca0 | 987 | list_del(&dtc->node); |
7cbd4877 | 988 | chan = dtc->chan; |
33df8ca0 | 989 | dmatest_cleanup_channel(dtc); |
0adff800 | 990 | pr_debug("dropped channel %s\n", dma_chan_name(chan)); |
7cbd4877 | 991 | dma_release_channel(chan); |
33df8ca0 | 992 | } |
838cc704 AS |
993 | |
994 | info->nr_channels = 0; | |
4a776f0a | 995 | } |
e03e93a9 | 996 | |
a9e55495 | 997 | static void restart_threaded_test(struct dmatest_info *info, bool run) |
851b7e16 | 998 | { |
a310d037 DW |
999 | /* we might be called early to set run=, defer running until all |
1000 | * parameters have been evaluated | |
1001 | */ | |
1002 | if (!info->did_init) | |
a9e55495 | 1003 | return; |
851b7e16 AS |
1004 | |
1005 | /* Stop any running test first */ | |
a310d037 | 1006 | stop_threaded_test(info); |
851b7e16 AS |
1007 | |
1008 | /* Run test with new parameters */ | |
a9e55495 | 1009 | run_threaded_test(info); |
851b7e16 AS |
1010 | } |
1011 | ||
a310d037 | 1012 | static int dmatest_run_get(char *val, const struct kernel_param *kp) |
851b7e16 | 1013 | { |
a310d037 | 1014 | struct dmatest_info *info = &test_info; |
851b7e16 AS |
1015 | |
1016 | mutex_lock(&info->lock); | |
a310d037 DW |
1017 | if (is_threaded_test_run(info)) { |
1018 | dmatest_run = true; | |
3e5ccd86 | 1019 | } else { |
a310d037 DW |
1020 | stop_threaded_test(info); |
1021 | dmatest_run = false; | |
3e5ccd86 | 1022 | } |
851b7e16 | 1023 | mutex_unlock(&info->lock); |
851b7e16 | 1024 | |
a310d037 | 1025 | return param_get_bool(val, kp); |
851b7e16 AS |
1026 | } |
1027 | ||
a310d037 | 1028 | static int dmatest_run_set(const char *val, const struct kernel_param *kp) |
95019c8c | 1029 | { |
a310d037 DW |
1030 | struct dmatest_info *info = &test_info; |
1031 | int ret; | |
95019c8c | 1032 | |
a310d037 DW |
1033 | mutex_lock(&info->lock); |
1034 | ret = param_set_bool(val, kp); | |
1035 | if (ret) { | |
851b7e16 | 1036 | mutex_unlock(&info->lock); |
a310d037 | 1037 | return ret; |
95019c8c AS |
1038 | } |
1039 | ||
a310d037 DW |
1040 | if (is_threaded_test_run(info)) |
1041 | ret = -EBUSY; | |
1042 | else if (dmatest_run) | |
a9e55495 | 1043 | restart_threaded_test(info, dmatest_run); |
851b7e16 | 1044 | |
a310d037 | 1045 | mutex_unlock(&info->lock); |
851b7e16 | 1046 | |
a310d037 | 1047 | return ret; |
851b7e16 AS |
1048 | } |
1049 | ||
e03e93a9 AS |
1050 | static int __init dmatest_init(void) |
1051 | { | |
1052 | struct dmatest_info *info = &test_info; | |
2d88ce76 | 1053 | struct dmatest_params *params = &info->params; |
e03e93a9 | 1054 | |
a310d037 DW |
1055 | if (dmatest_run) { |
1056 | mutex_lock(&info->lock); | |
a9e55495 | 1057 | run_threaded_test(info); |
a310d037 DW |
1058 | mutex_unlock(&info->lock); |
1059 | } | |
838cc704 | 1060 | |
2d88ce76 DW |
1061 | if (params->iterations && wait) |
1062 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
95019c8c | 1063 | |
a310d037 DW |
1064 | /* module parameters are stable, inittime tests are started, |
1065 | * let userspace take over 'run' control | |
1066 | */ | |
1067 | info->did_init = true; | |
851b7e16 | 1068 | |
851b7e16 | 1069 | return 0; |
e03e93a9 AS |
1070 | } |
1071 | /* when compiled-in wait for drivers to load first */ | |
1072 | late_initcall(dmatest_init); | |
1073 | ||
1074 | static void __exit dmatest_exit(void) | |
1075 | { | |
1076 | struct dmatest_info *info = &test_info; | |
1077 | ||
a310d037 | 1078 | mutex_lock(&info->lock); |
e03e93a9 | 1079 | stop_threaded_test(info); |
a310d037 | 1080 | mutex_unlock(&info->lock); |
e03e93a9 | 1081 | } |
4a776f0a HS |
1082 | module_exit(dmatest_exit); |
1083 | ||
e05503ef | 1084 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
4a776f0a | 1085 | MODULE_LICENSE("GPL v2"); |