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Commit | Line | Data |
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4a776f0a HS |
1 | /* |
2 | * DMA Engine test module | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
851b7e16 | 5 | * Copyright (C) 2013 Intel Corporation |
4a776f0a HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
872f05c6 DW |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
4a776f0a | 13 | #include <linux/delay.h> |
b7f080cf | 14 | #include <linux/dma-mapping.h> |
4a776f0a | 15 | #include <linux/dmaengine.h> |
981ed70d | 16 | #include <linux/freezer.h> |
4a776f0a HS |
17 | #include <linux/init.h> |
18 | #include <linux/kthread.h> | |
0881e7bd | 19 | #include <linux/sched/task.h> |
4a776f0a HS |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/random.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
4a776f0a HS |
24 | #include <linux/wait.h> |
25 | ||
26 | static unsigned int test_buf_size = 16384; | |
a6c268d0 | 27 | module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
28 | MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); |
29 | ||
06190d84 | 30 | static char test_channel[20]; |
a6c268d0 AS |
31 | module_param_string(channel, test_channel, sizeof(test_channel), |
32 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
33 | MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); |
34 | ||
a85159fe | 35 | static char test_device[32]; |
a6c268d0 AS |
36 | module_param_string(device, test_device, sizeof(test_device), |
37 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
38 | MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); |
39 | ||
40 | static unsigned int threads_per_chan = 1; | |
a6c268d0 | 41 | module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
42 | MODULE_PARM_DESC(threads_per_chan, |
43 | "Number of threads to start per channel (default: 1)"); | |
44 | ||
45 | static unsigned int max_channels; | |
a6c268d0 | 46 | module_param(max_channels, uint, S_IRUGO | S_IWUSR); |
33df8ca0 | 47 | MODULE_PARM_DESC(max_channels, |
4a776f0a HS |
48 | "Maximum number of channels to use (default: all)"); |
49 | ||
0a2ff57d | 50 | static unsigned int iterations; |
a6c268d0 | 51 | module_param(iterations, uint, S_IRUGO | S_IWUSR); |
0a2ff57d NF |
52 | MODULE_PARM_DESC(iterations, |
53 | "Iterations before stopping test (default: infinite)"); | |
54 | ||
a0d4cb44 KA |
55 | static unsigned int sg_buffers = 1; |
56 | module_param(sg_buffers, uint, S_IRUGO | S_IWUSR); | |
57 | MODULE_PARM_DESC(sg_buffers, | |
58 | "Number of scatter gather buffers (default: 1)"); | |
59 | ||
d8646724 | 60 | static unsigned int dmatest; |
a0d4cb44 KA |
61 | module_param(dmatest, uint, S_IRUGO | S_IWUSR); |
62 | MODULE_PARM_DESC(dmatest, | |
61b5f54d | 63 | "dmatest 0-memcpy 1-slave_sg 2-memset (default: 0)"); |
a0d4cb44 | 64 | |
b54d5cb9 | 65 | static unsigned int xor_sources = 3; |
a6c268d0 | 66 | module_param(xor_sources, uint, S_IRUGO | S_IWUSR); |
b54d5cb9 DW |
67 | MODULE_PARM_DESC(xor_sources, |
68 | "Number of xor source buffers (default: 3)"); | |
69 | ||
58691d64 | 70 | static unsigned int pq_sources = 3; |
a6c268d0 | 71 | module_param(pq_sources, uint, S_IRUGO | S_IWUSR); |
58691d64 DW |
72 | MODULE_PARM_DESC(pq_sources, |
73 | "Number of p+q source buffers (default: 3)"); | |
74 | ||
d42efe6b | 75 | static int timeout = 3000; |
a6c268d0 | 76 | module_param(timeout, uint, S_IRUGO | S_IWUSR); |
85ee7a1d JP |
77 | MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " |
78 | "Pass -1 for infinite timeout"); | |
d42efe6b | 79 | |
e3b9c347 DW |
80 | static bool noverify; |
81 | module_param(noverify, bool, S_IRUGO | S_IWUSR); | |
82 | MODULE_PARM_DESC(noverify, "Disable random data setup and verification"); | |
4a776f0a | 83 | |
50137a7d DW |
84 | static bool verbose; |
85 | module_param(verbose, bool, S_IRUGO | S_IWUSR); | |
86 | MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); | |
4a776f0a | 87 | |
e03e93a9 | 88 | /** |
15b8a8ea | 89 | * struct dmatest_params - test parameters. |
e03e93a9 AS |
90 | * @buf_size: size of the memcpy test buffer |
91 | * @channel: bus ID of the channel to test | |
92 | * @device: bus ID of the DMA Engine to test | |
93 | * @threads_per_chan: number of threads to start per channel | |
94 | * @max_channels: maximum number of channels to use | |
95 | * @iterations: iterations before stopping test | |
96 | * @xor_sources: number of xor source buffers | |
97 | * @pq_sources: number of p+q source buffers | |
98 | * @timeout: transfer timeout in msec, -1 for infinite timeout | |
99 | */ | |
15b8a8ea | 100 | struct dmatest_params { |
e03e93a9 AS |
101 | unsigned int buf_size; |
102 | char channel[20]; | |
a85159fe | 103 | char device[32]; |
e03e93a9 AS |
104 | unsigned int threads_per_chan; |
105 | unsigned int max_channels; | |
106 | unsigned int iterations; | |
107 | unsigned int xor_sources; | |
108 | unsigned int pq_sources; | |
109 | int timeout; | |
e3b9c347 | 110 | bool noverify; |
15b8a8ea AS |
111 | }; |
112 | ||
113 | /** | |
114 | * struct dmatest_info - test information. | |
115 | * @params: test parameters | |
851b7e16 | 116 | * @lock: access protection to the fields of this structure |
15b8a8ea | 117 | */ |
a310d037 | 118 | static struct dmatest_info { |
15b8a8ea AS |
119 | /* Test parameters */ |
120 | struct dmatest_params params; | |
838cc704 AS |
121 | |
122 | /* Internal state */ | |
123 | struct list_head channels; | |
124 | unsigned int nr_channels; | |
851b7e16 | 125 | struct mutex lock; |
a310d037 DW |
126 | bool did_init; |
127 | } test_info = { | |
128 | .channels = LIST_HEAD_INIT(test_info.channels), | |
129 | .lock = __MUTEX_INITIALIZER(test_info.lock), | |
130 | }; | |
851b7e16 | 131 | |
a310d037 DW |
132 | static int dmatest_run_set(const char *val, const struct kernel_param *kp); |
133 | static int dmatest_run_get(char *val, const struct kernel_param *kp); | |
9c27847d | 134 | static const struct kernel_param_ops run_ops = { |
a310d037 DW |
135 | .set = dmatest_run_set, |
136 | .get = dmatest_run_get, | |
e03e93a9 | 137 | }; |
a310d037 DW |
138 | static bool dmatest_run; |
139 | module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); | |
140 | MODULE_PARM_DESC(run, "Run the test (default: false)"); | |
e03e93a9 | 141 | |
a310d037 DW |
142 | /* Maximum amount of mismatched bytes in buffer to print */ |
143 | #define MAX_ERROR_COUNT 32 | |
144 | ||
145 | /* | |
146 | * Initialization patterns. All bytes in the source buffer has bit 7 | |
147 | * set, all bytes in the destination buffer has bit 7 cleared. | |
148 | * | |
149 | * Bit 6 is set for all bytes which are to be copied by the DMA | |
150 | * engine. Bit 5 is set for all bytes which are to be overwritten by | |
151 | * the DMA engine. | |
152 | * | |
153 | * The remaining bits are the inverse of a counter which increments by | |
154 | * one for each byte address. | |
155 | */ | |
156 | #define PATTERN_SRC 0x80 | |
157 | #define PATTERN_DST 0x00 | |
158 | #define PATTERN_COPY 0x40 | |
159 | #define PATTERN_OVERWRITE 0x20 | |
160 | #define PATTERN_COUNT_MASK 0x1f | |
61b5f54d | 161 | #define PATTERN_MEMSET_IDX 0x01 |
851b7e16 | 162 | |
a310d037 DW |
163 | struct dmatest_thread { |
164 | struct list_head node; | |
165 | struct dmatest_info *info; | |
166 | struct task_struct *task; | |
167 | struct dma_chan *chan; | |
168 | u8 **srcs; | |
d6481608 | 169 | u8 **usrcs; |
a310d037 | 170 | u8 **dsts; |
d6481608 | 171 | u8 **udsts; |
a310d037 DW |
172 | enum dma_transaction_type type; |
173 | bool done; | |
174 | }; | |
95019c8c | 175 | |
a310d037 DW |
176 | struct dmatest_chan { |
177 | struct list_head node; | |
178 | struct dma_chan *chan; | |
179 | struct list_head threads; | |
e03e93a9 AS |
180 | }; |
181 | ||
2d88ce76 DW |
182 | static DECLARE_WAIT_QUEUE_HEAD(thread_wait); |
183 | static bool wait; | |
184 | ||
185 | static bool is_threaded_test_run(struct dmatest_info *info) | |
186 | { | |
187 | struct dmatest_chan *dtc; | |
188 | ||
189 | list_for_each_entry(dtc, &info->channels, node) { | |
190 | struct dmatest_thread *thread; | |
191 | ||
192 | list_for_each_entry(thread, &dtc->threads, node) { | |
193 | if (!thread->done) | |
194 | return true; | |
195 | } | |
196 | } | |
197 | ||
198 | return false; | |
199 | } | |
200 | ||
201 | static int dmatest_wait_get(char *val, const struct kernel_param *kp) | |
202 | { | |
203 | struct dmatest_info *info = &test_info; | |
204 | struct dmatest_params *params = &info->params; | |
205 | ||
206 | if (params->iterations) | |
207 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
208 | wait = true; | |
209 | return param_get_bool(val, kp); | |
210 | } | |
211 | ||
9c27847d | 212 | static const struct kernel_param_ops wait_ops = { |
2d88ce76 DW |
213 | .get = dmatest_wait_get, |
214 | .set = param_set_bool, | |
215 | }; | |
216 | module_param_cb(wait, &wait_ops, &wait, S_IRUGO); | |
217 | MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); | |
e03e93a9 | 218 | |
15b8a8ea | 219 | static bool dmatest_match_channel(struct dmatest_params *params, |
e03e93a9 | 220 | struct dma_chan *chan) |
4a776f0a | 221 | { |
15b8a8ea | 222 | if (params->channel[0] == '\0') |
4a776f0a | 223 | return true; |
15b8a8ea | 224 | return strcmp(dma_chan_name(chan), params->channel) == 0; |
4a776f0a HS |
225 | } |
226 | ||
15b8a8ea | 227 | static bool dmatest_match_device(struct dmatest_params *params, |
e03e93a9 | 228 | struct dma_device *device) |
4a776f0a | 229 | { |
15b8a8ea | 230 | if (params->device[0] == '\0') |
4a776f0a | 231 | return true; |
15b8a8ea | 232 | return strcmp(dev_name(device->dev), params->device) == 0; |
4a776f0a HS |
233 | } |
234 | ||
235 | static unsigned long dmatest_random(void) | |
236 | { | |
237 | unsigned long buf; | |
238 | ||
be9fa5a4 | 239 | prandom_bytes(&buf, sizeof(buf)); |
4a776f0a HS |
240 | return buf; |
241 | } | |
242 | ||
61b5f54d SK |
243 | static inline u8 gen_inv_idx(u8 index, bool is_memset) |
244 | { | |
245 | u8 val = is_memset ? PATTERN_MEMSET_IDX : index; | |
246 | ||
247 | return ~val & PATTERN_COUNT_MASK; | |
248 | } | |
249 | ||
250 | static inline u8 gen_src_value(u8 index, bool is_memset) | |
251 | { | |
252 | return PATTERN_SRC | gen_inv_idx(index, is_memset); | |
253 | } | |
254 | ||
255 | static inline u8 gen_dst_value(u8 index, bool is_memset) | |
256 | { | |
257 | return PATTERN_DST | gen_inv_idx(index, is_memset); | |
258 | } | |
259 | ||
e03e93a9 | 260 | static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 261 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
262 | { |
263 | unsigned int i; | |
b54d5cb9 DW |
264 | u8 *buf; |
265 | ||
266 | for (; (buf = *bufs); bufs++) { | |
267 | for (i = 0; i < start; i++) | |
61b5f54d | 268 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 | 269 | for ( ; i < start + len; i++) |
61b5f54d | 270 | buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY; |
e03e93a9 | 271 | for ( ; i < buf_size; i++) |
61b5f54d | 272 | buf[i] = gen_src_value(i, is_memset); |
b54d5cb9 DW |
273 | buf++; |
274 | } | |
4a776f0a HS |
275 | } |
276 | ||
e03e93a9 | 277 | static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, |
61b5f54d | 278 | unsigned int buf_size, bool is_memset) |
4a776f0a HS |
279 | { |
280 | unsigned int i; | |
b54d5cb9 DW |
281 | u8 *buf; |
282 | ||
283 | for (; (buf = *bufs); bufs++) { | |
284 | for (i = 0; i < start; i++) | |
61b5f54d | 285 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 286 | for ( ; i < start + len; i++) |
61b5f54d SK |
287 | buf[i] = gen_dst_value(i, is_memset) | |
288 | PATTERN_OVERWRITE; | |
e03e93a9 | 289 | for ( ; i < buf_size; i++) |
61b5f54d | 290 | buf[i] = gen_dst_value(i, is_memset); |
b54d5cb9 | 291 | } |
4a776f0a HS |
292 | } |
293 | ||
7b610178 | 294 | static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, |
61b5f54d | 295 | unsigned int counter, bool is_srcbuf, bool is_memset) |
7b610178 DW |
296 | { |
297 | u8 diff = actual ^ pattern; | |
61b5f54d | 298 | u8 expected = pattern | gen_inv_idx(counter, is_memset); |
7b610178 DW |
299 | const char *thread_name = current->comm; |
300 | ||
301 | if (is_srcbuf) | |
302 | pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", | |
303 | thread_name, index, expected, actual); | |
304 | else if ((pattern & PATTERN_COPY) | |
305 | && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) | |
306 | pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", | |
307 | thread_name, index, expected, actual); | |
308 | else if (diff & PATTERN_SRC) | |
309 | pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", | |
310 | thread_name, index, expected, actual); | |
311 | else | |
312 | pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", | |
313 | thread_name, index, expected, actual); | |
314 | } | |
315 | ||
316 | static unsigned int dmatest_verify(u8 **bufs, unsigned int start, | |
317 | unsigned int end, unsigned int counter, u8 pattern, | |
61b5f54d | 318 | bool is_srcbuf, bool is_memset) |
4a776f0a HS |
319 | { |
320 | unsigned int i; | |
321 | unsigned int error_count = 0; | |
322 | u8 actual; | |
b54d5cb9 DW |
323 | u8 expected; |
324 | u8 *buf; | |
325 | unsigned int counter_orig = counter; | |
326 | ||
327 | for (; (buf = *bufs); bufs++) { | |
328 | counter = counter_orig; | |
329 | for (i = start; i < end; i++) { | |
330 | actual = buf[i]; | |
61b5f54d | 331 | expected = pattern | gen_inv_idx(counter, is_memset); |
b54d5cb9 | 332 | if (actual != expected) { |
7b610178 DW |
333 | if (error_count < MAX_ERROR_COUNT) |
334 | dmatest_mismatch(actual, pattern, i, | |
61b5f54d SK |
335 | counter, is_srcbuf, |
336 | is_memset); | |
b54d5cb9 DW |
337 | error_count++; |
338 | } | |
339 | counter++; | |
4a776f0a | 340 | } |
4a776f0a HS |
341 | } |
342 | ||
74b5c07a | 343 | if (error_count > MAX_ERROR_COUNT) |
7b610178 | 344 | pr_warn("%s: %u errors suppressed\n", |
74b5c07a | 345 | current->comm, error_count - MAX_ERROR_COUNT); |
4a776f0a HS |
346 | |
347 | return error_count; | |
348 | } | |
349 | ||
adfa543e TH |
350 | /* poor man's completion - we want to use wait_event_freezable() on it */ |
351 | struct dmatest_done { | |
352 | bool done; | |
353 | wait_queue_head_t *wait; | |
354 | }; | |
355 | ||
356 | static void dmatest_callback(void *arg) | |
e44e0aa3 | 357 | { |
adfa543e TH |
358 | struct dmatest_done *done = arg; |
359 | ||
360 | done->done = true; | |
361 | wake_up_all(done->wait); | |
e44e0aa3 DW |
362 | } |
363 | ||
8be9e32b AM |
364 | static unsigned int min_odd(unsigned int x, unsigned int y) |
365 | { | |
366 | unsigned int val = min(x, y); | |
367 | ||
368 | return val % 2 ? val : val - 1; | |
369 | } | |
370 | ||
872f05c6 DW |
371 | static void result(const char *err, unsigned int n, unsigned int src_off, |
372 | unsigned int dst_off, unsigned int len, unsigned long data) | |
d86b2f29 | 373 | { |
2acec150 | 374 | pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
872f05c6 | 375 | current->comm, n, err, src_off, dst_off, len, data); |
d86b2f29 AS |
376 | } |
377 | ||
872f05c6 DW |
378 | static void dbg_result(const char *err, unsigned int n, unsigned int src_off, |
379 | unsigned int dst_off, unsigned int len, | |
380 | unsigned long data) | |
95019c8c | 381 | { |
2acec150 | 382 | pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
a835bb85 | 383 | current->comm, n, err, src_off, dst_off, len, data); |
95019c8c AS |
384 | } |
385 | ||
a835bb85 AS |
386 | #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ |
387 | if (verbose) \ | |
388 | result(err, n, src_off, dst_off, len, data); \ | |
389 | else \ | |
390 | dbg_result(err, n, src_off, dst_off, len, data);\ | |
50137a7d | 391 | }) |
95019c8c | 392 | |
86727443 | 393 | static unsigned long long dmatest_persec(s64 runtime, unsigned int val) |
d86b2f29 | 394 | { |
86727443 | 395 | unsigned long long per_sec = 1000000; |
d86b2f29 | 396 | |
86727443 DW |
397 | if (runtime <= 0) |
398 | return 0; | |
95019c8c | 399 | |
86727443 DW |
400 | /* drop precision until runtime is 32-bits */ |
401 | while (runtime > UINT_MAX) { | |
402 | runtime >>= 1; | |
403 | per_sec <<= 1; | |
95019c8c AS |
404 | } |
405 | ||
86727443 DW |
406 | per_sec *= val; |
407 | do_div(per_sec, runtime); | |
408 | return per_sec; | |
95019c8c AS |
409 | } |
410 | ||
86727443 | 411 | static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) |
95019c8c | 412 | { |
86727443 | 413 | return dmatest_persec(runtime, len >> 10); |
95019c8c AS |
414 | } |
415 | ||
4a776f0a HS |
416 | /* |
417 | * This function repeatedly tests DMA transfers of various lengths and | |
b54d5cb9 DW |
418 | * offsets for a given operation type until it is told to exit by |
419 | * kthread_stop(). There may be multiple threads running this function | |
420 | * in parallel for a single channel, and there may be multiple channels | |
421 | * being tested in parallel. | |
4a776f0a HS |
422 | * |
423 | * Before each test, the source and destination buffer is initialized | |
424 | * with a known pattern. This pattern is different depending on | |
425 | * whether it's in an area which is supposed to be copied or | |
426 | * overwritten, and different in the source and destination buffers. | |
427 | * So if the DMA engine doesn't copy exactly what we tell it to copy, | |
428 | * we'll notice. | |
429 | */ | |
430 | static int dmatest_func(void *data) | |
431 | { | |
adfa543e | 432 | DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait); |
4a776f0a | 433 | struct dmatest_thread *thread = data; |
adfa543e | 434 | struct dmatest_done done = { .wait = &done_wait }; |
e03e93a9 | 435 | struct dmatest_info *info; |
15b8a8ea | 436 | struct dmatest_params *params; |
4a776f0a | 437 | struct dma_chan *chan; |
8be9e32b | 438 | struct dma_device *dev; |
4a776f0a HS |
439 | unsigned int error_count; |
440 | unsigned int failed_tests = 0; | |
441 | unsigned int total_tests = 0; | |
442 | dma_cookie_t cookie; | |
443 | enum dma_status status; | |
b54d5cb9 | 444 | enum dma_ctrl_flags flags; |
945b5af3 | 445 | u8 *pq_coefs = NULL; |
4a776f0a | 446 | int ret; |
b54d5cb9 DW |
447 | int src_cnt; |
448 | int dst_cnt; | |
449 | int i; | |
e9405ef0 | 450 | ktime_t ktime, start, diff; |
8b0e1953 TG |
451 | ktime_t filltime = 0; |
452 | ktime_t comparetime = 0; | |
86727443 DW |
453 | s64 runtime = 0; |
454 | unsigned long long total_len = 0; | |
d6481608 | 455 | u8 align = 0; |
61b5f54d | 456 | bool is_memset = false; |
4a776f0a | 457 | |
adfa543e | 458 | set_freezable(); |
4a776f0a HS |
459 | |
460 | ret = -ENOMEM; | |
4a776f0a HS |
461 | |
462 | smp_rmb(); | |
e03e93a9 | 463 | info = thread->info; |
15b8a8ea | 464 | params = &info->params; |
4a776f0a | 465 | chan = thread->chan; |
8be9e32b | 466 | dev = chan->device; |
d6481608 DJ |
467 | if (thread->type == DMA_MEMCPY) { |
468 | align = dev->copy_align; | |
b54d5cb9 | 469 | src_cnt = dst_cnt = 1; |
61b5f54d SK |
470 | } else if (thread->type == DMA_MEMSET) { |
471 | align = dev->fill_align; | |
472 | src_cnt = dst_cnt = 1; | |
473 | is_memset = true; | |
d6481608 DJ |
474 | } else if (thread->type == DMA_SG) { |
475 | align = dev->copy_align; | |
a0d4cb44 | 476 | src_cnt = dst_cnt = sg_buffers; |
d6481608 | 477 | } else if (thread->type == DMA_XOR) { |
8be9e32b | 478 | /* force odd to ensure dst = src */ |
15b8a8ea | 479 | src_cnt = min_odd(params->xor_sources | 1, dev->max_xor); |
b54d5cb9 | 480 | dst_cnt = 1; |
d6481608 | 481 | align = dev->xor_align; |
58691d64 | 482 | } else if (thread->type == DMA_PQ) { |
8be9e32b | 483 | /* force odd to ensure dst = src */ |
15b8a8ea | 484 | src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); |
58691d64 | 485 | dst_cnt = 2; |
d6481608 | 486 | align = dev->pq_align; |
945b5af3 | 487 | |
31d18257 | 488 | pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL); |
945b5af3 AS |
489 | if (!pq_coefs) |
490 | goto err_thread_type; | |
491 | ||
94de648d | 492 | for (i = 0; i < src_cnt; i++) |
58691d64 | 493 | pq_coefs[i] = 1; |
b54d5cb9 | 494 | } else |
945b5af3 | 495 | goto err_thread_type; |
b54d5cb9 | 496 | |
31d18257 | 497 | thread->srcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL); |
b54d5cb9 DW |
498 | if (!thread->srcs) |
499 | goto err_srcs; | |
d6481608 DJ |
500 | |
501 | thread->usrcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
502 | if (!thread->usrcs) | |
503 | goto err_usrcs; | |
504 | ||
b54d5cb9 | 505 | for (i = 0; i < src_cnt; i++) { |
d6481608 DJ |
506 | thread->usrcs[i] = kmalloc(params->buf_size + align, |
507 | GFP_KERNEL); | |
508 | if (!thread->usrcs[i]) | |
b54d5cb9 | 509 | goto err_srcbuf; |
d6481608 DJ |
510 | |
511 | /* align srcs to alignment restriction */ | |
512 | if (align) | |
513 | thread->srcs[i] = PTR_ALIGN(thread->usrcs[i], align); | |
514 | else | |
515 | thread->srcs[i] = thread->usrcs[i]; | |
b54d5cb9 DW |
516 | } |
517 | thread->srcs[i] = NULL; | |
518 | ||
31d18257 | 519 | thread->dsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL); |
b54d5cb9 DW |
520 | if (!thread->dsts) |
521 | goto err_dsts; | |
d6481608 DJ |
522 | |
523 | thread->udsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL); | |
524 | if (!thread->udsts) | |
525 | goto err_udsts; | |
526 | ||
b54d5cb9 | 527 | for (i = 0; i < dst_cnt; i++) { |
d6481608 DJ |
528 | thread->udsts[i] = kmalloc(params->buf_size + align, |
529 | GFP_KERNEL); | |
530 | if (!thread->udsts[i]) | |
b54d5cb9 | 531 | goto err_dstbuf; |
d6481608 DJ |
532 | |
533 | /* align dsts to alignment restriction */ | |
534 | if (align) | |
535 | thread->dsts[i] = PTR_ALIGN(thread->udsts[i], align); | |
536 | else | |
537 | thread->dsts[i] = thread->udsts[i]; | |
b54d5cb9 DW |
538 | } |
539 | thread->dsts[i] = NULL; | |
540 | ||
e44e0aa3 DW |
541 | set_user_nice(current, 10); |
542 | ||
b203bd3f | 543 | /* |
d1cab34c | 544 | * src and dst buffers are freed by ourselves below |
b203bd3f | 545 | */ |
0776ae7b | 546 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
4a776f0a | 547 | |
86727443 | 548 | ktime = ktime_get(); |
0a2ff57d | 549 | while (!kthread_should_stop() |
15b8a8ea | 550 | && !(params->iterations && total_tests >= params->iterations)) { |
b54d5cb9 | 551 | struct dma_async_tx_descriptor *tx = NULL; |
4076e755 DW |
552 | struct dmaengine_unmap_data *um; |
553 | dma_addr_t srcs[src_cnt]; | |
554 | dma_addr_t *dsts; | |
ede23a58 | 555 | unsigned int src_off, dst_off, len; |
a0d4cb44 KA |
556 | struct scatterlist tx_sg[src_cnt]; |
557 | struct scatterlist rx_sg[src_cnt]; | |
d86be86e | 558 | |
4a776f0a HS |
559 | total_tests++; |
560 | ||
fbfb8e1d SR |
561 | /* Check if buffer count fits into map count variable (u8) */ |
562 | if ((src_cnt + dst_cnt) >= 255) { | |
563 | pr_err("too many buffers (%d of 255 supported)\n", | |
564 | src_cnt + dst_cnt); | |
565 | break; | |
566 | } | |
567 | ||
15b8a8ea | 568 | if (1 << align > params->buf_size) { |
cfe4f275 | 569 | pr_err("%u-byte buffer too small for %d-byte alignment\n", |
15b8a8ea | 570 | params->buf_size, 1 << align); |
cfe4f275 GL |
571 | break; |
572 | } | |
573 | ||
ede23a58 | 574 | if (params->noverify) |
e3b9c347 | 575 | len = params->buf_size; |
ede23a58 AS |
576 | else |
577 | len = dmatest_random() % params->buf_size + 1; | |
578 | ||
579 | len = (len >> align) << align; | |
580 | if (!len) | |
581 | len = 1 << align; | |
582 | ||
583 | total_len += len; | |
584 | ||
585 | if (params->noverify) { | |
e3b9c347 DW |
586 | src_off = 0; |
587 | dst_off = 0; | |
588 | } else { | |
e9405ef0 | 589 | start = ktime_get(); |
e3b9c347 DW |
590 | src_off = dmatest_random() % (params->buf_size - len + 1); |
591 | dst_off = dmatest_random() % (params->buf_size - len + 1); | |
592 | ||
593 | src_off = (src_off >> align) << align; | |
594 | dst_off = (dst_off >> align) << align; | |
595 | ||
596 | dmatest_init_srcs(thread->srcs, src_off, len, | |
61b5f54d | 597 | params->buf_size, is_memset); |
e3b9c347 | 598 | dmatest_init_dsts(thread->dsts, dst_off, len, |
61b5f54d | 599 | params->buf_size, is_memset); |
e9405ef0 SK |
600 | |
601 | diff = ktime_sub(ktime_get(), start); | |
602 | filltime = ktime_add(filltime, diff); | |
e3b9c347 DW |
603 | } |
604 | ||
31d18257 | 605 | um = dmaengine_get_unmap_data(dev->dev, src_cnt + dst_cnt, |
4076e755 DW |
606 | GFP_KERNEL); |
607 | if (!um) { | |
608 | failed_tests++; | |
609 | result("unmap data NULL", total_tests, | |
610 | src_off, dst_off, len, ret); | |
611 | continue; | |
612 | } | |
4a776f0a | 613 | |
4076e755 | 614 | um->len = params->buf_size; |
b54d5cb9 | 615 | for (i = 0; i < src_cnt; i++) { |
745c00da | 616 | void *buf = thread->srcs[i]; |
4076e755 | 617 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 618 | unsigned long pg_off = offset_in_page(buf); |
4076e755 DW |
619 | |
620 | um->addr[i] = dma_map_page(dev->dev, pg, pg_off, | |
621 | um->len, DMA_TO_DEVICE); | |
622 | srcs[i] = um->addr[i] + src_off; | |
623 | ret = dma_mapping_error(dev->dev, um->addr[i]); | |
afde3be1 | 624 | if (ret) { |
4076e755 | 625 | dmaengine_unmap_put(um); |
872f05c6 DW |
626 | result("src mapping error", total_tests, |
627 | src_off, dst_off, len, ret); | |
afde3be1 AS |
628 | failed_tests++; |
629 | continue; | |
630 | } | |
4076e755 | 631 | um->to_cnt++; |
b54d5cb9 | 632 | } |
d86be86e | 633 | /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ |
4076e755 | 634 | dsts = &um->addr[src_cnt]; |
b54d5cb9 | 635 | for (i = 0; i < dst_cnt; i++) { |
745c00da | 636 | void *buf = thread->dsts[i]; |
4076e755 | 637 | struct page *pg = virt_to_page(buf); |
f62e5f61 | 638 | unsigned long pg_off = offset_in_page(buf); |
4076e755 DW |
639 | |
640 | dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, | |
641 | DMA_BIDIRECTIONAL); | |
642 | ret = dma_mapping_error(dev->dev, dsts[i]); | |
afde3be1 | 643 | if (ret) { |
4076e755 | 644 | dmaengine_unmap_put(um); |
872f05c6 DW |
645 | result("dst mapping error", total_tests, |
646 | src_off, dst_off, len, ret); | |
afde3be1 AS |
647 | failed_tests++; |
648 | continue; | |
649 | } | |
4076e755 | 650 | um->bidi_cnt++; |
b54d5cb9 DW |
651 | } |
652 | ||
a0d4cb44 KA |
653 | sg_init_table(tx_sg, src_cnt); |
654 | sg_init_table(rx_sg, src_cnt); | |
655 | for (i = 0; i < src_cnt; i++) { | |
656 | sg_dma_address(&rx_sg[i]) = srcs[i]; | |
657 | sg_dma_address(&tx_sg[i]) = dsts[i] + dst_off; | |
658 | sg_dma_len(&tx_sg[i]) = len; | |
659 | sg_dma_len(&rx_sg[i]) = len; | |
660 | } | |
661 | ||
b54d5cb9 DW |
662 | if (thread->type == DMA_MEMCPY) |
663 | tx = dev->device_prep_dma_memcpy(chan, | |
4076e755 DW |
664 | dsts[0] + dst_off, |
665 | srcs[0], len, flags); | |
61b5f54d SK |
666 | else if (thread->type == DMA_MEMSET) |
667 | tx = dev->device_prep_dma_memset(chan, | |
668 | dsts[0] + dst_off, | |
669 | *(thread->srcs[0] + src_off), | |
670 | len, flags); | |
a0d4cb44 KA |
671 | else if (thread->type == DMA_SG) |
672 | tx = dev->device_prep_dma_sg(chan, tx_sg, src_cnt, | |
673 | rx_sg, src_cnt, flags); | |
b54d5cb9 DW |
674 | else if (thread->type == DMA_XOR) |
675 | tx = dev->device_prep_dma_xor(chan, | |
4076e755 DW |
676 | dsts[0] + dst_off, |
677 | srcs, src_cnt, | |
b54d5cb9 | 678 | len, flags); |
58691d64 DW |
679 | else if (thread->type == DMA_PQ) { |
680 | dma_addr_t dma_pq[dst_cnt]; | |
681 | ||
682 | for (i = 0; i < dst_cnt; i++) | |
4076e755 DW |
683 | dma_pq[i] = dsts[i] + dst_off; |
684 | tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, | |
94de648d | 685 | src_cnt, pq_coefs, |
58691d64 DW |
686 | len, flags); |
687 | } | |
d86be86e | 688 | |
d86be86e | 689 | if (!tx) { |
4076e755 | 690 | dmaengine_unmap_put(um); |
872f05c6 DW |
691 | result("prep error", total_tests, src_off, |
692 | dst_off, len, ret); | |
d86be86e AN |
693 | msleep(100); |
694 | failed_tests++; | |
695 | continue; | |
696 | } | |
e44e0aa3 | 697 | |
adfa543e | 698 | done.done = false; |
e44e0aa3 | 699 | tx->callback = dmatest_callback; |
adfa543e | 700 | tx->callback_param = &done; |
d86be86e AN |
701 | cookie = tx->tx_submit(tx); |
702 | ||
4a776f0a | 703 | if (dma_submit_error(cookie)) { |
4076e755 | 704 | dmaengine_unmap_put(um); |
872f05c6 DW |
705 | result("submit error", total_tests, src_off, |
706 | dst_off, len, ret); | |
4a776f0a HS |
707 | msleep(100); |
708 | failed_tests++; | |
709 | continue; | |
710 | } | |
b54d5cb9 | 711 | dma_async_issue_pending(chan); |
4a776f0a | 712 | |
bcc567e3 | 713 | wait_event_freezable_timeout(done_wait, done.done, |
15b8a8ea | 714 | msecs_to_jiffies(params->timeout)); |
981ed70d | 715 | |
e44e0aa3 | 716 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); |
4a776f0a | 717 | |
adfa543e TH |
718 | if (!done.done) { |
719 | /* | |
720 | * We're leaving the timed out dma operation with | |
721 | * dangling pointer to done_wait. To make this | |
722 | * correct, we'll need to allocate wait_done for | |
723 | * each test iteration and perform "who's gonna | |
724 | * free it this time?" dancing. For now, just | |
725 | * leave it dangling. | |
726 | */ | |
4076e755 | 727 | dmaengine_unmap_put(um); |
872f05c6 DW |
728 | result("test timed out", total_tests, src_off, dst_off, |
729 | len, 0); | |
e44e0aa3 DW |
730 | failed_tests++; |
731 | continue; | |
19e9f99f | 732 | } else if (status != DMA_COMPLETE) { |
4076e755 | 733 | dmaengine_unmap_put(um); |
872f05c6 DW |
734 | result(status == DMA_ERROR ? |
735 | "completion error status" : | |
736 | "completion busy status", total_tests, src_off, | |
737 | dst_off, len, ret); | |
4a776f0a HS |
738 | failed_tests++; |
739 | continue; | |
740 | } | |
e44e0aa3 | 741 | |
4076e755 | 742 | dmaengine_unmap_put(um); |
4a776f0a | 743 | |
e3b9c347 | 744 | if (params->noverify) { |
50137a7d DW |
745 | verbose_result("test passed", total_tests, src_off, |
746 | dst_off, len, 0); | |
e3b9c347 DW |
747 | continue; |
748 | } | |
4a776f0a | 749 | |
e9405ef0 | 750 | start = ktime_get(); |
872f05c6 | 751 | pr_debug("%s: verifying source buffer...\n", current->comm); |
e3b9c347 | 752 | error_count = dmatest_verify(thread->srcs, 0, src_off, |
61b5f54d | 753 | 0, PATTERN_SRC, true, is_memset); |
7b610178 DW |
754 | error_count += dmatest_verify(thread->srcs, src_off, |
755 | src_off + len, src_off, | |
61b5f54d | 756 | PATTERN_SRC | PATTERN_COPY, true, is_memset); |
7b610178 DW |
757 | error_count += dmatest_verify(thread->srcs, src_off + len, |
758 | params->buf_size, src_off + len, | |
61b5f54d | 759 | PATTERN_SRC, true, is_memset); |
7b610178 | 760 | |
872f05c6 | 761 | pr_debug("%s: verifying dest buffer...\n", current->comm); |
7b610178 | 762 | error_count += dmatest_verify(thread->dsts, 0, dst_off, |
61b5f54d SK |
763 | 0, PATTERN_DST, false, is_memset); |
764 | ||
7b610178 DW |
765 | error_count += dmatest_verify(thread->dsts, dst_off, |
766 | dst_off + len, src_off, | |
61b5f54d SK |
767 | PATTERN_SRC | PATTERN_COPY, false, is_memset); |
768 | ||
7b610178 DW |
769 | error_count += dmatest_verify(thread->dsts, dst_off + len, |
770 | params->buf_size, dst_off + len, | |
61b5f54d | 771 | PATTERN_DST, false, is_memset); |
4a776f0a | 772 | |
e9405ef0 SK |
773 | diff = ktime_sub(ktime_get(), start); |
774 | comparetime = ktime_add(comparetime, diff); | |
775 | ||
4a776f0a | 776 | if (error_count) { |
872f05c6 DW |
777 | result("data error", total_tests, src_off, dst_off, |
778 | len, error_count); | |
4a776f0a HS |
779 | failed_tests++; |
780 | } else { | |
50137a7d DW |
781 | verbose_result("test passed", total_tests, src_off, |
782 | dst_off, len, 0); | |
4a776f0a HS |
783 | } |
784 | } | |
e9405ef0 SK |
785 | ktime = ktime_sub(ktime_get(), ktime); |
786 | ktime = ktime_sub(ktime, comparetime); | |
787 | ktime = ktime_sub(ktime, filltime); | |
788 | runtime = ktime_to_us(ktime); | |
4a776f0a HS |
789 | |
790 | ret = 0; | |
8e1f50d7 | 791 | err_dstbuf: |
d6481608 DJ |
792 | for (i = 0; thread->udsts[i]; i++) |
793 | kfree(thread->udsts[i]); | |
794 | kfree(thread->udsts); | |
795 | err_udsts: | |
b54d5cb9 DW |
796 | kfree(thread->dsts); |
797 | err_dsts: | |
8e1f50d7 | 798 | err_srcbuf: |
d6481608 DJ |
799 | for (i = 0; thread->usrcs[i]; i++) |
800 | kfree(thread->usrcs[i]); | |
801 | kfree(thread->usrcs); | |
802 | err_usrcs: | |
b54d5cb9 DW |
803 | kfree(thread->srcs); |
804 | err_srcs: | |
945b5af3 AS |
805 | kfree(pq_coefs); |
806 | err_thread_type: | |
86727443 DW |
807 | pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n", |
808 | current->comm, total_tests, failed_tests, | |
809 | dmatest_persec(runtime, total_tests), | |
810 | dmatest_KBs(runtime, total_len), ret); | |
0a2ff57d | 811 | |
9704efaa | 812 | /* terminate all transfers on specified channels */ |
5e034f7b SH |
813 | if (ret) |
814 | dmaengine_terminate_all(chan); | |
815 | ||
3e5ccd86 | 816 | thread->done = true; |
2d88ce76 | 817 | wake_up(&thread_wait); |
0a2ff57d | 818 | |
4a776f0a HS |
819 | return ret; |
820 | } | |
821 | ||
822 | static void dmatest_cleanup_channel(struct dmatest_chan *dtc) | |
823 | { | |
824 | struct dmatest_thread *thread; | |
825 | struct dmatest_thread *_thread; | |
826 | int ret; | |
827 | ||
828 | list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { | |
829 | ret = kthread_stop(thread->task); | |
0adff800 DW |
830 | pr_debug("thread %s exited with status %d\n", |
831 | thread->task->comm, ret); | |
4a776f0a | 832 | list_del(&thread->node); |
2d88ce76 | 833 | put_task_struct(thread->task); |
4a776f0a HS |
834 | kfree(thread); |
835 | } | |
9704efaa VK |
836 | |
837 | /* terminate all transfers on specified channels */ | |
944ea4dd | 838 | dmaengine_terminate_all(dtc->chan); |
9704efaa | 839 | |
4a776f0a HS |
840 | kfree(dtc); |
841 | } | |
842 | ||
e03e93a9 AS |
843 | static int dmatest_add_threads(struct dmatest_info *info, |
844 | struct dmatest_chan *dtc, enum dma_transaction_type type) | |
4a776f0a | 845 | { |
15b8a8ea | 846 | struct dmatest_params *params = &info->params; |
b54d5cb9 DW |
847 | struct dmatest_thread *thread; |
848 | struct dma_chan *chan = dtc->chan; | |
849 | char *op; | |
850 | unsigned int i; | |
4a776f0a | 851 | |
b54d5cb9 DW |
852 | if (type == DMA_MEMCPY) |
853 | op = "copy"; | |
61b5f54d SK |
854 | else if (type == DMA_MEMSET) |
855 | op = "set"; | |
a0d4cb44 KA |
856 | else if (type == DMA_SG) |
857 | op = "sg"; | |
b54d5cb9 DW |
858 | else if (type == DMA_XOR) |
859 | op = "xor"; | |
58691d64 DW |
860 | else if (type == DMA_PQ) |
861 | op = "pq"; | |
b54d5cb9 DW |
862 | else |
863 | return -EINVAL; | |
4a776f0a | 864 | |
15b8a8ea | 865 | for (i = 0; i < params->threads_per_chan; i++) { |
4a776f0a HS |
866 | thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); |
867 | if (!thread) { | |
0adff800 DW |
868 | pr_warn("No memory for %s-%s%u\n", |
869 | dma_chan_name(chan), op, i); | |
4a776f0a HS |
870 | break; |
871 | } | |
e03e93a9 | 872 | thread->info = info; |
4a776f0a | 873 | thread->chan = dtc->chan; |
b54d5cb9 | 874 | thread->type = type; |
4a776f0a | 875 | smp_wmb(); |
2d88ce76 | 876 | thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", |
b54d5cb9 | 877 | dma_chan_name(chan), op, i); |
4a776f0a | 878 | if (IS_ERR(thread->task)) { |
2d88ce76 | 879 | pr_warn("Failed to create thread %s-%s%u\n", |
0adff800 | 880 | dma_chan_name(chan), op, i); |
4a776f0a HS |
881 | kfree(thread); |
882 | break; | |
883 | } | |
884 | ||
885 | /* srcbuf and dstbuf are allocated by the thread itself */ | |
2d88ce76 | 886 | get_task_struct(thread->task); |
4a776f0a | 887 | list_add_tail(&thread->node, &dtc->threads); |
2d88ce76 | 888 | wake_up_process(thread->task); |
4a776f0a HS |
889 | } |
890 | ||
b54d5cb9 DW |
891 | return i; |
892 | } | |
893 | ||
e03e93a9 AS |
894 | static int dmatest_add_channel(struct dmatest_info *info, |
895 | struct dma_chan *chan) | |
b54d5cb9 DW |
896 | { |
897 | struct dmatest_chan *dtc; | |
898 | struct dma_device *dma_dev = chan->device; | |
899 | unsigned int thread_count = 0; | |
b9033e68 | 900 | int cnt; |
b54d5cb9 DW |
901 | |
902 | dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); | |
903 | if (!dtc) { | |
0adff800 | 904 | pr_warn("No memory for %s\n", dma_chan_name(chan)); |
b54d5cb9 DW |
905 | return -ENOMEM; |
906 | } | |
907 | ||
908 | dtc->chan = chan; | |
909 | INIT_LIST_HEAD(&dtc->threads); | |
910 | ||
911 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
a0d4cb44 KA |
912 | if (dmatest == 0) { |
913 | cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); | |
914 | thread_count += cnt > 0 ? cnt : 0; | |
915 | } | |
b54d5cb9 | 916 | } |
a0d4cb44 | 917 | |
61b5f54d SK |
918 | if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { |
919 | if (dmatest == 2) { | |
920 | cnt = dmatest_add_threads(info, dtc, DMA_MEMSET); | |
921 | thread_count += cnt > 0 ? cnt : 0; | |
922 | } | |
923 | } | |
924 | ||
a0d4cb44 KA |
925 | if (dma_has_cap(DMA_SG, dma_dev->cap_mask)) { |
926 | if (dmatest == 1) { | |
927 | cnt = dmatest_add_threads(info, dtc, DMA_SG); | |
928 | thread_count += cnt > 0 ? cnt : 0; | |
929 | } | |
930 | } | |
931 | ||
b54d5cb9 | 932 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
e03e93a9 | 933 | cnt = dmatest_add_threads(info, dtc, DMA_XOR); |
f1aef8b6 | 934 | thread_count += cnt > 0 ? cnt : 0; |
b54d5cb9 | 935 | } |
58691d64 | 936 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
e03e93a9 | 937 | cnt = dmatest_add_threads(info, dtc, DMA_PQ); |
d07a74a5 | 938 | thread_count += cnt > 0 ? cnt : 0; |
58691d64 | 939 | } |
b54d5cb9 | 940 | |
0adff800 | 941 | pr_info("Started %u threads using %s\n", |
b54d5cb9 | 942 | thread_count, dma_chan_name(chan)); |
4a776f0a | 943 | |
838cc704 AS |
944 | list_add_tail(&dtc->node, &info->channels); |
945 | info->nr_channels++; | |
4a776f0a | 946 | |
33df8ca0 | 947 | return 0; |
4a776f0a HS |
948 | } |
949 | ||
7dd60251 | 950 | static bool filter(struct dma_chan *chan, void *param) |
4a776f0a | 951 | { |
15b8a8ea | 952 | struct dmatest_params *params = param; |
e03e93a9 | 953 | |
15b8a8ea AS |
954 | if (!dmatest_match_channel(params, chan) || |
955 | !dmatest_match_device(params, chan->device)) | |
7dd60251 | 956 | return false; |
33df8ca0 | 957 | else |
7dd60251 | 958 | return true; |
4a776f0a HS |
959 | } |
960 | ||
a9e55495 DW |
961 | static void request_channels(struct dmatest_info *info, |
962 | enum dma_transaction_type type) | |
4a776f0a | 963 | { |
33df8ca0 | 964 | dma_cap_mask_t mask; |
33df8ca0 DW |
965 | |
966 | dma_cap_zero(mask); | |
a9e55495 | 967 | dma_cap_set(type, mask); |
33df8ca0 | 968 | for (;;) { |
a9e55495 DW |
969 | struct dmatest_params *params = &info->params; |
970 | struct dma_chan *chan; | |
971 | ||
15b8a8ea | 972 | chan = dma_request_channel(mask, filter, params); |
33df8ca0 | 973 | if (chan) { |
a9e55495 | 974 | if (dmatest_add_channel(info, chan)) { |
33df8ca0 DW |
975 | dma_release_channel(chan); |
976 | break; /* add_channel failed, punt */ | |
977 | } | |
978 | } else | |
979 | break; /* no more channels available */ | |
15b8a8ea AS |
980 | if (params->max_channels && |
981 | info->nr_channels >= params->max_channels) | |
33df8ca0 DW |
982 | break; /* we have all we need */ |
983 | } | |
4a776f0a | 984 | } |
4a776f0a | 985 | |
a9e55495 | 986 | static void run_threaded_test(struct dmatest_info *info) |
851b7e16 | 987 | { |
a9e55495 | 988 | struct dmatest_params *params = &info->params; |
851b7e16 | 989 | |
a9e55495 DW |
990 | /* Copy test parameters */ |
991 | params->buf_size = test_buf_size; | |
992 | strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); | |
993 | strlcpy(params->device, strim(test_device), sizeof(params->device)); | |
994 | params->threads_per_chan = threads_per_chan; | |
995 | params->max_channels = max_channels; | |
996 | params->iterations = iterations; | |
997 | params->xor_sources = xor_sources; | |
998 | params->pq_sources = pq_sources; | |
999 | params->timeout = timeout; | |
e3b9c347 | 1000 | params->noverify = noverify; |
a9e55495 DW |
1001 | |
1002 | request_channels(info, DMA_MEMCPY); | |
61b5f54d | 1003 | request_channels(info, DMA_MEMSET); |
a9e55495 | 1004 | request_channels(info, DMA_XOR); |
a0d4cb44 | 1005 | request_channels(info, DMA_SG); |
a9e55495 | 1006 | request_channels(info, DMA_PQ); |
851b7e16 | 1007 | } |
851b7e16 | 1008 | |
a310d037 | 1009 | static void stop_threaded_test(struct dmatest_info *info) |
4a776f0a | 1010 | { |
33df8ca0 | 1011 | struct dmatest_chan *dtc, *_dtc; |
7cbd4877 | 1012 | struct dma_chan *chan; |
33df8ca0 | 1013 | |
838cc704 | 1014 | list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { |
33df8ca0 | 1015 | list_del(&dtc->node); |
7cbd4877 | 1016 | chan = dtc->chan; |
33df8ca0 | 1017 | dmatest_cleanup_channel(dtc); |
0adff800 | 1018 | pr_debug("dropped channel %s\n", dma_chan_name(chan)); |
7cbd4877 | 1019 | dma_release_channel(chan); |
33df8ca0 | 1020 | } |
838cc704 AS |
1021 | |
1022 | info->nr_channels = 0; | |
4a776f0a | 1023 | } |
e03e93a9 | 1024 | |
a9e55495 | 1025 | static void restart_threaded_test(struct dmatest_info *info, bool run) |
851b7e16 | 1026 | { |
a310d037 DW |
1027 | /* we might be called early to set run=, defer running until all |
1028 | * parameters have been evaluated | |
1029 | */ | |
1030 | if (!info->did_init) | |
a9e55495 | 1031 | return; |
851b7e16 AS |
1032 | |
1033 | /* Stop any running test first */ | |
a310d037 | 1034 | stop_threaded_test(info); |
851b7e16 AS |
1035 | |
1036 | /* Run test with new parameters */ | |
a9e55495 | 1037 | run_threaded_test(info); |
851b7e16 AS |
1038 | } |
1039 | ||
a310d037 | 1040 | static int dmatest_run_get(char *val, const struct kernel_param *kp) |
851b7e16 | 1041 | { |
a310d037 | 1042 | struct dmatest_info *info = &test_info; |
851b7e16 AS |
1043 | |
1044 | mutex_lock(&info->lock); | |
a310d037 DW |
1045 | if (is_threaded_test_run(info)) { |
1046 | dmatest_run = true; | |
3e5ccd86 | 1047 | } else { |
a310d037 DW |
1048 | stop_threaded_test(info); |
1049 | dmatest_run = false; | |
3e5ccd86 | 1050 | } |
851b7e16 | 1051 | mutex_unlock(&info->lock); |
851b7e16 | 1052 | |
a310d037 | 1053 | return param_get_bool(val, kp); |
851b7e16 AS |
1054 | } |
1055 | ||
a310d037 | 1056 | static int dmatest_run_set(const char *val, const struct kernel_param *kp) |
95019c8c | 1057 | { |
a310d037 DW |
1058 | struct dmatest_info *info = &test_info; |
1059 | int ret; | |
95019c8c | 1060 | |
a310d037 DW |
1061 | mutex_lock(&info->lock); |
1062 | ret = param_set_bool(val, kp); | |
1063 | if (ret) { | |
851b7e16 | 1064 | mutex_unlock(&info->lock); |
a310d037 | 1065 | return ret; |
95019c8c AS |
1066 | } |
1067 | ||
a310d037 DW |
1068 | if (is_threaded_test_run(info)) |
1069 | ret = -EBUSY; | |
1070 | else if (dmatest_run) | |
a9e55495 | 1071 | restart_threaded_test(info, dmatest_run); |
851b7e16 | 1072 | |
a310d037 | 1073 | mutex_unlock(&info->lock); |
851b7e16 | 1074 | |
a310d037 | 1075 | return ret; |
851b7e16 AS |
1076 | } |
1077 | ||
e03e93a9 AS |
1078 | static int __init dmatest_init(void) |
1079 | { | |
1080 | struct dmatest_info *info = &test_info; | |
2d88ce76 | 1081 | struct dmatest_params *params = &info->params; |
e03e93a9 | 1082 | |
a310d037 DW |
1083 | if (dmatest_run) { |
1084 | mutex_lock(&info->lock); | |
a9e55495 | 1085 | run_threaded_test(info); |
a310d037 DW |
1086 | mutex_unlock(&info->lock); |
1087 | } | |
838cc704 | 1088 | |
2d88ce76 DW |
1089 | if (params->iterations && wait) |
1090 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
95019c8c | 1091 | |
a310d037 DW |
1092 | /* module parameters are stable, inittime tests are started, |
1093 | * let userspace take over 'run' control | |
1094 | */ | |
1095 | info->did_init = true; | |
851b7e16 | 1096 | |
851b7e16 | 1097 | return 0; |
e03e93a9 AS |
1098 | } |
1099 | /* when compiled-in wait for drivers to load first */ | |
1100 | late_initcall(dmatest_init); | |
1101 | ||
1102 | static void __exit dmatest_exit(void) | |
1103 | { | |
1104 | struct dmatest_info *info = &test_info; | |
1105 | ||
a310d037 | 1106 | mutex_lock(&info->lock); |
e03e93a9 | 1107 | stop_threaded_test(info); |
a310d037 | 1108 | mutex_unlock(&info->lock); |
e03e93a9 | 1109 | } |
4a776f0a HS |
1110 | module_exit(dmatest_exit); |
1111 | ||
e05503ef | 1112 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
4a776f0a | 1113 | MODULE_LICENSE("GPL v2"); |