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Commit | Line | Data |
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3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/delay.h> |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/module.h> | |
3bfb1d20 | 24 | #include <linux/slab.h> |
bb32baf7 | 25 | #include <linux/pm_runtime.h> |
3bfb1d20 | 26 | |
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
327e6970 | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 45 | DW_DMA_MSIZE_16; \ |
495aea4b | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 47 | DW_DMA_MSIZE_16; \ |
bb3450ad | 48 | u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ |
9217a5bf | 49 | _dwc->dws.p_master : _dwc->dws.m_master; \ |
bb3450ad | 50 | u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ |
9217a5bf | 51 | _dwc->dws.p_master : _dwc->dws.m_master; \ |
f301c062 | 52 | \ |
327e6970 VK |
53 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
54 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
55 | | DWC_CTLL_LLP_D_EN \ |
56 | | DWC_CTLL_LLP_S_EN \ | |
bb3450ad MR |
57 | | DWC_CTLL_DMS(_dms) \ |
58 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 59 | }) |
3bfb1d20 | 60 | |
029a40e9 AS |
61 | /* The set of bus widths supported by the DMA controller */ |
62 | #define DW_DMA_BUSWIDTHS \ | |
63 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
64 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
65 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
66 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
67 | ||
3bfb1d20 | 68 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 69 | |
41d5e59c DW |
70 | static struct device *chan2dev(struct dma_chan *chan) |
71 | { | |
72 | return &chan->dev->device; | |
73 | } | |
41d5e59c | 74 | |
3bfb1d20 HS |
75 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
76 | { | |
e63a47a3 | 77 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
78 | } |
79 | ||
ab703f81 | 80 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
3bfb1d20 | 81 | { |
ab703f81 CL |
82 | struct dw_desc *desc = txd_to_dw_desc(tx); |
83 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
84 | dma_cookie_t cookie; | |
85 | unsigned long flags; | |
3bfb1d20 | 86 | |
69cea5a0 | 87 | spin_lock_irqsave(&dwc->lock, flags); |
ab703f81 CL |
88 | cookie = dma_cookie_assign(tx); |
89 | ||
90 | /* | |
91 | * REVISIT: We should attempt to chain as many descriptors as | |
92 | * possible, perhaps even appending to those already submitted | |
93 | * for DMA. But this is hard to do in a race-free manner. | |
94 | */ | |
95 | ||
96 | list_add_tail(&desc->desc_node, &dwc->queue); | |
69cea5a0 | 97 | spin_unlock_irqrestore(&dwc->lock, flags); |
ab703f81 CL |
98 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", |
99 | __func__, desc->txd.cookie); | |
3bfb1d20 | 100 | |
ab703f81 CL |
101 | return cookie; |
102 | } | |
3bfb1d20 | 103 | |
ab703f81 CL |
104 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
105 | { | |
106 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
107 | struct dw_desc *desc; | |
108 | dma_addr_t phys; | |
109 | ||
110 | desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); | |
111 | if (!desc) | |
112 | return NULL; | |
113 | ||
114 | dwc->descs_allocated++; | |
115 | INIT_LIST_HEAD(&desc->tx_list); | |
116 | dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); | |
117 | desc->txd.tx_submit = dwc_tx_submit; | |
118 | desc->txd.flags = DMA_CTRL_ACK; | |
119 | desc->txd.phys = phys; | |
120 | return desc; | |
3bfb1d20 HS |
121 | } |
122 | ||
3bfb1d20 HS |
123 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
124 | { | |
ab703f81 CL |
125 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
126 | struct dw_desc *child, *_next; | |
69cea5a0 | 127 | |
ab703f81 CL |
128 | if (unlikely(!desc)) |
129 | return; | |
3bfb1d20 | 130 | |
ab703f81 CL |
131 | list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { |
132 | list_del(&child->desc_node); | |
133 | dma_pool_free(dw->desc_pool, child, child->txd.phys); | |
134 | dwc->descs_allocated--; | |
3bfb1d20 | 135 | } |
ab703f81 CL |
136 | |
137 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); | |
138 | dwc->descs_allocated--; | |
3bfb1d20 HS |
139 | } |
140 | ||
199244d6 AS |
141 | static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc) |
142 | { | |
143 | u32 cfghi = 0; | |
144 | u32 cfglo = 0; | |
145 | ||
146 | /* Set default burst alignment */ | |
147 | cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN; | |
148 | ||
149 | /* Low 4 bits of the request lines */ | |
150 | cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); | |
151 | cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); | |
152 | ||
153 | /* Request line extension (2 bits) */ | |
154 | cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); | |
155 | cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); | |
156 | ||
157 | channel_writel(dwc, CFG_LO, cfglo); | |
158 | channel_writel(dwc, CFG_HI, cfghi); | |
159 | } | |
160 | ||
161 | static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc) | |
61e183f8 | 162 | { |
61e183f8 VK |
163 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
164 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
c072e113 | 165 | bool hs_polarity = dwc->dws.hs_polarity; |
61e183f8 | 166 | |
9217a5bf AS |
167 | cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); |
168 | cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); | |
61e183f8 | 169 | |
c072e113 AS |
170 | /* Set polarity of handshake interface */ |
171 | cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; | |
172 | ||
61e183f8 VK |
173 | channel_writel(dwc, CFG_LO, cfglo); |
174 | channel_writel(dwc, CFG_HI, cfghi); | |
199244d6 AS |
175 | } |
176 | ||
177 | static void dwc_initialize(struct dw_dma_chan *dwc) | |
178 | { | |
179 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
180 | ||
181 | if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) | |
182 | return; | |
183 | ||
184 | if (dw->pdata->is_idma32) | |
185 | dwc_initialize_chan_idma32(dwc); | |
186 | else | |
187 | dwc_initialize_chan_dw(dwc); | |
61e183f8 VK |
188 | |
189 | /* Enable interrupts */ | |
190 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
191 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
192 | ||
423f9cbf | 193 | set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
61e183f8 VK |
194 | } |
195 | ||
3bfb1d20 HS |
196 | /*----------------------------------------------------------------------*/ |
197 | ||
f52b36d2 | 198 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
199 | { |
200 | dev_err(chan2dev(&dwc->chan), | |
201 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
202 | channel_readl(dwc, SAR), | |
203 | channel_readl(dwc, DAR), | |
204 | channel_readl(dwc, LLP), | |
205 | channel_readl(dwc, CTL_HI), | |
206 | channel_readl(dwc, CTL_LO)); | |
207 | } | |
208 | ||
3f936207 AS |
209 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
210 | { | |
211 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
212 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
213 | cpu_relax(); | |
214 | } | |
215 | ||
2d248812 AS |
216 | static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes, |
217 | unsigned int width, size_t *len) | |
218 | { | |
199244d6 | 219 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
2d248812 AS |
220 | u32 block; |
221 | ||
199244d6 AS |
222 | /* Always in bytes for iDMA 32-bit */ |
223 | if (dw->pdata->is_idma32) | |
224 | width = 0; | |
225 | ||
2d248812 AS |
226 | if ((bytes >> width) > dwc->block_size) { |
227 | block = dwc->block_size; | |
228 | *len = block << width; | |
229 | } else { | |
230 | block = bytes >> width; | |
231 | *len = bytes; | |
232 | } | |
233 | ||
234 | return block; | |
235 | } | |
236 | ||
237 | static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) | |
238 | { | |
199244d6 AS |
239 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
240 | ||
241 | if (dw->pdata->is_idma32) | |
242 | return IDMA32C_CTLH_BLOCK_TS(block); | |
243 | ||
2d248812 AS |
244 | return DWC_CTLH_BLOCK_TS(block) << width; |
245 | } | |
246 | ||
1d455437 AS |
247 | /*----------------------------------------------------------------------*/ |
248 | ||
fed2574b AS |
249 | /* Perform single block transfer */ |
250 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
251 | struct dw_desc *desc) | |
252 | { | |
253 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
254 | u32 ctllo; | |
255 | ||
1d566f11 AS |
256 | /* |
257 | * Software emulation of LLP mode relies on interrupts to continue | |
258 | * multi block transfer. | |
259 | */ | |
df1f3a23 | 260 | ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
fed2574b | 261 | |
df1f3a23 MR |
262 | channel_writel(dwc, SAR, lli_read(desc, sar)); |
263 | channel_writel(dwc, DAR, lli_read(desc, dar)); | |
fed2574b | 264 | channel_writel(dwc, CTL_LO, ctllo); |
df1f3a23 | 265 | channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
fed2574b | 266 | channel_set_bit(dw, CH_EN, dwc->mask); |
f5c6a7df AS |
267 | |
268 | /* Move pointer to next descriptor */ | |
269 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
270 | } |
271 | ||
3bfb1d20 HS |
272 | /* Called with dwc->lock held and bh disabled */ |
273 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
274 | { | |
275 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
9217a5bf | 276 | u8 lms = DWC_LLP_LMS(dwc->dws.m_master); |
fed2574b | 277 | unsigned long was_soft_llp; |
3bfb1d20 HS |
278 | |
279 | /* ASSERT: channel is idle */ | |
280 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 281 | dev_err(chan2dev(&dwc->chan), |
550da64b JN |
282 | "%s: BUG: Attempted to start non-idle channel\n", |
283 | __func__); | |
1d455437 | 284 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
285 | |
286 | /* The tasklet will hopefully advance the queue... */ | |
287 | return; | |
288 | } | |
289 | ||
fed2574b AS |
290 | if (dwc->nollp) { |
291 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
292 | &dwc->flags); | |
293 | if (was_soft_llp) { | |
294 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 295 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
296 | return; |
297 | } | |
298 | ||
299 | dwc_initialize(dwc); | |
300 | ||
b68fd097 | 301 | first->residue = first->total_len; |
f5c6a7df | 302 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 303 | |
fdf475fa | 304 | /* Submit first block */ |
fed2574b AS |
305 | dwc_do_single_block(dwc, first); |
306 | ||
307 | return; | |
308 | } | |
309 | ||
61e183f8 VK |
310 | dwc_initialize(dwc); |
311 | ||
2a0fae02 MR |
312 | channel_writel(dwc, LLP, first->txd.phys | lms); |
313 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
3bfb1d20 HS |
314 | channel_writel(dwc, CTL_HI, 0); |
315 | channel_set_bit(dw, CH_EN, dwc->mask); | |
316 | } | |
317 | ||
e7637c6c AS |
318 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
319 | { | |
cba15617 AS |
320 | struct dw_desc *desc; |
321 | ||
e7637c6c AS |
322 | if (list_empty(&dwc->queue)) |
323 | return; | |
324 | ||
325 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
326 | desc = dwc_first_active(dwc); |
327 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
328 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
329 | } |
330 | ||
3bfb1d20 HS |
331 | /*----------------------------------------------------------------------*/ |
332 | ||
333 | static void | |
5fedefb8 VK |
334 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
335 | bool callback_required) | |
3bfb1d20 | 336 | { |
3bfb1d20 | 337 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 338 | struct dw_desc *child; |
69cea5a0 | 339 | unsigned long flags; |
577ef925 | 340 | struct dmaengine_desc_callback cb; |
3bfb1d20 | 341 | |
41d5e59c | 342 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 343 | |
69cea5a0 | 344 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 345 | dma_cookie_complete(txd); |
577ef925 DJ |
346 | if (callback_required) |
347 | dmaengine_desc_get_callback(txd, &cb); | |
348 | else | |
349 | memset(&cb, 0, sizeof(cb)); | |
3bfb1d20 | 350 | |
e518076e VK |
351 | /* async_tx_ack */ |
352 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
353 | async_tx_ack(&child->txd); | |
354 | async_tx_ack(&desc->txd); | |
ab703f81 | 355 | dwc_desc_put(dwc, desc); |
69cea5a0 VK |
356 | spin_unlock_irqrestore(&dwc->lock, flags); |
357 | ||
577ef925 | 358 | dmaengine_desc_callback_invoke(&cb, NULL); |
3bfb1d20 HS |
359 | } |
360 | ||
361 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
362 | { | |
363 | struct dw_desc *desc, *_desc; | |
364 | LIST_HEAD(list); | |
69cea5a0 | 365 | unsigned long flags; |
3bfb1d20 | 366 | |
69cea5a0 | 367 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 368 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 369 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
370 | "BUG: XFER bit set, but channel not idle!\n"); |
371 | ||
372 | /* Try to continue after resetting the channel... */ | |
3f936207 | 373 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
374 | } |
375 | ||
376 | /* | |
377 | * Submit queued descriptors ASAP, i.e. before we go through | |
378 | * the completed ones. | |
379 | */ | |
3bfb1d20 | 380 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 381 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 382 | |
69cea5a0 VK |
383 | spin_unlock_irqrestore(&dwc->lock, flags); |
384 | ||
3bfb1d20 | 385 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 386 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
387 | } |
388 | ||
4702d524 AS |
389 | /* Returns how many bytes were already received from source */ |
390 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
391 | { | |
392 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
393 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
394 | ||
2d248812 | 395 | return block2bytes(dwc, ctlhi, ctllo >> 4 & 7); |
4702d524 AS |
396 | } |
397 | ||
3bfb1d20 HS |
398 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
399 | { | |
400 | dma_addr_t llp; | |
401 | struct dw_desc *desc, *_desc; | |
402 | struct dw_desc *child; | |
403 | u32 status_xfer; | |
69cea5a0 | 404 | unsigned long flags; |
3bfb1d20 | 405 | |
69cea5a0 | 406 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
407 | llp = channel_readl(dwc, LLP); |
408 | status_xfer = dma_readl(dw, RAW.XFER); | |
409 | ||
410 | if (status_xfer & dwc->mask) { | |
411 | /* Everything we've submitted is done */ | |
412 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
413 | |
414 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
415 | struct list_head *head, *active = dwc->tx_node_active; |
416 | ||
417 | /* | |
418 | * We are inside first active descriptor. | |
419 | * Otherwise something is really wrong. | |
420 | */ | |
421 | desc = dwc_first_active(dwc); | |
422 | ||
423 | head = &desc->tx_list; | |
424 | if (active != head) { | |
b68fd097 AS |
425 | /* Update residue to reflect last sent descriptor */ |
426 | if (active == head->next) | |
427 | desc->residue -= desc->len; | |
428 | else | |
429 | desc->residue -= to_dw_desc(active->prev)->len; | |
4702d524 | 430 | |
fdf475fa | 431 | child = to_dw_desc(active); |
77bcc497 AS |
432 | |
433 | /* Submit next block */ | |
fdf475fa | 434 | dwc_do_single_block(dwc, child); |
77bcc497 | 435 | |
fdf475fa | 436 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
437 | return; |
438 | } | |
fdf475fa | 439 | |
77bcc497 AS |
440 | /* We are done here */ |
441 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
442 | } | |
4702d524 | 443 | |
69cea5a0 VK |
444 | spin_unlock_irqrestore(&dwc->lock, flags); |
445 | ||
3bfb1d20 HS |
446 | dwc_complete_all(dw, dwc); |
447 | return; | |
448 | } | |
449 | ||
69cea5a0 VK |
450 | if (list_empty(&dwc->active_list)) { |
451 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 452 | return; |
69cea5a0 | 453 | } |
087809fc | 454 | |
77bcc497 AS |
455 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
456 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 458 | return; |
69cea5a0 | 459 | } |
087809fc | 460 | |
5a87f0e6 | 461 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
462 | |
463 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 464 | /* Initial residue value */ |
b68fd097 | 465 | desc->residue = desc->total_len; |
4702d524 | 466 | |
75c61225 | 467 | /* Check first descriptors addr */ |
2a0fae02 | 468 | if (desc->txd.phys == DWC_LLP_LOC(llp)) { |
69cea5a0 | 469 | spin_unlock_irqrestore(&dwc->lock, flags); |
84adccfb | 470 | return; |
69cea5a0 | 471 | } |
84adccfb | 472 | |
75c61225 | 473 | /* Check first descriptors llp */ |
df1f3a23 | 474 | if (lli_read(desc, llp) == llp) { |
3bfb1d20 | 475 | /* This one is currently in progress */ |
b68fd097 | 476 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 477 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 478 | return; |
69cea5a0 | 479 | } |
3bfb1d20 | 480 | |
b68fd097 | 481 | desc->residue -= desc->len; |
4702d524 | 482 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
df1f3a23 | 483 | if (lli_read(child, llp) == llp) { |
3bfb1d20 | 484 | /* Currently in progress */ |
b68fd097 | 485 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 486 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 487 | return; |
69cea5a0 | 488 | } |
b68fd097 | 489 | desc->residue -= child->len; |
4702d524 | 490 | } |
3bfb1d20 HS |
491 | |
492 | /* | |
493 | * No descriptors so far seem to be in progress, i.e. | |
494 | * this one must be done. | |
495 | */ | |
69cea5a0 | 496 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 497 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 498 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
499 | } |
500 | ||
41d5e59c | 501 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
502 | "BUG: All descriptors done, but channel not idle!\n"); |
503 | ||
504 | /* Try to continue after resetting the channel... */ | |
3f936207 | 505 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 506 | |
e7637c6c | 507 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 508 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
509 | } |
510 | ||
df1f3a23 | 511 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
3bfb1d20 | 512 | { |
21d43f49 | 513 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
df1f3a23 MR |
514 | lli_read(desc, sar), |
515 | lli_read(desc, dar), | |
516 | lli_read(desc, llp), | |
517 | lli_read(desc, ctlhi), | |
518 | lli_read(desc, ctllo)); | |
3bfb1d20 HS |
519 | } |
520 | ||
521 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
522 | { | |
523 | struct dw_desc *bad_desc; | |
524 | struct dw_desc *child; | |
69cea5a0 | 525 | unsigned long flags; |
3bfb1d20 HS |
526 | |
527 | dwc_scan_descriptors(dw, dwc); | |
528 | ||
69cea5a0 VK |
529 | spin_lock_irqsave(&dwc->lock, flags); |
530 | ||
3bfb1d20 HS |
531 | /* |
532 | * The descriptor currently at the head of the active list is | |
533 | * borked. Since we don't have any way to report errors, we'll | |
534 | * just have to scream loudly and try to carry on. | |
535 | */ | |
536 | bad_desc = dwc_first_active(dwc); | |
537 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 538 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
539 | |
540 | /* Clear the error flag and try to restart the controller */ | |
541 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
542 | if (!list_empty(&dwc->active_list)) | |
543 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
544 | ||
545 | /* | |
ba84bd71 | 546 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
547 | * when someone submits a bad physical address in a |
548 | * descriptor, we should consider ourselves lucky that the | |
549 | * controller flagged an error instead of scribbling over | |
550 | * random memory locations. | |
551 | */ | |
ba84bd71 AS |
552 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
553 | " cookie: %d\n", bad_desc->txd.cookie); | |
df1f3a23 | 554 | dwc_dump_lli(dwc, bad_desc); |
e0bd0f8c | 555 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
df1f3a23 | 556 | dwc_dump_lli(dwc, child); |
3bfb1d20 | 557 | |
69cea5a0 VK |
558 | spin_unlock_irqrestore(&dwc->lock, flags); |
559 | ||
3bfb1d20 | 560 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 561 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
562 | } |
563 | ||
564 | static void dw_dma_tasklet(unsigned long data) | |
565 | { | |
566 | struct dw_dma *dw = (struct dw_dma *)data; | |
567 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
568 | u32 status_xfer; |
569 | u32 status_err; | |
7794e5b9 | 570 | unsigned int i; |
3bfb1d20 | 571 | |
7fe7b2f4 | 572 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
573 | status_err = dma_readl(dw, RAW.ERROR); |
574 | ||
2e4c364e | 575 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
576 | |
577 | for (i = 0; i < dw->dma.chancnt; i++) { | |
578 | dwc = &dw->chan[i]; | |
d9de4519 | 579 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
14bebd01 | 580 | dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); |
d9de4519 | 581 | else if (status_err & (1 << i)) |
3bfb1d20 | 582 | dwc_handle_error(dw, dwc); |
77bcc497 | 583 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 584 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
585 | } |
586 | ||
ee1cdcda | 587 | /* Re-enable interrupts */ |
3bfb1d20 | 588 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
3bfb1d20 HS |
589 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
590 | } | |
591 | ||
592 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
593 | { | |
594 | struct dw_dma *dw = dev_id; | |
02a21b79 | 595 | u32 status; |
3bfb1d20 | 596 | |
02a21b79 AS |
597 | /* Check if we have any interrupt from the DMAC which is not in use */ |
598 | if (!dw->in_use) | |
599 | return IRQ_NONE; | |
600 | ||
601 | status = dma_readl(dw, STATUS_INT); | |
3783cef8 AS |
602 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
603 | ||
604 | /* Check if we have any interrupt from the DMAC */ | |
02a21b79 | 605 | if (!status) |
3783cef8 | 606 | return IRQ_NONE; |
3bfb1d20 HS |
607 | |
608 | /* | |
609 | * Just disable the interrupts. We'll turn them back on in the | |
610 | * softirq handler. | |
611 | */ | |
612 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 613 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
614 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
615 | ||
616 | status = dma_readl(dw, STATUS_INT); | |
617 | if (status) { | |
618 | dev_err(dw->dma.dev, | |
619 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
620 | status); | |
621 | ||
622 | /* Try to recover */ | |
623 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
2895b2ca | 624 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
3bfb1d20 HS |
625 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
626 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
627 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
628 | } | |
629 | ||
630 | tasklet_schedule(&dw->tasklet); | |
631 | ||
632 | return IRQ_HANDLED; | |
633 | } | |
634 | ||
635 | /*----------------------------------------------------------------------*/ | |
636 | ||
3bfb1d20 HS |
637 | static struct dma_async_tx_descriptor * |
638 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
639 | size_t len, unsigned long flags) | |
640 | { | |
641 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 642 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
643 | struct dw_desc *desc; |
644 | struct dw_desc *first; | |
645 | struct dw_desc *prev; | |
646 | size_t xfer_count; | |
647 | size_t offset; | |
9217a5bf | 648 | u8 m_master = dwc->dws.m_master; |
3bfb1d20 HS |
649 | unsigned int src_width; |
650 | unsigned int dst_width; | |
161c3d04 | 651 | unsigned int data_width = dw->pdata->data_width[m_master]; |
3bfb1d20 | 652 | u32 ctllo; |
2e65060e | 653 | u8 lms = DWC_LLP_LMS(m_master); |
3bfb1d20 | 654 | |
2f45d613 | 655 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
656 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
657 | &dest, &src, len, flags); | |
3bfb1d20 HS |
658 | |
659 | if (unlikely(!len)) { | |
2e4c364e | 660 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
661 | return NULL; |
662 | } | |
663 | ||
0fdb567f AS |
664 | dwc->direction = DMA_MEM_TO_MEM; |
665 | ||
2e65060e | 666 | src_width = dst_width = __ffs(data_width | src | dest | len); |
3bfb1d20 | 667 | |
327e6970 | 668 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
669 | | DWC_CTLL_DST_WIDTH(dst_width) |
670 | | DWC_CTLL_SRC_WIDTH(src_width) | |
671 | | DWC_CTLL_DST_INC | |
672 | | DWC_CTLL_SRC_INC | |
673 | | DWC_CTLL_FC_M2M; | |
674 | prev = first = NULL; | |
675 | ||
2d248812 | 676 | for (offset = 0; offset < len; offset += xfer_count) { |
3bfb1d20 HS |
677 | desc = dwc_desc_get(dwc); |
678 | if (!desc) | |
679 | goto err_desc_get; | |
680 | ||
df1f3a23 MR |
681 | lli_write(desc, sar, src + offset); |
682 | lli_write(desc, dar, dest + offset); | |
683 | lli_write(desc, ctllo, ctllo); | |
2d248812 AS |
684 | lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count)); |
685 | desc->len = xfer_count; | |
3bfb1d20 HS |
686 | |
687 | if (!first) { | |
688 | first = desc; | |
689 | } else { | |
2a0fae02 | 690 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 691 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
692 | } |
693 | prev = desc; | |
694 | } | |
695 | ||
3bfb1d20 HS |
696 | if (flags & DMA_PREP_INTERRUPT) |
697 | /* Trigger interrupt after last block */ | |
df1f3a23 | 698 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
699 | |
700 | prev->lli.llp = 0; | |
a3e55799 | 701 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
3bfb1d20 | 702 | first->txd.flags = flags; |
30d38a32 | 703 | first->total_len = len; |
3bfb1d20 HS |
704 | |
705 | return &first->txd; | |
706 | ||
707 | err_desc_get: | |
708 | dwc_desc_put(dwc, first); | |
709 | return NULL; | |
710 | } | |
711 | ||
712 | static struct dma_async_tx_descriptor * | |
713 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 714 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 715 | unsigned long flags, void *context) |
3bfb1d20 HS |
716 | { |
717 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 718 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 719 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
720 | struct dw_desc *prev; |
721 | struct dw_desc *first; | |
722 | u32 ctllo; | |
9217a5bf | 723 | u8 m_master = dwc->dws.m_master; |
2e65060e | 724 | u8 lms = DWC_LLP_LMS(m_master); |
3bfb1d20 HS |
725 | dma_addr_t reg; |
726 | unsigned int reg_width; | |
727 | unsigned int mem_width; | |
161c3d04 | 728 | unsigned int data_width = dw->pdata->data_width[m_master]; |
3bfb1d20 HS |
729 | unsigned int i; |
730 | struct scatterlist *sg; | |
731 | size_t total_len = 0; | |
732 | ||
2e4c364e | 733 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 734 | |
495aea4b | 735 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
736 | return NULL; |
737 | ||
0fdb567f AS |
738 | dwc->direction = direction; |
739 | ||
3bfb1d20 HS |
740 | prev = first = NULL; |
741 | ||
3bfb1d20 | 742 | switch (direction) { |
db8196df | 743 | case DMA_MEM_TO_DEV: |
39416677 | 744 | reg_width = __ffs(sconfig->dst_addr_width); |
327e6970 VK |
745 | reg = sconfig->dst_addr; |
746 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
747 | | DWC_CTLL_DST_WIDTH(reg_width) |
748 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
749 | | DWC_CTLL_SRC_INC); |
750 | ||
751 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
752 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
753 | ||
3bfb1d20 HS |
754 | for_each_sg(sgl, sg, sg_len, i) { |
755 | struct dw_desc *desc; | |
2d248812 AS |
756 | u32 len, mem; |
757 | size_t dlen; | |
3bfb1d20 | 758 | |
cbb796cc | 759 | mem = sg_dma_address(sg); |
69dc14b5 | 760 | len = sg_dma_len(sg); |
6bc711f6 | 761 | |
2e65060e | 762 | mem_width = __ffs(data_width | mem | len); |
3bfb1d20 | 763 | |
69dc14b5 | 764 | slave_sg_todev_fill_desc: |
3bfb1d20 | 765 | desc = dwc_desc_get(dwc); |
b2607227 | 766 | if (!desc) |
3bfb1d20 | 767 | goto err_desc_get; |
3bfb1d20 | 768 | |
df1f3a23 MR |
769 | lli_write(desc, sar, mem); |
770 | lli_write(desc, dar, reg); | |
2d248812 | 771 | lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen)); |
a46a7634 | 772 | lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); |
176dcec5 | 773 | desc->len = dlen; |
3bfb1d20 HS |
774 | |
775 | if (!first) { | |
776 | first = desc; | |
777 | } else { | |
2a0fae02 | 778 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 779 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
780 | } |
781 | prev = desc; | |
a46a7634 JN |
782 | |
783 | mem += dlen; | |
784 | len -= dlen; | |
69dc14b5 VK |
785 | total_len += dlen; |
786 | ||
787 | if (len) | |
788 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
789 | } |
790 | break; | |
db8196df | 791 | case DMA_DEV_TO_MEM: |
39416677 | 792 | reg_width = __ffs(sconfig->src_addr_width); |
327e6970 VK |
793 | reg = sconfig->src_addr; |
794 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
795 | | DWC_CTLL_SRC_WIDTH(reg_width) |
796 | | DWC_CTLL_DST_INC | |
327e6970 VK |
797 | | DWC_CTLL_SRC_FIX); |
798 | ||
799 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
800 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 801 | |
3bfb1d20 HS |
802 | for_each_sg(sgl, sg, sg_len, i) { |
803 | struct dw_desc *desc; | |
2d248812 AS |
804 | u32 len, mem; |
805 | size_t dlen; | |
3bfb1d20 | 806 | |
cbb796cc | 807 | mem = sg_dma_address(sg); |
3bfb1d20 | 808 | len = sg_dma_len(sg); |
6bc711f6 | 809 | |
69dc14b5 VK |
810 | slave_sg_fromdev_fill_desc: |
811 | desc = dwc_desc_get(dwc); | |
b2607227 | 812 | if (!desc) |
69dc14b5 | 813 | goto err_desc_get; |
69dc14b5 | 814 | |
df1f3a23 MR |
815 | lli_write(desc, sar, reg); |
816 | lli_write(desc, dar, mem); | |
2d248812 | 817 | lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen)); |
a46a7634 JN |
818 | mem_width = __ffs(data_width | mem | dlen); |
819 | lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); | |
176dcec5 | 820 | desc->len = dlen; |
3bfb1d20 HS |
821 | |
822 | if (!first) { | |
823 | first = desc; | |
824 | } else { | |
2a0fae02 | 825 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 826 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
827 | } |
828 | prev = desc; | |
a46a7634 JN |
829 | |
830 | mem += dlen; | |
831 | len -= dlen; | |
69dc14b5 VK |
832 | total_len += dlen; |
833 | ||
834 | if (len) | |
835 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
836 | } |
837 | break; | |
838 | default: | |
839 | return NULL; | |
840 | } | |
841 | ||
842 | if (flags & DMA_PREP_INTERRUPT) | |
843 | /* Trigger interrupt after last block */ | |
df1f3a23 | 844 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
845 | |
846 | prev->lli.llp = 0; | |
a3e55799 | 847 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
30d38a32 | 848 | first->total_len = total_len; |
3bfb1d20 HS |
849 | |
850 | return &first->txd; | |
851 | ||
852 | err_desc_get: | |
b2607227 JN |
853 | dev_err(chan2dev(chan), |
854 | "not enough descriptors available. Direction %d\n", direction); | |
3bfb1d20 HS |
855 | dwc_desc_put(dwc, first); |
856 | return NULL; | |
857 | } | |
858 | ||
4d130de2 AS |
859 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
860 | { | |
861 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
862 | struct dw_dma_slave *dws = param; | |
863 | ||
3fe6409c | 864 | if (dws->dma_dev != chan->device->dev) |
4d130de2 AS |
865 | return false; |
866 | ||
867 | /* We have to copy data since dws can be temporary storage */ | |
9217a5bf | 868 | memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); |
4d130de2 AS |
869 | |
870 | return true; | |
871 | } | |
872 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
873 | ||
a4b0d348 | 874 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
327e6970 VK |
875 | { |
876 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
be242f4e | 877 | struct dma_slave_config *sc = &dwc->dma_sconfig; |
199244d6 | 878 | struct dw_dma *dw = to_dw_dma(chan->device); |
be242f4e AS |
879 | /* |
880 | * Fix sconfig's burst size according to dw_dmac. We need to convert | |
881 | * them as: | |
882 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
883 | * | |
884 | * NOTE: burst size 2 is not supported by DesignWare controller. | |
199244d6 | 885 | * iDMA 32-bit supports it. |
be242f4e | 886 | */ |
199244d6 | 887 | u32 s = dw->pdata->is_idma32 ? 1 : 2; |
327e6970 | 888 | |
495aea4b AS |
889 | /* Check if chan will be configured for slave transfers */ |
890 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
891 | return -EINVAL; |
892 | ||
893 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 894 | dwc->direction = sconfig->direction; |
327e6970 | 895 | |
be242f4e AS |
896 | sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0; |
897 | sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0; | |
327e6970 VK |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
199244d6 | 902 | static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) |
21fe3c52 | 903 | { |
199244d6 | 904 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
a4b0d348 MR |
905 | unsigned int count = 20; /* timeout iterations */ |
906 | u32 cfglo; | |
907 | ||
a4b0d348 | 908 | cfglo = channel_readl(dwc, CFG_LO); |
199244d6 AS |
909 | if (dw->pdata->is_idma32) { |
910 | if (drain) | |
911 | cfglo |= IDMA32C_CFGL_CH_DRAIN; | |
912 | else | |
913 | cfglo &= ~IDMA32C_CFGL_CH_DRAIN; | |
914 | } | |
21fe3c52 | 915 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
123b69ab AS |
916 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
917 | udelay(2); | |
21fe3c52 | 918 | |
5e09f98e | 919 | set_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
f4aa3183 | 920 | } |
a4b0d348 | 921 | |
f4aa3183 AS |
922 | static int dwc_pause(struct dma_chan *chan) |
923 | { | |
924 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
925 | unsigned long flags; | |
926 | ||
927 | spin_lock_irqsave(&dwc->lock, flags); | |
199244d6 | 928 | dwc_chan_pause(dwc, false); |
a4b0d348 MR |
929 | spin_unlock_irqrestore(&dwc->lock, flags); |
930 | ||
931 | return 0; | |
21fe3c52 AS |
932 | } |
933 | ||
934 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
935 | { | |
936 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
937 | ||
938 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
939 | ||
5e09f98e | 940 | clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
21fe3c52 AS |
941 | } |
942 | ||
a4b0d348 | 943 | static int dwc_resume(struct dma_chan *chan) |
3bfb1d20 HS |
944 | { |
945 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
69cea5a0 | 946 | unsigned long flags; |
3bfb1d20 | 947 | |
a4b0d348 | 948 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 949 | |
5e09f98e AS |
950 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) |
951 | dwc_chan_resume(dwc); | |
3bfb1d20 | 952 | |
a4b0d348 | 953 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 954 | |
a4b0d348 MR |
955 | return 0; |
956 | } | |
3bfb1d20 | 957 | |
a4b0d348 MR |
958 | static int dwc_terminate_all(struct dma_chan *chan) |
959 | { | |
960 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
961 | struct dw_dma *dw = to_dw_dma(chan->device); | |
962 | struct dw_desc *desc, *_desc; | |
963 | unsigned long flags; | |
964 | LIST_HEAD(list); | |
3bfb1d20 | 965 | |
a4b0d348 | 966 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b | 967 | |
a4b0d348 | 968 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
fed2574b | 969 | |
199244d6 AS |
970 | dwc_chan_pause(dwc, true); |
971 | ||
a4b0d348 | 972 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 973 | |
a4b0d348 | 974 | dwc_chan_resume(dwc); |
a7c57cf7 | 975 | |
a4b0d348 MR |
976 | /* active_list entries will end up before queued entries */ |
977 | list_splice_init(&dwc->queue, &list); | |
978 | list_splice_init(&dwc->active_list, &list); | |
a7c57cf7 | 979 | |
a4b0d348 | 980 | spin_unlock_irqrestore(&dwc->lock, flags); |
a7c57cf7 | 981 | |
a4b0d348 MR |
982 | /* Flush all pending and queued descriptors */ |
983 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
984 | dwc_descriptor_complete(dwc, desc, false); | |
c3635c78 LW |
985 | |
986 | return 0; | |
3bfb1d20 HS |
987 | } |
988 | ||
b68fd097 AS |
989 | static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) |
990 | { | |
991 | struct dw_desc *desc; | |
992 | ||
993 | list_for_each_entry(desc, &dwc->active_list, desc_node) | |
994 | if (desc->txd.cookie == c) | |
995 | return desc; | |
996 | ||
997 | return NULL; | |
998 | } | |
999 | ||
1000 | static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) | |
4702d524 | 1001 | { |
b68fd097 | 1002 | struct dw_desc *desc; |
4702d524 AS |
1003 | unsigned long flags; |
1004 | u32 residue; | |
1005 | ||
1006 | spin_lock_irqsave(&dwc->lock, flags); | |
1007 | ||
b68fd097 AS |
1008 | desc = dwc_find_desc(dwc, cookie); |
1009 | if (desc) { | |
1010 | if (desc == dwc_first_active(dwc)) { | |
1011 | residue = desc->residue; | |
1012 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1013 | residue -= dwc_get_sent(dwc); | |
1014 | } else { | |
1015 | residue = desc->total_len; | |
1016 | } | |
1017 | } else { | |
1018 | residue = 0; | |
1019 | } | |
4702d524 AS |
1020 | |
1021 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1022 | return residue; | |
1023 | } | |
1024 | ||
3bfb1d20 | 1025 | static enum dma_status |
07934481 LW |
1026 | dwc_tx_status(struct dma_chan *chan, |
1027 | dma_cookie_t cookie, | |
1028 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1029 | { |
1030 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1031 | enum dma_status ret; |
3bfb1d20 | 1032 | |
96a2af41 | 1033 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1034 | if (ret == DMA_COMPLETE) |
12381dc0 | 1035 | return ret; |
3bfb1d20 | 1036 | |
12381dc0 | 1037 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1038 | |
12381dc0 | 1039 | ret = dma_cookie_status(chan, cookie, txstate); |
b68fd097 AS |
1040 | if (ret == DMA_COMPLETE) |
1041 | return ret; | |
1042 | ||
1043 | dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); | |
3bfb1d20 | 1044 | |
5e09f98e | 1045 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1046 | return DMA_PAUSED; |
3bfb1d20 HS |
1047 | |
1048 | return ret; | |
1049 | } | |
1050 | ||
1051 | static void dwc_issue_pending(struct dma_chan *chan) | |
1052 | { | |
1053 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1054 | unsigned long flags; |
3bfb1d20 | 1055 | |
dd8ecfca AS |
1056 | spin_lock_irqsave(&dwc->lock, flags); |
1057 | if (list_empty(&dwc->active_list)) | |
1058 | dwc_dostart_first_queued(dwc); | |
1059 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1060 | } |
1061 | ||
99d9bf4e AS |
1062 | /*----------------------------------------------------------------------*/ |
1063 | ||
199244d6 AS |
1064 | /* |
1065 | * Program FIFO size of channels. | |
1066 | * | |
584293c9 | 1067 | * By default full FIFO (512 bytes) is assigned to channel 0. Here we |
199244d6 AS |
1068 | * slice FIFO on equal parts between channels. |
1069 | */ | |
1070 | static void idma32_fifo_partition(struct dw_dma *dw) | |
1071 | { | |
584293c9 | 1072 | u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) | |
199244d6 AS |
1073 | IDMA32C_FP_UPDATE; |
1074 | u64 fifo_partition = 0; | |
1075 | ||
1076 | if (!dw->pdata->is_idma32) | |
1077 | return; | |
1078 | ||
1079 | /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */ | |
1080 | fifo_partition |= value << 0; | |
1081 | ||
1082 | /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */ | |
1083 | fifo_partition |= value << 32; | |
1084 | ||
584293c9 | 1085 | /* Program FIFO Partition registers - 64 bytes per channel */ |
199244d6 AS |
1086 | idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); |
1087 | idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); | |
1088 | } | |
1089 | ||
99d9bf4e AS |
1090 | static void dw_dma_off(struct dw_dma *dw) |
1091 | { | |
7794e5b9 | 1092 | unsigned int i; |
99d9bf4e AS |
1093 | |
1094 | dma_writel(dw, CFG, 0); | |
1095 | ||
1096 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 1097 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
99d9bf4e AS |
1098 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1099 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1100 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1101 | ||
1102 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1103 | cpu_relax(); | |
1104 | ||
1105 | for (i = 0; i < dw->dma.chancnt; i++) | |
423f9cbf | 1106 | clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); |
99d9bf4e AS |
1107 | } |
1108 | ||
1109 | static void dw_dma_on(struct dw_dma *dw) | |
1110 | { | |
1111 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1112 | } | |
1113 | ||
aa1e6f1a | 1114 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1115 | { |
1116 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1117 | struct dw_dma *dw = to_dw_dma(chan->device); | |
3bfb1d20 | 1118 | |
2e4c364e | 1119 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1120 | |
3bfb1d20 HS |
1121 | /* ASSERT: channel is idle */ |
1122 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1123 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1124 | return -EIO; |
1125 | } | |
1126 | ||
d3ee98cd | 1127 | dma_cookie_init(chan); |
3bfb1d20 | 1128 | |
3bfb1d20 HS |
1129 | /* |
1130 | * NOTE: some controllers may have additional features that we | |
1131 | * need to initialize here, like "scatter-gather" (which | |
1132 | * doesn't mean what you think it means), and status writeback. | |
1133 | */ | |
1134 | ||
3fe6409c AS |
1135 | /* |
1136 | * We need controller-specific data to set up slave transfers. | |
1137 | */ | |
1138 | if (chan->private && !dw_dma_filter(chan, chan->private)) { | |
1139 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); | |
1140 | return -EINVAL; | |
1141 | } | |
1142 | ||
99d9bf4e AS |
1143 | /* Enable controller here if needed */ |
1144 | if (!dw->in_use) | |
1145 | dw_dma_on(dw); | |
1146 | dw->in_use |= dwc->mask; | |
1147 | ||
ab703f81 | 1148 | return 0; |
3bfb1d20 HS |
1149 | } |
1150 | ||
1151 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1152 | { | |
1153 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1154 | struct dw_dma *dw = to_dw_dma(chan->device); | |
69cea5a0 | 1155 | unsigned long flags; |
3bfb1d20 HS |
1156 | LIST_HEAD(list); |
1157 | ||
2e4c364e | 1158 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1159 | dwc->descs_allocated); |
1160 | ||
1161 | /* ASSERT: channel is idle */ | |
1162 | BUG_ON(!list_empty(&dwc->active_list)); | |
1163 | BUG_ON(!list_empty(&dwc->queue)); | |
1164 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1165 | ||
69cea5a0 | 1166 | spin_lock_irqsave(&dwc->lock, flags); |
3fe6409c AS |
1167 | |
1168 | /* Clear custom channel configuration */ | |
9217a5bf | 1169 | memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); |
3fe6409c | 1170 | |
423f9cbf | 1171 | clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
3bfb1d20 HS |
1172 | |
1173 | /* Disable interrupts */ | |
1174 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
2895b2ca | 1175 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
3bfb1d20 HS |
1176 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1177 | ||
69cea5a0 | 1178 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1179 | |
99d9bf4e AS |
1180 | /* Disable controller in case it was a last user */ |
1181 | dw->in_use &= ~dwc->mask; | |
1182 | if (!dw->in_use) | |
1183 | dw_dma_off(dw); | |
1184 | ||
2e4c364e | 1185 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1186 | } |
1187 | ||
3a14c66d | 1188 | int dw_dma_probe(struct dw_dma_chip *chip) |
a9ddb575 | 1189 | { |
3a14c66d | 1190 | struct dw_dma_platform_data *pdata; |
3bfb1d20 | 1191 | struct dw_dma *dw; |
30cb2639 | 1192 | bool autocfg = false; |
482c67ea | 1193 | unsigned int dw_params; |
7794e5b9 | 1194 | unsigned int i; |
3bfb1d20 | 1195 | int err; |
3bfb1d20 | 1196 | |
000871ce AS |
1197 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1198 | if (!dw) | |
1199 | return -ENOMEM; | |
1200 | ||
161c3d04 AS |
1201 | dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); |
1202 | if (!dw->pdata) | |
1203 | return -ENOMEM; | |
1204 | ||
000871ce AS |
1205 | dw->regs = chip->regs; |
1206 | chip->dw = dw; | |
1207 | ||
bb32baf7 AS |
1208 | pm_runtime_get_sync(chip->dev); |
1209 | ||
3a14c66d | 1210 | if (!chip->pdata) { |
897e40d3 | 1211 | dw_params = dma_readl(dw, DW_PARAMS); |
30cb2639 | 1212 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
482c67ea | 1213 | |
30cb2639 AS |
1214 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
1215 | if (!autocfg) { | |
1216 | err = -EINVAL; | |
1217 | goto err_pdata; | |
1218 | } | |
123de543 | 1219 | |
161c3d04 AS |
1220 | /* Reassign the platform data pointer */ |
1221 | pdata = dw->pdata; | |
123de543 | 1222 | |
30cb2639 AS |
1223 | /* Get hardware configuration parameters */ |
1224 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; | |
1225 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; | |
1226 | for (i = 0; i < pdata->nr_masters; i++) { | |
1227 | pdata->data_width[i] = | |
2e65060e | 1228 | 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); |
30cb2639 | 1229 | } |
161c3d04 | 1230 | pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); |
30cb2639 | 1231 | |
123de543 AS |
1232 | /* Fill platform data with the default values */ |
1233 | pdata->is_private = true; | |
df5c7386 | 1234 | pdata->is_memcpy = true; |
123de543 AS |
1235 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
1236 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
3a14c66d | 1237 | } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
8be4f523 AS |
1238 | err = -EINVAL; |
1239 | goto err_pdata; | |
161c3d04 | 1240 | } else { |
3a14c66d | 1241 | memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); |
161c3d04 AS |
1242 | |
1243 | /* Reassign the platform data pointer */ | |
1244 | pdata = dw->pdata; | |
8be4f523 | 1245 | } |
123de543 | 1246 | |
30cb2639 | 1247 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
000871ce | 1248 | GFP_KERNEL); |
8be4f523 AS |
1249 | if (!dw->chan) { |
1250 | err = -ENOMEM; | |
1251 | goto err_pdata; | |
1252 | } | |
3bfb1d20 | 1253 | |
11f932ec | 1254 | /* Calculate all channel mask before DMA setup */ |
30cb2639 | 1255 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
11f932ec | 1256 | |
75c61225 | 1257 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1258 | dw_dma_off(dw); |
1259 | ||
199244d6 AS |
1260 | idma32_fifo_partition(dw); |
1261 | ||
08d62f58 | 1262 | /* Device and instance ID for IRQ and DMA pool */ |
199244d6 AS |
1263 | if (pdata->is_idma32) |
1264 | snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id); | |
1265 | else | |
1266 | snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id); | |
08d62f58 | 1267 | |
75c61225 | 1268 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
08d62f58 | 1269 | dw->desc_pool = dmam_pool_create(dw->name, chip->dev, |
f8122a82 AS |
1270 | sizeof(struct dw_desc), 4, 0); |
1271 | if (!dw->desc_pool) { | |
9cade1a4 | 1272 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1273 | err = -ENOMEM; |
1274 | goto err_pdata; | |
f8122a82 AS |
1275 | } |
1276 | ||
3bfb1d20 HS |
1277 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1278 | ||
97977f75 | 1279 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
08d62f58 | 1280 | dw->name, dw); |
97977f75 | 1281 | if (err) |
8be4f523 | 1282 | goto err_pdata; |
97977f75 | 1283 | |
3bfb1d20 | 1284 | INIT_LIST_HEAD(&dw->dma.channels); |
30cb2639 | 1285 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1286 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1287 | ||
1288 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1289 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1290 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1291 | list_add_tail(&dwc->chan.device_node, | |
1292 | &dw->dma.channels); | |
1293 | else | |
1294 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1295 | |
93317e8e VK |
1296 | /* 7 is highest priority & 0 is lowest. */ |
1297 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
30cb2639 | 1298 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1299 | else |
1300 | dwc->priority = i; | |
1301 | ||
3bfb1d20 HS |
1302 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1303 | spin_lock_init(&dwc->lock); | |
1304 | dwc->mask = 1 << i; | |
1305 | ||
1306 | INIT_LIST_HEAD(&dwc->active_list); | |
1307 | INIT_LIST_HEAD(&dwc->queue); | |
3bfb1d20 HS |
1308 | |
1309 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1310 | |
0fdb567f | 1311 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1312 | |
75c61225 | 1313 | /* Hardware configuration */ |
fed2574b | 1314 | if (autocfg) { |
6bea0f6d | 1315 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
897e40d3 | 1316 | void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; |
14bebd01 | 1317 | unsigned int dwc_params = readl(addr); |
fed2574b | 1318 | |
9cade1a4 AS |
1319 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1320 | dwc_params); | |
985a6c7d | 1321 | |
1d566f11 AS |
1322 | /* |
1323 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1324 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1325 | * up to 0x0a for 4095. |
1326 | */ | |
4a63a8b3 | 1327 | dwc->block_size = |
161c3d04 | 1328 | (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; |
fed2574b AS |
1329 | dwc->nollp = |
1330 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1331 | } else { | |
4a63a8b3 | 1332 | dwc->block_size = pdata->block_size; |
bd2c6636 | 1333 | dwc->nollp = !pdata->multi_block[i]; |
fed2574b | 1334 | } |
3bfb1d20 HS |
1335 | } |
1336 | ||
11f932ec | 1337 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1338 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1339 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1340 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1341 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1342 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1343 | ||
df5c7386 | 1344 | /* Set capabilities */ |
3bfb1d20 | 1345 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
95ea759e JI |
1346 | if (pdata->is_private) |
1347 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
df5c7386 AS |
1348 | if (pdata->is_memcpy) |
1349 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1350 | ||
9cade1a4 | 1351 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1352 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1353 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1354 | ||
1355 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
3bfb1d20 | 1356 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
029a40e9 | 1357 | |
a4b0d348 MR |
1358 | dw->dma.device_config = dwc_config; |
1359 | dw->dma.device_pause = dwc_pause; | |
1360 | dw->dma.device_resume = dwc_resume; | |
1361 | dw->dma.device_terminate_all = dwc_terminate_all; | |
3bfb1d20 | 1362 | |
07934481 | 1363 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1364 | dw->dma.device_issue_pending = dwc_issue_pending; |
1365 | ||
029a40e9 AS |
1366 | /* DMA capabilities */ |
1367 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; | |
1368 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; | |
1369 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | | |
1370 | BIT(DMA_MEM_TO_MEM); | |
1371 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1372 | ||
1222934e AS |
1373 | err = dma_async_device_register(&dw->dma); |
1374 | if (err) | |
1375 | goto err_dma_register; | |
1376 | ||
9cade1a4 | 1377 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
30cb2639 | 1378 | pdata->nr_channels); |
3bfb1d20 | 1379 | |
bb32baf7 AS |
1380 | pm_runtime_put_sync_suspend(chip->dev); |
1381 | ||
3bfb1d20 | 1382 | return 0; |
8be4f523 | 1383 | |
1222934e AS |
1384 | err_dma_register: |
1385 | free_irq(chip->irq, dw); | |
8be4f523 | 1386 | err_pdata: |
bb32baf7 | 1387 | pm_runtime_put_sync_suspend(chip->dev); |
8be4f523 | 1388 | return err; |
3bfb1d20 | 1389 | } |
9cade1a4 | 1390 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1391 | |
9cade1a4 | 1392 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1393 | { |
9cade1a4 | 1394 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1395 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 | 1396 | |
bb32baf7 AS |
1397 | pm_runtime_get_sync(chip->dev); |
1398 | ||
3bfb1d20 HS |
1399 | dw_dma_off(dw); |
1400 | dma_async_device_unregister(&dw->dma); | |
1401 | ||
97977f75 | 1402 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1403 | tasklet_kill(&dw->tasklet); |
1404 | ||
1405 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1406 | chan.device_node) { | |
1407 | list_del(&dwc->chan.device_node); | |
1408 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1409 | } | |
1410 | ||
bb32baf7 | 1411 | pm_runtime_put_sync_suspend(chip->dev); |
3bfb1d20 HS |
1412 | return 0; |
1413 | } | |
9cade1a4 | 1414 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1415 | |
2540f74b | 1416 | int dw_dma_disable(struct dw_dma_chip *chip) |
3bfb1d20 | 1417 | { |
9cade1a4 | 1418 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1419 | |
6168d567 | 1420 | dw_dma_off(dw); |
3bfb1d20 HS |
1421 | return 0; |
1422 | } | |
2540f74b | 1423 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
3bfb1d20 | 1424 | |
2540f74b | 1425 | int dw_dma_enable(struct dw_dma_chip *chip) |
3bfb1d20 | 1426 | { |
9cade1a4 | 1427 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1428 | |
199244d6 AS |
1429 | idma32_fifo_partition(dw); |
1430 | ||
7a83c045 | 1431 | dw_dma_on(dw); |
3bfb1d20 | 1432 | return 0; |
3bfb1d20 | 1433 | } |
2540f74b | 1434 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
3bfb1d20 HS |
1435 | |
1436 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1437 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1438 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
da89947b | 1439 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |