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Commit | Line | Data |
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b466a37f | 1 | // SPDX-License-Identifier: GPL-2.0 |
3bfb1d20 | 2 | /* |
b801479b | 3 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
4 | * |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 7 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 | 8 | */ |
b801479b | 9 | |
327e6970 | 10 | #include <linux/bitops.h> |
3bfb1d20 HS |
11 | #include <linux/delay.h> |
12 | #include <linux/dmaengine.h> | |
13 | #include <linux/dma-mapping.h> | |
f8122a82 | 14 | #include <linux/dmapool.h> |
7331205a | 15 | #include <linux/err.h> |
3bfb1d20 HS |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/module.h> | |
3bfb1d20 | 21 | #include <linux/slab.h> |
bb32baf7 | 22 | #include <linux/pm_runtime.h> |
3bfb1d20 | 23 | |
61a76496 | 24 | #include "../dmaengine.h" |
9cade1a4 | 25 | #include "internal.h" |
3bfb1d20 HS |
26 | |
27 | /* | |
28 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
29 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
30 | * of which use ARM any more). See the "Databook" from Synopsys for | |
31 | * information beyond what licensees probably provide. | |
32 | * | |
dd5720b3 AS |
33 | * The driver has been tested with the Atmel AT32AP7000, which does not |
34 | * support descriptor writeback. | |
3bfb1d20 HS |
35 | */ |
36 | ||
029a40e9 AS |
37 | /* The set of bus widths supported by the DMA controller */ |
38 | #define DW_DMA_BUSWIDTHS \ | |
39 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
40 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
41 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
42 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
43 | ||
3bfb1d20 | 44 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 45 | |
41d5e59c DW |
46 | static struct device *chan2dev(struct dma_chan *chan) |
47 | { | |
48 | return &chan->dev->device; | |
49 | } | |
41d5e59c | 50 | |
3bfb1d20 HS |
51 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
52 | { | |
e63a47a3 | 53 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
54 | } |
55 | ||
ab703f81 | 56 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
3bfb1d20 | 57 | { |
ab703f81 CL |
58 | struct dw_desc *desc = txd_to_dw_desc(tx); |
59 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
60 | dma_cookie_t cookie; | |
61 | unsigned long flags; | |
3bfb1d20 | 62 | |
69cea5a0 | 63 | spin_lock_irqsave(&dwc->lock, flags); |
ab703f81 CL |
64 | cookie = dma_cookie_assign(tx); |
65 | ||
66 | /* | |
67 | * REVISIT: We should attempt to chain as many descriptors as | |
68 | * possible, perhaps even appending to those already submitted | |
69 | * for DMA. But this is hard to do in a race-free manner. | |
70 | */ | |
71 | ||
72 | list_add_tail(&desc->desc_node, &dwc->queue); | |
69cea5a0 | 73 | spin_unlock_irqrestore(&dwc->lock, flags); |
ab703f81 CL |
74 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", |
75 | __func__, desc->txd.cookie); | |
3bfb1d20 | 76 | |
ab703f81 CL |
77 | return cookie; |
78 | } | |
3bfb1d20 | 79 | |
ab703f81 CL |
80 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
81 | { | |
82 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
83 | struct dw_desc *desc; | |
84 | dma_addr_t phys; | |
85 | ||
86 | desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); | |
87 | if (!desc) | |
88 | return NULL; | |
89 | ||
90 | dwc->descs_allocated++; | |
91 | INIT_LIST_HEAD(&desc->tx_list); | |
92 | dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); | |
93 | desc->txd.tx_submit = dwc_tx_submit; | |
94 | desc->txd.flags = DMA_CTRL_ACK; | |
95 | desc->txd.phys = phys; | |
96 | return desc; | |
3bfb1d20 HS |
97 | } |
98 | ||
3bfb1d20 HS |
99 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
100 | { | |
ab703f81 CL |
101 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
102 | struct dw_desc *child, *_next; | |
69cea5a0 | 103 | |
ab703f81 CL |
104 | if (unlikely(!desc)) |
105 | return; | |
3bfb1d20 | 106 | |
ab703f81 CL |
107 | list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { |
108 | list_del(&child->desc_node); | |
109 | dma_pool_free(dw->desc_pool, child, child->txd.phys); | |
110 | dwc->descs_allocated--; | |
3bfb1d20 | 111 | } |
ab703f81 CL |
112 | |
113 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); | |
114 | dwc->descs_allocated--; | |
3bfb1d20 HS |
115 | } |
116 | ||
199244d6 AS |
117 | static void dwc_initialize(struct dw_dma_chan *dwc) |
118 | { | |
119 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
120 | ||
121 | if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) | |
122 | return; | |
123 | ||
69da8be9 | 124 | dw->initialize_chan(dwc); |
61e183f8 VK |
125 | |
126 | /* Enable interrupts */ | |
127 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
128 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
129 | ||
423f9cbf | 130 | set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
61e183f8 VK |
131 | } |
132 | ||
3bfb1d20 HS |
133 | /*----------------------------------------------------------------------*/ |
134 | ||
f52b36d2 | 135 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
136 | { |
137 | dev_err(chan2dev(&dwc->chan), | |
138 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
139 | channel_readl(dwc, SAR), | |
140 | channel_readl(dwc, DAR), | |
141 | channel_readl(dwc, LLP), | |
142 | channel_readl(dwc, CTL_HI), | |
143 | channel_readl(dwc, CTL_LO)); | |
144 | } | |
145 | ||
3f936207 AS |
146 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
147 | { | |
148 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
149 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
150 | cpu_relax(); | |
151 | } | |
152 | ||
1d455437 AS |
153 | /*----------------------------------------------------------------------*/ |
154 | ||
fed2574b AS |
155 | /* Perform single block transfer */ |
156 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
157 | struct dw_desc *desc) | |
158 | { | |
159 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
160 | u32 ctllo; | |
161 | ||
1d566f11 AS |
162 | /* |
163 | * Software emulation of LLP mode relies on interrupts to continue | |
164 | * multi block transfer. | |
165 | */ | |
df1f3a23 | 166 | ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
fed2574b | 167 | |
df1f3a23 MR |
168 | channel_writel(dwc, SAR, lli_read(desc, sar)); |
169 | channel_writel(dwc, DAR, lli_read(desc, dar)); | |
fed2574b | 170 | channel_writel(dwc, CTL_LO, ctllo); |
df1f3a23 | 171 | channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
fed2574b | 172 | channel_set_bit(dw, CH_EN, dwc->mask); |
f5c6a7df AS |
173 | |
174 | /* Move pointer to next descriptor */ | |
175 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
176 | } |
177 | ||
3bfb1d20 HS |
178 | /* Called with dwc->lock held and bh disabled */ |
179 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
180 | { | |
181 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
9217a5bf | 182 | u8 lms = DWC_LLP_LMS(dwc->dws.m_master); |
fed2574b | 183 | unsigned long was_soft_llp; |
3bfb1d20 HS |
184 | |
185 | /* ASSERT: channel is idle */ | |
186 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 187 | dev_err(chan2dev(&dwc->chan), |
550da64b JN |
188 | "%s: BUG: Attempted to start non-idle channel\n", |
189 | __func__); | |
1d455437 | 190 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
191 | |
192 | /* The tasklet will hopefully advance the queue... */ | |
193 | return; | |
194 | } | |
195 | ||
fed2574b AS |
196 | if (dwc->nollp) { |
197 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
198 | &dwc->flags); | |
199 | if (was_soft_llp) { | |
200 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 201 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
202 | return; |
203 | } | |
204 | ||
205 | dwc_initialize(dwc); | |
206 | ||
b68fd097 | 207 | first->residue = first->total_len; |
f5c6a7df | 208 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 209 | |
fdf475fa | 210 | /* Submit first block */ |
fed2574b AS |
211 | dwc_do_single_block(dwc, first); |
212 | ||
213 | return; | |
214 | } | |
215 | ||
61e183f8 VK |
216 | dwc_initialize(dwc); |
217 | ||
2a0fae02 MR |
218 | channel_writel(dwc, LLP, first->txd.phys | lms); |
219 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
3bfb1d20 HS |
220 | channel_writel(dwc, CTL_HI, 0); |
221 | channel_set_bit(dw, CH_EN, dwc->mask); | |
222 | } | |
223 | ||
e7637c6c AS |
224 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
225 | { | |
cba15617 AS |
226 | struct dw_desc *desc; |
227 | ||
e7637c6c AS |
228 | if (list_empty(&dwc->queue)) |
229 | return; | |
230 | ||
231 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
232 | desc = dwc_first_active(dwc); |
233 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
234 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
235 | } |
236 | ||
3bfb1d20 HS |
237 | /*----------------------------------------------------------------------*/ |
238 | ||
239 | static void | |
5fedefb8 VK |
240 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
241 | bool callback_required) | |
3bfb1d20 | 242 | { |
3bfb1d20 | 243 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 244 | struct dw_desc *child; |
69cea5a0 | 245 | unsigned long flags; |
577ef925 | 246 | struct dmaengine_desc_callback cb; |
3bfb1d20 | 247 | |
41d5e59c | 248 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 249 | |
69cea5a0 | 250 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 251 | dma_cookie_complete(txd); |
577ef925 DJ |
252 | if (callback_required) |
253 | dmaengine_desc_get_callback(txd, &cb); | |
254 | else | |
255 | memset(&cb, 0, sizeof(cb)); | |
3bfb1d20 | 256 | |
e518076e VK |
257 | /* async_tx_ack */ |
258 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
259 | async_tx_ack(&child->txd); | |
260 | async_tx_ack(&desc->txd); | |
ab703f81 | 261 | dwc_desc_put(dwc, desc); |
69cea5a0 VK |
262 | spin_unlock_irqrestore(&dwc->lock, flags); |
263 | ||
577ef925 | 264 | dmaengine_desc_callback_invoke(&cb, NULL); |
3bfb1d20 HS |
265 | } |
266 | ||
267 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
268 | { | |
269 | struct dw_desc *desc, *_desc; | |
270 | LIST_HEAD(list); | |
69cea5a0 | 271 | unsigned long flags; |
3bfb1d20 | 272 | |
69cea5a0 | 273 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 274 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 275 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
276 | "BUG: XFER bit set, but channel not idle!\n"); |
277 | ||
278 | /* Try to continue after resetting the channel... */ | |
3f936207 | 279 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
280 | } |
281 | ||
282 | /* | |
283 | * Submit queued descriptors ASAP, i.e. before we go through | |
284 | * the completed ones. | |
285 | */ | |
3bfb1d20 | 286 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 287 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 288 | |
69cea5a0 VK |
289 | spin_unlock_irqrestore(&dwc->lock, flags); |
290 | ||
3bfb1d20 | 291 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 292 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
293 | } |
294 | ||
4702d524 AS |
295 | /* Returns how many bytes were already received from source */ |
296 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
297 | { | |
69da8be9 | 298 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
4702d524 AS |
299 | u32 ctlhi = channel_readl(dwc, CTL_HI); |
300 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
301 | ||
69da8be9 | 302 | return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7); |
4702d524 AS |
303 | } |
304 | ||
3bfb1d20 HS |
305 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
306 | { | |
307 | dma_addr_t llp; | |
308 | struct dw_desc *desc, *_desc; | |
309 | struct dw_desc *child; | |
310 | u32 status_xfer; | |
69cea5a0 | 311 | unsigned long flags; |
3bfb1d20 | 312 | |
69cea5a0 | 313 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
314 | llp = channel_readl(dwc, LLP); |
315 | status_xfer = dma_readl(dw, RAW.XFER); | |
316 | ||
317 | if (status_xfer & dwc->mask) { | |
318 | /* Everything we've submitted is done */ | |
319 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
320 | |
321 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
322 | struct list_head *head, *active = dwc->tx_node_active; |
323 | ||
324 | /* | |
325 | * We are inside first active descriptor. | |
326 | * Otherwise something is really wrong. | |
327 | */ | |
328 | desc = dwc_first_active(dwc); | |
329 | ||
330 | head = &desc->tx_list; | |
331 | if (active != head) { | |
b68fd097 AS |
332 | /* Update residue to reflect last sent descriptor */ |
333 | if (active == head->next) | |
334 | desc->residue -= desc->len; | |
335 | else | |
336 | desc->residue -= to_dw_desc(active->prev)->len; | |
4702d524 | 337 | |
fdf475fa | 338 | child = to_dw_desc(active); |
77bcc497 AS |
339 | |
340 | /* Submit next block */ | |
fdf475fa | 341 | dwc_do_single_block(dwc, child); |
77bcc497 | 342 | |
fdf475fa | 343 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
344 | return; |
345 | } | |
fdf475fa | 346 | |
77bcc497 AS |
347 | /* We are done here */ |
348 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
349 | } | |
4702d524 | 350 | |
69cea5a0 VK |
351 | spin_unlock_irqrestore(&dwc->lock, flags); |
352 | ||
3bfb1d20 HS |
353 | dwc_complete_all(dw, dwc); |
354 | return; | |
355 | } | |
356 | ||
69cea5a0 VK |
357 | if (list_empty(&dwc->active_list)) { |
358 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 359 | return; |
69cea5a0 | 360 | } |
087809fc | 361 | |
77bcc497 AS |
362 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
363 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 364 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 365 | return; |
69cea5a0 | 366 | } |
087809fc | 367 | |
5a87f0e6 | 368 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
369 | |
370 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 371 | /* Initial residue value */ |
b68fd097 | 372 | desc->residue = desc->total_len; |
4702d524 | 373 | |
75c61225 | 374 | /* Check first descriptors addr */ |
2a0fae02 | 375 | if (desc->txd.phys == DWC_LLP_LOC(llp)) { |
69cea5a0 | 376 | spin_unlock_irqrestore(&dwc->lock, flags); |
84adccfb | 377 | return; |
69cea5a0 | 378 | } |
84adccfb | 379 | |
75c61225 | 380 | /* Check first descriptors llp */ |
df1f3a23 | 381 | if (lli_read(desc, llp) == llp) { |
3bfb1d20 | 382 | /* This one is currently in progress */ |
b68fd097 | 383 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 384 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 385 | return; |
69cea5a0 | 386 | } |
3bfb1d20 | 387 | |
b68fd097 | 388 | desc->residue -= desc->len; |
4702d524 | 389 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
df1f3a23 | 390 | if (lli_read(child, llp) == llp) { |
3bfb1d20 | 391 | /* Currently in progress */ |
b68fd097 | 392 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 393 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 394 | return; |
69cea5a0 | 395 | } |
b68fd097 | 396 | desc->residue -= child->len; |
4702d524 | 397 | } |
3bfb1d20 HS |
398 | |
399 | /* | |
400 | * No descriptors so far seem to be in progress, i.e. | |
401 | * this one must be done. | |
402 | */ | |
69cea5a0 | 403 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 404 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 405 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
406 | } |
407 | ||
41d5e59c | 408 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
409 | "BUG: All descriptors done, but channel not idle!\n"); |
410 | ||
411 | /* Try to continue after resetting the channel... */ | |
3f936207 | 412 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 413 | |
e7637c6c | 414 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 415 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
416 | } |
417 | ||
df1f3a23 | 418 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
3bfb1d20 | 419 | { |
21d43f49 | 420 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
df1f3a23 MR |
421 | lli_read(desc, sar), |
422 | lli_read(desc, dar), | |
423 | lli_read(desc, llp), | |
424 | lli_read(desc, ctlhi), | |
425 | lli_read(desc, ctllo)); | |
3bfb1d20 HS |
426 | } |
427 | ||
428 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
429 | { | |
430 | struct dw_desc *bad_desc; | |
431 | struct dw_desc *child; | |
69cea5a0 | 432 | unsigned long flags; |
3bfb1d20 HS |
433 | |
434 | dwc_scan_descriptors(dw, dwc); | |
435 | ||
69cea5a0 VK |
436 | spin_lock_irqsave(&dwc->lock, flags); |
437 | ||
3bfb1d20 HS |
438 | /* |
439 | * The descriptor currently at the head of the active list is | |
440 | * borked. Since we don't have any way to report errors, we'll | |
441 | * just have to scream loudly and try to carry on. | |
442 | */ | |
443 | bad_desc = dwc_first_active(dwc); | |
444 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 445 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
446 | |
447 | /* Clear the error flag and try to restart the controller */ | |
448 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
449 | if (!list_empty(&dwc->active_list)) | |
450 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
451 | ||
452 | /* | |
ba84bd71 | 453 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
454 | * when someone submits a bad physical address in a |
455 | * descriptor, we should consider ourselves lucky that the | |
456 | * controller flagged an error instead of scribbling over | |
457 | * random memory locations. | |
458 | */ | |
ba84bd71 AS |
459 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
460 | " cookie: %d\n", bad_desc->txd.cookie); | |
df1f3a23 | 461 | dwc_dump_lli(dwc, bad_desc); |
e0bd0f8c | 462 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
df1f3a23 | 463 | dwc_dump_lli(dwc, child); |
3bfb1d20 | 464 | |
69cea5a0 VK |
465 | spin_unlock_irqrestore(&dwc->lock, flags); |
466 | ||
3bfb1d20 | 467 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 468 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
469 | } |
470 | ||
471 | static void dw_dma_tasklet(unsigned long data) | |
472 | { | |
473 | struct dw_dma *dw = (struct dw_dma *)data; | |
474 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
475 | u32 status_xfer; |
476 | u32 status_err; | |
7794e5b9 | 477 | unsigned int i; |
3bfb1d20 | 478 | |
7fe7b2f4 | 479 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
480 | status_err = dma_readl(dw, RAW.ERROR); |
481 | ||
2e4c364e | 482 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
483 | |
484 | for (i = 0; i < dw->dma.chancnt; i++) { | |
485 | dwc = &dw->chan[i]; | |
d9de4519 | 486 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
14bebd01 | 487 | dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); |
d9de4519 | 488 | else if (status_err & (1 << i)) |
3bfb1d20 | 489 | dwc_handle_error(dw, dwc); |
77bcc497 | 490 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 491 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
492 | } |
493 | ||
ee1cdcda | 494 | /* Re-enable interrupts */ |
3bfb1d20 | 495 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
3bfb1d20 HS |
496 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
497 | } | |
498 | ||
499 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
500 | { | |
501 | struct dw_dma *dw = dev_id; | |
02a21b79 | 502 | u32 status; |
3bfb1d20 | 503 | |
02a21b79 AS |
504 | /* Check if we have any interrupt from the DMAC which is not in use */ |
505 | if (!dw->in_use) | |
506 | return IRQ_NONE; | |
507 | ||
508 | status = dma_readl(dw, STATUS_INT); | |
3783cef8 AS |
509 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
510 | ||
511 | /* Check if we have any interrupt from the DMAC */ | |
02a21b79 | 512 | if (!status) |
3783cef8 | 513 | return IRQ_NONE; |
3bfb1d20 HS |
514 | |
515 | /* | |
516 | * Just disable the interrupts. We'll turn them back on in the | |
517 | * softirq handler. | |
518 | */ | |
519 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 520 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
521 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
522 | ||
523 | status = dma_readl(dw, STATUS_INT); | |
524 | if (status) { | |
525 | dev_err(dw->dma.dev, | |
526 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
527 | status); | |
528 | ||
529 | /* Try to recover */ | |
530 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
2895b2ca | 531 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
3bfb1d20 HS |
532 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
533 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
534 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
535 | } | |
536 | ||
537 | tasklet_schedule(&dw->tasklet); | |
538 | ||
539 | return IRQ_HANDLED; | |
540 | } | |
541 | ||
542 | /*----------------------------------------------------------------------*/ | |
543 | ||
3bfb1d20 HS |
544 | static struct dma_async_tx_descriptor * |
545 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
546 | size_t len, unsigned long flags) | |
547 | { | |
548 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 549 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
550 | struct dw_desc *desc; |
551 | struct dw_desc *first; | |
552 | struct dw_desc *prev; | |
553 | size_t xfer_count; | |
554 | size_t offset; | |
9217a5bf | 555 | u8 m_master = dwc->dws.m_master; |
3bfb1d20 HS |
556 | unsigned int src_width; |
557 | unsigned int dst_width; | |
161c3d04 | 558 | unsigned int data_width = dw->pdata->data_width[m_master]; |
69da8be9 | 559 | u32 ctllo, ctlhi; |
2e65060e | 560 | u8 lms = DWC_LLP_LMS(m_master); |
3bfb1d20 | 561 | |
2f45d613 | 562 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
563 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
564 | &dest, &src, len, flags); | |
3bfb1d20 HS |
565 | |
566 | if (unlikely(!len)) { | |
2e4c364e | 567 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
568 | return NULL; |
569 | } | |
570 | ||
0fdb567f AS |
571 | dwc->direction = DMA_MEM_TO_MEM; |
572 | ||
2e65060e | 573 | src_width = dst_width = __ffs(data_width | src | dest | len); |
3bfb1d20 | 574 | |
934891b0 | 575 | ctllo = dw->prepare_ctllo(dwc) |
3bfb1d20 HS |
576 | | DWC_CTLL_DST_WIDTH(dst_width) |
577 | | DWC_CTLL_SRC_WIDTH(src_width) | |
578 | | DWC_CTLL_DST_INC | |
579 | | DWC_CTLL_SRC_INC | |
580 | | DWC_CTLL_FC_M2M; | |
581 | prev = first = NULL; | |
582 | ||
2d248812 | 583 | for (offset = 0; offset < len; offset += xfer_count) { |
3bfb1d20 HS |
584 | desc = dwc_desc_get(dwc); |
585 | if (!desc) | |
586 | goto err_desc_get; | |
587 | ||
69da8be9 AS |
588 | ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count); |
589 | ||
df1f3a23 MR |
590 | lli_write(desc, sar, src + offset); |
591 | lli_write(desc, dar, dest + offset); | |
592 | lli_write(desc, ctllo, ctllo); | |
69da8be9 | 593 | lli_write(desc, ctlhi, ctlhi); |
2d248812 | 594 | desc->len = xfer_count; |
3bfb1d20 HS |
595 | |
596 | if (!first) { | |
597 | first = desc; | |
598 | } else { | |
2a0fae02 | 599 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 600 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
601 | } |
602 | prev = desc; | |
603 | } | |
604 | ||
3bfb1d20 HS |
605 | if (flags & DMA_PREP_INTERRUPT) |
606 | /* Trigger interrupt after last block */ | |
df1f3a23 | 607 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
608 | |
609 | prev->lli.llp = 0; | |
a3e55799 | 610 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
3bfb1d20 | 611 | first->txd.flags = flags; |
30d38a32 | 612 | first->total_len = len; |
3bfb1d20 HS |
613 | |
614 | return &first->txd; | |
615 | ||
616 | err_desc_get: | |
617 | dwc_desc_put(dwc, first); | |
618 | return NULL; | |
619 | } | |
620 | ||
621 | static struct dma_async_tx_descriptor * | |
622 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 623 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 624 | unsigned long flags, void *context) |
3bfb1d20 HS |
625 | { |
626 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 627 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 628 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
629 | struct dw_desc *prev; |
630 | struct dw_desc *first; | |
69da8be9 | 631 | u32 ctllo, ctlhi; |
9217a5bf | 632 | u8 m_master = dwc->dws.m_master; |
2e65060e | 633 | u8 lms = DWC_LLP_LMS(m_master); |
3bfb1d20 HS |
634 | dma_addr_t reg; |
635 | unsigned int reg_width; | |
636 | unsigned int mem_width; | |
161c3d04 | 637 | unsigned int data_width = dw->pdata->data_width[m_master]; |
3bfb1d20 HS |
638 | unsigned int i; |
639 | struct scatterlist *sg; | |
640 | size_t total_len = 0; | |
641 | ||
2e4c364e | 642 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 643 | |
495aea4b | 644 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
645 | return NULL; |
646 | ||
0fdb567f AS |
647 | dwc->direction = direction; |
648 | ||
3bfb1d20 HS |
649 | prev = first = NULL; |
650 | ||
3bfb1d20 | 651 | switch (direction) { |
db8196df | 652 | case DMA_MEM_TO_DEV: |
39416677 | 653 | reg_width = __ffs(sconfig->dst_addr_width); |
327e6970 | 654 | reg = sconfig->dst_addr; |
934891b0 | 655 | ctllo = dw->prepare_ctllo(dwc) |
3bfb1d20 HS |
656 | | DWC_CTLL_DST_WIDTH(reg_width) |
657 | | DWC_CTLL_DST_FIX | |
934891b0 | 658 | | DWC_CTLL_SRC_INC; |
327e6970 VK |
659 | |
660 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
661 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
662 | ||
3bfb1d20 HS |
663 | for_each_sg(sgl, sg, sg_len, i) { |
664 | struct dw_desc *desc; | |
2d248812 AS |
665 | u32 len, mem; |
666 | size_t dlen; | |
3bfb1d20 | 667 | |
cbb796cc | 668 | mem = sg_dma_address(sg); |
69dc14b5 | 669 | len = sg_dma_len(sg); |
6bc711f6 | 670 | |
2e65060e | 671 | mem_width = __ffs(data_width | mem | len); |
3bfb1d20 | 672 | |
69dc14b5 | 673 | slave_sg_todev_fill_desc: |
3bfb1d20 | 674 | desc = dwc_desc_get(dwc); |
b2607227 | 675 | if (!desc) |
3bfb1d20 | 676 | goto err_desc_get; |
3bfb1d20 | 677 | |
69da8be9 AS |
678 | ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen); |
679 | ||
df1f3a23 MR |
680 | lli_write(desc, sar, mem); |
681 | lli_write(desc, dar, reg); | |
69da8be9 | 682 | lli_write(desc, ctlhi, ctlhi); |
a46a7634 | 683 | lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); |
176dcec5 | 684 | desc->len = dlen; |
3bfb1d20 HS |
685 | |
686 | if (!first) { | |
687 | first = desc; | |
688 | } else { | |
2a0fae02 | 689 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 690 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
691 | } |
692 | prev = desc; | |
a46a7634 JN |
693 | |
694 | mem += dlen; | |
695 | len -= dlen; | |
69dc14b5 VK |
696 | total_len += dlen; |
697 | ||
698 | if (len) | |
699 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
700 | } |
701 | break; | |
db8196df | 702 | case DMA_DEV_TO_MEM: |
39416677 | 703 | reg_width = __ffs(sconfig->src_addr_width); |
327e6970 | 704 | reg = sconfig->src_addr; |
934891b0 | 705 | ctllo = dw->prepare_ctllo(dwc) |
3bfb1d20 HS |
706 | | DWC_CTLL_SRC_WIDTH(reg_width) |
707 | | DWC_CTLL_DST_INC | |
934891b0 | 708 | | DWC_CTLL_SRC_FIX; |
327e6970 VK |
709 | |
710 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
711 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 712 | |
3bfb1d20 HS |
713 | for_each_sg(sgl, sg, sg_len, i) { |
714 | struct dw_desc *desc; | |
2d248812 AS |
715 | u32 len, mem; |
716 | size_t dlen; | |
3bfb1d20 | 717 | |
cbb796cc | 718 | mem = sg_dma_address(sg); |
3bfb1d20 | 719 | len = sg_dma_len(sg); |
6bc711f6 | 720 | |
69dc14b5 VK |
721 | slave_sg_fromdev_fill_desc: |
722 | desc = dwc_desc_get(dwc); | |
b2607227 | 723 | if (!desc) |
69dc14b5 | 724 | goto err_desc_get; |
69dc14b5 | 725 | |
69da8be9 AS |
726 | ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen); |
727 | ||
df1f3a23 MR |
728 | lli_write(desc, sar, reg); |
729 | lli_write(desc, dar, mem); | |
69da8be9 | 730 | lli_write(desc, ctlhi, ctlhi); |
a46a7634 JN |
731 | mem_width = __ffs(data_width | mem | dlen); |
732 | lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); | |
176dcec5 | 733 | desc->len = dlen; |
3bfb1d20 HS |
734 | |
735 | if (!first) { | |
736 | first = desc; | |
737 | } else { | |
2a0fae02 | 738 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 739 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
740 | } |
741 | prev = desc; | |
a46a7634 JN |
742 | |
743 | mem += dlen; | |
744 | len -= dlen; | |
69dc14b5 VK |
745 | total_len += dlen; |
746 | ||
747 | if (len) | |
748 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
749 | } |
750 | break; | |
751 | default: | |
752 | return NULL; | |
753 | } | |
754 | ||
755 | if (flags & DMA_PREP_INTERRUPT) | |
756 | /* Trigger interrupt after last block */ | |
df1f3a23 | 757 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
758 | |
759 | prev->lli.llp = 0; | |
a3e55799 | 760 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
30d38a32 | 761 | first->total_len = total_len; |
3bfb1d20 HS |
762 | |
763 | return &first->txd; | |
764 | ||
765 | err_desc_get: | |
b2607227 JN |
766 | dev_err(chan2dev(chan), |
767 | "not enough descriptors available. Direction %d\n", direction); | |
3bfb1d20 HS |
768 | dwc_desc_put(dwc, first); |
769 | return NULL; | |
770 | } | |
771 | ||
4d130de2 AS |
772 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
773 | { | |
774 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
775 | struct dw_dma_slave *dws = param; | |
776 | ||
3fe6409c | 777 | if (dws->dma_dev != chan->device->dev) |
4d130de2 AS |
778 | return false; |
779 | ||
780 | /* We have to copy data since dws can be temporary storage */ | |
9217a5bf | 781 | memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); |
4d130de2 AS |
782 | |
783 | return true; | |
784 | } | |
785 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
786 | ||
a4b0d348 | 787 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
327e6970 VK |
788 | { |
789 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
199244d6 | 790 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 791 | |
327e6970 VK |
792 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); |
793 | ||
69da8be9 AS |
794 | dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst); |
795 | dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst); | |
327e6970 VK |
796 | |
797 | return 0; | |
798 | } | |
799 | ||
199244d6 | 800 | static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) |
21fe3c52 | 801 | { |
199244d6 | 802 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
a4b0d348 | 803 | unsigned int count = 20; /* timeout iterations */ |
a4b0d348 | 804 | |
69da8be9 AS |
805 | dw->suspend_chan(dwc, drain); |
806 | ||
123b69ab AS |
807 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
808 | udelay(2); | |
21fe3c52 | 809 | |
5e09f98e | 810 | set_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
f4aa3183 | 811 | } |
a4b0d348 | 812 | |
f4aa3183 AS |
813 | static int dwc_pause(struct dma_chan *chan) |
814 | { | |
815 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
816 | unsigned long flags; | |
817 | ||
818 | spin_lock_irqsave(&dwc->lock, flags); | |
199244d6 | 819 | dwc_chan_pause(dwc, false); |
a4b0d348 MR |
820 | spin_unlock_irqrestore(&dwc->lock, flags); |
821 | ||
822 | return 0; | |
21fe3c52 AS |
823 | } |
824 | ||
91f0ff88 | 825 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain) |
21fe3c52 | 826 | { |
91f0ff88 | 827 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
21fe3c52 | 828 | |
91f0ff88 | 829 | dw->resume_chan(dwc, drain); |
21fe3c52 | 830 | |
5e09f98e | 831 | clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
21fe3c52 AS |
832 | } |
833 | ||
a4b0d348 | 834 | static int dwc_resume(struct dma_chan *chan) |
3bfb1d20 HS |
835 | { |
836 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
69cea5a0 | 837 | unsigned long flags; |
3bfb1d20 | 838 | |
a4b0d348 | 839 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 840 | |
5e09f98e | 841 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) |
91f0ff88 | 842 | dwc_chan_resume(dwc, false); |
3bfb1d20 | 843 | |
a4b0d348 | 844 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 845 | |
a4b0d348 MR |
846 | return 0; |
847 | } | |
3bfb1d20 | 848 | |
a4b0d348 MR |
849 | static int dwc_terminate_all(struct dma_chan *chan) |
850 | { | |
851 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
852 | struct dw_dma *dw = to_dw_dma(chan->device); | |
853 | struct dw_desc *desc, *_desc; | |
854 | unsigned long flags; | |
855 | LIST_HEAD(list); | |
3bfb1d20 | 856 | |
a4b0d348 | 857 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b | 858 | |
a4b0d348 | 859 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
fed2574b | 860 | |
199244d6 AS |
861 | dwc_chan_pause(dwc, true); |
862 | ||
a4b0d348 | 863 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 864 | |
91f0ff88 | 865 | dwc_chan_resume(dwc, true); |
a7c57cf7 | 866 | |
a4b0d348 MR |
867 | /* active_list entries will end up before queued entries */ |
868 | list_splice_init(&dwc->queue, &list); | |
869 | list_splice_init(&dwc->active_list, &list); | |
a7c57cf7 | 870 | |
a4b0d348 | 871 | spin_unlock_irqrestore(&dwc->lock, flags); |
a7c57cf7 | 872 | |
a4b0d348 MR |
873 | /* Flush all pending and queued descriptors */ |
874 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
875 | dwc_descriptor_complete(dwc, desc, false); | |
c3635c78 LW |
876 | |
877 | return 0; | |
3bfb1d20 HS |
878 | } |
879 | ||
b68fd097 AS |
880 | static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) |
881 | { | |
882 | struct dw_desc *desc; | |
883 | ||
884 | list_for_each_entry(desc, &dwc->active_list, desc_node) | |
885 | if (desc->txd.cookie == c) | |
886 | return desc; | |
887 | ||
888 | return NULL; | |
889 | } | |
890 | ||
891 | static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) | |
4702d524 | 892 | { |
b68fd097 | 893 | struct dw_desc *desc; |
4702d524 AS |
894 | unsigned long flags; |
895 | u32 residue; | |
896 | ||
897 | spin_lock_irqsave(&dwc->lock, flags); | |
898 | ||
b68fd097 AS |
899 | desc = dwc_find_desc(dwc, cookie); |
900 | if (desc) { | |
901 | if (desc == dwc_first_active(dwc)) { | |
902 | residue = desc->residue; | |
903 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
904 | residue -= dwc_get_sent(dwc); | |
905 | } else { | |
906 | residue = desc->total_len; | |
907 | } | |
908 | } else { | |
909 | residue = 0; | |
910 | } | |
4702d524 AS |
911 | |
912 | spin_unlock_irqrestore(&dwc->lock, flags); | |
913 | return residue; | |
914 | } | |
915 | ||
3bfb1d20 | 916 | static enum dma_status |
07934481 LW |
917 | dwc_tx_status(struct dma_chan *chan, |
918 | dma_cookie_t cookie, | |
919 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
920 | { |
921 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 922 | enum dma_status ret; |
3bfb1d20 | 923 | |
96a2af41 | 924 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 925 | if (ret == DMA_COMPLETE) |
12381dc0 | 926 | return ret; |
3bfb1d20 | 927 | |
12381dc0 | 928 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 929 | |
12381dc0 | 930 | ret = dma_cookie_status(chan, cookie, txstate); |
b68fd097 AS |
931 | if (ret == DMA_COMPLETE) |
932 | return ret; | |
933 | ||
934 | dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); | |
3bfb1d20 | 935 | |
5e09f98e | 936 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 937 | return DMA_PAUSED; |
3bfb1d20 HS |
938 | |
939 | return ret; | |
940 | } | |
941 | ||
942 | static void dwc_issue_pending(struct dma_chan *chan) | |
943 | { | |
944 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 945 | unsigned long flags; |
3bfb1d20 | 946 | |
dd8ecfca AS |
947 | spin_lock_irqsave(&dwc->lock, flags); |
948 | if (list_empty(&dwc->active_list)) | |
949 | dwc_dostart_first_queued(dwc); | |
950 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
951 | } |
952 | ||
99d9bf4e AS |
953 | /*----------------------------------------------------------------------*/ |
954 | ||
69da8be9 | 955 | void do_dw_dma_off(struct dw_dma *dw) |
99d9bf4e | 956 | { |
7794e5b9 | 957 | unsigned int i; |
99d9bf4e AS |
958 | |
959 | dma_writel(dw, CFG, 0); | |
960 | ||
961 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 962 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
99d9bf4e AS |
963 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
964 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
965 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
966 | ||
967 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
968 | cpu_relax(); | |
969 | ||
970 | for (i = 0; i < dw->dma.chancnt; i++) | |
423f9cbf | 971 | clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); |
99d9bf4e AS |
972 | } |
973 | ||
69da8be9 | 974 | void do_dw_dma_on(struct dw_dma *dw) |
99d9bf4e AS |
975 | { |
976 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
977 | } | |
978 | ||
aa1e6f1a | 979 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
980 | { |
981 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
982 | struct dw_dma *dw = to_dw_dma(chan->device); | |
3bfb1d20 | 983 | |
2e4c364e | 984 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 985 | |
3bfb1d20 HS |
986 | /* ASSERT: channel is idle */ |
987 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 988 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
989 | return -EIO; |
990 | } | |
991 | ||
d3ee98cd | 992 | dma_cookie_init(chan); |
3bfb1d20 | 993 | |
3bfb1d20 HS |
994 | /* |
995 | * NOTE: some controllers may have additional features that we | |
996 | * need to initialize here, like "scatter-gather" (which | |
997 | * doesn't mean what you think it means), and status writeback. | |
998 | */ | |
999 | ||
3fe6409c AS |
1000 | /* |
1001 | * We need controller-specific data to set up slave transfers. | |
1002 | */ | |
1003 | if (chan->private && !dw_dma_filter(chan, chan->private)) { | |
1004 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); | |
1005 | return -EINVAL; | |
1006 | } | |
1007 | ||
99d9bf4e AS |
1008 | /* Enable controller here if needed */ |
1009 | if (!dw->in_use) | |
69da8be9 | 1010 | do_dw_dma_on(dw); |
99d9bf4e AS |
1011 | dw->in_use |= dwc->mask; |
1012 | ||
ab703f81 | 1013 | return 0; |
3bfb1d20 HS |
1014 | } |
1015 | ||
1016 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1017 | { | |
1018 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1019 | struct dw_dma *dw = to_dw_dma(chan->device); | |
69cea5a0 | 1020 | unsigned long flags; |
3bfb1d20 | 1021 | |
2e4c364e | 1022 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1023 | dwc->descs_allocated); |
1024 | ||
1025 | /* ASSERT: channel is idle */ | |
1026 | BUG_ON(!list_empty(&dwc->active_list)); | |
1027 | BUG_ON(!list_empty(&dwc->queue)); | |
1028 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1029 | ||
69cea5a0 | 1030 | spin_lock_irqsave(&dwc->lock, flags); |
3fe6409c AS |
1031 | |
1032 | /* Clear custom channel configuration */ | |
9217a5bf | 1033 | memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); |
3fe6409c | 1034 | |
423f9cbf | 1035 | clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
3bfb1d20 HS |
1036 | |
1037 | /* Disable interrupts */ | |
1038 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
2895b2ca | 1039 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
3bfb1d20 HS |
1040 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1041 | ||
69cea5a0 | 1042 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1043 | |
99d9bf4e AS |
1044 | /* Disable controller in case it was a last user */ |
1045 | dw->in_use &= ~dwc->mask; | |
1046 | if (!dw->in_use) | |
69da8be9 | 1047 | do_dw_dma_off(dw); |
99d9bf4e | 1048 | |
2e4c364e | 1049 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1050 | } |
1051 | ||
69da8be9 | 1052 | int do_dma_probe(struct dw_dma_chip *chip) |
a9ddb575 | 1053 | { |
69da8be9 | 1054 | struct dw_dma *dw = chip->dw; |
3a14c66d | 1055 | struct dw_dma_platform_data *pdata; |
30cb2639 | 1056 | bool autocfg = false; |
482c67ea | 1057 | unsigned int dw_params; |
7794e5b9 | 1058 | unsigned int i; |
3bfb1d20 | 1059 | int err; |
3bfb1d20 | 1060 | |
161c3d04 AS |
1061 | dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); |
1062 | if (!dw->pdata) | |
1063 | return -ENOMEM; | |
1064 | ||
000871ce | 1065 | dw->regs = chip->regs; |
000871ce | 1066 | |
bb32baf7 AS |
1067 | pm_runtime_get_sync(chip->dev); |
1068 | ||
3a14c66d | 1069 | if (!chip->pdata) { |
897e40d3 | 1070 | dw_params = dma_readl(dw, DW_PARAMS); |
30cb2639 | 1071 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
482c67ea | 1072 | |
30cb2639 AS |
1073 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
1074 | if (!autocfg) { | |
1075 | err = -EINVAL; | |
1076 | goto err_pdata; | |
1077 | } | |
123de543 | 1078 | |
161c3d04 AS |
1079 | /* Reassign the platform data pointer */ |
1080 | pdata = dw->pdata; | |
123de543 | 1081 | |
30cb2639 AS |
1082 | /* Get hardware configuration parameters */ |
1083 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; | |
1084 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; | |
1085 | for (i = 0; i < pdata->nr_masters; i++) { | |
1086 | pdata->data_width[i] = | |
2e65060e | 1087 | 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); |
30cb2639 | 1088 | } |
161c3d04 | 1089 | pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); |
30cb2639 | 1090 | |
123de543 | 1091 | /* Fill platform data with the default values */ |
123de543 AS |
1092 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
1093 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
3a14c66d | 1094 | } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
8be4f523 AS |
1095 | err = -EINVAL; |
1096 | goto err_pdata; | |
161c3d04 | 1097 | } else { |
3a14c66d | 1098 | memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); |
161c3d04 AS |
1099 | |
1100 | /* Reassign the platform data pointer */ | |
1101 | pdata = dw->pdata; | |
8be4f523 | 1102 | } |
123de543 | 1103 | |
30cb2639 | 1104 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
000871ce | 1105 | GFP_KERNEL); |
8be4f523 AS |
1106 | if (!dw->chan) { |
1107 | err = -ENOMEM; | |
1108 | goto err_pdata; | |
1109 | } | |
3bfb1d20 | 1110 | |
11f932ec | 1111 | /* Calculate all channel mask before DMA setup */ |
30cb2639 | 1112 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
11f932ec | 1113 | |
75c61225 | 1114 | /* Force dma off, just in case */ |
69da8be9 | 1115 | dw->disable(dw); |
199244d6 | 1116 | |
08d62f58 | 1117 | /* Device and instance ID for IRQ and DMA pool */ |
69da8be9 | 1118 | dw->set_device_name(dw, chip->id); |
08d62f58 | 1119 | |
75c61225 | 1120 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
08d62f58 | 1121 | dw->desc_pool = dmam_pool_create(dw->name, chip->dev, |
f8122a82 AS |
1122 | sizeof(struct dw_desc), 4, 0); |
1123 | if (!dw->desc_pool) { | |
9cade1a4 | 1124 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1125 | err = -ENOMEM; |
1126 | goto err_pdata; | |
f8122a82 AS |
1127 | } |
1128 | ||
3bfb1d20 HS |
1129 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1130 | ||
97977f75 | 1131 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
08d62f58 | 1132 | dw->name, dw); |
97977f75 | 1133 | if (err) |
8be4f523 | 1134 | goto err_pdata; |
97977f75 | 1135 | |
3bfb1d20 | 1136 | INIT_LIST_HEAD(&dw->dma.channels); |
30cb2639 | 1137 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1138 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1139 | ||
1140 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1141 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1142 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1143 | list_add_tail(&dwc->chan.device_node, | |
1144 | &dw->dma.channels); | |
1145 | else | |
1146 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1147 | |
93317e8e VK |
1148 | /* 7 is highest priority & 0 is lowest. */ |
1149 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
30cb2639 | 1150 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1151 | else |
1152 | dwc->priority = i; | |
1153 | ||
3bfb1d20 HS |
1154 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1155 | spin_lock_init(&dwc->lock); | |
1156 | dwc->mask = 1 << i; | |
1157 | ||
1158 | INIT_LIST_HEAD(&dwc->active_list); | |
1159 | INIT_LIST_HEAD(&dwc->queue); | |
3bfb1d20 HS |
1160 | |
1161 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1162 | |
0fdb567f | 1163 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1164 | |
75c61225 | 1165 | /* Hardware configuration */ |
fed2574b | 1166 | if (autocfg) { |
6bea0f6d | 1167 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
897e40d3 | 1168 | void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; |
14bebd01 | 1169 | unsigned int dwc_params = readl(addr); |
fed2574b | 1170 | |
9cade1a4 AS |
1171 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1172 | dwc_params); | |
985a6c7d | 1173 | |
1d566f11 AS |
1174 | /* |
1175 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1176 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1177 | * up to 0x0a for 4095. |
1178 | */ | |
4a63a8b3 | 1179 | dwc->block_size = |
161c3d04 | 1180 | (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; |
fed2574b AS |
1181 | dwc->nollp = |
1182 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1183 | } else { | |
4a63a8b3 | 1184 | dwc->block_size = pdata->block_size; |
bd2c6636 | 1185 | dwc->nollp = !pdata->multi_block[i]; |
fed2574b | 1186 | } |
3bfb1d20 HS |
1187 | } |
1188 | ||
11f932ec | 1189 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1190 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1191 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1192 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1193 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1194 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1195 | ||
df5c7386 | 1196 | /* Set capabilities */ |
3bfb1d20 | 1197 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
d7dba6be | 1198 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); |
07816577 | 1199 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
df5c7386 | 1200 | |
9cade1a4 | 1201 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1202 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1203 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1204 | ||
1205 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
3bfb1d20 | 1206 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
029a40e9 | 1207 | |
a4b0d348 MR |
1208 | dw->dma.device_config = dwc_config; |
1209 | dw->dma.device_pause = dwc_pause; | |
1210 | dw->dma.device_resume = dwc_resume; | |
1211 | dw->dma.device_terminate_all = dwc_terminate_all; | |
3bfb1d20 | 1212 | |
07934481 | 1213 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1214 | dw->dma.device_issue_pending = dwc_issue_pending; |
1215 | ||
029a40e9 AS |
1216 | /* DMA capabilities */ |
1217 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; | |
1218 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; | |
1219 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | | |
1220 | BIT(DMA_MEM_TO_MEM); | |
1221 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1222 | ||
1222934e AS |
1223 | err = dma_async_device_register(&dw->dma); |
1224 | if (err) | |
1225 | goto err_dma_register; | |
1226 | ||
9cade1a4 | 1227 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
30cb2639 | 1228 | pdata->nr_channels); |
3bfb1d20 | 1229 | |
bb32baf7 AS |
1230 | pm_runtime_put_sync_suspend(chip->dev); |
1231 | ||
3bfb1d20 | 1232 | return 0; |
8be4f523 | 1233 | |
1222934e AS |
1234 | err_dma_register: |
1235 | free_irq(chip->irq, dw); | |
8be4f523 | 1236 | err_pdata: |
bb32baf7 | 1237 | pm_runtime_put_sync_suspend(chip->dev); |
8be4f523 | 1238 | return err; |
3bfb1d20 HS |
1239 | } |
1240 | ||
69da8be9 | 1241 | int do_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1242 | { |
9cade1a4 | 1243 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1244 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 | 1245 | |
bb32baf7 AS |
1246 | pm_runtime_get_sync(chip->dev); |
1247 | ||
69da8be9 | 1248 | do_dw_dma_off(dw); |
3bfb1d20 HS |
1249 | dma_async_device_unregister(&dw->dma); |
1250 | ||
97977f75 | 1251 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1252 | tasklet_kill(&dw->tasklet); |
1253 | ||
1254 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1255 | chan.device_node) { | |
1256 | list_del(&dwc->chan.device_node); | |
1257 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1258 | } | |
1259 | ||
bb32baf7 | 1260 | pm_runtime_put_sync_suspend(chip->dev); |
3bfb1d20 HS |
1261 | return 0; |
1262 | } | |
1263 | ||
69da8be9 | 1264 | int do_dw_dma_disable(struct dw_dma_chip *chip) |
3bfb1d20 | 1265 | { |
9cade1a4 | 1266 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1267 | |
69da8be9 | 1268 | dw->disable(dw); |
3bfb1d20 HS |
1269 | return 0; |
1270 | } | |
69da8be9 | 1271 | EXPORT_SYMBOL_GPL(do_dw_dma_disable); |
3bfb1d20 | 1272 | |
69da8be9 | 1273 | int do_dw_dma_enable(struct dw_dma_chip *chip) |
3bfb1d20 | 1274 | { |
9cade1a4 | 1275 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1276 | |
69da8be9 | 1277 | dw->enable(dw); |
3bfb1d20 | 1278 | return 0; |
3bfb1d20 | 1279 | } |
69da8be9 | 1280 | EXPORT_SYMBOL_GPL(do_dw_dma_enable); |
3bfb1d20 HS |
1281 | |
1282 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1283 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1284 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
da89947b | 1285 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |