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Commit | Line | Data |
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3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/delay.h> |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/module.h> | |
3bfb1d20 | 24 | #include <linux/slab.h> |
bb32baf7 | 25 | #include <linux/pm_runtime.h> |
3bfb1d20 | 26 | |
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
327e6970 | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 45 | DW_DMA_MSIZE_16; \ |
495aea4b | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 47 | DW_DMA_MSIZE_16; \ |
bb3450ad MR |
48 | u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ |
49 | _dwc->p_master : _dwc->m_master; \ | |
50 | u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ | |
51 | _dwc->p_master : _dwc->m_master; \ | |
f301c062 | 52 | \ |
327e6970 VK |
53 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
54 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
55 | | DWC_CTLL_LLP_D_EN \ |
56 | | DWC_CTLL_LLP_S_EN \ | |
bb3450ad MR |
57 | | DWC_CTLL_DMS(_dms) \ |
58 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 59 | }) |
3bfb1d20 | 60 | |
3bfb1d20 HS |
61 | /* |
62 | * Number of descriptors to allocate for each channel. This should be | |
63 | * made configurable somehow; preferably, the clients (at least the | |
64 | * ones using slave transfers) should be able to give us a hint. | |
65 | */ | |
66 | #define NR_DESCS_PER_CHANNEL 64 | |
67 | ||
029a40e9 AS |
68 | /* The set of bus widths supported by the DMA controller */ |
69 | #define DW_DMA_BUSWIDTHS \ | |
70 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
71 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
72 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
73 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
74 | ||
3bfb1d20 | 75 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 76 | |
41d5e59c DW |
77 | static struct device *chan2dev(struct dma_chan *chan) |
78 | { | |
79 | return &chan->dev->device; | |
80 | } | |
41d5e59c | 81 | |
3bfb1d20 HS |
82 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
83 | { | |
e63a47a3 | 84 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
85 | } |
86 | ||
3bfb1d20 HS |
87 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
88 | { | |
89 | struct dw_desc *desc, *_desc; | |
90 | struct dw_desc *ret = NULL; | |
91 | unsigned int i = 0; | |
69cea5a0 | 92 | unsigned long flags; |
3bfb1d20 | 93 | |
69cea5a0 | 94 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 95 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 96 | i++; |
3bfb1d20 HS |
97 | if (async_tx_test_ack(&desc->txd)) { |
98 | list_del(&desc->desc_node); | |
99 | ret = desc; | |
100 | break; | |
101 | } | |
41d5e59c | 102 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 103 | } |
69cea5a0 | 104 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 105 | |
41d5e59c | 106 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
107 | |
108 | return ret; | |
109 | } | |
110 | ||
3bfb1d20 HS |
111 | /* |
112 | * Move a descriptor, including any children, to the free list. | |
113 | * `desc' must not be on any lists. | |
114 | */ | |
115 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
116 | { | |
69cea5a0 VK |
117 | unsigned long flags; |
118 | ||
3bfb1d20 HS |
119 | if (desc) { |
120 | struct dw_desc *child; | |
121 | ||
69cea5a0 | 122 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 123 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 124 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
125 | "moving child desc %p to freelist\n", |
126 | child); | |
e0bd0f8c | 127 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 128 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 129 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 130 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
131 | } |
132 | } | |
133 | ||
61e183f8 VK |
134 | static void dwc_initialize(struct dw_dma_chan *dwc) |
135 | { | |
136 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
61e183f8 VK |
137 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
138 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
139 | ||
140 | if (dwc->initialized == true) | |
141 | return; | |
142 | ||
3fe6409c AS |
143 | cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); |
144 | cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); | |
61e183f8 VK |
145 | |
146 | channel_writel(dwc, CFG_LO, cfglo); | |
147 | channel_writel(dwc, CFG_HI, cfghi); | |
148 | ||
149 | /* Enable interrupts */ | |
150 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
151 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
152 | ||
153 | dwc->initialized = true; | |
154 | } | |
155 | ||
3bfb1d20 HS |
156 | /*----------------------------------------------------------------------*/ |
157 | ||
39416677 | 158 | static inline unsigned int dwc_fast_ffs(unsigned long long v) |
4c2d56c5 AS |
159 | { |
160 | /* | |
161 | * We can be a lot more clever here, but this should take care | |
162 | * of the most common optimization. | |
163 | */ | |
164 | if (!(v & 7)) | |
165 | return 3; | |
166 | else if (!(v & 3)) | |
167 | return 2; | |
168 | else if (!(v & 1)) | |
169 | return 1; | |
170 | return 0; | |
171 | } | |
172 | ||
f52b36d2 | 173 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
174 | { |
175 | dev_err(chan2dev(&dwc->chan), | |
176 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
177 | channel_readl(dwc, SAR), | |
178 | channel_readl(dwc, DAR), | |
179 | channel_readl(dwc, LLP), | |
180 | channel_readl(dwc, CTL_HI), | |
181 | channel_readl(dwc, CTL_LO)); | |
182 | } | |
183 | ||
3f936207 AS |
184 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
185 | { | |
186 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
187 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
188 | cpu_relax(); | |
189 | } | |
190 | ||
1d455437 AS |
191 | /*----------------------------------------------------------------------*/ |
192 | ||
fed2574b AS |
193 | /* Perform single block transfer */ |
194 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
195 | struct dw_desc *desc) | |
196 | { | |
197 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
198 | u32 ctllo; | |
199 | ||
1d566f11 AS |
200 | /* |
201 | * Software emulation of LLP mode relies on interrupts to continue | |
202 | * multi block transfer. | |
203 | */ | |
df1f3a23 | 204 | ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
fed2574b | 205 | |
df1f3a23 MR |
206 | channel_writel(dwc, SAR, lli_read(desc, sar)); |
207 | channel_writel(dwc, DAR, lli_read(desc, dar)); | |
fed2574b | 208 | channel_writel(dwc, CTL_LO, ctllo); |
df1f3a23 | 209 | channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
fed2574b | 210 | channel_set_bit(dw, CH_EN, dwc->mask); |
f5c6a7df AS |
211 | |
212 | /* Move pointer to next descriptor */ | |
213 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
214 | } |
215 | ||
3bfb1d20 HS |
216 | /* Called with dwc->lock held and bh disabled */ |
217 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
218 | { | |
219 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 220 | unsigned long was_soft_llp; |
3bfb1d20 HS |
221 | |
222 | /* ASSERT: channel is idle */ | |
223 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 224 | dev_err(chan2dev(&dwc->chan), |
550da64b JN |
225 | "%s: BUG: Attempted to start non-idle channel\n", |
226 | __func__); | |
1d455437 | 227 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
228 | |
229 | /* The tasklet will hopefully advance the queue... */ | |
230 | return; | |
231 | } | |
232 | ||
fed2574b AS |
233 | if (dwc->nollp) { |
234 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
235 | &dwc->flags); | |
236 | if (was_soft_llp) { | |
237 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 238 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
239 | return; |
240 | } | |
241 | ||
242 | dwc_initialize(dwc); | |
243 | ||
4702d524 | 244 | dwc->residue = first->total_len; |
f5c6a7df | 245 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 246 | |
fdf475fa | 247 | /* Submit first block */ |
fed2574b AS |
248 | dwc_do_single_block(dwc, first); |
249 | ||
250 | return; | |
251 | } | |
252 | ||
61e183f8 VK |
253 | dwc_initialize(dwc); |
254 | ||
3bfb1d20 HS |
255 | channel_writel(dwc, LLP, first->txd.phys); |
256 | channel_writel(dwc, CTL_LO, | |
257 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
258 | channel_writel(dwc, CTL_HI, 0); | |
259 | channel_set_bit(dw, CH_EN, dwc->mask); | |
260 | } | |
261 | ||
e7637c6c AS |
262 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
263 | { | |
cba15617 AS |
264 | struct dw_desc *desc; |
265 | ||
e7637c6c AS |
266 | if (list_empty(&dwc->queue)) |
267 | return; | |
268 | ||
269 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
270 | desc = dwc_first_active(dwc); |
271 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
272 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
273 | } |
274 | ||
3bfb1d20 HS |
275 | /*----------------------------------------------------------------------*/ |
276 | ||
277 | static void | |
5fedefb8 VK |
278 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
279 | bool callback_required) | |
3bfb1d20 | 280 | { |
5fedefb8 VK |
281 | dma_async_tx_callback callback = NULL; |
282 | void *param = NULL; | |
3bfb1d20 | 283 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 284 | struct dw_desc *child; |
69cea5a0 | 285 | unsigned long flags; |
3bfb1d20 | 286 | |
41d5e59c | 287 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 288 | |
69cea5a0 | 289 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 290 | dma_cookie_complete(txd); |
5fedefb8 VK |
291 | if (callback_required) { |
292 | callback = txd->callback; | |
293 | param = txd->callback_param; | |
294 | } | |
3bfb1d20 | 295 | |
e518076e VK |
296 | /* async_tx_ack */ |
297 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
298 | async_tx_ack(&child->txd); | |
299 | async_tx_ack(&desc->txd); | |
300 | ||
e0bd0f8c | 301 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
302 | list_move(&desc->desc_node, &dwc->free_list); |
303 | ||
d38a8c62 | 304 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
305 | spin_unlock_irqrestore(&dwc->lock, flags); |
306 | ||
21e93c1e | 307 | if (callback) |
3bfb1d20 HS |
308 | callback(param); |
309 | } | |
310 | ||
311 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
312 | { | |
313 | struct dw_desc *desc, *_desc; | |
314 | LIST_HEAD(list); | |
69cea5a0 | 315 | unsigned long flags; |
3bfb1d20 | 316 | |
69cea5a0 | 317 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 318 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 319 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
320 | "BUG: XFER bit set, but channel not idle!\n"); |
321 | ||
322 | /* Try to continue after resetting the channel... */ | |
3f936207 | 323 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
324 | } |
325 | ||
326 | /* | |
327 | * Submit queued descriptors ASAP, i.e. before we go through | |
328 | * the completed ones. | |
329 | */ | |
3bfb1d20 | 330 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 331 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 332 | |
69cea5a0 VK |
333 | spin_unlock_irqrestore(&dwc->lock, flags); |
334 | ||
3bfb1d20 | 335 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 336 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
337 | } |
338 | ||
4702d524 AS |
339 | /* Returns how many bytes were already received from source */ |
340 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
341 | { | |
342 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
343 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
344 | ||
345 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
346 | } | |
347 | ||
3bfb1d20 HS |
348 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
349 | { | |
350 | dma_addr_t llp; | |
351 | struct dw_desc *desc, *_desc; | |
352 | struct dw_desc *child; | |
353 | u32 status_xfer; | |
69cea5a0 | 354 | unsigned long flags; |
3bfb1d20 | 355 | |
69cea5a0 | 356 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
357 | llp = channel_readl(dwc, LLP); |
358 | status_xfer = dma_readl(dw, RAW.XFER); | |
359 | ||
360 | if (status_xfer & dwc->mask) { | |
361 | /* Everything we've submitted is done */ | |
362 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
363 | |
364 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
365 | struct list_head *head, *active = dwc->tx_node_active; |
366 | ||
367 | /* | |
368 | * We are inside first active descriptor. | |
369 | * Otherwise something is really wrong. | |
370 | */ | |
371 | desc = dwc_first_active(dwc); | |
372 | ||
373 | head = &desc->tx_list; | |
374 | if (active != head) { | |
4702d524 AS |
375 | /* Update desc to reflect last sent one */ |
376 | if (active != head->next) | |
377 | desc = to_dw_desc(active->prev); | |
378 | ||
379 | dwc->residue -= desc->len; | |
380 | ||
fdf475fa | 381 | child = to_dw_desc(active); |
77bcc497 AS |
382 | |
383 | /* Submit next block */ | |
fdf475fa | 384 | dwc_do_single_block(dwc, child); |
77bcc497 | 385 | |
fdf475fa | 386 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
387 | return; |
388 | } | |
fdf475fa | 389 | |
77bcc497 AS |
390 | /* We are done here */ |
391 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
392 | } | |
4702d524 AS |
393 | |
394 | dwc->residue = 0; | |
395 | ||
69cea5a0 VK |
396 | spin_unlock_irqrestore(&dwc->lock, flags); |
397 | ||
3bfb1d20 HS |
398 | dwc_complete_all(dw, dwc); |
399 | return; | |
400 | } | |
401 | ||
69cea5a0 | 402 | if (list_empty(&dwc->active_list)) { |
4702d524 | 403 | dwc->residue = 0; |
69cea5a0 | 404 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 405 | return; |
69cea5a0 | 406 | } |
087809fc | 407 | |
77bcc497 AS |
408 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
409 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 410 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 411 | return; |
69cea5a0 | 412 | } |
087809fc | 413 | |
5a87f0e6 | 414 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
415 | |
416 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 417 | /* Initial residue value */ |
4702d524 AS |
418 | dwc->residue = desc->total_len; |
419 | ||
75c61225 | 420 | /* Check first descriptors addr */ |
69cea5a0 VK |
421 | if (desc->txd.phys == llp) { |
422 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 423 | return; |
69cea5a0 | 424 | } |
84adccfb | 425 | |
75c61225 | 426 | /* Check first descriptors llp */ |
df1f3a23 | 427 | if (lli_read(desc, llp) == llp) { |
3bfb1d20 | 428 | /* This one is currently in progress */ |
4702d524 | 429 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 430 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 431 | return; |
69cea5a0 | 432 | } |
3bfb1d20 | 433 | |
4702d524 AS |
434 | dwc->residue -= desc->len; |
435 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
df1f3a23 | 436 | if (lli_read(child, llp) == llp) { |
3bfb1d20 | 437 | /* Currently in progress */ |
4702d524 | 438 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 439 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 440 | return; |
69cea5a0 | 441 | } |
4702d524 AS |
442 | dwc->residue -= child->len; |
443 | } | |
3bfb1d20 HS |
444 | |
445 | /* | |
446 | * No descriptors so far seem to be in progress, i.e. | |
447 | * this one must be done. | |
448 | */ | |
69cea5a0 | 449 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 450 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 451 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
452 | } |
453 | ||
41d5e59c | 454 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
455 | "BUG: All descriptors done, but channel not idle!\n"); |
456 | ||
457 | /* Try to continue after resetting the channel... */ | |
3f936207 | 458 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 459 | |
e7637c6c | 460 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 461 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
462 | } |
463 | ||
df1f3a23 | 464 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
3bfb1d20 | 465 | { |
21d43f49 | 466 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
df1f3a23 MR |
467 | lli_read(desc, sar), |
468 | lli_read(desc, dar), | |
469 | lli_read(desc, llp), | |
470 | lli_read(desc, ctlhi), | |
471 | lli_read(desc, ctllo)); | |
3bfb1d20 HS |
472 | } |
473 | ||
474 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
475 | { | |
476 | struct dw_desc *bad_desc; | |
477 | struct dw_desc *child; | |
69cea5a0 | 478 | unsigned long flags; |
3bfb1d20 HS |
479 | |
480 | dwc_scan_descriptors(dw, dwc); | |
481 | ||
69cea5a0 VK |
482 | spin_lock_irqsave(&dwc->lock, flags); |
483 | ||
3bfb1d20 HS |
484 | /* |
485 | * The descriptor currently at the head of the active list is | |
486 | * borked. Since we don't have any way to report errors, we'll | |
487 | * just have to scream loudly and try to carry on. | |
488 | */ | |
489 | bad_desc = dwc_first_active(dwc); | |
490 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 491 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
492 | |
493 | /* Clear the error flag and try to restart the controller */ | |
494 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
495 | if (!list_empty(&dwc->active_list)) | |
496 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
497 | ||
498 | /* | |
ba84bd71 | 499 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
500 | * when someone submits a bad physical address in a |
501 | * descriptor, we should consider ourselves lucky that the | |
502 | * controller flagged an error instead of scribbling over | |
503 | * random memory locations. | |
504 | */ | |
ba84bd71 AS |
505 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
506 | " cookie: %d\n", bad_desc->txd.cookie); | |
df1f3a23 | 507 | dwc_dump_lli(dwc, bad_desc); |
e0bd0f8c | 508 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
df1f3a23 | 509 | dwc_dump_lli(dwc, child); |
3bfb1d20 | 510 | |
69cea5a0 VK |
511 | spin_unlock_irqrestore(&dwc->lock, flags); |
512 | ||
3bfb1d20 | 513 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 514 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
515 | } |
516 | ||
d9de4519 HCE |
517 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
518 | ||
8004cbb4 | 519 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
520 | { |
521 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
522 | return channel_readl(dwc, SAR); | |
523 | } | |
524 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
525 | ||
8004cbb4 | 526 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
527 | { |
528 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
529 | return channel_readl(dwc, DAR); | |
530 | } | |
531 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
532 | ||
75c61225 | 533 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 534 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
2895b2ca | 535 | u32 status_block, u32 status_err, u32 status_xfer) |
d9de4519 | 536 | { |
69cea5a0 VK |
537 | unsigned long flags; |
538 | ||
2895b2ca | 539 | if (status_block & dwc->mask) { |
d9de4519 HCE |
540 | void (*callback)(void *param); |
541 | void *callback_param; | |
542 | ||
543 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
544 | channel_readl(dwc, LLP)); | |
2895b2ca | 545 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
546 | |
547 | callback = dwc->cdesc->period_callback; | |
548 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
549 | |
550 | if (callback) | |
d9de4519 | 551 | callback(callback_param); |
d9de4519 HCE |
552 | } |
553 | ||
554 | /* | |
555 | * Error and transfer complete are highly unlikely, and will most | |
556 | * likely be due to a configuration error by the user. | |
557 | */ | |
558 | if (unlikely(status_err & dwc->mask) || | |
559 | unlikely(status_xfer & dwc->mask)) { | |
560 | int i; | |
561 | ||
fc61f6b4 AS |
562 | dev_err(chan2dev(&dwc->chan), |
563 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
564 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
565 | |
566 | spin_lock_irqsave(&dwc->lock, flags); | |
567 | ||
1d455437 | 568 | dwc_dump_chan_regs(dwc); |
d9de4519 | 569 | |
3f936207 | 570 | dwc_chan_disable(dw, dwc); |
d9de4519 | 571 | |
75c61225 | 572 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
573 | channel_writel(dwc, LLP, 0); |
574 | channel_writel(dwc, CTL_LO, 0); | |
575 | channel_writel(dwc, CTL_HI, 0); | |
576 | ||
2895b2ca | 577 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
578 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
579 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
580 | ||
581 | for (i = 0; i < dwc->cdesc->periods; i++) | |
df1f3a23 | 582 | dwc_dump_lli(dwc, dwc->cdesc->desc[i]); |
69cea5a0 VK |
583 | |
584 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 | 585 | } |
ee1cdcda AS |
586 | |
587 | /* Re-enable interrupts */ | |
588 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
d9de4519 HCE |
589 | } |
590 | ||
591 | /* ------------------------------------------------------------------------- */ | |
592 | ||
3bfb1d20 HS |
593 | static void dw_dma_tasklet(unsigned long data) |
594 | { | |
595 | struct dw_dma *dw = (struct dw_dma *)data; | |
596 | struct dw_dma_chan *dwc; | |
2895b2ca | 597 | u32 status_block; |
3bfb1d20 HS |
598 | u32 status_xfer; |
599 | u32 status_err; | |
600 | int i; | |
601 | ||
2895b2ca | 602 | status_block = dma_readl(dw, RAW.BLOCK); |
7fe7b2f4 | 603 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
604 | status_err = dma_readl(dw, RAW.ERROR); |
605 | ||
2e4c364e | 606 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
607 | |
608 | for (i = 0; i < dw->dma.chancnt; i++) { | |
609 | dwc = &dw->chan[i]; | |
d9de4519 | 610 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
2895b2ca MR |
611 | dwc_handle_cyclic(dw, dwc, status_block, status_err, |
612 | status_xfer); | |
d9de4519 | 613 | else if (status_err & (1 << i)) |
3bfb1d20 | 614 | dwc_handle_error(dw, dwc); |
77bcc497 | 615 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 616 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
617 | } |
618 | ||
ee1cdcda | 619 | /* Re-enable interrupts */ |
3bfb1d20 | 620 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
3bfb1d20 HS |
621 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
622 | } | |
623 | ||
624 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
625 | { | |
626 | struct dw_dma *dw = dev_id; | |
02a21b79 | 627 | u32 status; |
3bfb1d20 | 628 | |
02a21b79 AS |
629 | /* Check if we have any interrupt from the DMAC which is not in use */ |
630 | if (!dw->in_use) | |
631 | return IRQ_NONE; | |
632 | ||
633 | status = dma_readl(dw, STATUS_INT); | |
3783cef8 AS |
634 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
635 | ||
636 | /* Check if we have any interrupt from the DMAC */ | |
02a21b79 | 637 | if (!status) |
3783cef8 | 638 | return IRQ_NONE; |
3bfb1d20 HS |
639 | |
640 | /* | |
641 | * Just disable the interrupts. We'll turn them back on in the | |
642 | * softirq handler. | |
643 | */ | |
644 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 645 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
646 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
647 | ||
648 | status = dma_readl(dw, STATUS_INT); | |
649 | if (status) { | |
650 | dev_err(dw->dma.dev, | |
651 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
652 | status); | |
653 | ||
654 | /* Try to recover */ | |
655 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
2895b2ca | 656 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
3bfb1d20 HS |
657 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
658 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
659 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
660 | } | |
661 | ||
662 | tasklet_schedule(&dw->tasklet); | |
663 | ||
664 | return IRQ_HANDLED; | |
665 | } | |
666 | ||
667 | /*----------------------------------------------------------------------*/ | |
668 | ||
669 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
670 | { | |
671 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
672 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
673 | dma_cookie_t cookie; | |
69cea5a0 | 674 | unsigned long flags; |
3bfb1d20 | 675 | |
69cea5a0 | 676 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 677 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
678 | |
679 | /* | |
680 | * REVISIT: We should attempt to chain as many descriptors as | |
681 | * possible, perhaps even appending to those already submitted | |
682 | * for DMA. But this is hard to do in a race-free manner. | |
683 | */ | |
3bfb1d20 | 684 | |
dd8ecfca AS |
685 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie); |
686 | list_add_tail(&desc->desc_node, &dwc->queue); | |
3bfb1d20 | 687 | |
69cea5a0 | 688 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
689 | |
690 | return cookie; | |
691 | } | |
692 | ||
693 | static struct dma_async_tx_descriptor * | |
694 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
695 | size_t len, unsigned long flags) | |
696 | { | |
697 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 698 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
699 | struct dw_desc *desc; |
700 | struct dw_desc *first; | |
701 | struct dw_desc *prev; | |
702 | size_t xfer_count; | |
703 | size_t offset; | |
704 | unsigned int src_width; | |
705 | unsigned int dst_width; | |
3d4f8605 | 706 | unsigned int data_width; |
3bfb1d20 HS |
707 | u32 ctllo; |
708 | ||
2f45d613 | 709 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
710 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
711 | &dest, &src, len, flags); | |
3bfb1d20 HS |
712 | |
713 | if (unlikely(!len)) { | |
2e4c364e | 714 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
715 | return NULL; |
716 | } | |
717 | ||
0fdb567f AS |
718 | dwc->direction = DMA_MEM_TO_MEM; |
719 | ||
c422025c | 720 | data_width = dw->data_width[dwc->m_master]; |
a0982004 | 721 | |
3d4f8605 | 722 | src_width = dst_width = min_t(unsigned int, data_width, |
39416677 | 723 | dwc_fast_ffs(src | dest | len)); |
3bfb1d20 | 724 | |
327e6970 | 725 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
726 | | DWC_CTLL_DST_WIDTH(dst_width) |
727 | | DWC_CTLL_SRC_WIDTH(src_width) | |
728 | | DWC_CTLL_DST_INC | |
729 | | DWC_CTLL_SRC_INC | |
730 | | DWC_CTLL_FC_M2M; | |
731 | prev = first = NULL; | |
732 | ||
733 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
734 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 735 | dwc->block_size); |
3bfb1d20 HS |
736 | |
737 | desc = dwc_desc_get(dwc); | |
738 | if (!desc) | |
739 | goto err_desc_get; | |
740 | ||
df1f3a23 MR |
741 | lli_write(desc, sar, src + offset); |
742 | lli_write(desc, dar, dest + offset); | |
743 | lli_write(desc, ctllo, ctllo); | |
744 | lli_write(desc, ctlhi, xfer_count); | |
176dcec5 | 745 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
746 | |
747 | if (!first) { | |
748 | first = desc; | |
749 | } else { | |
df1f3a23 MR |
750 | lli_write(prev, llp, desc->txd.phys); |
751 | list_add_tail(&desc->desc_node, &first->tx_list); | |
3bfb1d20 HS |
752 | } |
753 | prev = desc; | |
754 | } | |
755 | ||
3bfb1d20 HS |
756 | if (flags & DMA_PREP_INTERRUPT) |
757 | /* Trigger interrupt after last block */ | |
df1f3a23 | 758 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
759 | |
760 | prev->lli.llp = 0; | |
3bfb1d20 | 761 | first->txd.flags = flags; |
30d38a32 | 762 | first->total_len = len; |
3bfb1d20 HS |
763 | |
764 | return &first->txd; | |
765 | ||
766 | err_desc_get: | |
767 | dwc_desc_put(dwc, first); | |
768 | return NULL; | |
769 | } | |
770 | ||
771 | static struct dma_async_tx_descriptor * | |
772 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 773 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 774 | unsigned long flags, void *context) |
3bfb1d20 HS |
775 | { |
776 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 777 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 778 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
779 | struct dw_desc *prev; |
780 | struct dw_desc *first; | |
781 | u32 ctllo; | |
782 | dma_addr_t reg; | |
783 | unsigned int reg_width; | |
784 | unsigned int mem_width; | |
a0982004 | 785 | unsigned int data_width; |
3bfb1d20 HS |
786 | unsigned int i; |
787 | struct scatterlist *sg; | |
788 | size_t total_len = 0; | |
789 | ||
2e4c364e | 790 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 791 | |
495aea4b | 792 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
793 | return NULL; |
794 | ||
0fdb567f AS |
795 | dwc->direction = direction; |
796 | ||
3bfb1d20 HS |
797 | prev = first = NULL; |
798 | ||
3bfb1d20 | 799 | switch (direction) { |
db8196df | 800 | case DMA_MEM_TO_DEV: |
39416677 | 801 | reg_width = __ffs(sconfig->dst_addr_width); |
327e6970 VK |
802 | reg = sconfig->dst_addr; |
803 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
804 | | DWC_CTLL_DST_WIDTH(reg_width) |
805 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
806 | | DWC_CTLL_SRC_INC); |
807 | ||
808 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
809 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
810 | ||
c422025c | 811 | data_width = dw->data_width[dwc->m_master]; |
a0982004 | 812 | |
3bfb1d20 HS |
813 | for_each_sg(sgl, sg, sg_len, i) { |
814 | struct dw_desc *desc; | |
69dc14b5 | 815 | u32 len, dlen, mem; |
3bfb1d20 | 816 | |
cbb796cc | 817 | mem = sg_dma_address(sg); |
69dc14b5 | 818 | len = sg_dma_len(sg); |
6bc711f6 | 819 | |
a0982004 | 820 | mem_width = min_t(unsigned int, |
39416677 | 821 | data_width, dwc_fast_ffs(mem | len)); |
3bfb1d20 | 822 | |
69dc14b5 | 823 | slave_sg_todev_fill_desc: |
3bfb1d20 | 824 | desc = dwc_desc_get(dwc); |
b2607227 | 825 | if (!desc) |
3bfb1d20 | 826 | goto err_desc_get; |
3bfb1d20 | 827 | |
df1f3a23 MR |
828 | lli_write(desc, sar, mem); |
829 | lli_write(desc, dar, reg); | |
830 | lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); | |
4a63a8b3 AS |
831 | if ((len >> mem_width) > dwc->block_size) { |
832 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
833 | mem += dlen; |
834 | len -= dlen; | |
835 | } else { | |
836 | dlen = len; | |
837 | len = 0; | |
838 | } | |
839 | ||
df1f3a23 | 840 | lli_write(desc, ctlhi, dlen >> mem_width); |
176dcec5 | 841 | desc->len = dlen; |
3bfb1d20 HS |
842 | |
843 | if (!first) { | |
844 | first = desc; | |
845 | } else { | |
df1f3a23 MR |
846 | lli_write(prev, llp, desc->txd.phys); |
847 | list_add_tail(&desc->desc_node, &first->tx_list); | |
3bfb1d20 HS |
848 | } |
849 | prev = desc; | |
69dc14b5 VK |
850 | total_len += dlen; |
851 | ||
852 | if (len) | |
853 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
854 | } |
855 | break; | |
db8196df | 856 | case DMA_DEV_TO_MEM: |
39416677 | 857 | reg_width = __ffs(sconfig->src_addr_width); |
327e6970 VK |
858 | reg = sconfig->src_addr; |
859 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
860 | | DWC_CTLL_SRC_WIDTH(reg_width) |
861 | | DWC_CTLL_DST_INC | |
327e6970 VK |
862 | | DWC_CTLL_SRC_FIX); |
863 | ||
864 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
865 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 866 | |
c422025c | 867 | data_width = dw->data_width[dwc->m_master]; |
a0982004 | 868 | |
3bfb1d20 HS |
869 | for_each_sg(sgl, sg, sg_len, i) { |
870 | struct dw_desc *desc; | |
69dc14b5 | 871 | u32 len, dlen, mem; |
3bfb1d20 | 872 | |
cbb796cc | 873 | mem = sg_dma_address(sg); |
3bfb1d20 | 874 | len = sg_dma_len(sg); |
6bc711f6 | 875 | |
a0982004 | 876 | mem_width = min_t(unsigned int, |
39416677 | 877 | data_width, dwc_fast_ffs(mem | len)); |
3bfb1d20 | 878 | |
69dc14b5 VK |
879 | slave_sg_fromdev_fill_desc: |
880 | desc = dwc_desc_get(dwc); | |
b2607227 | 881 | if (!desc) |
69dc14b5 | 882 | goto err_desc_get; |
69dc14b5 | 883 | |
df1f3a23 MR |
884 | lli_write(desc, sar, reg); |
885 | lli_write(desc, dar, mem); | |
886 | lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); | |
4a63a8b3 AS |
887 | if ((len >> reg_width) > dwc->block_size) { |
888 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
889 | mem += dlen; |
890 | len -= dlen; | |
891 | } else { | |
892 | dlen = len; | |
893 | len = 0; | |
894 | } | |
df1f3a23 | 895 | lli_write(desc, ctlhi, dlen >> reg_width); |
176dcec5 | 896 | desc->len = dlen; |
3bfb1d20 HS |
897 | |
898 | if (!first) { | |
899 | first = desc; | |
900 | } else { | |
df1f3a23 MR |
901 | lli_write(prev, llp, desc->txd.phys); |
902 | list_add_tail(&desc->desc_node, &first->tx_list); | |
3bfb1d20 HS |
903 | } |
904 | prev = desc; | |
69dc14b5 VK |
905 | total_len += dlen; |
906 | ||
907 | if (len) | |
908 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
909 | } |
910 | break; | |
911 | default: | |
912 | return NULL; | |
913 | } | |
914 | ||
915 | if (flags & DMA_PREP_INTERRUPT) | |
916 | /* Trigger interrupt after last block */ | |
df1f3a23 | 917 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
918 | |
919 | prev->lli.llp = 0; | |
30d38a32 | 920 | first->total_len = total_len; |
3bfb1d20 HS |
921 | |
922 | return &first->txd; | |
923 | ||
924 | err_desc_get: | |
b2607227 JN |
925 | dev_err(chan2dev(chan), |
926 | "not enough descriptors available. Direction %d\n", direction); | |
3bfb1d20 HS |
927 | dwc_desc_put(dwc, first); |
928 | return NULL; | |
929 | } | |
930 | ||
4d130de2 AS |
931 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
932 | { | |
933 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
934 | struct dw_dma_slave *dws = param; | |
935 | ||
3fe6409c | 936 | if (dws->dma_dev != chan->device->dev) |
4d130de2 AS |
937 | return false; |
938 | ||
939 | /* We have to copy data since dws can be temporary storage */ | |
940 | ||
941 | dwc->src_id = dws->src_id; | |
942 | dwc->dst_id = dws->dst_id; | |
943 | ||
c422025c AS |
944 | dwc->m_master = dws->m_master; |
945 | dwc->p_master = dws->p_master; | |
4d130de2 AS |
946 | |
947 | return true; | |
948 | } | |
949 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
950 | ||
327e6970 VK |
951 | /* |
952 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
953 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
954 | * | |
955 | * NOTE: burst size 2 is not supported by controller. | |
956 | * | |
957 | * This can be done by finding least significant bit set: n & (n - 1) | |
958 | */ | |
959 | static inline void convert_burst(u32 *maxburst) | |
960 | { | |
961 | if (*maxburst > 1) | |
962 | *maxburst = fls(*maxburst) - 2; | |
963 | else | |
964 | *maxburst = 0; | |
965 | } | |
966 | ||
a4b0d348 | 967 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
327e6970 VK |
968 | { |
969 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
970 | ||
495aea4b AS |
971 | /* Check if chan will be configured for slave transfers */ |
972 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
973 | return -EINVAL; |
974 | ||
975 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 976 | dwc->direction = sconfig->direction; |
327e6970 VK |
977 | |
978 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
979 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
a4b0d348 | 984 | static int dwc_pause(struct dma_chan *chan) |
21fe3c52 | 985 | { |
a4b0d348 MR |
986 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
987 | unsigned long flags; | |
988 | unsigned int count = 20; /* timeout iterations */ | |
989 | u32 cfglo; | |
990 | ||
991 | spin_lock_irqsave(&dwc->lock, flags); | |
21fe3c52 | 992 | |
a4b0d348 | 993 | cfglo = channel_readl(dwc, CFG_LO); |
21fe3c52 | 994 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
123b69ab AS |
995 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
996 | udelay(2); | |
21fe3c52 AS |
997 | |
998 | dwc->paused = true; | |
a4b0d348 MR |
999 | |
1000 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1001 | ||
1002 | return 0; | |
21fe3c52 AS |
1003 | } |
1004 | ||
1005 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1006 | { | |
1007 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1008 | ||
1009 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1010 | ||
1011 | dwc->paused = false; | |
1012 | } | |
1013 | ||
a4b0d348 | 1014 | static int dwc_resume(struct dma_chan *chan) |
3bfb1d20 HS |
1015 | { |
1016 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
69cea5a0 | 1017 | unsigned long flags; |
3bfb1d20 | 1018 | |
a4b0d348 MR |
1019 | if (!dwc->paused) |
1020 | return 0; | |
c3635c78 | 1021 | |
a4b0d348 | 1022 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1023 | |
a4b0d348 | 1024 | dwc_chan_resume(dwc); |
3bfb1d20 | 1025 | |
a4b0d348 | 1026 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1027 | |
a4b0d348 MR |
1028 | return 0; |
1029 | } | |
3bfb1d20 | 1030 | |
a4b0d348 MR |
1031 | static int dwc_terminate_all(struct dma_chan *chan) |
1032 | { | |
1033 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1034 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1035 | struct dw_desc *desc, *_desc; | |
1036 | unsigned long flags; | |
1037 | LIST_HEAD(list); | |
3bfb1d20 | 1038 | |
a4b0d348 | 1039 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b | 1040 | |
a4b0d348 | 1041 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
fed2574b | 1042 | |
a4b0d348 | 1043 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1044 | |
a4b0d348 | 1045 | dwc_chan_resume(dwc); |
a7c57cf7 | 1046 | |
a4b0d348 MR |
1047 | /* active_list entries will end up before queued entries */ |
1048 | list_splice_init(&dwc->queue, &list); | |
1049 | list_splice_init(&dwc->active_list, &list); | |
a7c57cf7 | 1050 | |
a4b0d348 | 1051 | spin_unlock_irqrestore(&dwc->lock, flags); |
a7c57cf7 | 1052 | |
a4b0d348 MR |
1053 | /* Flush all pending and queued descriptors */ |
1054 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1055 | dwc_descriptor_complete(dwc, desc, false); | |
c3635c78 LW |
1056 | |
1057 | return 0; | |
3bfb1d20 HS |
1058 | } |
1059 | ||
4702d524 AS |
1060 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1061 | { | |
1062 | unsigned long flags; | |
1063 | u32 residue; | |
1064 | ||
1065 | spin_lock_irqsave(&dwc->lock, flags); | |
1066 | ||
1067 | residue = dwc->residue; | |
1068 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1069 | residue -= dwc_get_sent(dwc); | |
1070 | ||
1071 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1072 | return residue; | |
1073 | } | |
1074 | ||
3bfb1d20 | 1075 | static enum dma_status |
07934481 LW |
1076 | dwc_tx_status(struct dma_chan *chan, |
1077 | dma_cookie_t cookie, | |
1078 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1079 | { |
1080 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1081 | enum dma_status ret; |
3bfb1d20 | 1082 | |
96a2af41 | 1083 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1084 | if (ret == DMA_COMPLETE) |
12381dc0 | 1085 | return ret; |
3bfb1d20 | 1086 | |
12381dc0 | 1087 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1088 | |
12381dc0 | 1089 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1090 | if (ret != DMA_COMPLETE) |
4702d524 | 1091 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1092 | |
effd5cf6 | 1093 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1094 | return DMA_PAUSED; |
3bfb1d20 HS |
1095 | |
1096 | return ret; | |
1097 | } | |
1098 | ||
1099 | static void dwc_issue_pending(struct dma_chan *chan) | |
1100 | { | |
1101 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1102 | unsigned long flags; |
3bfb1d20 | 1103 | |
dd8ecfca AS |
1104 | spin_lock_irqsave(&dwc->lock, flags); |
1105 | if (list_empty(&dwc->active_list)) | |
1106 | dwc_dostart_first_queued(dwc); | |
1107 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1108 | } |
1109 | ||
99d9bf4e AS |
1110 | /*----------------------------------------------------------------------*/ |
1111 | ||
1112 | static void dw_dma_off(struct dw_dma *dw) | |
1113 | { | |
1114 | int i; | |
1115 | ||
1116 | dma_writel(dw, CFG, 0); | |
1117 | ||
1118 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 1119 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
99d9bf4e AS |
1120 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1121 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1122 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1123 | ||
1124 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1125 | cpu_relax(); | |
1126 | ||
1127 | for (i = 0; i < dw->dma.chancnt; i++) | |
1128 | dw->chan[i].initialized = false; | |
1129 | } | |
1130 | ||
1131 | static void dw_dma_on(struct dw_dma *dw) | |
1132 | { | |
1133 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1134 | } | |
1135 | ||
aa1e6f1a | 1136 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1137 | { |
1138 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1139 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1140 | struct dw_desc *desc; | |
3bfb1d20 | 1141 | int i; |
69cea5a0 | 1142 | unsigned long flags; |
3bfb1d20 | 1143 | |
2e4c364e | 1144 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1145 | |
3bfb1d20 HS |
1146 | /* ASSERT: channel is idle */ |
1147 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1148 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1149 | return -EIO; |
1150 | } | |
1151 | ||
d3ee98cd | 1152 | dma_cookie_init(chan); |
3bfb1d20 | 1153 | |
3bfb1d20 HS |
1154 | /* |
1155 | * NOTE: some controllers may have additional features that we | |
1156 | * need to initialize here, like "scatter-gather" (which | |
1157 | * doesn't mean what you think it means), and status writeback. | |
1158 | */ | |
1159 | ||
3fe6409c AS |
1160 | /* |
1161 | * We need controller-specific data to set up slave transfers. | |
1162 | */ | |
1163 | if (chan->private && !dw_dma_filter(chan, chan->private)) { | |
1164 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); | |
1165 | return -EINVAL; | |
1166 | } | |
1167 | ||
99d9bf4e AS |
1168 | /* Enable controller here if needed */ |
1169 | if (!dw->in_use) | |
1170 | dw_dma_on(dw); | |
1171 | dw->in_use |= dwc->mask; | |
1172 | ||
69cea5a0 | 1173 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1174 | i = dwc->descs_allocated; |
1175 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1176 | dma_addr_t phys; |
1177 | ||
69cea5a0 | 1178 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1179 | |
f8122a82 | 1180 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1181 | if (!desc) |
1182 | goto err_desc_alloc; | |
3bfb1d20 | 1183 | |
f8122a82 | 1184 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1185 | |
e0bd0f8c | 1186 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1187 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1188 | desc->txd.tx_submit = dwc_tx_submit; | |
1189 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1190 | desc->txd.phys = phys; |
cbd65312 | 1191 | |
3bfb1d20 HS |
1192 | dwc_desc_put(dwc, desc); |
1193 | ||
69cea5a0 | 1194 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1195 | i = ++dwc->descs_allocated; |
1196 | } | |
1197 | ||
69cea5a0 | 1198 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1199 | |
2e4c364e | 1200 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1201 | |
cbd65312 AS |
1202 | return i; |
1203 | ||
1204 | err_desc_alloc: | |
cbd65312 AS |
1205 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1206 | ||
3bfb1d20 HS |
1207 | return i; |
1208 | } | |
1209 | ||
1210 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1211 | { | |
1212 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1213 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1214 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1215 | unsigned long flags; |
3bfb1d20 HS |
1216 | LIST_HEAD(list); |
1217 | ||
2e4c364e | 1218 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1219 | dwc->descs_allocated); |
1220 | ||
1221 | /* ASSERT: channel is idle */ | |
1222 | BUG_ON(!list_empty(&dwc->active_list)); | |
1223 | BUG_ON(!list_empty(&dwc->queue)); | |
1224 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1225 | ||
69cea5a0 | 1226 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1227 | list_splice_init(&dwc->free_list, &list); |
1228 | dwc->descs_allocated = 0; | |
3fe6409c AS |
1229 | |
1230 | /* Clear custom channel configuration */ | |
1231 | dwc->src_id = 0; | |
1232 | dwc->dst_id = 0; | |
1233 | ||
c422025c AS |
1234 | dwc->m_master = 0; |
1235 | dwc->p_master = 0; | |
3fe6409c | 1236 | |
61e183f8 | 1237 | dwc->initialized = false; |
3bfb1d20 HS |
1238 | |
1239 | /* Disable interrupts */ | |
1240 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
2895b2ca | 1241 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
3bfb1d20 HS |
1242 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1243 | ||
69cea5a0 | 1244 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1245 | |
99d9bf4e AS |
1246 | /* Disable controller in case it was a last user */ |
1247 | dw->in_use &= ~dwc->mask; | |
1248 | if (!dw->in_use) | |
1249 | dw_dma_off(dw); | |
1250 | ||
3bfb1d20 | 1251 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { |
41d5e59c | 1252 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1253 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1254 | } |
1255 | ||
2e4c364e | 1256 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1257 | } |
1258 | ||
d9de4519 HCE |
1259 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1260 | ||
1261 | /** | |
1262 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1263 | * @chan: the DMA channel to start | |
1264 | * | |
1265 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1266 | * -errno on failure. | |
1267 | */ | |
1268 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1269 | { | |
1270 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
ee1cdcda | 1271 | struct dw_dma *dw = to_dw_dma(chan->device); |
69cea5a0 | 1272 | unsigned long flags; |
d9de4519 HCE |
1273 | |
1274 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1275 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1276 | return -ENODEV; | |
1277 | } | |
1278 | ||
69cea5a0 | 1279 | spin_lock_irqsave(&dwc->lock, flags); |
ee1cdcda AS |
1280 | |
1281 | /* Enable interrupts to perform cyclic transfer */ | |
1282 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
1283 | ||
df3bb8a0 | 1284 | dwc_dostart(dwc, dwc->cdesc->desc[0]); |
ee1cdcda | 1285 | |
69cea5a0 | 1286 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1287 | |
1288 | return 0; | |
1289 | } | |
1290 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1291 | ||
1292 | /** | |
1293 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1294 | * @chan: the DMA channel to stop | |
1295 | * | |
1296 | * Must be called with soft interrupts disabled. | |
1297 | */ | |
1298 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1299 | { | |
1300 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1301 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1302 | unsigned long flags; |
d9de4519 | 1303 | |
69cea5a0 | 1304 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1305 | |
3f936207 | 1306 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1307 | |
69cea5a0 | 1308 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1309 | } |
1310 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1311 | ||
1312 | /** | |
1313 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1314 | * @chan: the DMA channel to prepare | |
1315 | * @buf_addr: physical DMA address where the buffer starts | |
1316 | * @buf_len: total number of bytes for the entire buffer | |
1317 | * @period_len: number of bytes for each period | |
1318 | * @direction: transfer direction, to or from device | |
1319 | * | |
1320 | * Must be called before trying to start the transfer. Returns a valid struct | |
1321 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1322 | */ | |
1323 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1324 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1325 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1326 | { |
1327 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1328 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1329 | struct dw_cyclic_desc *cdesc; |
1330 | struct dw_cyclic_desc *retval = NULL; | |
1331 | struct dw_desc *desc; | |
1332 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1333 | unsigned long was_cyclic; |
1334 | unsigned int reg_width; | |
1335 | unsigned int periods; | |
1336 | unsigned int i; | |
69cea5a0 | 1337 | unsigned long flags; |
d9de4519 | 1338 | |
69cea5a0 | 1339 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1340 | if (dwc->nollp) { |
1341 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1342 | dev_dbg(chan2dev(&dwc->chan), | |
1343 | "channel doesn't support LLP transfers\n"); | |
1344 | return ERR_PTR(-EINVAL); | |
1345 | } | |
1346 | ||
d9de4519 | 1347 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1348 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1349 | dev_dbg(chan2dev(&dwc->chan), |
1350 | "queue and/or active list are not empty\n"); | |
1351 | return ERR_PTR(-EBUSY); | |
1352 | } | |
1353 | ||
1354 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1355 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1356 | if (was_cyclic) { |
1357 | dev_dbg(chan2dev(&dwc->chan), | |
1358 | "channel already prepared for cyclic DMA\n"); | |
1359 | return ERR_PTR(-EBUSY); | |
1360 | } | |
1361 | ||
1362 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1363 | |
f44b92f4 AS |
1364 | if (unlikely(!is_slave_direction(direction))) |
1365 | goto out_err; | |
1366 | ||
0fdb567f AS |
1367 | dwc->direction = direction; |
1368 | ||
327e6970 VK |
1369 | if (direction == DMA_MEM_TO_DEV) |
1370 | reg_width = __ffs(sconfig->dst_addr_width); | |
1371 | else | |
1372 | reg_width = __ffs(sconfig->src_addr_width); | |
1373 | ||
d9de4519 HCE |
1374 | periods = buf_len / period_len; |
1375 | ||
1376 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1377 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1378 | goto out_err; |
1379 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1380 | goto out_err; | |
1381 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1382 | goto out_err; | |
d9de4519 HCE |
1383 | |
1384 | retval = ERR_PTR(-ENOMEM); | |
1385 | ||
1386 | if (periods > NR_DESCS_PER_CHANNEL) | |
1387 | goto out_err; | |
1388 | ||
1389 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1390 | if (!cdesc) | |
1391 | goto out_err; | |
1392 | ||
1393 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1394 | if (!cdesc->desc) | |
1395 | goto out_err_alloc; | |
1396 | ||
1397 | for (i = 0; i < periods; i++) { | |
1398 | desc = dwc_desc_get(dwc); | |
1399 | if (!desc) | |
1400 | goto out_err_desc_get; | |
1401 | ||
1402 | switch (direction) { | |
db8196df | 1403 | case DMA_MEM_TO_DEV: |
df1f3a23 MR |
1404 | lli_write(desc, dar, sconfig->dst_addr); |
1405 | lli_write(desc, sar, buf_addr + period_len * i); | |
1406 | lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) | |
1407 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1408 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1409 | | DWC_CTLL_DST_FIX | |
1410 | | DWC_CTLL_SRC_INC | |
1411 | | DWC_CTLL_INT_EN)); | |
1412 | ||
1413 | lli_set(desc, ctllo, sconfig->device_fc ? | |
1414 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1415 | DWC_CTLL_FC(DW_DMA_FC_D_M2P)); | |
327e6970 | 1416 | |
d9de4519 | 1417 | break; |
db8196df | 1418 | case DMA_DEV_TO_MEM: |
df1f3a23 MR |
1419 | lli_write(desc, dar, buf_addr + period_len * i); |
1420 | lli_write(desc, sar, sconfig->src_addr); | |
1421 | lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) | |
1422 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1423 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1424 | | DWC_CTLL_DST_INC | |
1425 | | DWC_CTLL_SRC_FIX | |
1426 | | DWC_CTLL_INT_EN)); | |
1427 | ||
1428 | lli_set(desc, ctllo, sconfig->device_fc ? | |
1429 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1430 | DWC_CTLL_FC(DW_DMA_FC_D_P2M)); | |
327e6970 | 1431 | |
d9de4519 HCE |
1432 | break; |
1433 | default: | |
1434 | break; | |
1435 | } | |
1436 | ||
df1f3a23 | 1437 | lli_write(desc, ctlhi, period_len >> reg_width); |
d9de4519 HCE |
1438 | cdesc->desc[i] = desc; |
1439 | ||
f8122a82 | 1440 | if (last) |
df1f3a23 | 1441 | lli_write(last, llp, desc->txd.phys); |
d9de4519 HCE |
1442 | |
1443 | last = desc; | |
1444 | } | |
1445 | ||
75c61225 | 1446 | /* Let's make a cyclic list */ |
df1f3a23 | 1447 | lli_write(last, llp, cdesc->desc[0]->txd.phys); |
d9de4519 | 1448 | |
5a87f0e6 AS |
1449 | dev_dbg(chan2dev(&dwc->chan), |
1450 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1451 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1452 | |
1453 | cdesc->periods = periods; | |
1454 | dwc->cdesc = cdesc; | |
1455 | ||
1456 | return cdesc; | |
1457 | ||
1458 | out_err_desc_get: | |
1459 | while (i--) | |
1460 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1461 | out_err_alloc: | |
1462 | kfree(cdesc); | |
1463 | out_err: | |
1464 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1465 | return (struct dw_cyclic_desc *)retval; | |
1466 | } | |
1467 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1468 | ||
1469 | /** | |
1470 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1471 | * @chan: the DMA channel to free | |
1472 | */ | |
1473 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1474 | { | |
1475 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1476 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1477 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1478 | int i; | |
69cea5a0 | 1479 | unsigned long flags; |
d9de4519 | 1480 | |
2e4c364e | 1481 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1482 | |
1483 | if (!cdesc) | |
1484 | return; | |
1485 | ||
69cea5a0 | 1486 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1487 | |
3f936207 | 1488 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1489 | |
2895b2ca | 1490 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
1491 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1492 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1493 | ||
69cea5a0 | 1494 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1495 | |
1496 | for (i = 0; i < cdesc->periods; i++) | |
1497 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1498 | ||
1499 | kfree(cdesc->desc); | |
1500 | kfree(cdesc); | |
1501 | ||
1502 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1503 | } | |
1504 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1505 | ||
3bfb1d20 HS |
1506 | /*----------------------------------------------------------------------*/ |
1507 | ||
9cade1a4 | 1508 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1509 | { |
3bfb1d20 | 1510 | struct dw_dma *dw; |
30cb2639 | 1511 | bool autocfg = false; |
482c67ea | 1512 | unsigned int dw_params; |
4a63a8b3 | 1513 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1514 | int err; |
1515 | int i; | |
1516 | ||
000871ce AS |
1517 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1518 | if (!dw) | |
1519 | return -ENOMEM; | |
1520 | ||
1521 | dw->regs = chip->regs; | |
1522 | chip->dw = dw; | |
1523 | ||
bb32baf7 AS |
1524 | pm_runtime_get_sync(chip->dev); |
1525 | ||
30cb2639 AS |
1526 | if (!pdata) { |
1527 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); | |
1528 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); | |
482c67ea | 1529 | |
30cb2639 AS |
1530 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
1531 | if (!autocfg) { | |
1532 | err = -EINVAL; | |
1533 | goto err_pdata; | |
1534 | } | |
123de543 | 1535 | |
9cade1a4 | 1536 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
8be4f523 AS |
1537 | if (!pdata) { |
1538 | err = -ENOMEM; | |
1539 | goto err_pdata; | |
1540 | } | |
123de543 | 1541 | |
30cb2639 AS |
1542 | /* Get hardware configuration parameters */ |
1543 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; | |
1544 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; | |
1545 | for (i = 0; i < pdata->nr_masters; i++) { | |
1546 | pdata->data_width[i] = | |
1547 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1548 | } | |
1549 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); | |
1550 | ||
123de543 AS |
1551 | /* Fill platform data with the default values */ |
1552 | pdata->is_private = true; | |
df5c7386 | 1553 | pdata->is_memcpy = true; |
123de543 AS |
1554 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
1555 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
30cb2639 | 1556 | } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
8be4f523 AS |
1557 | err = -EINVAL; |
1558 | goto err_pdata; | |
1559 | } | |
123de543 | 1560 | |
30cb2639 | 1561 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
000871ce | 1562 | GFP_KERNEL); |
8be4f523 AS |
1563 | if (!dw->chan) { |
1564 | err = -ENOMEM; | |
1565 | goto err_pdata; | |
1566 | } | |
3bfb1d20 | 1567 | |
75c61225 | 1568 | /* Get hardware configuration parameters */ |
30cb2639 AS |
1569 | dw->nr_masters = pdata->nr_masters; |
1570 | for (i = 0; i < dw->nr_masters; i++) | |
1571 | dw->data_width[i] = pdata->data_width[i]; | |
a0982004 | 1572 | |
11f932ec | 1573 | /* Calculate all channel mask before DMA setup */ |
30cb2639 | 1574 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
11f932ec | 1575 | |
75c61225 | 1576 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1577 | dw_dma_off(dw); |
1578 | ||
75c61225 | 1579 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1580 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1581 | sizeof(struct dw_desc), 4, 0); |
1582 | if (!dw->desc_pool) { | |
9cade1a4 | 1583 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1584 | err = -ENOMEM; |
1585 | goto err_pdata; | |
f8122a82 AS |
1586 | } |
1587 | ||
3bfb1d20 HS |
1588 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1589 | ||
97977f75 AS |
1590 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1591 | "dw_dmac", dw); | |
1592 | if (err) | |
8be4f523 | 1593 | goto err_pdata; |
97977f75 | 1594 | |
3bfb1d20 | 1595 | INIT_LIST_HEAD(&dw->dma.channels); |
30cb2639 | 1596 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1597 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1598 | ||
1599 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1600 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1601 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1602 | list_add_tail(&dwc->chan.device_node, | |
1603 | &dw->dma.channels); | |
1604 | else | |
1605 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1606 | |
93317e8e VK |
1607 | /* 7 is highest priority & 0 is lowest. */ |
1608 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
30cb2639 | 1609 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1610 | else |
1611 | dwc->priority = i; | |
1612 | ||
3bfb1d20 HS |
1613 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1614 | spin_lock_init(&dwc->lock); | |
1615 | dwc->mask = 1 << i; | |
1616 | ||
1617 | INIT_LIST_HEAD(&dwc->active_list); | |
1618 | INIT_LIST_HEAD(&dwc->queue); | |
1619 | INIT_LIST_HEAD(&dwc->free_list); | |
1620 | ||
1621 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1622 | |
0fdb567f | 1623 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1624 | |
75c61225 | 1625 | /* Hardware configuration */ |
fed2574b AS |
1626 | if (autocfg) { |
1627 | unsigned int dwc_params; | |
6bea0f6d | 1628 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
9cade1a4 | 1629 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1630 | |
9cade1a4 | 1631 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1632 | |
9cade1a4 AS |
1633 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1634 | dwc_params); | |
985a6c7d | 1635 | |
1d566f11 AS |
1636 | /* |
1637 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1638 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1639 | * up to 0x0a for 4095. |
1640 | */ | |
4a63a8b3 AS |
1641 | dwc->block_size = |
1642 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1643 | dwc->nollp = |
1644 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1645 | } else { | |
4a63a8b3 | 1646 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1647 | |
1648 | /* Check if channel supports multi block transfer */ | |
1649 | channel_writel(dwc, LLP, 0xfffffffc); | |
1650 | dwc->nollp = | |
1651 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1652 | channel_writel(dwc, LLP, 0); | |
1653 | } | |
3bfb1d20 HS |
1654 | } |
1655 | ||
11f932ec | 1656 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1657 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1658 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1659 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1660 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1661 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1662 | ||
df5c7386 | 1663 | /* Set capabilities */ |
3bfb1d20 | 1664 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
95ea759e JI |
1665 | if (pdata->is_private) |
1666 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
df5c7386 AS |
1667 | if (pdata->is_memcpy) |
1668 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1669 | ||
9cade1a4 | 1670 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1671 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1672 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1673 | ||
1674 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
3bfb1d20 | 1675 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
029a40e9 | 1676 | |
a4b0d348 MR |
1677 | dw->dma.device_config = dwc_config; |
1678 | dw->dma.device_pause = dwc_pause; | |
1679 | dw->dma.device_resume = dwc_resume; | |
1680 | dw->dma.device_terminate_all = dwc_terminate_all; | |
3bfb1d20 | 1681 | |
07934481 | 1682 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1683 | dw->dma.device_issue_pending = dwc_issue_pending; |
1684 | ||
029a40e9 AS |
1685 | /* DMA capabilities */ |
1686 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; | |
1687 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; | |
1688 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | | |
1689 | BIT(DMA_MEM_TO_MEM); | |
1690 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1691 | ||
1222934e AS |
1692 | err = dma_async_device_register(&dw->dma); |
1693 | if (err) | |
1694 | goto err_dma_register; | |
1695 | ||
9cade1a4 | 1696 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
30cb2639 | 1697 | pdata->nr_channels); |
3bfb1d20 | 1698 | |
bb32baf7 AS |
1699 | pm_runtime_put_sync_suspend(chip->dev); |
1700 | ||
3bfb1d20 | 1701 | return 0; |
8be4f523 | 1702 | |
1222934e AS |
1703 | err_dma_register: |
1704 | free_irq(chip->irq, dw); | |
8be4f523 | 1705 | err_pdata: |
bb32baf7 | 1706 | pm_runtime_put_sync_suspend(chip->dev); |
8be4f523 | 1707 | return err; |
3bfb1d20 | 1708 | } |
9cade1a4 | 1709 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1710 | |
9cade1a4 | 1711 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1712 | { |
9cade1a4 | 1713 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1714 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 | 1715 | |
bb32baf7 AS |
1716 | pm_runtime_get_sync(chip->dev); |
1717 | ||
3bfb1d20 HS |
1718 | dw_dma_off(dw); |
1719 | dma_async_device_unregister(&dw->dma); | |
1720 | ||
97977f75 | 1721 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1722 | tasklet_kill(&dw->tasklet); |
1723 | ||
1724 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1725 | chan.device_node) { | |
1726 | list_del(&dwc->chan.device_node); | |
1727 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1728 | } | |
1729 | ||
bb32baf7 | 1730 | pm_runtime_put_sync_suspend(chip->dev); |
3bfb1d20 HS |
1731 | return 0; |
1732 | } | |
9cade1a4 | 1733 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1734 | |
2540f74b | 1735 | int dw_dma_disable(struct dw_dma_chip *chip) |
3bfb1d20 | 1736 | { |
9cade1a4 | 1737 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1738 | |
6168d567 | 1739 | dw_dma_off(dw); |
3bfb1d20 HS |
1740 | return 0; |
1741 | } | |
2540f74b | 1742 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
3bfb1d20 | 1743 | |
2540f74b | 1744 | int dw_dma_enable(struct dw_dma_chip *chip) |
3bfb1d20 | 1745 | { |
9cade1a4 | 1746 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1747 | |
7a83c045 | 1748 | dw_dma_on(dw); |
3bfb1d20 | 1749 | return 0; |
3bfb1d20 | 1750 | } |
2540f74b | 1751 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
3bfb1d20 HS |
1752 | |
1753 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1754 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1755 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
da89947b | 1756 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |