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Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/clk.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
f8122a82 | 18 | #include <linux/dmapool.h> |
7331205a | 19 | #include <linux/err.h> |
3bfb1d20 HS |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/module.h> | |
3bfb1d20 HS |
25 | #include <linux/slab.h> |
26 | ||
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
36 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
37 | * which does not support descriptor writeback. | |
38 | */ | |
39 | ||
78f3c9d2 AS |
40 | static inline bool is_request_line_unset(struct dw_dma_chan *dwc) |
41 | { | |
42 | return dwc->request_line == (typeof(dwc->request_line))~0; | |
43 | } | |
44 | ||
f776076b | 45 | static inline void dwc_set_masters(struct dw_dma_chan *dwc) |
5be10f34 | 46 | { |
f776076b AB |
47 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
48 | struct dw_dma_slave *dws = dwc->chan.private; | |
49 | unsigned char mmax = dw->nr_masters - 1; | |
5be10f34 | 50 | |
78f3c9d2 AS |
51 | if (!is_request_line_unset(dwc)) |
52 | return; | |
53 | ||
54 | dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws)); | |
55 | dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws)); | |
5be10f34 AS |
56 | } |
57 | ||
327e6970 | 58 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
59 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
60 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 61 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 62 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 63 | DW_DMA_MSIZE_16; \ |
495aea4b | 64 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 65 | DW_DMA_MSIZE_16; \ |
f301c062 | 66 | \ |
327e6970 VK |
67 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
68 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
69 | | DWC_CTLL_LLP_D_EN \ |
70 | | DWC_CTLL_LLP_S_EN \ | |
f776076b AB |
71 | | DWC_CTLL_DMS(_dwc->dst_master) \ |
72 | | DWC_CTLL_SMS(_dwc->src_master)); \ | |
f301c062 | 73 | }) |
3bfb1d20 | 74 | |
3bfb1d20 HS |
75 | /* |
76 | * Number of descriptors to allocate for each channel. This should be | |
77 | * made configurable somehow; preferably, the clients (at least the | |
78 | * ones using slave transfers) should be able to give us a hint. | |
79 | */ | |
80 | #define NR_DESCS_PER_CHANNEL 64 | |
81 | ||
82 | /*----------------------------------------------------------------------*/ | |
3bfb1d20 | 83 | |
41d5e59c DW |
84 | static struct device *chan2dev(struct dma_chan *chan) |
85 | { | |
86 | return &chan->dev->device; | |
87 | } | |
41d5e59c | 88 | |
3bfb1d20 HS |
89 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
90 | { | |
e63a47a3 | 91 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
92 | } |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
95 | { | |
96 | struct dw_desc *desc, *_desc; | |
97 | struct dw_desc *ret = NULL; | |
98 | unsigned int i = 0; | |
69cea5a0 | 99 | unsigned long flags; |
3bfb1d20 | 100 | |
69cea5a0 | 101 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 102 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 103 | i++; |
3bfb1d20 HS |
104 | if (async_tx_test_ack(&desc->txd)) { |
105 | list_del(&desc->desc_node); | |
106 | ret = desc; | |
107 | break; | |
108 | } | |
41d5e59c | 109 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 110 | } |
69cea5a0 | 111 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 112 | |
41d5e59c | 113 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
114 | |
115 | return ret; | |
116 | } | |
117 | ||
3bfb1d20 HS |
118 | /* |
119 | * Move a descriptor, including any children, to the free list. | |
120 | * `desc' must not be on any lists. | |
121 | */ | |
122 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
123 | { | |
69cea5a0 VK |
124 | unsigned long flags; |
125 | ||
3bfb1d20 HS |
126 | if (desc) { |
127 | struct dw_desc *child; | |
128 | ||
69cea5a0 | 129 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 130 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 131 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
132 | "moving child desc %p to freelist\n", |
133 | child); | |
e0bd0f8c | 134 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 135 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 136 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 137 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
138 | } |
139 | } | |
140 | ||
61e183f8 VK |
141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
142 | { | |
143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
144 | struct dw_dma_slave *dws = dwc->chan.private; | |
145 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
146 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
147 | ||
148 | if (dwc->initialized == true) | |
149 | return; | |
150 | ||
f776076b | 151 | if (dws) { |
61e183f8 VK |
152 | /* |
153 | * We need controller-specific data to set up slave | |
154 | * transfers. | |
155 | */ | |
156 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
157 | ||
158 | cfghi = dws->cfg_hi; | |
159 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 160 | } else { |
0fdb567f | 161 | if (dwc->direction == DMA_MEM_TO_DEV) |
f776076b | 162 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); |
0fdb567f | 163 | else if (dwc->direction == DMA_DEV_TO_MEM) |
f776076b | 164 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); |
61e183f8 VK |
165 | } |
166 | ||
167 | channel_writel(dwc, CFG_LO, cfglo); | |
168 | channel_writel(dwc, CFG_HI, cfghi); | |
169 | ||
170 | /* Enable interrupts */ | |
171 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
172 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
173 | ||
174 | dwc->initialized = true; | |
175 | } | |
176 | ||
3bfb1d20 HS |
177 | /*----------------------------------------------------------------------*/ |
178 | ||
4c2d56c5 AS |
179 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
180 | { | |
181 | /* | |
182 | * We can be a lot more clever here, but this should take care | |
183 | * of the most common optimization. | |
184 | */ | |
185 | if (!(v & 7)) | |
186 | return 3; | |
187 | else if (!(v & 3)) | |
188 | return 2; | |
189 | else if (!(v & 1)) | |
190 | return 1; | |
191 | return 0; | |
192 | } | |
193 | ||
f52b36d2 | 194 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
195 | { |
196 | dev_err(chan2dev(&dwc->chan), | |
197 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
198 | channel_readl(dwc, SAR), | |
199 | channel_readl(dwc, DAR), | |
200 | channel_readl(dwc, LLP), | |
201 | channel_readl(dwc, CTL_HI), | |
202 | channel_readl(dwc, CTL_LO)); | |
203 | } | |
204 | ||
3f936207 AS |
205 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
206 | { | |
207 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
208 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
209 | cpu_relax(); | |
210 | } | |
211 | ||
1d455437 AS |
212 | /*----------------------------------------------------------------------*/ |
213 | ||
fed2574b AS |
214 | /* Perform single block transfer */ |
215 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
216 | struct dw_desc *desc) | |
217 | { | |
218 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
219 | u32 ctllo; | |
220 | ||
1d566f11 AS |
221 | /* |
222 | * Software emulation of LLP mode relies on interrupts to continue | |
223 | * multi block transfer. | |
224 | */ | |
fed2574b AS |
225 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; |
226 | ||
227 | channel_writel(dwc, SAR, desc->lli.sar); | |
228 | channel_writel(dwc, DAR, desc->lli.dar); | |
229 | channel_writel(dwc, CTL_LO, ctllo); | |
230 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
231 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
232 | |
233 | /* Move pointer to next descriptor */ | |
234 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
235 | } |
236 | ||
3bfb1d20 HS |
237 | /* Called with dwc->lock held and bh disabled */ |
238 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
239 | { | |
240 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 241 | unsigned long was_soft_llp; |
3bfb1d20 HS |
242 | |
243 | /* ASSERT: channel is idle */ | |
244 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 245 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 246 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 247 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
248 | |
249 | /* The tasklet will hopefully advance the queue... */ | |
250 | return; | |
251 | } | |
252 | ||
fed2574b AS |
253 | if (dwc->nollp) { |
254 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
255 | &dwc->flags); | |
256 | if (was_soft_llp) { | |
257 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 258 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
259 | return; |
260 | } | |
261 | ||
262 | dwc_initialize(dwc); | |
263 | ||
4702d524 | 264 | dwc->residue = first->total_len; |
f5c6a7df | 265 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 266 | |
fdf475fa | 267 | /* Submit first block */ |
fed2574b AS |
268 | dwc_do_single_block(dwc, first); |
269 | ||
270 | return; | |
271 | } | |
272 | ||
61e183f8 VK |
273 | dwc_initialize(dwc); |
274 | ||
3bfb1d20 HS |
275 | channel_writel(dwc, LLP, first->txd.phys); |
276 | channel_writel(dwc, CTL_LO, | |
277 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
278 | channel_writel(dwc, CTL_HI, 0); | |
279 | channel_set_bit(dw, CH_EN, dwc->mask); | |
280 | } | |
281 | ||
282 | /*----------------------------------------------------------------------*/ | |
283 | ||
284 | static void | |
5fedefb8 VK |
285 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
286 | bool callback_required) | |
3bfb1d20 | 287 | { |
5fedefb8 VK |
288 | dma_async_tx_callback callback = NULL; |
289 | void *param = NULL; | |
3bfb1d20 | 290 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 291 | struct dw_desc *child; |
69cea5a0 | 292 | unsigned long flags; |
3bfb1d20 | 293 | |
41d5e59c | 294 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 295 | |
69cea5a0 | 296 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 297 | dma_cookie_complete(txd); |
5fedefb8 VK |
298 | if (callback_required) { |
299 | callback = txd->callback; | |
300 | param = txd->callback_param; | |
301 | } | |
3bfb1d20 | 302 | |
e518076e VK |
303 | /* async_tx_ack */ |
304 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
305 | async_tx_ack(&child->txd); | |
306 | async_tx_ack(&desc->txd); | |
307 | ||
e0bd0f8c | 308 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
309 | list_move(&desc->desc_node, &dwc->free_list); |
310 | ||
d38a8c62 | 311 | dma_descriptor_unmap(txd); |
69cea5a0 VK |
312 | spin_unlock_irqrestore(&dwc->lock, flags); |
313 | ||
21e93c1e | 314 | if (callback) |
3bfb1d20 HS |
315 | callback(param); |
316 | } | |
317 | ||
318 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
319 | { | |
320 | struct dw_desc *desc, *_desc; | |
321 | LIST_HEAD(list); | |
69cea5a0 | 322 | unsigned long flags; |
3bfb1d20 | 323 | |
69cea5a0 | 324 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 325 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 326 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
327 | "BUG: XFER bit set, but channel not idle!\n"); |
328 | ||
329 | /* Try to continue after resetting the channel... */ | |
3f936207 | 330 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
331 | } |
332 | ||
333 | /* | |
334 | * Submit queued descriptors ASAP, i.e. before we go through | |
335 | * the completed ones. | |
336 | */ | |
3bfb1d20 | 337 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
338 | if (!list_empty(&dwc->queue)) { |
339 | list_move(dwc->queue.next, &dwc->active_list); | |
340 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
341 | } | |
3bfb1d20 | 342 | |
69cea5a0 VK |
343 | spin_unlock_irqrestore(&dwc->lock, flags); |
344 | ||
3bfb1d20 | 345 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 346 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
347 | } |
348 | ||
4702d524 AS |
349 | /* Returns how many bytes were already received from source */ |
350 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
351 | { | |
352 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
353 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
354 | ||
355 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
356 | } | |
357 | ||
3bfb1d20 HS |
358 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
359 | { | |
360 | dma_addr_t llp; | |
361 | struct dw_desc *desc, *_desc; | |
362 | struct dw_desc *child; | |
363 | u32 status_xfer; | |
69cea5a0 | 364 | unsigned long flags; |
3bfb1d20 | 365 | |
69cea5a0 | 366 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
367 | llp = channel_readl(dwc, LLP); |
368 | status_xfer = dma_readl(dw, RAW.XFER); | |
369 | ||
370 | if (status_xfer & dwc->mask) { | |
371 | /* Everything we've submitted is done */ | |
372 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
373 | |
374 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
375 | struct list_head *head, *active = dwc->tx_node_active; |
376 | ||
377 | /* | |
378 | * We are inside first active descriptor. | |
379 | * Otherwise something is really wrong. | |
380 | */ | |
381 | desc = dwc_first_active(dwc); | |
382 | ||
383 | head = &desc->tx_list; | |
384 | if (active != head) { | |
4702d524 AS |
385 | /* Update desc to reflect last sent one */ |
386 | if (active != head->next) | |
387 | desc = to_dw_desc(active->prev); | |
388 | ||
389 | dwc->residue -= desc->len; | |
390 | ||
fdf475fa | 391 | child = to_dw_desc(active); |
77bcc497 AS |
392 | |
393 | /* Submit next block */ | |
fdf475fa | 394 | dwc_do_single_block(dwc, child); |
77bcc497 | 395 | |
fdf475fa | 396 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
397 | return; |
398 | } | |
fdf475fa | 399 | |
77bcc497 AS |
400 | /* We are done here */ |
401 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
402 | } | |
4702d524 AS |
403 | |
404 | dwc->residue = 0; | |
405 | ||
69cea5a0 VK |
406 | spin_unlock_irqrestore(&dwc->lock, flags); |
407 | ||
3bfb1d20 HS |
408 | dwc_complete_all(dw, dwc); |
409 | return; | |
410 | } | |
411 | ||
69cea5a0 | 412 | if (list_empty(&dwc->active_list)) { |
4702d524 | 413 | dwc->residue = 0; |
69cea5a0 | 414 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 415 | return; |
69cea5a0 | 416 | } |
087809fc | 417 | |
77bcc497 AS |
418 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
419 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 420 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 421 | return; |
69cea5a0 | 422 | } |
087809fc | 423 | |
2e4c364e | 424 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 425 | (unsigned long long)llp); |
3bfb1d20 HS |
426 | |
427 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 428 | /* Initial residue value */ |
4702d524 AS |
429 | dwc->residue = desc->total_len; |
430 | ||
75c61225 | 431 | /* Check first descriptors addr */ |
69cea5a0 VK |
432 | if (desc->txd.phys == llp) { |
433 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 434 | return; |
69cea5a0 | 435 | } |
84adccfb | 436 | |
75c61225 | 437 | /* Check first descriptors llp */ |
69cea5a0 | 438 | if (desc->lli.llp == llp) { |
3bfb1d20 | 439 | /* This one is currently in progress */ |
4702d524 | 440 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 441 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 442 | return; |
69cea5a0 | 443 | } |
3bfb1d20 | 444 | |
4702d524 AS |
445 | dwc->residue -= desc->len; |
446 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 447 | if (child->lli.llp == llp) { |
3bfb1d20 | 448 | /* Currently in progress */ |
4702d524 | 449 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 450 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 451 | return; |
69cea5a0 | 452 | } |
4702d524 AS |
453 | dwc->residue -= child->len; |
454 | } | |
3bfb1d20 HS |
455 | |
456 | /* | |
457 | * No descriptors so far seem to be in progress, i.e. | |
458 | * this one must be done. | |
459 | */ | |
69cea5a0 | 460 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 461 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 462 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
463 | } |
464 | ||
41d5e59c | 465 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
466 | "BUG: All descriptors done, but channel not idle!\n"); |
467 | ||
468 | /* Try to continue after resetting the channel... */ | |
3f936207 | 469 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
470 | |
471 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
472 | list_move(dwc->queue.next, &dwc->active_list); |
473 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 474 | } |
69cea5a0 | 475 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
476 | } |
477 | ||
93aad1bc | 478 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 479 | { |
21d43f49 AS |
480 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
481 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
482 | } |
483 | ||
484 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
485 | { | |
486 | struct dw_desc *bad_desc; | |
487 | struct dw_desc *child; | |
69cea5a0 | 488 | unsigned long flags; |
3bfb1d20 HS |
489 | |
490 | dwc_scan_descriptors(dw, dwc); | |
491 | ||
69cea5a0 VK |
492 | spin_lock_irqsave(&dwc->lock, flags); |
493 | ||
3bfb1d20 HS |
494 | /* |
495 | * The descriptor currently at the head of the active list is | |
496 | * borked. Since we don't have any way to report errors, we'll | |
497 | * just have to scream loudly and try to carry on. | |
498 | */ | |
499 | bad_desc = dwc_first_active(dwc); | |
500 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 501 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
502 | |
503 | /* Clear the error flag and try to restart the controller */ | |
504 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
505 | if (!list_empty(&dwc->active_list)) | |
506 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
507 | ||
508 | /* | |
ba84bd71 | 509 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
510 | * when someone submits a bad physical address in a |
511 | * descriptor, we should consider ourselves lucky that the | |
512 | * controller flagged an error instead of scribbling over | |
513 | * random memory locations. | |
514 | */ | |
ba84bd71 AS |
515 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
516 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 517 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 518 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
519 | dwc_dump_lli(dwc, &child->lli); |
520 | ||
69cea5a0 VK |
521 | spin_unlock_irqrestore(&dwc->lock, flags); |
522 | ||
3bfb1d20 | 523 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 524 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
525 | } |
526 | ||
d9de4519 HCE |
527 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
528 | ||
8004cbb4 | 529 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
530 | { |
531 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
532 | return channel_readl(dwc, SAR); | |
533 | } | |
534 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
535 | ||
8004cbb4 | 536 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
537 | { |
538 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
539 | return channel_readl(dwc, DAR); | |
540 | } | |
541 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
542 | ||
75c61225 | 543 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 544 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
ff7b05f2 | 545 | u32 status_err, u32 status_xfer) |
d9de4519 | 546 | { |
69cea5a0 VK |
547 | unsigned long flags; |
548 | ||
ff7b05f2 | 549 | if (dwc->mask) { |
d9de4519 HCE |
550 | void (*callback)(void *param); |
551 | void *callback_param; | |
552 | ||
553 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
554 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
555 | |
556 | callback = dwc->cdesc->period_callback; | |
557 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
558 | |
559 | if (callback) | |
d9de4519 | 560 | callback(callback_param); |
d9de4519 HCE |
561 | } |
562 | ||
563 | /* | |
564 | * Error and transfer complete are highly unlikely, and will most | |
565 | * likely be due to a configuration error by the user. | |
566 | */ | |
567 | if (unlikely(status_err & dwc->mask) || | |
568 | unlikely(status_xfer & dwc->mask)) { | |
569 | int i; | |
570 | ||
fc61f6b4 AS |
571 | dev_err(chan2dev(&dwc->chan), |
572 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
573 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
574 | |
575 | spin_lock_irqsave(&dwc->lock, flags); | |
576 | ||
1d455437 | 577 | dwc_dump_chan_regs(dwc); |
d9de4519 | 578 | |
3f936207 | 579 | dwc_chan_disable(dw, dwc); |
d9de4519 | 580 | |
75c61225 | 581 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
582 | channel_writel(dwc, LLP, 0); |
583 | channel_writel(dwc, CTL_LO, 0); | |
584 | channel_writel(dwc, CTL_HI, 0); | |
585 | ||
d9de4519 HCE |
586 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
587 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
588 | ||
589 | for (i = 0; i < dwc->cdesc->periods; i++) | |
590 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
591 | |
592 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
593 | } |
594 | } | |
595 | ||
596 | /* ------------------------------------------------------------------------- */ | |
597 | ||
3bfb1d20 HS |
598 | static void dw_dma_tasklet(unsigned long data) |
599 | { | |
600 | struct dw_dma *dw = (struct dw_dma *)data; | |
601 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
602 | u32 status_xfer; |
603 | u32 status_err; | |
604 | int i; | |
605 | ||
7fe7b2f4 | 606 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
607 | status_err = dma_readl(dw, RAW.ERROR); |
608 | ||
2e4c364e | 609 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
610 | |
611 | for (i = 0; i < dw->dma.chancnt; i++) { | |
612 | dwc = &dw->chan[i]; | |
d9de4519 | 613 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 614 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 615 | else if (status_err & (1 << i)) |
3bfb1d20 | 616 | dwc_handle_error(dw, dwc); |
77bcc497 | 617 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 618 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
619 | } |
620 | ||
621 | /* | |
ff7b05f2 | 622 | * Re-enable interrupts. |
3bfb1d20 HS |
623 | */ |
624 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
625 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
626 | } | |
627 | ||
628 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
629 | { | |
630 | struct dw_dma *dw = dev_id; | |
3783cef8 | 631 | u32 status = dma_readl(dw, STATUS_INT); |
3bfb1d20 | 632 | |
3783cef8 AS |
633 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
634 | ||
635 | /* Check if we have any interrupt from the DMAC */ | |
636 | if (!status) | |
637 | return IRQ_NONE; | |
3bfb1d20 HS |
638 | |
639 | /* | |
640 | * Just disable the interrupts. We'll turn them back on in the | |
641 | * softirq handler. | |
642 | */ | |
643 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
644 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
645 | ||
646 | status = dma_readl(dw, STATUS_INT); | |
647 | if (status) { | |
648 | dev_err(dw->dma.dev, | |
649 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
650 | status); | |
651 | ||
652 | /* Try to recover */ | |
653 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
654 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
655 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
656 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
657 | } | |
658 | ||
659 | tasklet_schedule(&dw->tasklet); | |
660 | ||
661 | return IRQ_HANDLED; | |
662 | } | |
663 | ||
664 | /*----------------------------------------------------------------------*/ | |
665 | ||
666 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
667 | { | |
668 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
669 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
670 | dma_cookie_t cookie; | |
69cea5a0 | 671 | unsigned long flags; |
3bfb1d20 | 672 | |
69cea5a0 | 673 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 674 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
675 | |
676 | /* | |
677 | * REVISIT: We should attempt to chain as many descriptors as | |
678 | * possible, perhaps even appending to those already submitted | |
679 | * for DMA. But this is hard to do in a race-free manner. | |
680 | */ | |
681 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 682 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 683 | desc->txd.cookie); |
3bfb1d20 | 684 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 685 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 686 | } else { |
2e4c364e | 687 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
688 | desc->txd.cookie); |
689 | ||
690 | list_add_tail(&desc->desc_node, &dwc->queue); | |
691 | } | |
692 | ||
69cea5a0 | 693 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
694 | |
695 | return cookie; | |
696 | } | |
697 | ||
698 | static struct dma_async_tx_descriptor * | |
699 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
700 | size_t len, unsigned long flags) | |
701 | { | |
702 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 703 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
704 | struct dw_desc *desc; |
705 | struct dw_desc *first; | |
706 | struct dw_desc *prev; | |
707 | size_t xfer_count; | |
708 | size_t offset; | |
709 | unsigned int src_width; | |
710 | unsigned int dst_width; | |
3d4f8605 | 711 | unsigned int data_width; |
3bfb1d20 HS |
712 | u32 ctllo; |
713 | ||
2f45d613 | 714 | dev_vdbg(chan2dev(chan), |
2e4c364e | 715 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
716 | (unsigned long long)dest, (unsigned long long)src, |
717 | len, flags); | |
3bfb1d20 HS |
718 | |
719 | if (unlikely(!len)) { | |
2e4c364e | 720 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
721 | return NULL; |
722 | } | |
723 | ||
0fdb567f AS |
724 | dwc->direction = DMA_MEM_TO_MEM; |
725 | ||
f776076b AB |
726 | data_width = min_t(unsigned int, dw->data_width[dwc->src_master], |
727 | dw->data_width[dwc->dst_master]); | |
a0982004 | 728 | |
3d4f8605 AS |
729 | src_width = dst_width = min_t(unsigned int, data_width, |
730 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 731 | |
327e6970 | 732 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
733 | | DWC_CTLL_DST_WIDTH(dst_width) |
734 | | DWC_CTLL_SRC_WIDTH(src_width) | |
735 | | DWC_CTLL_DST_INC | |
736 | | DWC_CTLL_SRC_INC | |
737 | | DWC_CTLL_FC_M2M; | |
738 | prev = first = NULL; | |
739 | ||
740 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
741 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 742 | dwc->block_size); |
3bfb1d20 HS |
743 | |
744 | desc = dwc_desc_get(dwc); | |
745 | if (!desc) | |
746 | goto err_desc_get; | |
747 | ||
748 | desc->lli.sar = src + offset; | |
749 | desc->lli.dar = dest + offset; | |
750 | desc->lli.ctllo = ctllo; | |
751 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 752 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
753 | |
754 | if (!first) { | |
755 | first = desc; | |
756 | } else { | |
757 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 758 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 759 | &first->tx_list); |
3bfb1d20 HS |
760 | } |
761 | prev = desc; | |
762 | } | |
763 | ||
3bfb1d20 HS |
764 | if (flags & DMA_PREP_INTERRUPT) |
765 | /* Trigger interrupt after last block */ | |
766 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
767 | ||
768 | prev->lli.llp = 0; | |
3bfb1d20 | 769 | first->txd.flags = flags; |
30d38a32 | 770 | first->total_len = len; |
3bfb1d20 HS |
771 | |
772 | return &first->txd; | |
773 | ||
774 | err_desc_get: | |
775 | dwc_desc_put(dwc, first); | |
776 | return NULL; | |
777 | } | |
778 | ||
779 | static struct dma_async_tx_descriptor * | |
780 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 781 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 782 | unsigned long flags, void *context) |
3bfb1d20 HS |
783 | { |
784 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 785 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 786 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
787 | struct dw_desc *prev; |
788 | struct dw_desc *first; | |
789 | u32 ctllo; | |
790 | dma_addr_t reg; | |
791 | unsigned int reg_width; | |
792 | unsigned int mem_width; | |
a0982004 | 793 | unsigned int data_width; |
3bfb1d20 HS |
794 | unsigned int i; |
795 | struct scatterlist *sg; | |
796 | size_t total_len = 0; | |
797 | ||
2e4c364e | 798 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 799 | |
495aea4b | 800 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
801 | return NULL; |
802 | ||
0fdb567f AS |
803 | dwc->direction = direction; |
804 | ||
3bfb1d20 HS |
805 | prev = first = NULL; |
806 | ||
3bfb1d20 | 807 | switch (direction) { |
db8196df | 808 | case DMA_MEM_TO_DEV: |
327e6970 VK |
809 | reg_width = __fls(sconfig->dst_addr_width); |
810 | reg = sconfig->dst_addr; | |
811 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
812 | | DWC_CTLL_DST_WIDTH(reg_width) |
813 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
814 | | DWC_CTLL_SRC_INC); |
815 | ||
816 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
817 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
818 | ||
f776076b | 819 | data_width = dw->data_width[dwc->src_master]; |
a0982004 | 820 | |
3bfb1d20 HS |
821 | for_each_sg(sgl, sg, sg_len, i) { |
822 | struct dw_desc *desc; | |
69dc14b5 | 823 | u32 len, dlen, mem; |
3bfb1d20 | 824 | |
cbb796cc | 825 | mem = sg_dma_address(sg); |
69dc14b5 | 826 | len = sg_dma_len(sg); |
6bc711f6 | 827 | |
a0982004 AS |
828 | mem_width = min_t(unsigned int, |
829 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 830 | |
69dc14b5 | 831 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
832 | desc = dwc_desc_get(dwc); |
833 | if (!desc) { | |
41d5e59c | 834 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
835 | "not enough descriptors available\n"); |
836 | goto err_desc_get; | |
837 | } | |
838 | ||
3bfb1d20 HS |
839 | desc->lli.sar = mem; |
840 | desc->lli.dar = reg; | |
841 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
842 | if ((len >> mem_width) > dwc->block_size) { |
843 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
844 | mem += dlen; |
845 | len -= dlen; | |
846 | } else { | |
847 | dlen = len; | |
848 | len = 0; | |
849 | } | |
850 | ||
851 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 852 | desc->len = dlen; |
3bfb1d20 HS |
853 | |
854 | if (!first) { | |
855 | first = desc; | |
856 | } else { | |
857 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 858 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 859 | &first->tx_list); |
3bfb1d20 HS |
860 | } |
861 | prev = desc; | |
69dc14b5 VK |
862 | total_len += dlen; |
863 | ||
864 | if (len) | |
865 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
866 | } |
867 | break; | |
db8196df | 868 | case DMA_DEV_TO_MEM: |
327e6970 VK |
869 | reg_width = __fls(sconfig->src_addr_width); |
870 | reg = sconfig->src_addr; | |
871 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
872 | | DWC_CTLL_SRC_WIDTH(reg_width) |
873 | | DWC_CTLL_DST_INC | |
327e6970 VK |
874 | | DWC_CTLL_SRC_FIX); |
875 | ||
876 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
877 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 878 | |
f776076b | 879 | data_width = dw->data_width[dwc->dst_master]; |
a0982004 | 880 | |
3bfb1d20 HS |
881 | for_each_sg(sgl, sg, sg_len, i) { |
882 | struct dw_desc *desc; | |
69dc14b5 | 883 | u32 len, dlen, mem; |
3bfb1d20 | 884 | |
cbb796cc | 885 | mem = sg_dma_address(sg); |
3bfb1d20 | 886 | len = sg_dma_len(sg); |
6bc711f6 | 887 | |
a0982004 AS |
888 | mem_width = min_t(unsigned int, |
889 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 890 | |
69dc14b5 VK |
891 | slave_sg_fromdev_fill_desc: |
892 | desc = dwc_desc_get(dwc); | |
893 | if (!desc) { | |
894 | dev_err(chan2dev(chan), | |
895 | "not enough descriptors available\n"); | |
896 | goto err_desc_get; | |
897 | } | |
898 | ||
3bfb1d20 HS |
899 | desc->lli.sar = reg; |
900 | desc->lli.dar = mem; | |
901 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
902 | if ((len >> reg_width) > dwc->block_size) { |
903 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
904 | mem += dlen; |
905 | len -= dlen; | |
906 | } else { | |
907 | dlen = len; | |
908 | len = 0; | |
909 | } | |
910 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 911 | desc->len = dlen; |
3bfb1d20 HS |
912 | |
913 | if (!first) { | |
914 | first = desc; | |
915 | } else { | |
916 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 917 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 918 | &first->tx_list); |
3bfb1d20 HS |
919 | } |
920 | prev = desc; | |
69dc14b5 VK |
921 | total_len += dlen; |
922 | ||
923 | if (len) | |
924 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
925 | } |
926 | break; | |
927 | default: | |
928 | return NULL; | |
929 | } | |
930 | ||
931 | if (flags & DMA_PREP_INTERRUPT) | |
932 | /* Trigger interrupt after last block */ | |
933 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
934 | ||
935 | prev->lli.llp = 0; | |
30d38a32 | 936 | first->total_len = total_len; |
3bfb1d20 HS |
937 | |
938 | return &first->txd; | |
939 | ||
940 | err_desc_get: | |
941 | dwc_desc_put(dwc, first); | |
942 | return NULL; | |
943 | } | |
944 | ||
327e6970 VK |
945 | /* |
946 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
947 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
948 | * | |
949 | * NOTE: burst size 2 is not supported by controller. | |
950 | * | |
951 | * This can be done by finding least significant bit set: n & (n - 1) | |
952 | */ | |
953 | static inline void convert_burst(u32 *maxburst) | |
954 | { | |
955 | if (*maxburst > 1) | |
956 | *maxburst = fls(*maxburst) - 2; | |
957 | else | |
958 | *maxburst = 0; | |
959 | } | |
960 | ||
961 | static int | |
962 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
963 | { | |
964 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
965 | ||
495aea4b AS |
966 | /* Check if chan will be configured for slave transfers */ |
967 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
968 | return -EINVAL; |
969 | ||
970 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 971 | dwc->direction = sconfig->direction; |
327e6970 | 972 | |
f776076b | 973 | /* Take the request line from slave_id member */ |
78f3c9d2 | 974 | if (is_request_line_unset(dwc)) |
f776076b AB |
975 | dwc->request_line = sconfig->slave_id; |
976 | ||
327e6970 VK |
977 | convert_burst(&dwc->dma_sconfig.src_maxburst); |
978 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
21fe3c52 AS |
983 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
984 | { | |
985 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 986 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
987 | |
988 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
989 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
990 | udelay(2); | |
21fe3c52 AS |
991 | |
992 | dwc->paused = true; | |
993 | } | |
994 | ||
995 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
996 | { | |
997 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
998 | ||
999 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1000 | ||
1001 | dwc->paused = false; | |
1002 | } | |
1003 | ||
05827630 LW |
1004 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1005 | unsigned long arg) | |
3bfb1d20 HS |
1006 | { |
1007 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1008 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1009 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1010 | unsigned long flags; |
3bfb1d20 HS |
1011 | LIST_HEAD(list); |
1012 | ||
a7c57cf7 LW |
1013 | if (cmd == DMA_PAUSE) { |
1014 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1015 | |
21fe3c52 | 1016 | dwc_chan_pause(dwc); |
3bfb1d20 | 1017 | |
a7c57cf7 LW |
1018 | spin_unlock_irqrestore(&dwc->lock, flags); |
1019 | } else if (cmd == DMA_RESUME) { | |
1020 | if (!dwc->paused) | |
1021 | return 0; | |
3bfb1d20 | 1022 | |
a7c57cf7 | 1023 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1024 | |
21fe3c52 | 1025 | dwc_chan_resume(dwc); |
3bfb1d20 | 1026 | |
a7c57cf7 LW |
1027 | spin_unlock_irqrestore(&dwc->lock, flags); |
1028 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1029 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1030 | |
fed2574b AS |
1031 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1032 | ||
3f936207 | 1033 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1034 | |
a5dbff11 | 1035 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1036 | |
1037 | /* active_list entries will end up before queued entries */ | |
1038 | list_splice_init(&dwc->queue, &list); | |
1039 | list_splice_init(&dwc->active_list, &list); | |
1040 | ||
1041 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1042 | ||
1043 | /* Flush all pending and queued descriptors */ | |
1044 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1045 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1046 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1047 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1048 | } else { | |
a7c57cf7 | 1049 | return -ENXIO; |
327e6970 | 1050 | } |
c3635c78 LW |
1051 | |
1052 | return 0; | |
3bfb1d20 HS |
1053 | } |
1054 | ||
4702d524 AS |
1055 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1056 | { | |
1057 | unsigned long flags; | |
1058 | u32 residue; | |
1059 | ||
1060 | spin_lock_irqsave(&dwc->lock, flags); | |
1061 | ||
1062 | residue = dwc->residue; | |
1063 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1064 | residue -= dwc_get_sent(dwc); | |
1065 | ||
1066 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1067 | return residue; | |
1068 | } | |
1069 | ||
3bfb1d20 | 1070 | static enum dma_status |
07934481 LW |
1071 | dwc_tx_status(struct dma_chan *chan, |
1072 | dma_cookie_t cookie, | |
1073 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1074 | { |
1075 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1076 | enum dma_status ret; |
3bfb1d20 | 1077 | |
96a2af41 | 1078 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1079 | if (ret == DMA_COMPLETE) |
12381dc0 | 1080 | return ret; |
3bfb1d20 | 1081 | |
12381dc0 | 1082 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1083 | |
12381dc0 | 1084 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1085 | if (ret != DMA_COMPLETE) |
4702d524 | 1086 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1087 | |
effd5cf6 | 1088 | if (dwc->paused && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1089 | return DMA_PAUSED; |
3bfb1d20 HS |
1090 | |
1091 | return ret; | |
1092 | } | |
1093 | ||
1094 | static void dwc_issue_pending(struct dma_chan *chan) | |
1095 | { | |
1096 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1097 | ||
3bfb1d20 HS |
1098 | if (!list_empty(&dwc->queue)) |
1099 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1100 | } |
1101 | ||
aa1e6f1a | 1102 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1103 | { |
1104 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1105 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1106 | struct dw_desc *desc; | |
3bfb1d20 | 1107 | int i; |
69cea5a0 | 1108 | unsigned long flags; |
3bfb1d20 | 1109 | |
2e4c364e | 1110 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1111 | |
3bfb1d20 HS |
1112 | /* ASSERT: channel is idle */ |
1113 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1114 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1115 | return -EIO; |
1116 | } | |
1117 | ||
d3ee98cd | 1118 | dma_cookie_init(chan); |
3bfb1d20 | 1119 | |
3bfb1d20 HS |
1120 | /* |
1121 | * NOTE: some controllers may have additional features that we | |
1122 | * need to initialize here, like "scatter-gather" (which | |
1123 | * doesn't mean what you think it means), and status writeback. | |
1124 | */ | |
1125 | ||
f776076b AB |
1126 | dwc_set_masters(dwc); |
1127 | ||
69cea5a0 | 1128 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1129 | i = dwc->descs_allocated; |
1130 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1131 | dma_addr_t phys; |
1132 | ||
69cea5a0 | 1133 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1134 | |
f8122a82 | 1135 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1136 | if (!desc) |
1137 | goto err_desc_alloc; | |
3bfb1d20 | 1138 | |
f8122a82 | 1139 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1140 | |
e0bd0f8c | 1141 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1142 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1143 | desc->txd.tx_submit = dwc_tx_submit; | |
1144 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1145 | desc->txd.phys = phys; |
cbd65312 | 1146 | |
3bfb1d20 HS |
1147 | dwc_desc_put(dwc, desc); |
1148 | ||
69cea5a0 | 1149 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1150 | i = ++dwc->descs_allocated; |
1151 | } | |
1152 | ||
69cea5a0 | 1153 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1154 | |
2e4c364e | 1155 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1156 | |
cbd65312 AS |
1157 | return i; |
1158 | ||
1159 | err_desc_alloc: | |
cbd65312 AS |
1160 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1161 | ||
3bfb1d20 HS |
1162 | return i; |
1163 | } | |
1164 | ||
1165 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1166 | { | |
1167 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1168 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1169 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1170 | unsigned long flags; |
3bfb1d20 HS |
1171 | LIST_HEAD(list); |
1172 | ||
2e4c364e | 1173 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1174 | dwc->descs_allocated); |
1175 | ||
1176 | /* ASSERT: channel is idle */ | |
1177 | BUG_ON(!list_empty(&dwc->active_list)); | |
1178 | BUG_ON(!list_empty(&dwc->queue)); | |
1179 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1180 | ||
69cea5a0 | 1181 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1182 | list_splice_init(&dwc->free_list, &list); |
1183 | dwc->descs_allocated = 0; | |
61e183f8 | 1184 | dwc->initialized = false; |
f776076b | 1185 | dwc->request_line = ~0; |
3bfb1d20 HS |
1186 | |
1187 | /* Disable interrupts */ | |
1188 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1189 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1190 | ||
69cea5a0 | 1191 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1192 | |
1193 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1194 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1195 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1196 | } |
1197 | ||
2e4c364e | 1198 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1199 | } |
1200 | ||
d9de4519 HCE |
1201 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1202 | ||
1203 | /** | |
1204 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1205 | * @chan: the DMA channel to start | |
1206 | * | |
1207 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1208 | * -errno on failure. | |
1209 | */ | |
1210 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1211 | { | |
1212 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1213 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1214 | unsigned long flags; |
d9de4519 HCE |
1215 | |
1216 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1217 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1218 | return -ENODEV; | |
1219 | } | |
1220 | ||
69cea5a0 | 1221 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1222 | |
75c61225 | 1223 | /* Assert channel is idle */ |
d9de4519 HCE |
1224 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
1225 | dev_err(chan2dev(&dwc->chan), | |
1226 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1227 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1228 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1229 | return -EBUSY; |
1230 | } | |
1231 | ||
d9de4519 HCE |
1232 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1233 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1234 | ||
75c61225 | 1235 | /* Setup DMAC channel registers */ |
d9de4519 HCE |
1236 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); |
1237 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1238 | channel_writel(dwc, CTL_HI, 0); | |
1239 | ||
1240 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1241 | ||
69cea5a0 | 1242 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1243 | |
1244 | return 0; | |
1245 | } | |
1246 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1247 | ||
1248 | /** | |
1249 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1250 | * @chan: the DMA channel to stop | |
1251 | * | |
1252 | * Must be called with soft interrupts disabled. | |
1253 | */ | |
1254 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1255 | { | |
1256 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1257 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1258 | unsigned long flags; |
d9de4519 | 1259 | |
69cea5a0 | 1260 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1261 | |
3f936207 | 1262 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1263 | |
69cea5a0 | 1264 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1265 | } |
1266 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1267 | ||
1268 | /** | |
1269 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1270 | * @chan: the DMA channel to prepare | |
1271 | * @buf_addr: physical DMA address where the buffer starts | |
1272 | * @buf_len: total number of bytes for the entire buffer | |
1273 | * @period_len: number of bytes for each period | |
1274 | * @direction: transfer direction, to or from device | |
1275 | * | |
1276 | * Must be called before trying to start the transfer. Returns a valid struct | |
1277 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1278 | */ | |
1279 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1280 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1281 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1282 | { |
1283 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1284 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1285 | struct dw_cyclic_desc *cdesc; |
1286 | struct dw_cyclic_desc *retval = NULL; | |
1287 | struct dw_desc *desc; | |
1288 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1289 | unsigned long was_cyclic; |
1290 | unsigned int reg_width; | |
1291 | unsigned int periods; | |
1292 | unsigned int i; | |
69cea5a0 | 1293 | unsigned long flags; |
d9de4519 | 1294 | |
69cea5a0 | 1295 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1296 | if (dwc->nollp) { |
1297 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1298 | dev_dbg(chan2dev(&dwc->chan), | |
1299 | "channel doesn't support LLP transfers\n"); | |
1300 | return ERR_PTR(-EINVAL); | |
1301 | } | |
1302 | ||
d9de4519 | 1303 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1304 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1305 | dev_dbg(chan2dev(&dwc->chan), |
1306 | "queue and/or active list are not empty\n"); | |
1307 | return ERR_PTR(-EBUSY); | |
1308 | } | |
1309 | ||
1310 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1311 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1312 | if (was_cyclic) { |
1313 | dev_dbg(chan2dev(&dwc->chan), | |
1314 | "channel already prepared for cyclic DMA\n"); | |
1315 | return ERR_PTR(-EBUSY); | |
1316 | } | |
1317 | ||
1318 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1319 | |
f44b92f4 AS |
1320 | if (unlikely(!is_slave_direction(direction))) |
1321 | goto out_err; | |
1322 | ||
0fdb567f AS |
1323 | dwc->direction = direction; |
1324 | ||
327e6970 VK |
1325 | if (direction == DMA_MEM_TO_DEV) |
1326 | reg_width = __ffs(sconfig->dst_addr_width); | |
1327 | else | |
1328 | reg_width = __ffs(sconfig->src_addr_width); | |
1329 | ||
d9de4519 HCE |
1330 | periods = buf_len / period_len; |
1331 | ||
1332 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1333 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1334 | goto out_err; |
1335 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1336 | goto out_err; | |
1337 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1338 | goto out_err; | |
d9de4519 HCE |
1339 | |
1340 | retval = ERR_PTR(-ENOMEM); | |
1341 | ||
1342 | if (periods > NR_DESCS_PER_CHANNEL) | |
1343 | goto out_err; | |
1344 | ||
1345 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1346 | if (!cdesc) | |
1347 | goto out_err; | |
1348 | ||
1349 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1350 | if (!cdesc->desc) | |
1351 | goto out_err_alloc; | |
1352 | ||
1353 | for (i = 0; i < periods; i++) { | |
1354 | desc = dwc_desc_get(dwc); | |
1355 | if (!desc) | |
1356 | goto out_err_desc_get; | |
1357 | ||
1358 | switch (direction) { | |
db8196df | 1359 | case DMA_MEM_TO_DEV: |
327e6970 | 1360 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1361 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1362 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1363 | | DWC_CTLL_DST_WIDTH(reg_width) |
1364 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1365 | | DWC_CTLL_DST_FIX | |
1366 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1367 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1368 | |
1369 | desc->lli.ctllo |= sconfig->device_fc ? | |
1370 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1371 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1372 | ||
d9de4519 | 1373 | break; |
db8196df | 1374 | case DMA_DEV_TO_MEM: |
d9de4519 | 1375 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1376 | desc->lli.sar = sconfig->src_addr; |
1377 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1378 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1379 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1380 | | DWC_CTLL_DST_INC | |
1381 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1382 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1383 | |
1384 | desc->lli.ctllo |= sconfig->device_fc ? | |
1385 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1386 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1387 | ||
d9de4519 HCE |
1388 | break; |
1389 | default: | |
1390 | break; | |
1391 | } | |
1392 | ||
1393 | desc->lli.ctlhi = (period_len >> reg_width); | |
1394 | cdesc->desc[i] = desc; | |
1395 | ||
f8122a82 | 1396 | if (last) |
d9de4519 | 1397 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1398 | |
1399 | last = desc; | |
1400 | } | |
1401 | ||
75c61225 | 1402 | /* Let's make a cyclic list */ |
d9de4519 | 1403 | last->lli.llp = cdesc->desc[0]->txd.phys; |
d9de4519 | 1404 | |
2f45d613 AS |
1405 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1406 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1407 | buf_len, period_len, periods); | |
d9de4519 HCE |
1408 | |
1409 | cdesc->periods = periods; | |
1410 | dwc->cdesc = cdesc; | |
1411 | ||
1412 | return cdesc; | |
1413 | ||
1414 | out_err_desc_get: | |
1415 | while (i--) | |
1416 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1417 | out_err_alloc: | |
1418 | kfree(cdesc); | |
1419 | out_err: | |
1420 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1421 | return (struct dw_cyclic_desc *)retval; | |
1422 | } | |
1423 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1424 | ||
1425 | /** | |
1426 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1427 | * @chan: the DMA channel to free | |
1428 | */ | |
1429 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1430 | { | |
1431 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1432 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1433 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1434 | int i; | |
69cea5a0 | 1435 | unsigned long flags; |
d9de4519 | 1436 | |
2e4c364e | 1437 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1438 | |
1439 | if (!cdesc) | |
1440 | return; | |
1441 | ||
69cea5a0 | 1442 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1443 | |
3f936207 | 1444 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1445 | |
d9de4519 HCE |
1446 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1447 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1448 | ||
69cea5a0 | 1449 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1450 | |
1451 | for (i = 0; i < cdesc->periods; i++) | |
1452 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1453 | ||
1454 | kfree(cdesc->desc); | |
1455 | kfree(cdesc); | |
1456 | ||
1457 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1458 | } | |
1459 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1460 | ||
3bfb1d20 HS |
1461 | /*----------------------------------------------------------------------*/ |
1462 | ||
1463 | static void dw_dma_off(struct dw_dma *dw) | |
1464 | { | |
61e183f8 VK |
1465 | int i; |
1466 | ||
3bfb1d20 HS |
1467 | dma_writel(dw, CFG, 0); |
1468 | ||
1469 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1470 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1471 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1472 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1473 | ||
1474 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1475 | cpu_relax(); | |
61e183f8 VK |
1476 | |
1477 | for (i = 0; i < dw->dma.chancnt; i++) | |
1478 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1479 | } |
1480 | ||
9cade1a4 | 1481 | int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) |
a9ddb575 | 1482 | { |
3bfb1d20 HS |
1483 | struct dw_dma *dw; |
1484 | size_t size; | |
482c67ea AS |
1485 | bool autocfg; |
1486 | unsigned int dw_params; | |
1487 | unsigned int nr_channels; | |
4a63a8b3 | 1488 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1489 | int err; |
1490 | int i; | |
1491 | ||
9cade1a4 | 1492 | dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); |
482c67ea AS |
1493 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; |
1494 | ||
9cade1a4 | 1495 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
123de543 AS |
1496 | |
1497 | if (!pdata && autocfg) { | |
9cade1a4 | 1498 | pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); |
123de543 AS |
1499 | if (!pdata) |
1500 | return -ENOMEM; | |
1501 | ||
1502 | /* Fill platform data with the default values */ | |
1503 | pdata->is_private = true; | |
1504 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1505 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1506 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1507 | return -EINVAL; | |
1508 | ||
482c67ea AS |
1509 | if (autocfg) |
1510 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1511 | else | |
1512 | nr_channels = pdata->nr_channels; | |
1513 | ||
1514 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
9cade1a4 | 1515 | dw = devm_kzalloc(chip->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1516 | if (!dw) |
1517 | return -ENOMEM; | |
1518 | ||
9cade1a4 | 1519 | dw->clk = devm_clk_get(chip->dev, "hclk"); |
dbde5c29 AS |
1520 | if (IS_ERR(dw->clk)) |
1521 | return PTR_ERR(dw->clk); | |
3075528d | 1522 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1523 | |
9cade1a4 AS |
1524 | dw->regs = chip->regs; |
1525 | chip->dw = dw; | |
482c67ea | 1526 | |
75c61225 | 1527 | /* Get hardware configuration parameters */ |
a0982004 | 1528 | if (autocfg) { |
4a63a8b3 AS |
1529 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1530 | ||
a0982004 AS |
1531 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1532 | for (i = 0; i < dw->nr_masters; i++) { | |
1533 | dw->data_width[i] = | |
1534 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1535 | } | |
1536 | } else { | |
1537 | dw->nr_masters = pdata->nr_masters; | |
1538 | memcpy(dw->data_width, pdata->data_width, 4); | |
1539 | } | |
1540 | ||
11f932ec | 1541 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1542 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1543 | |
75c61225 | 1544 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1545 | dw_dma_off(dw); |
1546 | ||
75c61225 | 1547 | /* Disable BLOCK interrupts as well */ |
236b106f AS |
1548 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
1549 | ||
3783cef8 AS |
1550 | err = devm_request_irq(chip->dev, chip->irq, dw_dma_interrupt, |
1551 | IRQF_SHARED, "dw_dmac", dw); | |
3bfb1d20 | 1552 | if (err) |
dbde5c29 | 1553 | return err; |
3bfb1d20 | 1554 | |
75c61225 | 1555 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1556 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1557 | sizeof(struct dw_desc), 4, 0); |
1558 | if (!dw->desc_pool) { | |
9cade1a4 | 1559 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
f8122a82 AS |
1560 | return -ENOMEM; |
1561 | } | |
1562 | ||
3bfb1d20 HS |
1563 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1564 | ||
3bfb1d20 | 1565 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1566 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1567 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1568 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1569 | |
1570 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1571 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1572 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1573 | list_add_tail(&dwc->chan.device_node, | |
1574 | &dw->dma.channels); | |
1575 | else | |
1576 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1577 | |
93317e8e VK |
1578 | /* 7 is highest priority & 0 is lowest. */ |
1579 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1580 | dwc->priority = r; |
93317e8e VK |
1581 | else |
1582 | dwc->priority = i; | |
1583 | ||
3bfb1d20 HS |
1584 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1585 | spin_lock_init(&dwc->lock); | |
1586 | dwc->mask = 1 << i; | |
1587 | ||
1588 | INIT_LIST_HEAD(&dwc->active_list); | |
1589 | INIT_LIST_HEAD(&dwc->queue); | |
1590 | INIT_LIST_HEAD(&dwc->free_list); | |
1591 | ||
1592 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1593 | |
0fdb567f | 1594 | dwc->direction = DMA_TRANS_NONE; |
f776076b | 1595 | dwc->request_line = ~0; |
a0982004 | 1596 | |
75c61225 | 1597 | /* Hardware configuration */ |
fed2574b AS |
1598 | if (autocfg) { |
1599 | unsigned int dwc_params; | |
9cade1a4 | 1600 | void __iomem *addr = chip->regs + r * sizeof(u32); |
fed2574b | 1601 | |
9cade1a4 | 1602 | dwc_params = dma_read_byaddr(addr, DWC_PARAMS); |
fed2574b | 1603 | |
9cade1a4 AS |
1604 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1605 | dwc_params); | |
985a6c7d | 1606 | |
1d566f11 AS |
1607 | /* |
1608 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1609 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1610 | * up to 0x0a for 4095. |
1611 | */ | |
4a63a8b3 AS |
1612 | dwc->block_size = |
1613 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1614 | dwc->nollp = |
1615 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1616 | } else { | |
4a63a8b3 | 1617 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1618 | |
1619 | /* Check if channel supports multi block transfer */ | |
1620 | channel_writel(dwc, LLP, 0xfffffffc); | |
1621 | dwc->nollp = | |
1622 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1623 | channel_writel(dwc, LLP, 0); | |
1624 | } | |
3bfb1d20 HS |
1625 | } |
1626 | ||
11f932ec | 1627 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1628 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1629 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1630 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1631 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1632 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1633 | ||
3bfb1d20 HS |
1634 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1635 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1636 | if (pdata->is_private) |
1637 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
9cade1a4 | 1638 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1639 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1640 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1641 | ||
1642 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1643 | ||
1644 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1645 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1646 | |
07934481 | 1647 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1648 | dw->dma.device_issue_pending = dwc_issue_pending; |
1649 | ||
1650 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1651 | ||
9cade1a4 | 1652 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
21d43f49 | 1653 | nr_channels); |
3bfb1d20 HS |
1654 | |
1655 | dma_async_device_register(&dw->dma); | |
1656 | ||
1657 | return 0; | |
3bfb1d20 | 1658 | } |
9cade1a4 | 1659 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1660 | |
9cade1a4 | 1661 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1662 | { |
9cade1a4 | 1663 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1664 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 HS |
1665 | |
1666 | dw_dma_off(dw); | |
1667 | dma_async_device_unregister(&dw->dma); | |
1668 | ||
3bfb1d20 HS |
1669 | tasklet_kill(&dw->tasklet); |
1670 | ||
1671 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1672 | chan.device_node) { | |
1673 | list_del(&dwc->chan.device_node); | |
1674 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1675 | } | |
1676 | ||
3bfb1d20 HS |
1677 | return 0; |
1678 | } | |
9cade1a4 | 1679 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1680 | |
9cade1a4 | 1681 | void dw_dma_shutdown(struct dw_dma_chip *chip) |
3bfb1d20 | 1682 | { |
9cade1a4 | 1683 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1684 | |
6168d567 | 1685 | dw_dma_off(dw); |
3075528d | 1686 | clk_disable_unprepare(dw->clk); |
3bfb1d20 | 1687 | } |
9cade1a4 | 1688 | EXPORT_SYMBOL_GPL(dw_dma_shutdown); |
3bfb1d20 | 1689 | |
9cade1a4 AS |
1690 | #ifdef CONFIG_PM_SLEEP |
1691 | ||
1692 | int dw_dma_suspend(struct dw_dma_chip *chip) | |
3bfb1d20 | 1693 | { |
9cade1a4 | 1694 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1695 | |
6168d567 | 1696 | dw_dma_off(dw); |
3075528d | 1697 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1698 | |
3bfb1d20 HS |
1699 | return 0; |
1700 | } | |
9cade1a4 | 1701 | EXPORT_SYMBOL_GPL(dw_dma_suspend); |
3bfb1d20 | 1702 | |
9cade1a4 | 1703 | int dw_dma_resume(struct dw_dma_chip *chip) |
3bfb1d20 | 1704 | { |
9cade1a4 | 1705 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1706 | |
3075528d | 1707 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1708 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1709 | |
3bfb1d20 | 1710 | return 0; |
3bfb1d20 | 1711 | } |
9cade1a4 | 1712 | EXPORT_SYMBOL_GPL(dw_dma_resume); |
3bfb1d20 | 1713 | |
9cade1a4 | 1714 | #endif /* CONFIG_PM_SLEEP */ |
3bfb1d20 HS |
1715 | |
1716 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1717 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1718 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1719 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |