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9cade1a4 AS |
1 | /* |
2 | * Platform driver for the Synopsys DesignWare DMA Controller | |
3 | * | |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
5 | * Copyright (C) 2010-2011 ST Microelectronics | |
6 | * Copyright (C) 2013 Intel Corporation | |
7 | * | |
8 | * Some parts of this driver are derived from the original dw_dmac. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/clk.h> | |
6acf3998 | 18 | #include <linux/pm_runtime.h> |
9cade1a4 AS |
19 | #include <linux/platform_device.h> |
20 | #include <linux/dmaengine.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_dma.h> | |
24 | #include <linux/acpi.h> | |
25 | #include <linux/acpi_dma.h> | |
26 | ||
27 | #include "internal.h" | |
28 | ||
a104a45b AS |
29 | #define DRV_NAME "dw_dmac" |
30 | ||
9cade1a4 AS |
31 | static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, |
32 | struct of_dma *ofdma) | |
33 | { | |
34 | struct dw_dma *dw = ofdma->of_dma_data; | |
4d130de2 AS |
35 | struct dw_dma_slave slave = { |
36 | .dma_dev = dw->dma.dev, | |
9cade1a4 AS |
37 | }; |
38 | dma_cap_mask_t cap; | |
39 | ||
40 | if (dma_spec->args_count != 3) | |
41 | return NULL; | |
42 | ||
4d130de2 AS |
43 | slave.src_id = dma_spec->args[0]; |
44 | slave.dst_id = dma_spec->args[0]; | |
c422025c AS |
45 | slave.m_master = dma_spec->args[1]; |
46 | slave.p_master = dma_spec->args[2]; | |
9cade1a4 | 47 | |
4d130de2 AS |
48 | if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS || |
49 | slave.dst_id >= DW_DMA_MAX_NR_REQUESTS || | |
161c3d04 AS |
50 | slave.m_master >= dw->pdata->nr_masters || |
51 | slave.p_master >= dw->pdata->nr_masters)) | |
9cade1a4 AS |
52 | return NULL; |
53 | ||
54 | dma_cap_zero(cap); | |
55 | dma_cap_set(DMA_SLAVE, cap); | |
56 | ||
57 | /* TODO: there should be a simpler way to do this */ | |
4d130de2 | 58 | return dma_request_channel(cap, dw_dma_filter, &slave); |
9cade1a4 AS |
59 | } |
60 | ||
61 | #ifdef CONFIG_ACPI | |
62 | static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param) | |
63 | { | |
9cade1a4 | 64 | struct acpi_dma_spec *dma_spec = param; |
4d130de2 AS |
65 | struct dw_dma_slave slave = { |
66 | .dma_dev = dma_spec->dev, | |
67 | .src_id = dma_spec->slave_id, | |
68 | .dst_id = dma_spec->slave_id, | |
c422025c AS |
69 | .m_master = 0, |
70 | .p_master = 1, | |
4d130de2 | 71 | }; |
9cade1a4 | 72 | |
4d130de2 | 73 | return dw_dma_filter(chan, &slave); |
9cade1a4 AS |
74 | } |
75 | ||
76 | static void dw_dma_acpi_controller_register(struct dw_dma *dw) | |
77 | { | |
78 | struct device *dev = dw->dma.dev; | |
79 | struct acpi_dma_filter_info *info; | |
80 | int ret; | |
81 | ||
82 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
83 | if (!info) | |
84 | return; | |
85 | ||
86 | dma_cap_zero(info->dma_cap); | |
87 | dma_cap_set(DMA_SLAVE, info->dma_cap); | |
88 | info->filter_fn = dw_dma_acpi_filter; | |
89 | ||
90 | ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate, | |
91 | info); | |
92 | if (ret) | |
93 | dev_err(dev, "could not register acpi_dma_controller\n"); | |
94 | } | |
95 | #else /* !CONFIG_ACPI */ | |
96 | static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} | |
97 | #endif /* !CONFIG_ACPI */ | |
98 | ||
99 | #ifdef CONFIG_OF | |
100 | static struct dw_dma_platform_data * | |
101 | dw_dma_parse_dt(struct platform_device *pdev) | |
102 | { | |
103 | struct device_node *np = pdev->dev.of_node; | |
104 | struct dw_dma_platform_data *pdata; | |
bd2c6636 | 105 | u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS]; |
969f750f | 106 | u32 nr_masters; |
2b574ba9 | 107 | u32 nr_channels; |
9cade1a4 AS |
108 | |
109 | if (!np) { | |
110 | dev_err(&pdev->dev, "Missing DT data\n"); | |
111 | return NULL; | |
112 | } | |
113 | ||
969f750f AS |
114 | if (of_property_read_u32(np, "dma-masters", &nr_masters)) |
115 | return NULL; | |
116 | if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS) | |
117 | return NULL; | |
118 | ||
2b574ba9 MR |
119 | if (of_property_read_u32(np, "dma-channels", &nr_channels)) |
120 | return NULL; | |
bd2c6636 EP |
121 | if (nr_channels > DW_DMA_MAX_NR_CHANNELS) |
122 | return NULL; | |
2b574ba9 | 123 | |
9cade1a4 AS |
124 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
125 | if (!pdata) | |
126 | return NULL; | |
127 | ||
969f750f | 128 | pdata->nr_masters = nr_masters; |
2b574ba9 | 129 | pdata->nr_channels = nr_channels; |
9cade1a4 AS |
130 | |
131 | if (of_property_read_bool(np, "is_private")) | |
132 | pdata->is_private = true; | |
133 | ||
258f2277 EP |
134 | /* |
135 | * All known devices, which use DT for configuration, support | |
136 | * memory-to-memory transfers. So enable it by default. | |
137 | */ | |
138 | pdata->is_memcpy = true; | |
139 | ||
9cade1a4 AS |
140 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) |
141 | pdata->chan_allocation_order = (unsigned char)tmp; | |
142 | ||
143 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
144 | pdata->chan_priority = tmp; | |
145 | ||
146 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
147 | pdata->block_size = tmp; | |
148 | ||
2e65060e | 149 | if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) { |
969f750f | 150 | for (tmp = 0; tmp < nr_masters; tmp++) |
9cade1a4 | 151 | pdata->data_width[tmp] = arr[tmp]; |
2e65060e AS |
152 | } else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) { |
153 | for (tmp = 0; tmp < nr_masters; tmp++) | |
154 | pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); | |
969f750f | 155 | } |
9cade1a4 | 156 | |
bd2c6636 EP |
157 | if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) { |
158 | for (tmp = 0; tmp < nr_channels; tmp++) | |
159 | pdata->multi_block[tmp] = mb[tmp]; | |
160 | } else { | |
161 | for (tmp = 0; tmp < nr_channels; tmp++) | |
162 | pdata->multi_block[tmp] = 1; | |
163 | } | |
164 | ||
9cade1a4 AS |
165 | return pdata; |
166 | } | |
167 | #else | |
168 | static inline struct dw_dma_platform_data * | |
169 | dw_dma_parse_dt(struct platform_device *pdev) | |
170 | { | |
171 | return NULL; | |
172 | } | |
173 | #endif | |
174 | ||
175 | static int dw_probe(struct platform_device *pdev) | |
176 | { | |
177 | struct dw_dma_chip *chip; | |
178 | struct device *dev = &pdev->dev; | |
179 | struct resource *mem; | |
3a14c66d | 180 | const struct dw_dma_platform_data *pdata; |
9cade1a4 AS |
181 | int err; |
182 | ||
183 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); | |
184 | if (!chip) | |
185 | return -ENOMEM; | |
186 | ||
187 | chip->irq = platform_get_irq(pdev, 0); | |
188 | if (chip->irq < 0) | |
189 | return chip->irq; | |
190 | ||
191 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
192 | chip->regs = devm_ioremap_resource(dev, mem); | |
193 | if (IS_ERR(chip->regs)) | |
194 | return PTR_ERR(chip->regs); | |
195 | ||
24353b8b RK |
196 | err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
197 | if (err) | |
198 | return err; | |
9cade1a4 AS |
199 | |
200 | pdata = dev_get_platdata(dev); | |
201 | if (!pdata) | |
202 | pdata = dw_dma_parse_dt(pdev); | |
203 | ||
204 | chip->dev = dev; | |
08d62f58 | 205 | chip->id = pdev->id; |
3a14c66d | 206 | chip->pdata = pdata; |
9cade1a4 | 207 | |
a15636e8 AS |
208 | chip->clk = devm_clk_get(chip->dev, "hclk"); |
209 | if (IS_ERR(chip->clk)) | |
210 | return PTR_ERR(chip->clk); | |
211 | err = clk_prepare_enable(chip->clk); | |
9cade1a4 AS |
212 | if (err) |
213 | return err; | |
214 | ||
6acf3998 AS |
215 | pm_runtime_enable(&pdev->dev); |
216 | ||
3a14c66d | 217 | err = dw_dma_probe(chip); |
a15636e8 AS |
218 | if (err) |
219 | goto err_dw_dma_probe; | |
220 | ||
9cade1a4 AS |
221 | platform_set_drvdata(pdev, chip); |
222 | ||
223 | if (pdev->dev.of_node) { | |
224 | err = of_dma_controller_register(pdev->dev.of_node, | |
225 | dw_dma_of_xlate, chip->dw); | |
226 | if (err) | |
227 | dev_err(&pdev->dev, | |
228 | "could not register of_dma_controller\n"); | |
229 | } | |
230 | ||
231 | if (ACPI_HANDLE(&pdev->dev)) | |
232 | dw_dma_acpi_controller_register(chip->dw); | |
233 | ||
234 | return 0; | |
a15636e8 AS |
235 | |
236 | err_dw_dma_probe: | |
6acf3998 | 237 | pm_runtime_disable(&pdev->dev); |
a15636e8 AS |
238 | clk_disable_unprepare(chip->clk); |
239 | return err; | |
9cade1a4 AS |
240 | } |
241 | ||
242 | static int dw_remove(struct platform_device *pdev) | |
243 | { | |
244 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
245 | ||
246 | if (pdev->dev.of_node) | |
247 | of_dma_controller_free(pdev->dev.of_node); | |
248 | ||
a15636e8 | 249 | dw_dma_remove(chip); |
6acf3998 | 250 | pm_runtime_disable(&pdev->dev); |
a15636e8 AS |
251 | clk_disable_unprepare(chip->clk); |
252 | ||
253 | return 0; | |
9cade1a4 AS |
254 | } |
255 | ||
256 | static void dw_shutdown(struct platform_device *pdev) | |
257 | { | |
258 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
259 | ||
32146588 AS |
260 | /* |
261 | * We have to call dw_dma_disable() to stop any ongoing transfer. On | |
262 | * some platforms we can't do that since DMA device is powered off. | |
263 | * Moreover we have no possibility to check if the platform is affected | |
264 | * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put() | |
265 | * unconditionally. On the other hand we can't use | |
266 | * pm_runtime_suspended() because runtime PM framework is not fully | |
267 | * used by the driver. | |
268 | */ | |
269 | pm_runtime_get_sync(chip->dev); | |
2540f74b | 270 | dw_dma_disable(chip); |
32146588 AS |
271 | pm_runtime_put_sync_suspend(chip->dev); |
272 | ||
a15636e8 | 273 | clk_disable_unprepare(chip->clk); |
9cade1a4 AS |
274 | } |
275 | ||
276 | #ifdef CONFIG_OF | |
277 | static const struct of_device_id dw_dma_of_id_table[] = { | |
278 | { .compatible = "snps,dma-spear1340" }, | |
279 | {} | |
280 | }; | |
281 | MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); | |
282 | #endif | |
283 | ||
284 | #ifdef CONFIG_ACPI | |
285 | static const struct acpi_device_id dw_dma_acpi_id_table[] = { | |
bc0bb1fd | 286 | { "INTL9C60", 0 }, |
9cade1a4 AS |
287 | { } |
288 | }; | |
be480dcb | 289 | MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table); |
9cade1a4 AS |
290 | #endif |
291 | ||
292 | #ifdef CONFIG_PM_SLEEP | |
293 | ||
067bd4fd | 294 | static int dw_suspend_late(struct device *dev) |
9cade1a4 AS |
295 | { |
296 | struct platform_device *pdev = to_platform_device(dev); | |
297 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
298 | ||
2540f74b | 299 | dw_dma_disable(chip); |
a15636e8 AS |
300 | clk_disable_unprepare(chip->clk); |
301 | ||
302 | return 0; | |
9cade1a4 AS |
303 | } |
304 | ||
067bd4fd | 305 | static int dw_resume_early(struct device *dev) |
9cade1a4 AS |
306 | { |
307 | struct platform_device *pdev = to_platform_device(dev); | |
308 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
309 | ||
a15636e8 | 310 | clk_prepare_enable(chip->clk); |
2540f74b | 311 | return dw_dma_enable(chip); |
9cade1a4 AS |
312 | } |
313 | ||
067bd4fd | 314 | #endif /* CONFIG_PM_SLEEP */ |
9cade1a4 AS |
315 | |
316 | static const struct dev_pm_ops dw_dev_pm_ops = { | |
067bd4fd | 317 | SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early) |
9cade1a4 AS |
318 | }; |
319 | ||
320 | static struct platform_driver dw_driver = { | |
321 | .probe = dw_probe, | |
322 | .remove = dw_remove, | |
2540f74b | 323 | .shutdown = dw_shutdown, |
9cade1a4 | 324 | .driver = { |
a104a45b | 325 | .name = DRV_NAME, |
9cade1a4 AS |
326 | .pm = &dw_dev_pm_ops, |
327 | .of_match_table = of_match_ptr(dw_dma_of_id_table), | |
328 | .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table), | |
329 | }, | |
330 | }; | |
331 | ||
332 | static int __init dw_init(void) | |
333 | { | |
334 | return platform_driver_register(&dw_driver); | |
335 | } | |
336 | subsys_initcall(dw_init); | |
337 | ||
338 | static void __exit dw_exit(void) | |
339 | { | |
340 | platform_driver_unregister(&dw_driver); | |
341 | } | |
342 | module_exit(dw_exit); | |
343 | ||
344 | MODULE_LICENSE("GPL v2"); | |
345 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver"); | |
a104a45b | 346 | MODULE_ALIAS("platform:" DRV_NAME); |