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9cade1a4 AS |
1 | /* |
2 | * Platform driver for the Synopsys DesignWare DMA Controller | |
3 | * | |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
5 | * Copyright (C) 2010-2011 ST Microelectronics | |
6 | * Copyright (C) 2013 Intel Corporation | |
7 | * | |
8 | * Some parts of this driver are derived from the original dw_dmac. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/clk.h> | |
6acf3998 | 18 | #include <linux/pm_runtime.h> |
9cade1a4 AS |
19 | #include <linux/platform_device.h> |
20 | #include <linux/dmaengine.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_dma.h> | |
24 | #include <linux/acpi.h> | |
25 | #include <linux/acpi_dma.h> | |
26 | ||
27 | #include "internal.h" | |
28 | ||
a104a45b AS |
29 | #define DRV_NAME "dw_dmac" |
30 | ||
9cade1a4 AS |
31 | static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, |
32 | struct of_dma *ofdma) | |
33 | { | |
34 | struct dw_dma *dw = ofdma->of_dma_data; | |
4d130de2 AS |
35 | struct dw_dma_slave slave = { |
36 | .dma_dev = dw->dma.dev, | |
9cade1a4 AS |
37 | }; |
38 | dma_cap_mask_t cap; | |
39 | ||
40 | if (dma_spec->args_count != 3) | |
41 | return NULL; | |
42 | ||
4d130de2 AS |
43 | slave.src_id = dma_spec->args[0]; |
44 | slave.dst_id = dma_spec->args[0]; | |
c422025c AS |
45 | slave.m_master = dma_spec->args[1]; |
46 | slave.p_master = dma_spec->args[2]; | |
9cade1a4 | 47 | |
4d130de2 AS |
48 | if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS || |
49 | slave.dst_id >= DW_DMA_MAX_NR_REQUESTS || | |
161c3d04 AS |
50 | slave.m_master >= dw->pdata->nr_masters || |
51 | slave.p_master >= dw->pdata->nr_masters)) | |
9cade1a4 AS |
52 | return NULL; |
53 | ||
54 | dma_cap_zero(cap); | |
55 | dma_cap_set(DMA_SLAVE, cap); | |
56 | ||
57 | /* TODO: there should be a simpler way to do this */ | |
4d130de2 | 58 | return dma_request_channel(cap, dw_dma_filter, &slave); |
9cade1a4 AS |
59 | } |
60 | ||
61 | #ifdef CONFIG_ACPI | |
62 | static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param) | |
63 | { | |
9cade1a4 | 64 | struct acpi_dma_spec *dma_spec = param; |
4d130de2 AS |
65 | struct dw_dma_slave slave = { |
66 | .dma_dev = dma_spec->dev, | |
67 | .src_id = dma_spec->slave_id, | |
68 | .dst_id = dma_spec->slave_id, | |
c422025c AS |
69 | .m_master = 0, |
70 | .p_master = 1, | |
4d130de2 | 71 | }; |
9cade1a4 | 72 | |
4d130de2 | 73 | return dw_dma_filter(chan, &slave); |
9cade1a4 AS |
74 | } |
75 | ||
76 | static void dw_dma_acpi_controller_register(struct dw_dma *dw) | |
77 | { | |
78 | struct device *dev = dw->dma.dev; | |
79 | struct acpi_dma_filter_info *info; | |
80 | int ret; | |
81 | ||
82 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
83 | if (!info) | |
84 | return; | |
85 | ||
86 | dma_cap_zero(info->dma_cap); | |
87 | dma_cap_set(DMA_SLAVE, info->dma_cap); | |
88 | info->filter_fn = dw_dma_acpi_filter; | |
89 | ||
90 | ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate, | |
91 | info); | |
92 | if (ret) | |
93 | dev_err(dev, "could not register acpi_dma_controller\n"); | |
94 | } | |
95 | #else /* !CONFIG_ACPI */ | |
96 | static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {} | |
97 | #endif /* !CONFIG_ACPI */ | |
98 | ||
99 | #ifdef CONFIG_OF | |
100 | static struct dw_dma_platform_data * | |
101 | dw_dma_parse_dt(struct platform_device *pdev) | |
102 | { | |
103 | struct device_node *np = pdev->dev.of_node; | |
104 | struct dw_dma_platform_data *pdata; | |
d8ded50f | 105 | u32 tmp, arr[DW_DMA_MAX_NR_MASTERS]; |
969f750f | 106 | u32 nr_masters; |
2b574ba9 | 107 | u32 nr_channels; |
9cade1a4 AS |
108 | |
109 | if (!np) { | |
110 | dev_err(&pdev->dev, "Missing DT data\n"); | |
111 | return NULL; | |
112 | } | |
113 | ||
969f750f AS |
114 | if (of_property_read_u32(np, "dma-masters", &nr_masters)) |
115 | return NULL; | |
116 | if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS) | |
117 | return NULL; | |
118 | ||
2b574ba9 MR |
119 | if (of_property_read_u32(np, "dma-channels", &nr_channels)) |
120 | return NULL; | |
121 | ||
9cade1a4 AS |
122 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
123 | if (!pdata) | |
124 | return NULL; | |
125 | ||
969f750f | 126 | pdata->nr_masters = nr_masters; |
2b574ba9 | 127 | pdata->nr_channels = nr_channels; |
9cade1a4 AS |
128 | |
129 | if (of_property_read_bool(np, "is_private")) | |
130 | pdata->is_private = true; | |
131 | ||
258f2277 EP |
132 | /* |
133 | * All known devices, which use DT for configuration, support | |
134 | * memory-to-memory transfers. So enable it by default. | |
135 | */ | |
136 | pdata->is_memcpy = true; | |
137 | ||
9cade1a4 AS |
138 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) |
139 | pdata->chan_allocation_order = (unsigned char)tmp; | |
140 | ||
141 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
142 | pdata->chan_priority = tmp; | |
143 | ||
144 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
145 | pdata->block_size = tmp; | |
146 | ||
2e65060e | 147 | if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) { |
969f750f | 148 | for (tmp = 0; tmp < nr_masters; tmp++) |
9cade1a4 | 149 | pdata->data_width[tmp] = arr[tmp]; |
2e65060e AS |
150 | } else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) { |
151 | for (tmp = 0; tmp < nr_masters; tmp++) | |
152 | pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); | |
969f750f | 153 | } |
9cade1a4 AS |
154 | |
155 | return pdata; | |
156 | } | |
157 | #else | |
158 | static inline struct dw_dma_platform_data * | |
159 | dw_dma_parse_dt(struct platform_device *pdev) | |
160 | { | |
161 | return NULL; | |
162 | } | |
163 | #endif | |
164 | ||
165 | static int dw_probe(struct platform_device *pdev) | |
166 | { | |
167 | struct dw_dma_chip *chip; | |
168 | struct device *dev = &pdev->dev; | |
169 | struct resource *mem; | |
3a14c66d | 170 | const struct dw_dma_platform_data *pdata; |
9cade1a4 AS |
171 | int err; |
172 | ||
173 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); | |
174 | if (!chip) | |
175 | return -ENOMEM; | |
176 | ||
177 | chip->irq = platform_get_irq(pdev, 0); | |
178 | if (chip->irq < 0) | |
179 | return chip->irq; | |
180 | ||
181 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
182 | chip->regs = devm_ioremap_resource(dev, mem); | |
183 | if (IS_ERR(chip->regs)) | |
184 | return PTR_ERR(chip->regs); | |
185 | ||
24353b8b RK |
186 | err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
187 | if (err) | |
188 | return err; | |
9cade1a4 AS |
189 | |
190 | pdata = dev_get_platdata(dev); | |
191 | if (!pdata) | |
192 | pdata = dw_dma_parse_dt(pdev); | |
193 | ||
194 | chip->dev = dev; | |
3a14c66d | 195 | chip->pdata = pdata; |
9cade1a4 | 196 | |
a15636e8 AS |
197 | chip->clk = devm_clk_get(chip->dev, "hclk"); |
198 | if (IS_ERR(chip->clk)) | |
199 | return PTR_ERR(chip->clk); | |
200 | err = clk_prepare_enable(chip->clk); | |
9cade1a4 AS |
201 | if (err) |
202 | return err; | |
203 | ||
6acf3998 AS |
204 | pm_runtime_enable(&pdev->dev); |
205 | ||
3a14c66d | 206 | err = dw_dma_probe(chip); |
a15636e8 AS |
207 | if (err) |
208 | goto err_dw_dma_probe; | |
209 | ||
9cade1a4 AS |
210 | platform_set_drvdata(pdev, chip); |
211 | ||
212 | if (pdev->dev.of_node) { | |
213 | err = of_dma_controller_register(pdev->dev.of_node, | |
214 | dw_dma_of_xlate, chip->dw); | |
215 | if (err) | |
216 | dev_err(&pdev->dev, | |
217 | "could not register of_dma_controller\n"); | |
218 | } | |
219 | ||
220 | if (ACPI_HANDLE(&pdev->dev)) | |
221 | dw_dma_acpi_controller_register(chip->dw); | |
222 | ||
223 | return 0; | |
a15636e8 AS |
224 | |
225 | err_dw_dma_probe: | |
6acf3998 | 226 | pm_runtime_disable(&pdev->dev); |
a15636e8 AS |
227 | clk_disable_unprepare(chip->clk); |
228 | return err; | |
9cade1a4 AS |
229 | } |
230 | ||
231 | static int dw_remove(struct platform_device *pdev) | |
232 | { | |
233 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
234 | ||
235 | if (pdev->dev.of_node) | |
236 | of_dma_controller_free(pdev->dev.of_node); | |
237 | ||
a15636e8 | 238 | dw_dma_remove(chip); |
6acf3998 | 239 | pm_runtime_disable(&pdev->dev); |
a15636e8 AS |
240 | clk_disable_unprepare(chip->clk); |
241 | ||
242 | return 0; | |
9cade1a4 AS |
243 | } |
244 | ||
245 | static void dw_shutdown(struct platform_device *pdev) | |
246 | { | |
247 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
248 | ||
32146588 AS |
249 | /* |
250 | * We have to call dw_dma_disable() to stop any ongoing transfer. On | |
251 | * some platforms we can't do that since DMA device is powered off. | |
252 | * Moreover we have no possibility to check if the platform is affected | |
253 | * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put() | |
254 | * unconditionally. On the other hand we can't use | |
255 | * pm_runtime_suspended() because runtime PM framework is not fully | |
256 | * used by the driver. | |
257 | */ | |
258 | pm_runtime_get_sync(chip->dev); | |
2540f74b | 259 | dw_dma_disable(chip); |
32146588 AS |
260 | pm_runtime_put_sync_suspend(chip->dev); |
261 | ||
a15636e8 | 262 | clk_disable_unprepare(chip->clk); |
9cade1a4 AS |
263 | } |
264 | ||
265 | #ifdef CONFIG_OF | |
266 | static const struct of_device_id dw_dma_of_id_table[] = { | |
267 | { .compatible = "snps,dma-spear1340" }, | |
268 | {} | |
269 | }; | |
270 | MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); | |
271 | #endif | |
272 | ||
273 | #ifdef CONFIG_ACPI | |
274 | static const struct acpi_device_id dw_dma_acpi_id_table[] = { | |
bc0bb1fd | 275 | { "INTL9C60", 0 }, |
9cade1a4 AS |
276 | { } |
277 | }; | |
be480dcb | 278 | MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table); |
9cade1a4 AS |
279 | #endif |
280 | ||
281 | #ifdef CONFIG_PM_SLEEP | |
282 | ||
067bd4fd | 283 | static int dw_suspend_late(struct device *dev) |
9cade1a4 AS |
284 | { |
285 | struct platform_device *pdev = to_platform_device(dev); | |
286 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
287 | ||
2540f74b | 288 | dw_dma_disable(chip); |
a15636e8 AS |
289 | clk_disable_unprepare(chip->clk); |
290 | ||
291 | return 0; | |
9cade1a4 AS |
292 | } |
293 | ||
067bd4fd | 294 | static int dw_resume_early(struct device *dev) |
9cade1a4 AS |
295 | { |
296 | struct platform_device *pdev = to_platform_device(dev); | |
297 | struct dw_dma_chip *chip = platform_get_drvdata(pdev); | |
298 | ||
a15636e8 | 299 | clk_prepare_enable(chip->clk); |
2540f74b | 300 | return dw_dma_enable(chip); |
9cade1a4 AS |
301 | } |
302 | ||
067bd4fd | 303 | #endif /* CONFIG_PM_SLEEP */ |
9cade1a4 AS |
304 | |
305 | static const struct dev_pm_ops dw_dev_pm_ops = { | |
067bd4fd | 306 | SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early) |
9cade1a4 AS |
307 | }; |
308 | ||
309 | static struct platform_driver dw_driver = { | |
310 | .probe = dw_probe, | |
311 | .remove = dw_remove, | |
2540f74b | 312 | .shutdown = dw_shutdown, |
9cade1a4 | 313 | .driver = { |
a104a45b | 314 | .name = DRV_NAME, |
9cade1a4 AS |
315 | .pm = &dw_dev_pm_ops, |
316 | .of_match_table = of_match_ptr(dw_dma_of_id_table), | |
317 | .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table), | |
318 | }, | |
319 | }; | |
320 | ||
321 | static int __init dw_init(void) | |
322 | { | |
323 | return platform_driver_register(&dw_driver); | |
324 | } | |
325 | subsys_initcall(dw_init); | |
326 | ||
327 | static void __exit dw_exit(void) | |
328 | { | |
329 | platform_driver_unregister(&dw_driver); | |
330 | } | |
331 | module_exit(dw_exit); | |
332 | ||
333 | MODULE_LICENSE("GPL v2"); | |
334 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver"); | |
a104a45b | 335 | MODULE_ALIAS("platform:" DRV_NAME); |