]>
Commit | Line | Data |
---|---|---|
3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
d3f797d9 | 20 | #include <linux/of.h> |
3bfb1d20 HS |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | ||
26 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 27 | #include "dmaengine.h" |
3bfb1d20 HS |
28 | |
29 | /* | |
30 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
31 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
32 | * of which use ARM any more). See the "Databook" from Synopsys for | |
33 | * information beyond what licensees probably provide. | |
34 | * | |
35 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
36 | * which does not support descriptor writeback. | |
37 | */ | |
38 | ||
327e6970 VK |
39 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
40 | struct dw_dma_slave *__slave = (_chan->private); \ | |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ | |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
43 | int _dms = __slave ? __slave->dst_master : 0; \ | |
44 | int _sms = __slave ? __slave->src_master : 1; \ | |
45 | u8 _smsize = __slave ? _sconfig->src_maxburst : \ | |
46 | DW_DMA_MSIZE_16; \ | |
47 | u8 _dmsize = __slave ? _sconfig->dst_maxburst : \ | |
48 | DW_DMA_MSIZE_16; \ | |
f301c062 | 49 | \ |
327e6970 VK |
50 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
51 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
52 | | DWC_CTLL_LLP_D_EN \ |
53 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
54 | | DWC_CTLL_DMS(_dms) \ |
55 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 56 | }) |
3bfb1d20 HS |
57 | |
58 | /* | |
59 | * This is configuration-dependent and usually a funny size like 4095. | |
3bfb1d20 HS |
60 | * |
61 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
418e7407 | 62 | * words, we can do 16380 bytes per descriptor. |
3bfb1d20 HS |
63 | * |
64 | * This parameter is also system-specific. | |
65 | */ | |
418e7407 | 66 | #define DWC_MAX_COUNT 4095U |
3bfb1d20 HS |
67 | |
68 | /* | |
69 | * Number of descriptors to allocate for each channel. This should be | |
70 | * made configurable somehow; preferably, the clients (at least the | |
71 | * ones using slave transfers) should be able to give us a hint. | |
72 | */ | |
73 | #define NR_DESCS_PER_CHANNEL 64 | |
74 | ||
75 | /*----------------------------------------------------------------------*/ | |
76 | ||
77 | /* | |
78 | * Because we're not relying on writeback from the controller (it may not | |
79 | * even be configured into the core!) we don't need to use dma_pool. These | |
80 | * descriptors -- and associated data -- are cacheable. We do need to make | |
81 | * sure their dcache entries are written back before handing them off to | |
82 | * the controller, though. | |
83 | */ | |
84 | ||
41d5e59c DW |
85 | static struct device *chan2dev(struct dma_chan *chan) |
86 | { | |
87 | return &chan->dev->device; | |
88 | } | |
89 | static struct device *chan2parent(struct dma_chan *chan) | |
90 | { | |
91 | return chan->dev->device.parent; | |
92 | } | |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
95 | { | |
96 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
97 | } | |
98 | ||
3bfb1d20 HS |
99 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
100 | { | |
101 | struct dw_desc *desc, *_desc; | |
102 | struct dw_desc *ret = NULL; | |
103 | unsigned int i = 0; | |
69cea5a0 | 104 | unsigned long flags; |
3bfb1d20 | 105 | |
69cea5a0 | 106 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
107 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
108 | if (async_tx_test_ack(&desc->txd)) { | |
109 | list_del(&desc->desc_node); | |
110 | ret = desc; | |
111 | break; | |
112 | } | |
41d5e59c | 113 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 HS |
114 | i++; |
115 | } | |
69cea5a0 | 116 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 117 | |
41d5e59c | 118 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
119 | |
120 | return ret; | |
121 | } | |
122 | ||
123 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
124 | { | |
125 | struct dw_desc *child; | |
126 | ||
e0bd0f8c | 127 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 128 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
129 | child->txd.phys, sizeof(child->lli), |
130 | DMA_TO_DEVICE); | |
41d5e59c | 131 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
132 | desc->txd.phys, sizeof(desc->lli), |
133 | DMA_TO_DEVICE); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Move a descriptor, including any children, to the free list. | |
138 | * `desc' must not be on any lists. | |
139 | */ | |
140 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
141 | { | |
69cea5a0 VK |
142 | unsigned long flags; |
143 | ||
3bfb1d20 HS |
144 | if (desc) { |
145 | struct dw_desc *child; | |
146 | ||
147 | dwc_sync_desc_for_cpu(dwc, desc); | |
148 | ||
69cea5a0 | 149 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 150 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 151 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
152 | "moving child desc %p to freelist\n", |
153 | child); | |
e0bd0f8c | 154 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 155 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 156 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 157 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
158 | } |
159 | } | |
160 | ||
61e183f8 VK |
161 | static void dwc_initialize(struct dw_dma_chan *dwc) |
162 | { | |
163 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
164 | struct dw_dma_slave *dws = dwc->chan.private; | |
165 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
166 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
167 | ||
168 | if (dwc->initialized == true) | |
169 | return; | |
170 | ||
171 | if (dws) { | |
172 | /* | |
173 | * We need controller-specific data to set up slave | |
174 | * transfers. | |
175 | */ | |
176 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
177 | ||
178 | cfghi = dws->cfg_hi; | |
179 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
180 | } | |
181 | ||
182 | channel_writel(dwc, CFG_LO, cfglo); | |
183 | channel_writel(dwc, CFG_HI, cfghi); | |
184 | ||
185 | /* Enable interrupts */ | |
186 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
187 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
188 | ||
189 | dwc->initialized = true; | |
190 | } | |
191 | ||
3bfb1d20 HS |
192 | /*----------------------------------------------------------------------*/ |
193 | ||
194 | /* Called with dwc->lock held and bh disabled */ | |
195 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
196 | { | |
197 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
198 | ||
199 | /* ASSERT: channel is idle */ | |
200 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 201 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 202 | "BUG: Attempted to start non-idle channel\n"); |
41d5e59c | 203 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
204 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
205 | channel_readl(dwc, SAR), | |
206 | channel_readl(dwc, DAR), | |
207 | channel_readl(dwc, LLP), | |
208 | channel_readl(dwc, CTL_HI), | |
209 | channel_readl(dwc, CTL_LO)); | |
210 | ||
211 | /* The tasklet will hopefully advance the queue... */ | |
212 | return; | |
213 | } | |
214 | ||
61e183f8 VK |
215 | dwc_initialize(dwc); |
216 | ||
3bfb1d20 HS |
217 | channel_writel(dwc, LLP, first->txd.phys); |
218 | channel_writel(dwc, CTL_LO, | |
219 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
220 | channel_writel(dwc, CTL_HI, 0); | |
221 | channel_set_bit(dw, CH_EN, dwc->mask); | |
222 | } | |
223 | ||
224 | /*----------------------------------------------------------------------*/ | |
225 | ||
226 | static void | |
5fedefb8 VK |
227 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
228 | bool callback_required) | |
3bfb1d20 | 229 | { |
5fedefb8 VK |
230 | dma_async_tx_callback callback = NULL; |
231 | void *param = NULL; | |
3bfb1d20 | 232 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 233 | struct dw_desc *child; |
69cea5a0 | 234 | unsigned long flags; |
3bfb1d20 | 235 | |
41d5e59c | 236 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 237 | |
69cea5a0 | 238 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 239 | dma_cookie_complete(txd); |
5fedefb8 VK |
240 | if (callback_required) { |
241 | callback = txd->callback; | |
242 | param = txd->callback_param; | |
243 | } | |
3bfb1d20 HS |
244 | |
245 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
246 | |
247 | /* async_tx_ack */ | |
248 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
249 | async_tx_ack(&child->txd); | |
250 | async_tx_ack(&desc->txd); | |
251 | ||
e0bd0f8c | 252 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
253 | list_move(&desc->desc_node, &dwc->free_list); |
254 | ||
657a77fa AN |
255 | if (!dwc->chan.private) { |
256 | struct device *parent = chan2parent(&dwc->chan); | |
257 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
258 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
259 | dma_unmap_single(parent, desc->lli.dar, | |
260 | desc->len, DMA_FROM_DEVICE); | |
261 | else | |
262 | dma_unmap_page(parent, desc->lli.dar, | |
263 | desc->len, DMA_FROM_DEVICE); | |
264 | } | |
265 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
266 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
267 | dma_unmap_single(parent, desc->lli.sar, | |
268 | desc->len, DMA_TO_DEVICE); | |
269 | else | |
270 | dma_unmap_page(parent, desc->lli.sar, | |
271 | desc->len, DMA_TO_DEVICE); | |
272 | } | |
273 | } | |
3bfb1d20 | 274 | |
69cea5a0 VK |
275 | spin_unlock_irqrestore(&dwc->lock, flags); |
276 | ||
5fedefb8 | 277 | if (callback_required && callback) |
3bfb1d20 HS |
278 | callback(param); |
279 | } | |
280 | ||
281 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
282 | { | |
283 | struct dw_desc *desc, *_desc; | |
284 | LIST_HEAD(list); | |
69cea5a0 | 285 | unsigned long flags; |
3bfb1d20 | 286 | |
69cea5a0 | 287 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 288 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 289 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
290 | "BUG: XFER bit set, but channel not idle!\n"); |
291 | ||
292 | /* Try to continue after resetting the channel... */ | |
293 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
294 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
295 | cpu_relax(); | |
296 | } | |
297 | ||
298 | /* | |
299 | * Submit queued descriptors ASAP, i.e. before we go through | |
300 | * the completed ones. | |
301 | */ | |
3bfb1d20 | 302 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
303 | if (!list_empty(&dwc->queue)) { |
304 | list_move(dwc->queue.next, &dwc->active_list); | |
305 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
306 | } | |
3bfb1d20 | 307 | |
69cea5a0 VK |
308 | spin_unlock_irqrestore(&dwc->lock, flags); |
309 | ||
3bfb1d20 | 310 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 311 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
312 | } |
313 | ||
314 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
315 | { | |
316 | dma_addr_t llp; | |
317 | struct dw_desc *desc, *_desc; | |
318 | struct dw_desc *child; | |
319 | u32 status_xfer; | |
69cea5a0 | 320 | unsigned long flags; |
3bfb1d20 | 321 | |
69cea5a0 | 322 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
323 | llp = channel_readl(dwc, LLP); |
324 | status_xfer = dma_readl(dw, RAW.XFER); | |
325 | ||
326 | if (status_xfer & dwc->mask) { | |
327 | /* Everything we've submitted is done */ | |
328 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
69cea5a0 VK |
329 | spin_unlock_irqrestore(&dwc->lock, flags); |
330 | ||
3bfb1d20 HS |
331 | dwc_complete_all(dw, dwc); |
332 | return; | |
333 | } | |
334 | ||
69cea5a0 VK |
335 | if (list_empty(&dwc->active_list)) { |
336 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 337 | return; |
69cea5a0 | 338 | } |
087809fc | 339 | |
2f45d613 AS |
340 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%llx\n", |
341 | (unsigned long long)llp); | |
3bfb1d20 HS |
342 | |
343 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb | 344 | /* check first descriptors addr */ |
69cea5a0 VK |
345 | if (desc->txd.phys == llp) { |
346 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 347 | return; |
69cea5a0 | 348 | } |
84adccfb VK |
349 | |
350 | /* check first descriptors llp */ | |
69cea5a0 | 351 | if (desc->lli.llp == llp) { |
3bfb1d20 | 352 | /* This one is currently in progress */ |
69cea5a0 | 353 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 354 | return; |
69cea5a0 | 355 | } |
3bfb1d20 | 356 | |
e0bd0f8c | 357 | list_for_each_entry(child, &desc->tx_list, desc_node) |
69cea5a0 | 358 | if (child->lli.llp == llp) { |
3bfb1d20 | 359 | /* Currently in progress */ |
69cea5a0 | 360 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 361 | return; |
69cea5a0 | 362 | } |
3bfb1d20 HS |
363 | |
364 | /* | |
365 | * No descriptors so far seem to be in progress, i.e. | |
366 | * this one must be done. | |
367 | */ | |
69cea5a0 | 368 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 369 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 370 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
371 | } |
372 | ||
41d5e59c | 373 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
374 | "BUG: All descriptors done, but channel not idle!\n"); |
375 | ||
376 | /* Try to continue after resetting the channel... */ | |
377 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
378 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
379 | cpu_relax(); | |
380 | ||
381 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
382 | list_move(dwc->queue.next, &dwc->active_list); |
383 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 384 | } |
69cea5a0 | 385 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
386 | } |
387 | ||
388 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
389 | { | |
41d5e59c | 390 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
2f45d613 AS |
391 | " desc: s0x%llx d0x%llx l0x%llx c0x%x:%x\n", |
392 | (unsigned long long)lli->sar, | |
393 | (unsigned long long)lli->dar, | |
394 | (unsigned long long)lli->llp, | |
3bfb1d20 HS |
395 | lli->ctlhi, lli->ctllo); |
396 | } | |
397 | ||
398 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
399 | { | |
400 | struct dw_desc *bad_desc; | |
401 | struct dw_desc *child; | |
69cea5a0 | 402 | unsigned long flags; |
3bfb1d20 HS |
403 | |
404 | dwc_scan_descriptors(dw, dwc); | |
405 | ||
69cea5a0 VK |
406 | spin_lock_irqsave(&dwc->lock, flags); |
407 | ||
3bfb1d20 HS |
408 | /* |
409 | * The descriptor currently at the head of the active list is | |
410 | * borked. Since we don't have any way to report errors, we'll | |
411 | * just have to scream loudly and try to carry on. | |
412 | */ | |
413 | bad_desc = dwc_first_active(dwc); | |
414 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 415 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
416 | |
417 | /* Clear the error flag and try to restart the controller */ | |
418 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
419 | if (!list_empty(&dwc->active_list)) | |
420 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
421 | ||
422 | /* | |
423 | * KERN_CRITICAL may seem harsh, but since this only happens | |
424 | * when someone submits a bad physical address in a | |
425 | * descriptor, we should consider ourselves lucky that the | |
426 | * controller flagged an error instead of scribbling over | |
427 | * random memory locations. | |
428 | */ | |
41d5e59c | 429 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 430 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 431 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
432 | " cookie: %d\n", bad_desc->txd.cookie); |
433 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 434 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
435 | dwc_dump_lli(dwc, &child->lli); |
436 | ||
69cea5a0 VK |
437 | spin_unlock_irqrestore(&dwc->lock, flags); |
438 | ||
3bfb1d20 | 439 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 440 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
441 | } |
442 | ||
d9de4519 HCE |
443 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
444 | ||
445 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
446 | { | |
447 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
448 | return channel_readl(dwc, SAR); | |
449 | } | |
450 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
451 | ||
452 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
453 | { | |
454 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
455 | return channel_readl(dwc, DAR); | |
456 | } | |
457 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
458 | ||
459 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
460 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 461 | u32 status_err, u32 status_xfer) |
d9de4519 | 462 | { |
69cea5a0 VK |
463 | unsigned long flags; |
464 | ||
ff7b05f2 | 465 | if (dwc->mask) { |
d9de4519 HCE |
466 | void (*callback)(void *param); |
467 | void *callback_param; | |
468 | ||
469 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
470 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
471 | |
472 | callback = dwc->cdesc->period_callback; | |
473 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
474 | |
475 | if (callback) | |
d9de4519 | 476 | callback(callback_param); |
d9de4519 HCE |
477 | } |
478 | ||
479 | /* | |
480 | * Error and transfer complete are highly unlikely, and will most | |
481 | * likely be due to a configuration error by the user. | |
482 | */ | |
483 | if (unlikely(status_err & dwc->mask) || | |
484 | unlikely(status_xfer & dwc->mask)) { | |
485 | int i; | |
486 | ||
487 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
488 | "interrupt, stopping DMA transfer\n", | |
489 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
490 | |
491 | spin_lock_irqsave(&dwc->lock, flags); | |
492 | ||
d9de4519 HCE |
493 | dev_err(chan2dev(&dwc->chan), |
494 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
495 | channel_readl(dwc, SAR), | |
496 | channel_readl(dwc, DAR), | |
497 | channel_readl(dwc, LLP), | |
498 | channel_readl(dwc, CTL_HI), | |
499 | channel_readl(dwc, CTL_LO)); | |
500 | ||
501 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
502 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
503 | cpu_relax(); | |
504 | ||
505 | /* make sure DMA does not restart by loading a new list */ | |
506 | channel_writel(dwc, LLP, 0); | |
507 | channel_writel(dwc, CTL_LO, 0); | |
508 | channel_writel(dwc, CTL_HI, 0); | |
509 | ||
d9de4519 HCE |
510 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
511 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
512 | ||
513 | for (i = 0; i < dwc->cdesc->periods; i++) | |
514 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
515 | |
516 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
517 | } |
518 | } | |
519 | ||
520 | /* ------------------------------------------------------------------------- */ | |
521 | ||
3bfb1d20 HS |
522 | static void dw_dma_tasklet(unsigned long data) |
523 | { | |
524 | struct dw_dma *dw = (struct dw_dma *)data; | |
525 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
526 | u32 status_xfer; |
527 | u32 status_err; | |
528 | int i; | |
529 | ||
7fe7b2f4 | 530 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
531 | status_err = dma_readl(dw, RAW.ERROR); |
532 | ||
ff7b05f2 | 533 | dev_vdbg(dw->dma.dev, "tasklet: status_err=%x\n", status_err); |
3bfb1d20 HS |
534 | |
535 | for (i = 0; i < dw->dma.chancnt; i++) { | |
536 | dwc = &dw->chan[i]; | |
d9de4519 | 537 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 538 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 539 | else if (status_err & (1 << i)) |
3bfb1d20 | 540 | dwc_handle_error(dw, dwc); |
ff7b05f2 | 541 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 542 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
543 | } |
544 | ||
545 | /* | |
ff7b05f2 | 546 | * Re-enable interrupts. |
3bfb1d20 HS |
547 | */ |
548 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
549 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
550 | } | |
551 | ||
552 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
553 | { | |
554 | struct dw_dma *dw = dev_id; | |
555 | u32 status; | |
556 | ||
557 | dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n", | |
558 | dma_readl(dw, STATUS_INT)); | |
559 | ||
560 | /* | |
561 | * Just disable the interrupts. We'll turn them back on in the | |
562 | * softirq handler. | |
563 | */ | |
564 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
565 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
566 | ||
567 | status = dma_readl(dw, STATUS_INT); | |
568 | if (status) { | |
569 | dev_err(dw->dma.dev, | |
570 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
571 | status); | |
572 | ||
573 | /* Try to recover */ | |
574 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
575 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
576 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
577 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
578 | } | |
579 | ||
580 | tasklet_schedule(&dw->tasklet); | |
581 | ||
582 | return IRQ_HANDLED; | |
583 | } | |
584 | ||
585 | /*----------------------------------------------------------------------*/ | |
586 | ||
587 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
588 | { | |
589 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
590 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
591 | dma_cookie_t cookie; | |
69cea5a0 | 592 | unsigned long flags; |
3bfb1d20 | 593 | |
69cea5a0 | 594 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 595 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
596 | |
597 | /* | |
598 | * REVISIT: We should attempt to chain as many descriptors as | |
599 | * possible, perhaps even appending to those already submitted | |
600 | * for DMA. But this is hard to do in a race-free manner. | |
601 | */ | |
602 | if (list_empty(&dwc->active_list)) { | |
41d5e59c | 603 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", |
3bfb1d20 | 604 | desc->txd.cookie); |
3bfb1d20 | 605 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 606 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 607 | } else { |
41d5e59c | 608 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", |
3bfb1d20 HS |
609 | desc->txd.cookie); |
610 | ||
611 | list_add_tail(&desc->desc_node, &dwc->queue); | |
612 | } | |
613 | ||
69cea5a0 | 614 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
615 | |
616 | return cookie; | |
617 | } | |
618 | ||
619 | static struct dma_async_tx_descriptor * | |
620 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
621 | size_t len, unsigned long flags) | |
622 | { | |
623 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
624 | struct dw_desc *desc; | |
625 | struct dw_desc *first; | |
626 | struct dw_desc *prev; | |
627 | size_t xfer_count; | |
628 | size_t offset; | |
629 | unsigned int src_width; | |
630 | unsigned int dst_width; | |
631 | u32 ctllo; | |
632 | ||
2f45d613 AS |
633 | dev_vdbg(chan2dev(chan), |
634 | "prep_dma_memcpy d0x%llx s0x%llx l0x%zx f0x%lx\n", | |
635 | (unsigned long long)dest, (unsigned long long)src, | |
636 | len, flags); | |
3bfb1d20 HS |
637 | |
638 | if (unlikely(!len)) { | |
41d5e59c | 639 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
3bfb1d20 HS |
640 | return NULL; |
641 | } | |
642 | ||
643 | /* | |
644 | * We can be a lot more clever here, but this should take care | |
645 | * of the most common optimization. | |
646 | */ | |
a0227456 VK |
647 | if (!((src | dest | len) & 7)) |
648 | src_width = dst_width = 3; | |
649 | else if (!((src | dest | len) & 3)) | |
3bfb1d20 HS |
650 | src_width = dst_width = 2; |
651 | else if (!((src | dest | len) & 1)) | |
652 | src_width = dst_width = 1; | |
653 | else | |
654 | src_width = dst_width = 0; | |
655 | ||
327e6970 | 656 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
657 | | DWC_CTLL_DST_WIDTH(dst_width) |
658 | | DWC_CTLL_SRC_WIDTH(src_width) | |
659 | | DWC_CTLL_DST_INC | |
660 | | DWC_CTLL_SRC_INC | |
661 | | DWC_CTLL_FC_M2M; | |
662 | prev = first = NULL; | |
663 | ||
664 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
665 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
666 | DWC_MAX_COUNT); | |
667 | ||
668 | desc = dwc_desc_get(dwc); | |
669 | if (!desc) | |
670 | goto err_desc_get; | |
671 | ||
672 | desc->lli.sar = src + offset; | |
673 | desc->lli.dar = dest + offset; | |
674 | desc->lli.ctllo = ctllo; | |
675 | desc->lli.ctlhi = xfer_count; | |
676 | ||
677 | if (!first) { | |
678 | first = desc; | |
679 | } else { | |
680 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 681 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
682 | prev->txd.phys, sizeof(prev->lli), |
683 | DMA_TO_DEVICE); | |
684 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 685 | &first->tx_list); |
3bfb1d20 HS |
686 | } |
687 | prev = desc; | |
688 | } | |
689 | ||
690 | ||
691 | if (flags & DMA_PREP_INTERRUPT) | |
692 | /* Trigger interrupt after last block */ | |
693 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
694 | ||
695 | prev->lli.llp = 0; | |
41d5e59c | 696 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
697 | prev->txd.phys, sizeof(prev->lli), |
698 | DMA_TO_DEVICE); | |
699 | ||
700 | first->txd.flags = flags; | |
701 | first->len = len; | |
702 | ||
703 | return &first->txd; | |
704 | ||
705 | err_desc_get: | |
706 | dwc_desc_put(dwc, first); | |
707 | return NULL; | |
708 | } | |
709 | ||
710 | static struct dma_async_tx_descriptor * | |
711 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 712 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 713 | unsigned long flags, void *context) |
3bfb1d20 HS |
714 | { |
715 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 716 | struct dw_dma_slave *dws = chan->private; |
327e6970 | 717 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
718 | struct dw_desc *prev; |
719 | struct dw_desc *first; | |
720 | u32 ctllo; | |
721 | dma_addr_t reg; | |
722 | unsigned int reg_width; | |
723 | unsigned int mem_width; | |
724 | unsigned int i; | |
725 | struct scatterlist *sg; | |
726 | size_t total_len = 0; | |
727 | ||
41d5e59c | 728 | dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); |
3bfb1d20 HS |
729 | |
730 | if (unlikely(!dws || !sg_len)) | |
731 | return NULL; | |
732 | ||
3bfb1d20 HS |
733 | prev = first = NULL; |
734 | ||
3bfb1d20 | 735 | switch (direction) { |
db8196df | 736 | case DMA_MEM_TO_DEV: |
327e6970 VK |
737 | reg_width = __fls(sconfig->dst_addr_width); |
738 | reg = sconfig->dst_addr; | |
739 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
740 | | DWC_CTLL_DST_WIDTH(reg_width) |
741 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
742 | | DWC_CTLL_SRC_INC); |
743 | ||
744 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
745 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
746 | ||
3bfb1d20 HS |
747 | for_each_sg(sgl, sg, sg_len, i) { |
748 | struct dw_desc *desc; | |
69dc14b5 | 749 | u32 len, dlen, mem; |
3bfb1d20 | 750 | |
cbb796cc | 751 | mem = sg_dma_address(sg); |
69dc14b5 | 752 | len = sg_dma_len(sg); |
6bc711f6 VK |
753 | |
754 | if (!((mem | len) & 7)) | |
755 | mem_width = 3; | |
756 | else if (!((mem | len) & 3)) | |
757 | mem_width = 2; | |
758 | else if (!((mem | len) & 1)) | |
759 | mem_width = 1; | |
760 | else | |
69dc14b5 | 761 | mem_width = 0; |
3bfb1d20 | 762 | |
69dc14b5 | 763 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
764 | desc = dwc_desc_get(dwc); |
765 | if (!desc) { | |
41d5e59c | 766 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
767 | "not enough descriptors available\n"); |
768 | goto err_desc_get; | |
769 | } | |
770 | ||
3bfb1d20 HS |
771 | desc->lli.sar = mem; |
772 | desc->lli.dar = reg; | |
773 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
69dc14b5 VK |
774 | if ((len >> mem_width) > DWC_MAX_COUNT) { |
775 | dlen = DWC_MAX_COUNT << mem_width; | |
776 | mem += dlen; | |
777 | len -= dlen; | |
778 | } else { | |
779 | dlen = len; | |
780 | len = 0; | |
781 | } | |
782 | ||
783 | desc->lli.ctlhi = dlen >> mem_width; | |
3bfb1d20 HS |
784 | |
785 | if (!first) { | |
786 | first = desc; | |
787 | } else { | |
788 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 789 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
790 | prev->txd.phys, |
791 | sizeof(prev->lli), | |
792 | DMA_TO_DEVICE); | |
793 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 794 | &first->tx_list); |
3bfb1d20 HS |
795 | } |
796 | prev = desc; | |
69dc14b5 VK |
797 | total_len += dlen; |
798 | ||
799 | if (len) | |
800 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
801 | } |
802 | break; | |
db8196df | 803 | case DMA_DEV_TO_MEM: |
327e6970 VK |
804 | reg_width = __fls(sconfig->src_addr_width); |
805 | reg = sconfig->src_addr; | |
806 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
807 | | DWC_CTLL_SRC_WIDTH(reg_width) |
808 | | DWC_CTLL_DST_INC | |
327e6970 VK |
809 | | DWC_CTLL_SRC_FIX); |
810 | ||
811 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
812 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 813 | |
3bfb1d20 HS |
814 | for_each_sg(sgl, sg, sg_len, i) { |
815 | struct dw_desc *desc; | |
69dc14b5 | 816 | u32 len, dlen, mem; |
3bfb1d20 | 817 | |
cbb796cc | 818 | mem = sg_dma_address(sg); |
3bfb1d20 | 819 | len = sg_dma_len(sg); |
6bc711f6 VK |
820 | |
821 | if (!((mem | len) & 7)) | |
822 | mem_width = 3; | |
823 | else if (!((mem | len) & 3)) | |
824 | mem_width = 2; | |
825 | else if (!((mem | len) & 1)) | |
826 | mem_width = 1; | |
827 | else | |
3bfb1d20 HS |
828 | mem_width = 0; |
829 | ||
69dc14b5 VK |
830 | slave_sg_fromdev_fill_desc: |
831 | desc = dwc_desc_get(dwc); | |
832 | if (!desc) { | |
833 | dev_err(chan2dev(chan), | |
834 | "not enough descriptors available\n"); | |
835 | goto err_desc_get; | |
836 | } | |
837 | ||
3bfb1d20 HS |
838 | desc->lli.sar = reg; |
839 | desc->lli.dar = mem; | |
840 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
69dc14b5 VK |
841 | if ((len >> reg_width) > DWC_MAX_COUNT) { |
842 | dlen = DWC_MAX_COUNT << reg_width; | |
843 | mem += dlen; | |
844 | len -= dlen; | |
845 | } else { | |
846 | dlen = len; | |
847 | len = 0; | |
848 | } | |
849 | desc->lli.ctlhi = dlen >> reg_width; | |
3bfb1d20 HS |
850 | |
851 | if (!first) { | |
852 | first = desc; | |
853 | } else { | |
854 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 855 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
856 | prev->txd.phys, |
857 | sizeof(prev->lli), | |
858 | DMA_TO_DEVICE); | |
859 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 860 | &first->tx_list); |
3bfb1d20 HS |
861 | } |
862 | prev = desc; | |
69dc14b5 VK |
863 | total_len += dlen; |
864 | ||
865 | if (len) | |
866 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
867 | } |
868 | break; | |
869 | default: | |
870 | return NULL; | |
871 | } | |
872 | ||
873 | if (flags & DMA_PREP_INTERRUPT) | |
874 | /* Trigger interrupt after last block */ | |
875 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
876 | ||
877 | prev->lli.llp = 0; | |
41d5e59c | 878 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
879 | prev->txd.phys, sizeof(prev->lli), |
880 | DMA_TO_DEVICE); | |
881 | ||
882 | first->len = total_len; | |
883 | ||
884 | return &first->txd; | |
885 | ||
886 | err_desc_get: | |
887 | dwc_desc_put(dwc, first); | |
888 | return NULL; | |
889 | } | |
890 | ||
327e6970 VK |
891 | /* |
892 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
893 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
894 | * | |
895 | * NOTE: burst size 2 is not supported by controller. | |
896 | * | |
897 | * This can be done by finding least significant bit set: n & (n - 1) | |
898 | */ | |
899 | static inline void convert_burst(u32 *maxburst) | |
900 | { | |
901 | if (*maxburst > 1) | |
902 | *maxburst = fls(*maxburst) - 2; | |
903 | else | |
904 | *maxburst = 0; | |
905 | } | |
906 | ||
907 | static int | |
908 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
909 | { | |
910 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
911 | ||
912 | /* Check if it is chan is configured for slave transfers */ | |
913 | if (!chan->private) | |
914 | return -EINVAL; | |
915 | ||
916 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
917 | ||
918 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
919 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
05827630 LW |
924 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
925 | unsigned long arg) | |
3bfb1d20 HS |
926 | { |
927 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
928 | struct dw_dma *dw = to_dw_dma(chan->device); | |
929 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 930 | unsigned long flags; |
a7c57cf7 | 931 | u32 cfglo; |
3bfb1d20 HS |
932 | LIST_HEAD(list); |
933 | ||
a7c57cf7 LW |
934 | if (cmd == DMA_PAUSE) { |
935 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 936 | |
a7c57cf7 LW |
937 | cfglo = channel_readl(dwc, CFG_LO); |
938 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
939 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
940 | cpu_relax(); | |
3bfb1d20 | 941 | |
a7c57cf7 LW |
942 | dwc->paused = true; |
943 | spin_unlock_irqrestore(&dwc->lock, flags); | |
944 | } else if (cmd == DMA_RESUME) { | |
945 | if (!dwc->paused) | |
946 | return 0; | |
3bfb1d20 | 947 | |
a7c57cf7 | 948 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 949 | |
a7c57cf7 LW |
950 | cfglo = channel_readl(dwc, CFG_LO); |
951 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
952 | dwc->paused = false; | |
3bfb1d20 | 953 | |
a7c57cf7 LW |
954 | spin_unlock_irqrestore(&dwc->lock, flags); |
955 | } else if (cmd == DMA_TERMINATE_ALL) { | |
956 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 957 | |
a7c57cf7 LW |
958 | channel_clear_bit(dw, CH_EN, dwc->mask); |
959 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
960 | cpu_relax(); | |
961 | ||
962 | dwc->paused = false; | |
963 | ||
964 | /* active_list entries will end up before queued entries */ | |
965 | list_splice_init(&dwc->queue, &list); | |
966 | list_splice_init(&dwc->active_list, &list); | |
967 | ||
968 | spin_unlock_irqrestore(&dwc->lock, flags); | |
969 | ||
970 | /* Flush all pending and queued descriptors */ | |
971 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
972 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
973 | } else if (cmd == DMA_SLAVE_CONFIG) { |
974 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
975 | } else { | |
a7c57cf7 | 976 | return -ENXIO; |
327e6970 | 977 | } |
c3635c78 LW |
978 | |
979 | return 0; | |
3bfb1d20 HS |
980 | } |
981 | ||
982 | static enum dma_status | |
07934481 LW |
983 | dwc_tx_status(struct dma_chan *chan, |
984 | dma_cookie_t cookie, | |
985 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
986 | { |
987 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 988 | enum dma_status ret; |
3bfb1d20 | 989 | |
96a2af41 | 990 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
991 | if (ret != DMA_SUCCESS) { |
992 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
993 | ||
96a2af41 | 994 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
995 | } |
996 | ||
abf53902 | 997 | if (ret != DMA_SUCCESS) |
96a2af41 | 998 | dma_set_residue(txstate, dwc_first_active(dwc)->len); |
3bfb1d20 | 999 | |
a7c57cf7 LW |
1000 | if (dwc->paused) |
1001 | return DMA_PAUSED; | |
3bfb1d20 HS |
1002 | |
1003 | return ret; | |
1004 | } | |
1005 | ||
1006 | static void dwc_issue_pending(struct dma_chan *chan) | |
1007 | { | |
1008 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1009 | ||
3bfb1d20 HS |
1010 | if (!list_empty(&dwc->queue)) |
1011 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1012 | } |
1013 | ||
aa1e6f1a | 1014 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1015 | { |
1016 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1017 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1018 | struct dw_desc *desc; | |
3bfb1d20 | 1019 | int i; |
69cea5a0 | 1020 | unsigned long flags; |
3bfb1d20 | 1021 | |
41d5e59c | 1022 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); |
3bfb1d20 | 1023 | |
3bfb1d20 HS |
1024 | /* ASSERT: channel is idle */ |
1025 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1026 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1027 | return -EIO; |
1028 | } | |
1029 | ||
d3ee98cd | 1030 | dma_cookie_init(chan); |
3bfb1d20 | 1031 | |
3bfb1d20 HS |
1032 | /* |
1033 | * NOTE: some controllers may have additional features that we | |
1034 | * need to initialize here, like "scatter-gather" (which | |
1035 | * doesn't mean what you think it means), and status writeback. | |
1036 | */ | |
1037 | ||
69cea5a0 | 1038 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1039 | i = dwc->descs_allocated; |
1040 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
69cea5a0 | 1041 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1042 | |
1043 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
1044 | if (!desc) { | |
41d5e59c | 1045 | dev_info(chan2dev(chan), |
3bfb1d20 | 1046 | "only allocated %d descriptors\n", i); |
69cea5a0 | 1047 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1048 | break; |
1049 | } | |
1050 | ||
e0bd0f8c | 1051 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1052 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1053 | desc->txd.tx_submit = dwc_tx_submit; | |
1054 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 1055 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
1056 | sizeof(desc->lli), DMA_TO_DEVICE); |
1057 | dwc_desc_put(dwc, desc); | |
1058 | ||
69cea5a0 | 1059 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1060 | i = ++dwc->descs_allocated; |
1061 | } | |
1062 | ||
69cea5a0 | 1063 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1064 | |
41d5e59c | 1065 | dev_dbg(chan2dev(chan), |
3bfb1d20 HS |
1066 | "alloc_chan_resources allocated %d descriptors\n", i); |
1067 | ||
1068 | return i; | |
1069 | } | |
1070 | ||
1071 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1072 | { | |
1073 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1074 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1075 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1076 | unsigned long flags; |
3bfb1d20 HS |
1077 | LIST_HEAD(list); |
1078 | ||
41d5e59c | 1079 | dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", |
3bfb1d20 HS |
1080 | dwc->descs_allocated); |
1081 | ||
1082 | /* ASSERT: channel is idle */ | |
1083 | BUG_ON(!list_empty(&dwc->active_list)); | |
1084 | BUG_ON(!list_empty(&dwc->queue)); | |
1085 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1086 | ||
69cea5a0 | 1087 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1088 | list_splice_init(&dwc->free_list, &list); |
1089 | dwc->descs_allocated = 0; | |
61e183f8 | 1090 | dwc->initialized = false; |
3bfb1d20 HS |
1091 | |
1092 | /* Disable interrupts */ | |
1093 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1094 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1095 | ||
69cea5a0 | 1096 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1097 | |
1098 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
1099 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
1100 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
1101 | sizeof(desc->lli), DMA_TO_DEVICE); |
1102 | kfree(desc); | |
1103 | } | |
1104 | ||
41d5e59c | 1105 | dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); |
3bfb1d20 HS |
1106 | } |
1107 | ||
d9de4519 HCE |
1108 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1109 | ||
1110 | /** | |
1111 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1112 | * @chan: the DMA channel to start | |
1113 | * | |
1114 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1115 | * -errno on failure. | |
1116 | */ | |
1117 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1118 | { | |
1119 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1120 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1121 | unsigned long flags; |
d9de4519 HCE |
1122 | |
1123 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1124 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1125 | return -ENODEV; | |
1126 | } | |
1127 | ||
69cea5a0 | 1128 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1129 | |
1130 | /* assert channel is idle */ | |
1131 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1132 | dev_err(chan2dev(&dwc->chan), | |
1133 | "BUG: Attempted to start non-idle channel\n"); | |
1134 | dev_err(chan2dev(&dwc->chan), | |
1135 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
1136 | channel_readl(dwc, SAR), | |
1137 | channel_readl(dwc, DAR), | |
1138 | channel_readl(dwc, LLP), | |
1139 | channel_readl(dwc, CTL_HI), | |
1140 | channel_readl(dwc, CTL_LO)); | |
69cea5a0 | 1141 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1142 | return -EBUSY; |
1143 | } | |
1144 | ||
d9de4519 HCE |
1145 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1146 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1147 | ||
1148 | /* setup DMAC channel registers */ | |
1149 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1150 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1151 | channel_writel(dwc, CTL_HI, 0); | |
1152 | ||
1153 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1154 | ||
69cea5a0 | 1155 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1156 | |
1157 | return 0; | |
1158 | } | |
1159 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1160 | ||
1161 | /** | |
1162 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1163 | * @chan: the DMA channel to stop | |
1164 | * | |
1165 | * Must be called with soft interrupts disabled. | |
1166 | */ | |
1167 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1168 | { | |
1169 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1170 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1171 | unsigned long flags; |
d9de4519 | 1172 | |
69cea5a0 | 1173 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1174 | |
1175 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1176 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1177 | cpu_relax(); | |
1178 | ||
69cea5a0 | 1179 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1180 | } |
1181 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1182 | ||
1183 | /** | |
1184 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1185 | * @chan: the DMA channel to prepare | |
1186 | * @buf_addr: physical DMA address where the buffer starts | |
1187 | * @buf_len: total number of bytes for the entire buffer | |
1188 | * @period_len: number of bytes for each period | |
1189 | * @direction: transfer direction, to or from device | |
1190 | * | |
1191 | * Must be called before trying to start the transfer. Returns a valid struct | |
1192 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1193 | */ | |
1194 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1195 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1196 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1197 | { |
1198 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1199 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1200 | struct dw_cyclic_desc *cdesc; |
1201 | struct dw_cyclic_desc *retval = NULL; | |
1202 | struct dw_desc *desc; | |
1203 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1204 | unsigned long was_cyclic; |
1205 | unsigned int reg_width; | |
1206 | unsigned int periods; | |
1207 | unsigned int i; | |
69cea5a0 | 1208 | unsigned long flags; |
d9de4519 | 1209 | |
69cea5a0 | 1210 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1211 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1212 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1213 | dev_dbg(chan2dev(&dwc->chan), |
1214 | "queue and/or active list are not empty\n"); | |
1215 | return ERR_PTR(-EBUSY); | |
1216 | } | |
1217 | ||
1218 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1219 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1220 | if (was_cyclic) { |
1221 | dev_dbg(chan2dev(&dwc->chan), | |
1222 | "channel already prepared for cyclic DMA\n"); | |
1223 | return ERR_PTR(-EBUSY); | |
1224 | } | |
1225 | ||
1226 | retval = ERR_PTR(-EINVAL); | |
327e6970 VK |
1227 | |
1228 | if (direction == DMA_MEM_TO_DEV) | |
1229 | reg_width = __ffs(sconfig->dst_addr_width); | |
1230 | else | |
1231 | reg_width = __ffs(sconfig->src_addr_width); | |
1232 | ||
d9de4519 HCE |
1233 | periods = buf_len / period_len; |
1234 | ||
1235 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
1236 | if (period_len > (DWC_MAX_COUNT << reg_width)) | |
1237 | goto out_err; | |
1238 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1239 | goto out_err; | |
1240 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1241 | goto out_err; | |
db8196df | 1242 | if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM)))) |
d9de4519 HCE |
1243 | goto out_err; |
1244 | ||
1245 | retval = ERR_PTR(-ENOMEM); | |
1246 | ||
1247 | if (periods > NR_DESCS_PER_CHANNEL) | |
1248 | goto out_err; | |
1249 | ||
1250 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1251 | if (!cdesc) | |
1252 | goto out_err; | |
1253 | ||
1254 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1255 | if (!cdesc->desc) | |
1256 | goto out_err_alloc; | |
1257 | ||
1258 | for (i = 0; i < periods; i++) { | |
1259 | desc = dwc_desc_get(dwc); | |
1260 | if (!desc) | |
1261 | goto out_err_desc_get; | |
1262 | ||
1263 | switch (direction) { | |
db8196df | 1264 | case DMA_MEM_TO_DEV: |
327e6970 | 1265 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1266 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1267 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1268 | | DWC_CTLL_DST_WIDTH(reg_width) |
1269 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1270 | | DWC_CTLL_DST_FIX | |
1271 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1272 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1273 | |
1274 | desc->lli.ctllo |= sconfig->device_fc ? | |
1275 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1276 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1277 | ||
d9de4519 | 1278 | break; |
db8196df | 1279 | case DMA_DEV_TO_MEM: |
d9de4519 | 1280 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1281 | desc->lli.sar = sconfig->src_addr; |
1282 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1283 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1284 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1285 | | DWC_CTLL_DST_INC | |
1286 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1287 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1288 | |
1289 | desc->lli.ctllo |= sconfig->device_fc ? | |
1290 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1291 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1292 | ||
d9de4519 HCE |
1293 | break; |
1294 | default: | |
1295 | break; | |
1296 | } | |
1297 | ||
1298 | desc->lli.ctlhi = (period_len >> reg_width); | |
1299 | cdesc->desc[i] = desc; | |
1300 | ||
1301 | if (last) { | |
1302 | last->lli.llp = desc->txd.phys; | |
1303 | dma_sync_single_for_device(chan2parent(chan), | |
1304 | last->txd.phys, sizeof(last->lli), | |
1305 | DMA_TO_DEVICE); | |
1306 | } | |
1307 | ||
1308 | last = desc; | |
1309 | } | |
1310 | ||
1311 | /* lets make a cyclic list */ | |
1312 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1313 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1314 | sizeof(last->lli), DMA_TO_DEVICE); | |
1315 | ||
2f45d613 AS |
1316 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1317 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1318 | buf_len, period_len, periods); | |
d9de4519 HCE |
1319 | |
1320 | cdesc->periods = periods; | |
1321 | dwc->cdesc = cdesc; | |
1322 | ||
1323 | return cdesc; | |
1324 | ||
1325 | out_err_desc_get: | |
1326 | while (i--) | |
1327 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1328 | out_err_alloc: | |
1329 | kfree(cdesc); | |
1330 | out_err: | |
1331 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1332 | return (struct dw_cyclic_desc *)retval; | |
1333 | } | |
1334 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1335 | ||
1336 | /** | |
1337 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1338 | * @chan: the DMA channel to free | |
1339 | */ | |
1340 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1341 | { | |
1342 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1343 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1344 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1345 | int i; | |
69cea5a0 | 1346 | unsigned long flags; |
d9de4519 HCE |
1347 | |
1348 | dev_dbg(chan2dev(&dwc->chan), "cyclic free\n"); | |
1349 | ||
1350 | if (!cdesc) | |
1351 | return; | |
1352 | ||
69cea5a0 | 1353 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1354 | |
1355 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1356 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1357 | cpu_relax(); | |
1358 | ||
d9de4519 HCE |
1359 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1360 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1361 | ||
69cea5a0 | 1362 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1363 | |
1364 | for (i = 0; i < cdesc->periods; i++) | |
1365 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1366 | ||
1367 | kfree(cdesc->desc); | |
1368 | kfree(cdesc); | |
1369 | ||
1370 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1371 | } | |
1372 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1373 | ||
3bfb1d20 HS |
1374 | /*----------------------------------------------------------------------*/ |
1375 | ||
1376 | static void dw_dma_off(struct dw_dma *dw) | |
1377 | { | |
61e183f8 VK |
1378 | int i; |
1379 | ||
3bfb1d20 HS |
1380 | dma_writel(dw, CFG, 0); |
1381 | ||
1382 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1383 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1384 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1385 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1386 | ||
1387 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1388 | cpu_relax(); | |
61e183f8 VK |
1389 | |
1390 | for (i = 0; i < dw->dma.chancnt; i++) | |
1391 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1392 | } |
1393 | ||
1394 | static int __init dw_probe(struct platform_device *pdev) | |
1395 | { | |
1396 | struct dw_dma_platform_data *pdata; | |
1397 | struct resource *io; | |
1398 | struct dw_dma *dw; | |
1399 | size_t size; | |
1400 | int irq; | |
1401 | int err; | |
1402 | int i; | |
1403 | ||
6c618c9d | 1404 | pdata = dev_get_platdata(&pdev->dev); |
3bfb1d20 HS |
1405 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) |
1406 | return -EINVAL; | |
1407 | ||
1408 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1409 | if (!io) | |
1410 | return -EINVAL; | |
1411 | ||
1412 | irq = platform_get_irq(pdev, 0); | |
1413 | if (irq < 0) | |
1414 | return irq; | |
1415 | ||
1416 | size = sizeof(struct dw_dma); | |
1417 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
1418 | dw = kzalloc(size, GFP_KERNEL); | |
1419 | if (!dw) | |
1420 | return -ENOMEM; | |
1421 | ||
1422 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
1423 | err = -EBUSY; | |
1424 | goto err_kfree; | |
1425 | } | |
1426 | ||
3bfb1d20 HS |
1427 | dw->regs = ioremap(io->start, DW_REGLEN); |
1428 | if (!dw->regs) { | |
1429 | err = -ENOMEM; | |
1430 | goto err_release_r; | |
1431 | } | |
1432 | ||
1433 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
1434 | if (IS_ERR(dw->clk)) { | |
1435 | err = PTR_ERR(dw->clk); | |
1436 | goto err_clk; | |
1437 | } | |
3075528d | 1438 | clk_prepare_enable(dw->clk); |
3bfb1d20 HS |
1439 | |
1440 | /* force dma off, just in case */ | |
1441 | dw_dma_off(dw); | |
1442 | ||
1443 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); | |
1444 | if (err) | |
1445 | goto err_irq; | |
1446 | ||
1447 | platform_set_drvdata(pdev, dw); | |
1448 | ||
1449 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1450 | ||
1451 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1452 | ||
1453 | INIT_LIST_HEAD(&dw->dma.channels); | |
46389470 | 1454 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1455 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1456 | ||
1457 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1458 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1459 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1460 | list_add_tail(&dwc->chan.device_node, | |
1461 | &dw->dma.channels); | |
1462 | else | |
1463 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1464 | |
93317e8e VK |
1465 | /* 7 is highest priority & 0 is lowest. */ |
1466 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
e8d9f875 | 1467 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1468 | else |
1469 | dwc->priority = i; | |
1470 | ||
3bfb1d20 HS |
1471 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1472 | spin_lock_init(&dwc->lock); | |
1473 | dwc->mask = 1 << i; | |
1474 | ||
1475 | INIT_LIST_HEAD(&dwc->active_list); | |
1476 | INIT_LIST_HEAD(&dwc->queue); | |
1477 | INIT_LIST_HEAD(&dwc->free_list); | |
1478 | ||
1479 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1480 | } | |
1481 | ||
1482 | /* Clear/disable all interrupts on all channels. */ | |
1483 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1484 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1485 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1486 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1487 | ||
1488 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1489 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1490 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1491 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1492 | ||
1493 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1494 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1495 | if (pdata->is_private) |
1496 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1497 | dw->dma.dev = &pdev->dev; |
1498 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1499 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1500 | ||
1501 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1502 | ||
1503 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1504 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1505 | |
07934481 | 1506 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1507 | dw->dma.device_issue_pending = dwc_issue_pending; |
1508 | ||
1509 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1510 | ||
1511 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
46389470 | 1512 | dev_name(&pdev->dev), pdata->nr_channels); |
3bfb1d20 HS |
1513 | |
1514 | dma_async_device_register(&dw->dma); | |
1515 | ||
1516 | return 0; | |
1517 | ||
1518 | err_irq: | |
3075528d | 1519 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1520 | clk_put(dw->clk); |
1521 | err_clk: | |
1522 | iounmap(dw->regs); | |
1523 | dw->regs = NULL; | |
1524 | err_release_r: | |
1525 | release_resource(io); | |
1526 | err_kfree: | |
1527 | kfree(dw); | |
1528 | return err; | |
1529 | } | |
1530 | ||
1531 | static int __exit dw_remove(struct platform_device *pdev) | |
1532 | { | |
1533 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1534 | struct dw_dma_chan *dwc, *_dwc; | |
1535 | struct resource *io; | |
1536 | ||
1537 | dw_dma_off(dw); | |
1538 | dma_async_device_unregister(&dw->dma); | |
1539 | ||
1540 | free_irq(platform_get_irq(pdev, 0), dw); | |
1541 | tasklet_kill(&dw->tasklet); | |
1542 | ||
1543 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1544 | chan.device_node) { | |
1545 | list_del(&dwc->chan.device_node); | |
1546 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1547 | } | |
1548 | ||
3075528d | 1549 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1550 | clk_put(dw->clk); |
1551 | ||
1552 | iounmap(dw->regs); | |
1553 | dw->regs = NULL; | |
1554 | ||
1555 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1556 | release_mem_region(io->start, DW_REGLEN); | |
1557 | ||
1558 | kfree(dw); | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
1563 | static void dw_shutdown(struct platform_device *pdev) | |
1564 | { | |
1565 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1566 | ||
1567 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1568 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1569 | } |
1570 | ||
4a256b5f | 1571 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1572 | { |
4a256b5f | 1573 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1574 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1575 | ||
1576 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1577 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1578 | |
3bfb1d20 HS |
1579 | return 0; |
1580 | } | |
1581 | ||
4a256b5f | 1582 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1583 | { |
4a256b5f | 1584 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1585 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1586 | ||
3075528d | 1587 | clk_prepare_enable(dw->clk); |
3bfb1d20 HS |
1588 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
1589 | return 0; | |
3bfb1d20 HS |
1590 | } |
1591 | ||
47145210 | 1592 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1593 | .suspend_noirq = dw_suspend_noirq, |
1594 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1595 | .freeze_noirq = dw_suspend_noirq, |
1596 | .thaw_noirq = dw_resume_noirq, | |
1597 | .restore_noirq = dw_resume_noirq, | |
1598 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1599 | }; |
1600 | ||
d3f797d9 VK |
1601 | #ifdef CONFIG_OF |
1602 | static const struct of_device_id dw_dma_id_table[] = { | |
1603 | { .compatible = "snps,dma-spear1340" }, | |
1604 | {} | |
1605 | }; | |
1606 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1607 | #endif | |
1608 | ||
3bfb1d20 HS |
1609 | static struct platform_driver dw_driver = { |
1610 | .remove = __exit_p(dw_remove), | |
1611 | .shutdown = dw_shutdown, | |
3bfb1d20 HS |
1612 | .driver = { |
1613 | .name = "dw_dmac", | |
4a256b5f | 1614 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1615 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 HS |
1616 | }, |
1617 | }; | |
1618 | ||
1619 | static int __init dw_init(void) | |
1620 | { | |
1621 | return platform_driver_probe(&dw_driver, dw_probe); | |
1622 | } | |
cb689a70 | 1623 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1624 | |
1625 | static void __exit dw_exit(void) | |
1626 | { | |
1627 | platform_driver_unregister(&dw_driver); | |
1628 | } | |
1629 | module_exit(dw_exit); | |
1630 | ||
1631 | MODULE_LICENSE("GPL v2"); | |
1632 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1633 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
aecb7b64 | 1634 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); |