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Commit | Line | Data |
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3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
b801479b | 11 | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
d3f797d9 | 22 | #include <linux/of.h> |
f9c6a655 | 23 | #include <linux/of_dma.h> |
3bfb1d20 HS |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/slab.h> | |
28 | ||
29 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 30 | #include "dmaengine.h" |
3bfb1d20 HS |
31 | |
32 | /* | |
33 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
34 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
35 | * of which use ARM any more). See the "Databook" from Synopsys for | |
36 | * information beyond what licensees probably provide. | |
37 | * | |
38 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
39 | * which does not support descriptor writeback. | |
40 | */ | |
41 | ||
a0982004 AS |
42 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
43 | { | |
44 | return slave ? slave->dst_master : 0; | |
45 | } | |
46 | ||
47 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
48 | { | |
49 | return slave ? slave->src_master : 1; | |
50 | } | |
51 | ||
5be10f34 AS |
52 | #define SRC_MASTER 0 |
53 | #define DST_MASTER 1 | |
54 | ||
55 | static inline unsigned int dwc_get_master(struct dma_chan *chan, int master) | |
56 | { | |
57 | struct dw_dma *dw = to_dw_dma(chan->device); | |
58 | struct dw_dma_slave *dws = chan->private; | |
59 | unsigned int m; | |
60 | ||
61 | if (master == SRC_MASTER) | |
62 | m = dwc_get_sms(dws); | |
63 | else | |
64 | m = dwc_get_dms(dws); | |
65 | ||
66 | return min_t(unsigned int, dw->nr_masters - 1, m); | |
67 | } | |
68 | ||
327e6970 | 69 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
70 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
71 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 72 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
5be10f34 AS |
73 | int _dms = dwc_get_master(_chan, DST_MASTER); \ |
74 | int _sms = dwc_get_master(_chan, SRC_MASTER); \ | |
495aea4b | 75 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 76 | DW_DMA_MSIZE_16; \ |
495aea4b | 77 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 78 | DW_DMA_MSIZE_16; \ |
f301c062 | 79 | \ |
327e6970 VK |
80 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
81 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
82 | | DWC_CTLL_LLP_D_EN \ |
83 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
84 | | DWC_CTLL_DMS(_dms) \ |
85 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 86 | }) |
3bfb1d20 | 87 | |
3bfb1d20 HS |
88 | /* |
89 | * Number of descriptors to allocate for each channel. This should be | |
90 | * made configurable somehow; preferably, the clients (at least the | |
91 | * ones using slave transfers) should be able to give us a hint. | |
92 | */ | |
93 | #define NR_DESCS_PER_CHANNEL 64 | |
94 | ||
23d5f4ec AS |
95 | static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master) |
96 | { | |
97 | struct dw_dma *dw = to_dw_dma(chan->device); | |
3bfb1d20 | 98 | |
5be10f34 | 99 | return dw->data_width[dwc_get_master(chan, master)]; |
23d5f4ec AS |
100 | } |
101 | ||
3bfb1d20 | 102 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 103 | |
41d5e59c DW |
104 | static struct device *chan2dev(struct dma_chan *chan) |
105 | { | |
106 | return &chan->dev->device; | |
107 | } | |
108 | static struct device *chan2parent(struct dma_chan *chan) | |
109 | { | |
110 | return chan->dev->device.parent; | |
111 | } | |
112 | ||
3bfb1d20 HS |
113 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
114 | { | |
e63a47a3 | 115 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
116 | } |
117 | ||
3bfb1d20 HS |
118 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
119 | { | |
120 | struct dw_desc *desc, *_desc; | |
121 | struct dw_desc *ret = NULL; | |
122 | unsigned int i = 0; | |
69cea5a0 | 123 | unsigned long flags; |
3bfb1d20 | 124 | |
69cea5a0 | 125 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 126 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 127 | i++; |
3bfb1d20 HS |
128 | if (async_tx_test_ack(&desc->txd)) { |
129 | list_del(&desc->desc_node); | |
130 | ret = desc; | |
131 | break; | |
132 | } | |
41d5e59c | 133 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 134 | } |
69cea5a0 | 135 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 136 | |
41d5e59c | 137 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
138 | |
139 | return ret; | |
140 | } | |
141 | ||
3bfb1d20 HS |
142 | /* |
143 | * Move a descriptor, including any children, to the free list. | |
144 | * `desc' must not be on any lists. | |
145 | */ | |
146 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
147 | { | |
69cea5a0 VK |
148 | unsigned long flags; |
149 | ||
3bfb1d20 HS |
150 | if (desc) { |
151 | struct dw_desc *child; | |
152 | ||
69cea5a0 | 153 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 154 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 155 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
156 | "moving child desc %p to freelist\n", |
157 | child); | |
e0bd0f8c | 158 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 159 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 160 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 161 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
162 | } |
163 | } | |
164 | ||
61e183f8 VK |
165 | static void dwc_initialize(struct dw_dma_chan *dwc) |
166 | { | |
167 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
168 | struct dw_dma_slave *dws = dwc->chan.private; | |
169 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
170 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
171 | ||
172 | if (dwc->initialized == true) | |
173 | return; | |
174 | ||
f9c6a655 AB |
175 | if (dws && dws->cfg_hi == ~0 && dws->cfg_lo == ~0) { |
176 | /* autoconfigure based on request line from DT */ | |
177 | if (dwc->direction == DMA_MEM_TO_DEV) | |
178 | cfghi = DWC_CFGH_DST_PER(dwc->request_line); | |
179 | else if (dwc->direction == DMA_DEV_TO_MEM) | |
180 | cfghi = DWC_CFGH_SRC_PER(dwc->request_line); | |
181 | } else if (dws) { | |
61e183f8 VK |
182 | /* |
183 | * We need controller-specific data to set up slave | |
184 | * transfers. | |
185 | */ | |
186 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
187 | ||
188 | cfghi = dws->cfg_hi; | |
189 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf | 190 | } else { |
0fdb567f | 191 | if (dwc->direction == DMA_MEM_TO_DEV) |
8fccc5bf | 192 | cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); |
0fdb567f | 193 | else if (dwc->direction == DMA_DEV_TO_MEM) |
8fccc5bf | 194 | cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); |
61e183f8 VK |
195 | } |
196 | ||
197 | channel_writel(dwc, CFG_LO, cfglo); | |
198 | channel_writel(dwc, CFG_HI, cfghi); | |
199 | ||
200 | /* Enable interrupts */ | |
201 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
202 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
203 | ||
204 | dwc->initialized = true; | |
205 | } | |
206 | ||
3bfb1d20 HS |
207 | /*----------------------------------------------------------------------*/ |
208 | ||
4c2d56c5 AS |
209 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
210 | { | |
211 | /* | |
212 | * We can be a lot more clever here, but this should take care | |
213 | * of the most common optimization. | |
214 | */ | |
215 | if (!(v & 7)) | |
216 | return 3; | |
217 | else if (!(v & 3)) | |
218 | return 2; | |
219 | else if (!(v & 1)) | |
220 | return 1; | |
221 | return 0; | |
222 | } | |
223 | ||
f52b36d2 | 224 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
225 | { |
226 | dev_err(chan2dev(&dwc->chan), | |
227 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
228 | channel_readl(dwc, SAR), | |
229 | channel_readl(dwc, DAR), | |
230 | channel_readl(dwc, LLP), | |
231 | channel_readl(dwc, CTL_HI), | |
232 | channel_readl(dwc, CTL_LO)); | |
233 | } | |
234 | ||
3f936207 AS |
235 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
236 | { | |
237 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
238 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
239 | cpu_relax(); | |
240 | } | |
241 | ||
1d455437 AS |
242 | /*----------------------------------------------------------------------*/ |
243 | ||
fed2574b AS |
244 | /* Perform single block transfer */ |
245 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
246 | struct dw_desc *desc) | |
247 | { | |
248 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
249 | u32 ctllo; | |
250 | ||
251 | /* Software emulation of LLP mode relies on interrupts to continue | |
252 | * multi block transfer. */ | |
253 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
254 | ||
255 | channel_writel(dwc, SAR, desc->lli.sar); | |
256 | channel_writel(dwc, DAR, desc->lli.dar); | |
257 | channel_writel(dwc, CTL_LO, ctllo); | |
258 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
259 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
260 | |
261 | /* Move pointer to next descriptor */ | |
262 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
263 | } |
264 | ||
3bfb1d20 HS |
265 | /* Called with dwc->lock held and bh disabled */ |
266 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
267 | { | |
268 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 269 | unsigned long was_soft_llp; |
3bfb1d20 HS |
270 | |
271 | /* ASSERT: channel is idle */ | |
272 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 273 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 274 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 275 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
276 | |
277 | /* The tasklet will hopefully advance the queue... */ | |
278 | return; | |
279 | } | |
280 | ||
fed2574b AS |
281 | if (dwc->nollp) { |
282 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
283 | &dwc->flags); | |
284 | if (was_soft_llp) { | |
285 | dev_err(chan2dev(&dwc->chan), | |
286 | "BUG: Attempted to start new LLP transfer " | |
287 | "inside ongoing one\n"); | |
288 | return; | |
289 | } | |
290 | ||
291 | dwc_initialize(dwc); | |
292 | ||
4702d524 | 293 | dwc->residue = first->total_len; |
f5c6a7df | 294 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 295 | |
fdf475fa | 296 | /* Submit first block */ |
fed2574b AS |
297 | dwc_do_single_block(dwc, first); |
298 | ||
299 | return; | |
300 | } | |
301 | ||
61e183f8 VK |
302 | dwc_initialize(dwc); |
303 | ||
3bfb1d20 HS |
304 | channel_writel(dwc, LLP, first->txd.phys); |
305 | channel_writel(dwc, CTL_LO, | |
306 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
307 | channel_writel(dwc, CTL_HI, 0); | |
308 | channel_set_bit(dw, CH_EN, dwc->mask); | |
309 | } | |
310 | ||
311 | /*----------------------------------------------------------------------*/ | |
312 | ||
313 | static void | |
5fedefb8 VK |
314 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
315 | bool callback_required) | |
3bfb1d20 | 316 | { |
5fedefb8 VK |
317 | dma_async_tx_callback callback = NULL; |
318 | void *param = NULL; | |
3bfb1d20 | 319 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 320 | struct dw_desc *child; |
69cea5a0 | 321 | unsigned long flags; |
3bfb1d20 | 322 | |
41d5e59c | 323 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 324 | |
69cea5a0 | 325 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 326 | dma_cookie_complete(txd); |
5fedefb8 VK |
327 | if (callback_required) { |
328 | callback = txd->callback; | |
329 | param = txd->callback_param; | |
330 | } | |
3bfb1d20 | 331 | |
e518076e VK |
332 | /* async_tx_ack */ |
333 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
334 | async_tx_ack(&child->txd); | |
335 | async_tx_ack(&desc->txd); | |
336 | ||
e0bd0f8c | 337 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
338 | list_move(&desc->desc_node, &dwc->free_list); |
339 | ||
495aea4b | 340 | if (!is_slave_direction(dwc->direction)) { |
657a77fa AN |
341 | struct device *parent = chan2parent(&dwc->chan); |
342 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
343 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
344 | dma_unmap_single(parent, desc->lli.dar, | |
30d38a32 | 345 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
346 | else |
347 | dma_unmap_page(parent, desc->lli.dar, | |
30d38a32 | 348 | desc->total_len, DMA_FROM_DEVICE); |
657a77fa AN |
349 | } |
350 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
351 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
352 | dma_unmap_single(parent, desc->lli.sar, | |
30d38a32 | 353 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
354 | else |
355 | dma_unmap_page(parent, desc->lli.sar, | |
30d38a32 | 356 | desc->total_len, DMA_TO_DEVICE); |
657a77fa AN |
357 | } |
358 | } | |
3bfb1d20 | 359 | |
69cea5a0 VK |
360 | spin_unlock_irqrestore(&dwc->lock, flags); |
361 | ||
21e93c1e | 362 | if (callback) |
3bfb1d20 HS |
363 | callback(param); |
364 | } | |
365 | ||
366 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
367 | { | |
368 | struct dw_desc *desc, *_desc; | |
369 | LIST_HEAD(list); | |
69cea5a0 | 370 | unsigned long flags; |
3bfb1d20 | 371 | |
69cea5a0 | 372 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 373 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 374 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
375 | "BUG: XFER bit set, but channel not idle!\n"); |
376 | ||
377 | /* Try to continue after resetting the channel... */ | |
3f936207 | 378 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
379 | } |
380 | ||
381 | /* | |
382 | * Submit queued descriptors ASAP, i.e. before we go through | |
383 | * the completed ones. | |
384 | */ | |
3bfb1d20 | 385 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
386 | if (!list_empty(&dwc->queue)) { |
387 | list_move(dwc->queue.next, &dwc->active_list); | |
388 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
389 | } | |
3bfb1d20 | 390 | |
69cea5a0 VK |
391 | spin_unlock_irqrestore(&dwc->lock, flags); |
392 | ||
3bfb1d20 | 393 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 394 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
395 | } |
396 | ||
4702d524 AS |
397 | /* Returns how many bytes were already received from source */ |
398 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
399 | { | |
400 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
401 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
402 | ||
403 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
404 | } | |
405 | ||
3bfb1d20 HS |
406 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
407 | { | |
408 | dma_addr_t llp; | |
409 | struct dw_desc *desc, *_desc; | |
410 | struct dw_desc *child; | |
411 | u32 status_xfer; | |
69cea5a0 | 412 | unsigned long flags; |
3bfb1d20 | 413 | |
69cea5a0 | 414 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
415 | llp = channel_readl(dwc, LLP); |
416 | status_xfer = dma_readl(dw, RAW.XFER); | |
417 | ||
418 | if (status_xfer & dwc->mask) { | |
419 | /* Everything we've submitted is done */ | |
420 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
421 | |
422 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
423 | struct list_head *head, *active = dwc->tx_node_active; |
424 | ||
425 | /* | |
426 | * We are inside first active descriptor. | |
427 | * Otherwise something is really wrong. | |
428 | */ | |
429 | desc = dwc_first_active(dwc); | |
430 | ||
431 | head = &desc->tx_list; | |
432 | if (active != head) { | |
4702d524 AS |
433 | /* Update desc to reflect last sent one */ |
434 | if (active != head->next) | |
435 | desc = to_dw_desc(active->prev); | |
436 | ||
437 | dwc->residue -= desc->len; | |
438 | ||
fdf475fa | 439 | child = to_dw_desc(active); |
77bcc497 AS |
440 | |
441 | /* Submit next block */ | |
fdf475fa | 442 | dwc_do_single_block(dwc, child); |
77bcc497 | 443 | |
fdf475fa | 444 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
445 | return; |
446 | } | |
fdf475fa | 447 | |
77bcc497 AS |
448 | /* We are done here */ |
449 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
450 | } | |
4702d524 AS |
451 | |
452 | dwc->residue = 0; | |
453 | ||
69cea5a0 VK |
454 | spin_unlock_irqrestore(&dwc->lock, flags); |
455 | ||
3bfb1d20 HS |
456 | dwc_complete_all(dw, dwc); |
457 | return; | |
458 | } | |
459 | ||
69cea5a0 | 460 | if (list_empty(&dwc->active_list)) { |
4702d524 | 461 | dwc->residue = 0; |
69cea5a0 | 462 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 463 | return; |
69cea5a0 | 464 | } |
087809fc | 465 | |
77bcc497 AS |
466 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
467 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 468 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 469 | return; |
69cea5a0 | 470 | } |
087809fc | 471 | |
2e4c364e | 472 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 473 | (unsigned long long)llp); |
3bfb1d20 HS |
474 | |
475 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
4702d524 AS |
476 | /* initial residue value */ |
477 | dwc->residue = desc->total_len; | |
478 | ||
84adccfb | 479 | /* check first descriptors addr */ |
69cea5a0 VK |
480 | if (desc->txd.phys == llp) { |
481 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 482 | return; |
69cea5a0 | 483 | } |
84adccfb VK |
484 | |
485 | /* check first descriptors llp */ | |
69cea5a0 | 486 | if (desc->lli.llp == llp) { |
3bfb1d20 | 487 | /* This one is currently in progress */ |
4702d524 | 488 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 489 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 490 | return; |
69cea5a0 | 491 | } |
3bfb1d20 | 492 | |
4702d524 AS |
493 | dwc->residue -= desc->len; |
494 | list_for_each_entry(child, &desc->tx_list, desc_node) { | |
69cea5a0 | 495 | if (child->lli.llp == llp) { |
3bfb1d20 | 496 | /* Currently in progress */ |
4702d524 | 497 | dwc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 498 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 499 | return; |
69cea5a0 | 500 | } |
4702d524 AS |
501 | dwc->residue -= child->len; |
502 | } | |
3bfb1d20 HS |
503 | |
504 | /* | |
505 | * No descriptors so far seem to be in progress, i.e. | |
506 | * this one must be done. | |
507 | */ | |
69cea5a0 | 508 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 509 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 510 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
511 | } |
512 | ||
41d5e59c | 513 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
514 | "BUG: All descriptors done, but channel not idle!\n"); |
515 | ||
516 | /* Try to continue after resetting the channel... */ | |
3f936207 | 517 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
518 | |
519 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
520 | list_move(dwc->queue.next, &dwc->active_list); |
521 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 522 | } |
69cea5a0 | 523 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
524 | } |
525 | ||
93aad1bc | 526 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 527 | { |
21d43f49 AS |
528 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
529 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
530 | } |
531 | ||
532 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
533 | { | |
534 | struct dw_desc *bad_desc; | |
535 | struct dw_desc *child; | |
69cea5a0 | 536 | unsigned long flags; |
3bfb1d20 HS |
537 | |
538 | dwc_scan_descriptors(dw, dwc); | |
539 | ||
69cea5a0 VK |
540 | spin_lock_irqsave(&dwc->lock, flags); |
541 | ||
3bfb1d20 HS |
542 | /* |
543 | * The descriptor currently at the head of the active list is | |
544 | * borked. Since we don't have any way to report errors, we'll | |
545 | * just have to scream loudly and try to carry on. | |
546 | */ | |
547 | bad_desc = dwc_first_active(dwc); | |
548 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 549 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
550 | |
551 | /* Clear the error flag and try to restart the controller */ | |
552 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
553 | if (!list_empty(&dwc->active_list)) | |
554 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
555 | ||
556 | /* | |
ba84bd71 | 557 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
558 | * when someone submits a bad physical address in a |
559 | * descriptor, we should consider ourselves lucky that the | |
560 | * controller flagged an error instead of scribbling over | |
561 | * random memory locations. | |
562 | */ | |
ba84bd71 AS |
563 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
564 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 565 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 566 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
567 | dwc_dump_lli(dwc, &child->lli); |
568 | ||
69cea5a0 VK |
569 | spin_unlock_irqrestore(&dwc->lock, flags); |
570 | ||
3bfb1d20 | 571 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 572 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
573 | } |
574 | ||
d9de4519 HCE |
575 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
576 | ||
577 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
578 | { | |
579 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
580 | return channel_readl(dwc, SAR); | |
581 | } | |
582 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
583 | ||
584 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
585 | { | |
586 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
587 | return channel_readl(dwc, DAR); | |
588 | } | |
589 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
590 | ||
591 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
592 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 593 | u32 status_err, u32 status_xfer) |
d9de4519 | 594 | { |
69cea5a0 VK |
595 | unsigned long flags; |
596 | ||
ff7b05f2 | 597 | if (dwc->mask) { |
d9de4519 HCE |
598 | void (*callback)(void *param); |
599 | void *callback_param; | |
600 | ||
601 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
602 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
603 | |
604 | callback = dwc->cdesc->period_callback; | |
605 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
606 | |
607 | if (callback) | |
d9de4519 | 608 | callback(callback_param); |
d9de4519 HCE |
609 | } |
610 | ||
611 | /* | |
612 | * Error and transfer complete are highly unlikely, and will most | |
613 | * likely be due to a configuration error by the user. | |
614 | */ | |
615 | if (unlikely(status_err & dwc->mask) || | |
616 | unlikely(status_xfer & dwc->mask)) { | |
617 | int i; | |
618 | ||
619 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
620 | "interrupt, stopping DMA transfer\n", | |
621 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
622 | |
623 | spin_lock_irqsave(&dwc->lock, flags); | |
624 | ||
1d455437 | 625 | dwc_dump_chan_regs(dwc); |
d9de4519 | 626 | |
3f936207 | 627 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
628 | |
629 | /* make sure DMA does not restart by loading a new list */ | |
630 | channel_writel(dwc, LLP, 0); | |
631 | channel_writel(dwc, CTL_LO, 0); | |
632 | channel_writel(dwc, CTL_HI, 0); | |
633 | ||
d9de4519 HCE |
634 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
635 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
636 | ||
637 | for (i = 0; i < dwc->cdesc->periods; i++) | |
638 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
639 | |
640 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
641 | } |
642 | } | |
643 | ||
644 | /* ------------------------------------------------------------------------- */ | |
645 | ||
3bfb1d20 HS |
646 | static void dw_dma_tasklet(unsigned long data) |
647 | { | |
648 | struct dw_dma *dw = (struct dw_dma *)data; | |
649 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
650 | u32 status_xfer; |
651 | u32 status_err; | |
652 | int i; | |
653 | ||
7fe7b2f4 | 654 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
655 | status_err = dma_readl(dw, RAW.ERROR); |
656 | ||
2e4c364e | 657 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
658 | |
659 | for (i = 0; i < dw->dma.chancnt; i++) { | |
660 | dwc = &dw->chan[i]; | |
d9de4519 | 661 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 662 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 663 | else if (status_err & (1 << i)) |
3bfb1d20 | 664 | dwc_handle_error(dw, dwc); |
77bcc497 | 665 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 666 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
667 | } |
668 | ||
669 | /* | |
ff7b05f2 | 670 | * Re-enable interrupts. |
3bfb1d20 HS |
671 | */ |
672 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
673 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
674 | } | |
675 | ||
676 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
677 | { | |
678 | struct dw_dma *dw = dev_id; | |
679 | u32 status; | |
680 | ||
2e4c364e | 681 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
682 | dma_readl(dw, STATUS_INT)); |
683 | ||
684 | /* | |
685 | * Just disable the interrupts. We'll turn them back on in the | |
686 | * softirq handler. | |
687 | */ | |
688 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
689 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
690 | ||
691 | status = dma_readl(dw, STATUS_INT); | |
692 | if (status) { | |
693 | dev_err(dw->dma.dev, | |
694 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
695 | status); | |
696 | ||
697 | /* Try to recover */ | |
698 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
699 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
700 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
701 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
702 | } | |
703 | ||
704 | tasklet_schedule(&dw->tasklet); | |
705 | ||
706 | return IRQ_HANDLED; | |
707 | } | |
708 | ||
709 | /*----------------------------------------------------------------------*/ | |
710 | ||
711 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
712 | { | |
713 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
714 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
715 | dma_cookie_t cookie; | |
69cea5a0 | 716 | unsigned long flags; |
3bfb1d20 | 717 | |
69cea5a0 | 718 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 719 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
720 | |
721 | /* | |
722 | * REVISIT: We should attempt to chain as many descriptors as | |
723 | * possible, perhaps even appending to those already submitted | |
724 | * for DMA. But this is hard to do in a race-free manner. | |
725 | */ | |
726 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 727 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 728 | desc->txd.cookie); |
3bfb1d20 | 729 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 730 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 731 | } else { |
2e4c364e | 732 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
733 | desc->txd.cookie); |
734 | ||
735 | list_add_tail(&desc->desc_node, &dwc->queue); | |
736 | } | |
737 | ||
69cea5a0 | 738 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
739 | |
740 | return cookie; | |
741 | } | |
742 | ||
743 | static struct dma_async_tx_descriptor * | |
744 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
745 | size_t len, unsigned long flags) | |
746 | { | |
747 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
748 | struct dw_desc *desc; | |
749 | struct dw_desc *first; | |
750 | struct dw_desc *prev; | |
751 | size_t xfer_count; | |
752 | size_t offset; | |
753 | unsigned int src_width; | |
754 | unsigned int dst_width; | |
3d4f8605 | 755 | unsigned int data_width; |
3bfb1d20 HS |
756 | u32 ctllo; |
757 | ||
2f45d613 | 758 | dev_vdbg(chan2dev(chan), |
2e4c364e | 759 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
760 | (unsigned long long)dest, (unsigned long long)src, |
761 | len, flags); | |
3bfb1d20 HS |
762 | |
763 | if (unlikely(!len)) { | |
2e4c364e | 764 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
765 | return NULL; |
766 | } | |
767 | ||
0fdb567f AS |
768 | dwc->direction = DMA_MEM_TO_MEM; |
769 | ||
23d5f4ec AS |
770 | data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER), |
771 | dwc_get_data_width(chan, DST_MASTER)); | |
a0982004 | 772 | |
3d4f8605 AS |
773 | src_width = dst_width = min_t(unsigned int, data_width, |
774 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 775 | |
327e6970 | 776 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
777 | | DWC_CTLL_DST_WIDTH(dst_width) |
778 | | DWC_CTLL_SRC_WIDTH(src_width) | |
779 | | DWC_CTLL_DST_INC | |
780 | | DWC_CTLL_SRC_INC | |
781 | | DWC_CTLL_FC_M2M; | |
782 | prev = first = NULL; | |
783 | ||
784 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
785 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 786 | dwc->block_size); |
3bfb1d20 HS |
787 | |
788 | desc = dwc_desc_get(dwc); | |
789 | if (!desc) | |
790 | goto err_desc_get; | |
791 | ||
792 | desc->lli.sar = src + offset; | |
793 | desc->lli.dar = dest + offset; | |
794 | desc->lli.ctllo = ctllo; | |
795 | desc->lli.ctlhi = xfer_count; | |
176dcec5 | 796 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
797 | |
798 | if (!first) { | |
799 | first = desc; | |
800 | } else { | |
801 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 802 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 803 | &first->tx_list); |
3bfb1d20 HS |
804 | } |
805 | prev = desc; | |
806 | } | |
807 | ||
3bfb1d20 HS |
808 | if (flags & DMA_PREP_INTERRUPT) |
809 | /* Trigger interrupt after last block */ | |
810 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
811 | ||
812 | prev->lli.llp = 0; | |
3bfb1d20 | 813 | first->txd.flags = flags; |
30d38a32 | 814 | first->total_len = len; |
3bfb1d20 HS |
815 | |
816 | return &first->txd; | |
817 | ||
818 | err_desc_get: | |
819 | dwc_desc_put(dwc, first); | |
820 | return NULL; | |
821 | } | |
822 | ||
823 | static struct dma_async_tx_descriptor * | |
824 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 825 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 826 | unsigned long flags, void *context) |
3bfb1d20 HS |
827 | { |
828 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 829 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
830 | struct dw_desc *prev; |
831 | struct dw_desc *first; | |
832 | u32 ctllo; | |
833 | dma_addr_t reg; | |
834 | unsigned int reg_width; | |
835 | unsigned int mem_width; | |
a0982004 | 836 | unsigned int data_width; |
3bfb1d20 HS |
837 | unsigned int i; |
838 | struct scatterlist *sg; | |
839 | size_t total_len = 0; | |
840 | ||
2e4c364e | 841 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 842 | |
495aea4b | 843 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
844 | return NULL; |
845 | ||
0fdb567f AS |
846 | dwc->direction = direction; |
847 | ||
3bfb1d20 HS |
848 | prev = first = NULL; |
849 | ||
3bfb1d20 | 850 | switch (direction) { |
db8196df | 851 | case DMA_MEM_TO_DEV: |
327e6970 VK |
852 | reg_width = __fls(sconfig->dst_addr_width); |
853 | reg = sconfig->dst_addr; | |
854 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
855 | | DWC_CTLL_DST_WIDTH(reg_width) |
856 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
857 | | DWC_CTLL_SRC_INC); |
858 | ||
859 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
860 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
861 | ||
23d5f4ec | 862 | data_width = dwc_get_data_width(chan, SRC_MASTER); |
a0982004 | 863 | |
3bfb1d20 HS |
864 | for_each_sg(sgl, sg, sg_len, i) { |
865 | struct dw_desc *desc; | |
69dc14b5 | 866 | u32 len, dlen, mem; |
3bfb1d20 | 867 | |
cbb796cc | 868 | mem = sg_dma_address(sg); |
69dc14b5 | 869 | len = sg_dma_len(sg); |
6bc711f6 | 870 | |
a0982004 AS |
871 | mem_width = min_t(unsigned int, |
872 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 873 | |
69dc14b5 | 874 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
875 | desc = dwc_desc_get(dwc); |
876 | if (!desc) { | |
41d5e59c | 877 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
878 | "not enough descriptors available\n"); |
879 | goto err_desc_get; | |
880 | } | |
881 | ||
3bfb1d20 HS |
882 | desc->lli.sar = mem; |
883 | desc->lli.dar = reg; | |
884 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
885 | if ((len >> mem_width) > dwc->block_size) { |
886 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
887 | mem += dlen; |
888 | len -= dlen; | |
889 | } else { | |
890 | dlen = len; | |
891 | len = 0; | |
892 | } | |
893 | ||
894 | desc->lli.ctlhi = dlen >> mem_width; | |
176dcec5 | 895 | desc->len = dlen; |
3bfb1d20 HS |
896 | |
897 | if (!first) { | |
898 | first = desc; | |
899 | } else { | |
900 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 901 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 902 | &first->tx_list); |
3bfb1d20 HS |
903 | } |
904 | prev = desc; | |
69dc14b5 VK |
905 | total_len += dlen; |
906 | ||
907 | if (len) | |
908 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
909 | } |
910 | break; | |
db8196df | 911 | case DMA_DEV_TO_MEM: |
327e6970 VK |
912 | reg_width = __fls(sconfig->src_addr_width); |
913 | reg = sconfig->src_addr; | |
914 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
915 | | DWC_CTLL_SRC_WIDTH(reg_width) |
916 | | DWC_CTLL_DST_INC | |
327e6970 VK |
917 | | DWC_CTLL_SRC_FIX); |
918 | ||
919 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
920 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 921 | |
23d5f4ec | 922 | data_width = dwc_get_data_width(chan, DST_MASTER); |
a0982004 | 923 | |
3bfb1d20 HS |
924 | for_each_sg(sgl, sg, sg_len, i) { |
925 | struct dw_desc *desc; | |
69dc14b5 | 926 | u32 len, dlen, mem; |
3bfb1d20 | 927 | |
cbb796cc | 928 | mem = sg_dma_address(sg); |
3bfb1d20 | 929 | len = sg_dma_len(sg); |
6bc711f6 | 930 | |
a0982004 AS |
931 | mem_width = min_t(unsigned int, |
932 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 933 | |
69dc14b5 VK |
934 | slave_sg_fromdev_fill_desc: |
935 | desc = dwc_desc_get(dwc); | |
936 | if (!desc) { | |
937 | dev_err(chan2dev(chan), | |
938 | "not enough descriptors available\n"); | |
939 | goto err_desc_get; | |
940 | } | |
941 | ||
3bfb1d20 HS |
942 | desc->lli.sar = reg; |
943 | desc->lli.dar = mem; | |
944 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
945 | if ((len >> reg_width) > dwc->block_size) { |
946 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
947 | mem += dlen; |
948 | len -= dlen; | |
949 | } else { | |
950 | dlen = len; | |
951 | len = 0; | |
952 | } | |
953 | desc->lli.ctlhi = dlen >> reg_width; | |
176dcec5 | 954 | desc->len = dlen; |
3bfb1d20 HS |
955 | |
956 | if (!first) { | |
957 | first = desc; | |
958 | } else { | |
959 | prev->lli.llp = desc->txd.phys; | |
3bfb1d20 | 960 | list_add_tail(&desc->desc_node, |
e0bd0f8c | 961 | &first->tx_list); |
3bfb1d20 HS |
962 | } |
963 | prev = desc; | |
69dc14b5 VK |
964 | total_len += dlen; |
965 | ||
966 | if (len) | |
967 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
968 | } |
969 | break; | |
970 | default: | |
971 | return NULL; | |
972 | } | |
973 | ||
974 | if (flags & DMA_PREP_INTERRUPT) | |
975 | /* Trigger interrupt after last block */ | |
976 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
977 | ||
978 | prev->lli.llp = 0; | |
30d38a32 | 979 | first->total_len = total_len; |
3bfb1d20 HS |
980 | |
981 | return &first->txd; | |
982 | ||
983 | err_desc_get: | |
984 | dwc_desc_put(dwc, first); | |
985 | return NULL; | |
986 | } | |
987 | ||
327e6970 VK |
988 | /* |
989 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
990 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
991 | * | |
992 | * NOTE: burst size 2 is not supported by controller. | |
993 | * | |
994 | * This can be done by finding least significant bit set: n & (n - 1) | |
995 | */ | |
996 | static inline void convert_burst(u32 *maxburst) | |
997 | { | |
998 | if (*maxburst > 1) | |
999 | *maxburst = fls(*maxburst) - 2; | |
1000 | else | |
1001 | *maxburst = 0; | |
1002 | } | |
1003 | ||
bce95c63 AS |
1004 | static inline void convert_slave_id(struct dw_dma_chan *dwc) |
1005 | { | |
1006 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1007 | ||
1008 | dwc->dma_sconfig.slave_id -= dw->request_line_base; | |
1009 | } | |
1010 | ||
327e6970 VK |
1011 | static int |
1012 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
1013 | { | |
1014 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1015 | ||
495aea4b AS |
1016 | /* Check if chan will be configured for slave transfers */ |
1017 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
1018 | return -EINVAL; |
1019 | ||
1020 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 1021 | dwc->direction = sconfig->direction; |
327e6970 VK |
1022 | |
1023 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
1024 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
bce95c63 | 1025 | convert_slave_id(dwc); |
327e6970 VK |
1026 | |
1027 | return 0; | |
1028 | } | |
1029 | ||
21fe3c52 AS |
1030 | static inline void dwc_chan_pause(struct dw_dma_chan *dwc) |
1031 | { | |
1032 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
123b69ab | 1033 | unsigned int count = 20; /* timeout iterations */ |
21fe3c52 AS |
1034 | |
1035 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
123b69ab AS |
1036 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
1037 | udelay(2); | |
21fe3c52 AS |
1038 | |
1039 | dwc->paused = true; | |
1040 | } | |
1041 | ||
1042 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
1043 | { | |
1044 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
1045 | ||
1046 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1047 | ||
1048 | dwc->paused = false; | |
1049 | } | |
1050 | ||
05827630 LW |
1051 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
1052 | unsigned long arg) | |
3bfb1d20 HS |
1053 | { |
1054 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1055 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1056 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1057 | unsigned long flags; |
3bfb1d20 HS |
1058 | LIST_HEAD(list); |
1059 | ||
a7c57cf7 LW |
1060 | if (cmd == DMA_PAUSE) { |
1061 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1062 | |
21fe3c52 | 1063 | dwc_chan_pause(dwc); |
3bfb1d20 | 1064 | |
a7c57cf7 LW |
1065 | spin_unlock_irqrestore(&dwc->lock, flags); |
1066 | } else if (cmd == DMA_RESUME) { | |
1067 | if (!dwc->paused) | |
1068 | return 0; | |
3bfb1d20 | 1069 | |
a7c57cf7 | 1070 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1071 | |
21fe3c52 | 1072 | dwc_chan_resume(dwc); |
3bfb1d20 | 1073 | |
a7c57cf7 LW |
1074 | spin_unlock_irqrestore(&dwc->lock, flags); |
1075 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1076 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1077 | |
fed2574b AS |
1078 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1079 | ||
3f936207 | 1080 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1081 | |
a5dbff11 | 1082 | dwc_chan_resume(dwc); |
a7c57cf7 LW |
1083 | |
1084 | /* active_list entries will end up before queued entries */ | |
1085 | list_splice_init(&dwc->queue, &list); | |
1086 | list_splice_init(&dwc->active_list, &list); | |
1087 | ||
1088 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1089 | ||
1090 | /* Flush all pending and queued descriptors */ | |
1091 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1092 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1093 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1094 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1095 | } else { | |
a7c57cf7 | 1096 | return -ENXIO; |
327e6970 | 1097 | } |
c3635c78 LW |
1098 | |
1099 | return 0; | |
3bfb1d20 HS |
1100 | } |
1101 | ||
4702d524 AS |
1102 | static inline u32 dwc_get_residue(struct dw_dma_chan *dwc) |
1103 | { | |
1104 | unsigned long flags; | |
1105 | u32 residue; | |
1106 | ||
1107 | spin_lock_irqsave(&dwc->lock, flags); | |
1108 | ||
1109 | residue = dwc->residue; | |
1110 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1111 | residue -= dwc_get_sent(dwc); | |
1112 | ||
1113 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1114 | return residue; | |
1115 | } | |
1116 | ||
3bfb1d20 | 1117 | static enum dma_status |
07934481 LW |
1118 | dwc_tx_status(struct dma_chan *chan, |
1119 | dma_cookie_t cookie, | |
1120 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1121 | { |
1122 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1123 | enum dma_status ret; |
3bfb1d20 | 1124 | |
96a2af41 | 1125 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1126 | if (ret != DMA_SUCCESS) { |
1127 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1128 | ||
96a2af41 | 1129 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1130 | } |
1131 | ||
abf53902 | 1132 | if (ret != DMA_SUCCESS) |
4702d524 | 1133 | dma_set_residue(txstate, dwc_get_residue(dwc)); |
3bfb1d20 | 1134 | |
a7c57cf7 LW |
1135 | if (dwc->paused) |
1136 | return DMA_PAUSED; | |
3bfb1d20 HS |
1137 | |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | static void dwc_issue_pending(struct dma_chan *chan) | |
1142 | { | |
1143 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1144 | ||
3bfb1d20 HS |
1145 | if (!list_empty(&dwc->queue)) |
1146 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1147 | } |
1148 | ||
aa1e6f1a | 1149 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1150 | { |
1151 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1152 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1153 | struct dw_desc *desc; | |
3bfb1d20 | 1154 | int i; |
69cea5a0 | 1155 | unsigned long flags; |
3bfb1d20 | 1156 | |
2e4c364e | 1157 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1158 | |
3bfb1d20 HS |
1159 | /* ASSERT: channel is idle */ |
1160 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1161 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1162 | return -EIO; |
1163 | } | |
1164 | ||
d3ee98cd | 1165 | dma_cookie_init(chan); |
3bfb1d20 | 1166 | |
3bfb1d20 HS |
1167 | /* |
1168 | * NOTE: some controllers may have additional features that we | |
1169 | * need to initialize here, like "scatter-gather" (which | |
1170 | * doesn't mean what you think it means), and status writeback. | |
1171 | */ | |
1172 | ||
69cea5a0 | 1173 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1174 | i = dwc->descs_allocated; |
1175 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
f8122a82 AS |
1176 | dma_addr_t phys; |
1177 | ||
69cea5a0 | 1178 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1179 | |
f8122a82 | 1180 | desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys); |
cbd65312 AS |
1181 | if (!desc) |
1182 | goto err_desc_alloc; | |
3bfb1d20 | 1183 | |
f8122a82 | 1184 | memset(desc, 0, sizeof(struct dw_desc)); |
3bfb1d20 | 1185 | |
e0bd0f8c | 1186 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1187 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1188 | desc->txd.tx_submit = dwc_tx_submit; | |
1189 | desc->txd.flags = DMA_CTRL_ACK; | |
f8122a82 | 1190 | desc->txd.phys = phys; |
cbd65312 | 1191 | |
3bfb1d20 HS |
1192 | dwc_desc_put(dwc, desc); |
1193 | ||
69cea5a0 | 1194 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1195 | i = ++dwc->descs_allocated; |
1196 | } | |
1197 | ||
69cea5a0 | 1198 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1199 | |
2e4c364e | 1200 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1201 | |
cbd65312 AS |
1202 | return i; |
1203 | ||
1204 | err_desc_alloc: | |
cbd65312 AS |
1205 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); |
1206 | ||
3bfb1d20 HS |
1207 | return i; |
1208 | } | |
1209 | ||
1210 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1211 | { | |
1212 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1213 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1214 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1215 | unsigned long flags; |
3bfb1d20 HS |
1216 | LIST_HEAD(list); |
1217 | ||
2e4c364e | 1218 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1219 | dwc->descs_allocated); |
1220 | ||
1221 | /* ASSERT: channel is idle */ | |
1222 | BUG_ON(!list_empty(&dwc->active_list)); | |
1223 | BUG_ON(!list_empty(&dwc->queue)); | |
1224 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1225 | ||
69cea5a0 | 1226 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1227 | list_splice_init(&dwc->free_list, &list); |
1228 | dwc->descs_allocated = 0; | |
61e183f8 | 1229 | dwc->initialized = false; |
3bfb1d20 HS |
1230 | |
1231 | /* Disable interrupts */ | |
1232 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1233 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1234 | ||
69cea5a0 | 1235 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1236 | |
1237 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c | 1238 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
f8122a82 | 1239 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
3bfb1d20 HS |
1240 | } |
1241 | ||
2e4c364e | 1242 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1243 | } |
1244 | ||
f9c6a655 AB |
1245 | struct dw_dma_filter_args { |
1246 | struct dw_dma *dw; | |
1247 | unsigned int req; | |
1248 | unsigned int src; | |
1249 | unsigned int dst; | |
1250 | }; | |
1251 | ||
1252 | static bool dw_dma_generic_filter(struct dma_chan *chan, void *param) | |
a9ddb575 | 1253 | { |
f9c6a655 | 1254 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
a9ddb575 | 1255 | struct dw_dma *dw = to_dw_dma(chan->device); |
f9c6a655 AB |
1256 | struct dw_dma_filter_args *fargs = param; |
1257 | struct dw_dma_slave *dws = &dwc->slave; | |
a9ddb575 | 1258 | |
f9c6a655 AB |
1259 | /* ensure the device matches our channel */ |
1260 | if (chan->device != &fargs->dw->dma) | |
1261 | return false; | |
a9ddb575 | 1262 | |
f9c6a655 AB |
1263 | dws->dma_dev = dw->dma.dev; |
1264 | dws->cfg_hi = ~0; | |
1265 | dws->cfg_lo = ~0; | |
1266 | dws->src_master = fargs->src; | |
1267 | dws->dst_master = fargs->dst; | |
a9ddb575 | 1268 | |
f9c6a655 AB |
1269 | dwc->request_line = fargs->req; |
1270 | ||
1271 | chan->private = dws; | |
1272 | ||
1273 | return true; | |
1274 | } | |
1275 | ||
1276 | static struct dma_chan *dw_dma_xlate(struct of_phandle_args *dma_spec, | |
1277 | struct of_dma *ofdma) | |
1278 | { | |
1279 | struct dw_dma *dw = ofdma->of_dma_data; | |
1280 | struct dw_dma_filter_args fargs = { | |
1281 | .dw = dw, | |
1282 | }; | |
1283 | dma_cap_mask_t cap; | |
1284 | ||
1285 | if (dma_spec->args_count != 3) | |
1286 | return NULL; | |
1287 | ||
f73bb9b3 AB |
1288 | fargs.req = dma_spec->args[0]; |
1289 | fargs.src = dma_spec->args[1]; | |
1290 | fargs.dst = dma_spec->args[2]; | |
f9c6a655 AB |
1291 | |
1292 | if (WARN_ON(fargs.req >= DW_DMA_MAX_NR_REQUESTS || | |
1293 | fargs.src >= dw->nr_masters || | |
1294 | fargs.dst >= dw->nr_masters)) | |
1295 | return NULL; | |
a9ddb575 | 1296 | |
f9c6a655 AB |
1297 | dma_cap_zero(cap); |
1298 | dma_cap_set(DMA_SLAVE, cap); | |
1299 | ||
1300 | /* TODO: there should be a simpler way to do this */ | |
1301 | return dma_request_channel(cap, dw_dma_generic_filter, &fargs); | |
a9ddb575 | 1302 | } |
a9ddb575 | 1303 | |
d9de4519 HCE |
1304 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1305 | ||
1306 | /** | |
1307 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1308 | * @chan: the DMA channel to start | |
1309 | * | |
1310 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1311 | * -errno on failure. | |
1312 | */ | |
1313 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1314 | { | |
1315 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1316 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1317 | unsigned long flags; |
d9de4519 HCE |
1318 | |
1319 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1320 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1321 | return -ENODEV; | |
1322 | } | |
1323 | ||
69cea5a0 | 1324 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1325 | |
1326 | /* assert channel is idle */ | |
1327 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1328 | dev_err(chan2dev(&dwc->chan), | |
1329 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1330 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1331 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1332 | return -EBUSY; |
1333 | } | |
1334 | ||
d9de4519 HCE |
1335 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1336 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1337 | ||
1338 | /* setup DMAC channel registers */ | |
1339 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1340 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1341 | channel_writel(dwc, CTL_HI, 0); | |
1342 | ||
1343 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1344 | ||
69cea5a0 | 1345 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1350 | ||
1351 | /** | |
1352 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1353 | * @chan: the DMA channel to stop | |
1354 | * | |
1355 | * Must be called with soft interrupts disabled. | |
1356 | */ | |
1357 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1358 | { | |
1359 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1360 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1361 | unsigned long flags; |
d9de4519 | 1362 | |
69cea5a0 | 1363 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1364 | |
3f936207 | 1365 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1366 | |
69cea5a0 | 1367 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1368 | } |
1369 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1370 | ||
1371 | /** | |
1372 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1373 | * @chan: the DMA channel to prepare | |
1374 | * @buf_addr: physical DMA address where the buffer starts | |
1375 | * @buf_len: total number of bytes for the entire buffer | |
1376 | * @period_len: number of bytes for each period | |
1377 | * @direction: transfer direction, to or from device | |
1378 | * | |
1379 | * Must be called before trying to start the transfer. Returns a valid struct | |
1380 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1381 | */ | |
1382 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1383 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1384 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1385 | { |
1386 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1387 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1388 | struct dw_cyclic_desc *cdesc; |
1389 | struct dw_cyclic_desc *retval = NULL; | |
1390 | struct dw_desc *desc; | |
1391 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1392 | unsigned long was_cyclic; |
1393 | unsigned int reg_width; | |
1394 | unsigned int periods; | |
1395 | unsigned int i; | |
69cea5a0 | 1396 | unsigned long flags; |
d9de4519 | 1397 | |
69cea5a0 | 1398 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1399 | if (dwc->nollp) { |
1400 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1401 | dev_dbg(chan2dev(&dwc->chan), | |
1402 | "channel doesn't support LLP transfers\n"); | |
1403 | return ERR_PTR(-EINVAL); | |
1404 | } | |
1405 | ||
d9de4519 | 1406 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1407 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1408 | dev_dbg(chan2dev(&dwc->chan), |
1409 | "queue and/or active list are not empty\n"); | |
1410 | return ERR_PTR(-EBUSY); | |
1411 | } | |
1412 | ||
1413 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1414 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1415 | if (was_cyclic) { |
1416 | dev_dbg(chan2dev(&dwc->chan), | |
1417 | "channel already prepared for cyclic DMA\n"); | |
1418 | return ERR_PTR(-EBUSY); | |
1419 | } | |
1420 | ||
1421 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1422 | |
f44b92f4 AS |
1423 | if (unlikely(!is_slave_direction(direction))) |
1424 | goto out_err; | |
1425 | ||
0fdb567f AS |
1426 | dwc->direction = direction; |
1427 | ||
327e6970 VK |
1428 | if (direction == DMA_MEM_TO_DEV) |
1429 | reg_width = __ffs(sconfig->dst_addr_width); | |
1430 | else | |
1431 | reg_width = __ffs(sconfig->src_addr_width); | |
1432 | ||
d9de4519 HCE |
1433 | periods = buf_len / period_len; |
1434 | ||
1435 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1436 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1437 | goto out_err; |
1438 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1439 | goto out_err; | |
1440 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1441 | goto out_err; | |
d9de4519 HCE |
1442 | |
1443 | retval = ERR_PTR(-ENOMEM); | |
1444 | ||
1445 | if (periods > NR_DESCS_PER_CHANNEL) | |
1446 | goto out_err; | |
1447 | ||
1448 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1449 | if (!cdesc) | |
1450 | goto out_err; | |
1451 | ||
1452 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1453 | if (!cdesc->desc) | |
1454 | goto out_err_alloc; | |
1455 | ||
1456 | for (i = 0; i < periods; i++) { | |
1457 | desc = dwc_desc_get(dwc); | |
1458 | if (!desc) | |
1459 | goto out_err_desc_get; | |
1460 | ||
1461 | switch (direction) { | |
db8196df | 1462 | case DMA_MEM_TO_DEV: |
327e6970 | 1463 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1464 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1465 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1466 | | DWC_CTLL_DST_WIDTH(reg_width) |
1467 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1468 | | DWC_CTLL_DST_FIX | |
1469 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1470 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1471 | |
1472 | desc->lli.ctllo |= sconfig->device_fc ? | |
1473 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1474 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1475 | ||
d9de4519 | 1476 | break; |
db8196df | 1477 | case DMA_DEV_TO_MEM: |
d9de4519 | 1478 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1479 | desc->lli.sar = sconfig->src_addr; |
1480 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1481 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1482 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1483 | | DWC_CTLL_DST_INC | |
1484 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1485 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1486 | |
1487 | desc->lli.ctllo |= sconfig->device_fc ? | |
1488 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1489 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1490 | ||
d9de4519 HCE |
1491 | break; |
1492 | default: | |
1493 | break; | |
1494 | } | |
1495 | ||
1496 | desc->lli.ctlhi = (period_len >> reg_width); | |
1497 | cdesc->desc[i] = desc; | |
1498 | ||
f8122a82 | 1499 | if (last) |
d9de4519 | 1500 | last->lli.llp = desc->txd.phys; |
d9de4519 HCE |
1501 | |
1502 | last = desc; | |
1503 | } | |
1504 | ||
1505 | /* lets make a cyclic list */ | |
1506 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
d9de4519 | 1507 | |
2f45d613 AS |
1508 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1509 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1510 | buf_len, period_len, periods); | |
d9de4519 HCE |
1511 | |
1512 | cdesc->periods = periods; | |
1513 | dwc->cdesc = cdesc; | |
1514 | ||
1515 | return cdesc; | |
1516 | ||
1517 | out_err_desc_get: | |
1518 | while (i--) | |
1519 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1520 | out_err_alloc: | |
1521 | kfree(cdesc); | |
1522 | out_err: | |
1523 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1524 | return (struct dw_cyclic_desc *)retval; | |
1525 | } | |
1526 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1527 | ||
1528 | /** | |
1529 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1530 | * @chan: the DMA channel to free | |
1531 | */ | |
1532 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1533 | { | |
1534 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1535 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1536 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1537 | int i; | |
69cea5a0 | 1538 | unsigned long flags; |
d9de4519 | 1539 | |
2e4c364e | 1540 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1541 | |
1542 | if (!cdesc) | |
1543 | return; | |
1544 | ||
69cea5a0 | 1545 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1546 | |
3f936207 | 1547 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1548 | |
d9de4519 HCE |
1549 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1550 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1551 | ||
69cea5a0 | 1552 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1553 | |
1554 | for (i = 0; i < cdesc->periods; i++) | |
1555 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1556 | ||
1557 | kfree(cdesc->desc); | |
1558 | kfree(cdesc); | |
1559 | ||
1560 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1561 | } | |
1562 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1563 | ||
3bfb1d20 HS |
1564 | /*----------------------------------------------------------------------*/ |
1565 | ||
1566 | static void dw_dma_off(struct dw_dma *dw) | |
1567 | { | |
61e183f8 VK |
1568 | int i; |
1569 | ||
3bfb1d20 HS |
1570 | dma_writel(dw, CFG, 0); |
1571 | ||
1572 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1573 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1574 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1575 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1576 | ||
1577 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1578 | cpu_relax(); | |
61e183f8 VK |
1579 | |
1580 | for (i = 0; i < dw->dma.chancnt; i++) | |
1581 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1582 | } |
1583 | ||
a9ddb575 VK |
1584 | #ifdef CONFIG_OF |
1585 | static struct dw_dma_platform_data * | |
1586 | dw_dma_parse_dt(struct platform_device *pdev) | |
1587 | { | |
f9c6a655 | 1588 | struct device_node *np = pdev->dev.of_node; |
a9ddb575 | 1589 | struct dw_dma_platform_data *pdata; |
a9ddb575 VK |
1590 | u32 tmp, arr[4]; |
1591 | ||
1592 | if (!np) { | |
1593 | dev_err(&pdev->dev, "Missing DT data\n"); | |
1594 | return NULL; | |
1595 | } | |
1596 | ||
1597 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1598 | if (!pdata) | |
1599 | return NULL; | |
1600 | ||
f9c6a655 | 1601 | if (of_property_read_u32(np, "dma-channels", &pdata->nr_channels)) |
a9ddb575 VK |
1602 | return NULL; |
1603 | ||
1604 | if (of_property_read_bool(np, "is_private")) | |
1605 | pdata->is_private = true; | |
1606 | ||
1607 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) | |
1608 | pdata->chan_allocation_order = (unsigned char)tmp; | |
1609 | ||
1610 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
1611 | pdata->chan_priority = tmp; | |
1612 | ||
1613 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
1614 | pdata->block_size = tmp; | |
1615 | ||
f9c6a655 | 1616 | if (!of_property_read_u32(np, "dma-masters", &tmp)) { |
a9ddb575 VK |
1617 | if (tmp > 4) |
1618 | return NULL; | |
1619 | ||
1620 | pdata->nr_masters = tmp; | |
1621 | } | |
1622 | ||
1623 | if (!of_property_read_u32_array(np, "data_width", arr, | |
1624 | pdata->nr_masters)) | |
1625 | for (tmp = 0; tmp < pdata->nr_masters; tmp++) | |
1626 | pdata->data_width[tmp] = arr[tmp]; | |
1627 | ||
a9ddb575 VK |
1628 | return pdata; |
1629 | } | |
1630 | #else | |
1631 | static inline struct dw_dma_platform_data * | |
1632 | dw_dma_parse_dt(struct platform_device *pdev) | |
1633 | { | |
1634 | return NULL; | |
1635 | } | |
1636 | #endif | |
1637 | ||
463a1f8b | 1638 | static int dw_probe(struct platform_device *pdev) |
3bfb1d20 | 1639 | { |
bce95c63 | 1640 | const struct platform_device_id *match; |
3bfb1d20 HS |
1641 | struct dw_dma_platform_data *pdata; |
1642 | struct resource *io; | |
1643 | struct dw_dma *dw; | |
1644 | size_t size; | |
482c67ea AS |
1645 | void __iomem *regs; |
1646 | bool autocfg; | |
1647 | unsigned int dw_params; | |
1648 | unsigned int nr_channels; | |
4a63a8b3 | 1649 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1650 | int irq; |
1651 | int err; | |
1652 | int i; | |
1653 | ||
3bfb1d20 HS |
1654 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1655 | if (!io) | |
1656 | return -EINVAL; | |
1657 | ||
1658 | irq = platform_get_irq(pdev, 0); | |
1659 | if (irq < 0) | |
1660 | return irq; | |
1661 | ||
7331205a TR |
1662 | regs = devm_ioremap_resource(&pdev->dev, io); |
1663 | if (IS_ERR(regs)) | |
1664 | return PTR_ERR(regs); | |
482c67ea | 1665 | |
877e86f2 AS |
1666 | /* Apply default dma_mask if needed */ |
1667 | if (!pdev->dev.dma_mask) { | |
1668 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
1669 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
1670 | } | |
1671 | ||
482c67ea AS |
1672 | dw_params = dma_read_byaddr(regs, DW_PARAMS); |
1673 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1674 | ||
985a6c7d AS |
1675 | dev_dbg(&pdev->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
1676 | ||
123de543 AS |
1677 | pdata = dev_get_platdata(&pdev->dev); |
1678 | if (!pdata) | |
1679 | pdata = dw_dma_parse_dt(pdev); | |
1680 | ||
1681 | if (!pdata && autocfg) { | |
1682 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1683 | if (!pdata) | |
1684 | return -ENOMEM; | |
1685 | ||
1686 | /* Fill platform data with the default values */ | |
1687 | pdata->is_private = true; | |
1688 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1689 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1690 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1691 | return -EINVAL; | |
1692 | ||
482c67ea AS |
1693 | if (autocfg) |
1694 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1695 | else | |
1696 | nr_channels = pdata->nr_channels; | |
1697 | ||
1698 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1699 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1700 | if (!dw) |
1701 | return -ENOMEM; | |
1702 | ||
dbde5c29 AS |
1703 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1704 | if (IS_ERR(dw->clk)) | |
1705 | return PTR_ERR(dw->clk); | |
3075528d | 1706 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1707 | |
482c67ea AS |
1708 | dw->regs = regs; |
1709 | ||
4a63a8b3 | 1710 | /* get hardware configuration parameters */ |
a0982004 | 1711 | if (autocfg) { |
4a63a8b3 AS |
1712 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1713 | ||
a0982004 AS |
1714 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1715 | for (i = 0; i < dw->nr_masters; i++) { | |
1716 | dw->data_width[i] = | |
1717 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1718 | } | |
1719 | } else { | |
1720 | dw->nr_masters = pdata->nr_masters; | |
1721 | memcpy(dw->data_width, pdata->data_width, 4); | |
1722 | } | |
1723 | ||
bce95c63 AS |
1724 | /* Get the base request line if set */ |
1725 | match = platform_get_device_id(pdev); | |
1726 | if (match) | |
1727 | dw->request_line_base = (unsigned int)match->driver_data; | |
1728 | ||
11f932ec | 1729 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1730 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1731 | |
3bfb1d20 HS |
1732 | /* force dma off, just in case */ |
1733 | dw_dma_off(dw); | |
1734 | ||
236b106f AS |
1735 | /* disable BLOCK interrupts as well */ |
1736 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1737 | ||
dbde5c29 AS |
1738 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1739 | "dw_dmac", dw); | |
3bfb1d20 | 1740 | if (err) |
dbde5c29 | 1741 | return err; |
3bfb1d20 HS |
1742 | |
1743 | platform_set_drvdata(pdev, dw); | |
1744 | ||
f8122a82 AS |
1745 | /* create a pool of consistent memory blocks for hardware descriptors */ |
1746 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev, | |
1747 | sizeof(struct dw_desc), 4, 0); | |
1748 | if (!dw->desc_pool) { | |
1749 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1750 | return -ENOMEM; | |
1751 | } | |
1752 | ||
3bfb1d20 HS |
1753 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1754 | ||
3bfb1d20 | 1755 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1756 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1757 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1758 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1759 | |
1760 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1761 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1762 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1763 | list_add_tail(&dwc->chan.device_node, | |
1764 | &dw->dma.channels); | |
1765 | else | |
1766 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1767 | |
93317e8e VK |
1768 | /* 7 is highest priority & 0 is lowest. */ |
1769 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1770 | dwc->priority = r; |
93317e8e VK |
1771 | else |
1772 | dwc->priority = i; | |
1773 | ||
3bfb1d20 HS |
1774 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1775 | spin_lock_init(&dwc->lock); | |
1776 | dwc->mask = 1 << i; | |
1777 | ||
1778 | INIT_LIST_HEAD(&dwc->active_list); | |
1779 | INIT_LIST_HEAD(&dwc->queue); | |
1780 | INIT_LIST_HEAD(&dwc->free_list); | |
1781 | ||
1782 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1783 | |
0fdb567f | 1784 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1785 | |
4a63a8b3 | 1786 | /* hardware configuration */ |
fed2574b AS |
1787 | if (autocfg) { |
1788 | unsigned int dwc_params; | |
1789 | ||
1790 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1791 | DWC_PARAMS); | |
1792 | ||
985a6c7d AS |
1793 | dev_dbg(&pdev->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1794 | dwc_params); | |
1795 | ||
4a63a8b3 AS |
1796 | /* Decode maximum block size for given channel. The |
1797 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1798 | * up to 0x0a for 4095. */ | |
1799 | dwc->block_size = | |
1800 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1801 | dwc->nollp = |
1802 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1803 | } else { | |
4a63a8b3 | 1804 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1805 | |
1806 | /* Check if channel supports multi block transfer */ | |
1807 | channel_writel(dwc, LLP, 0xfffffffc); | |
1808 | dwc->nollp = | |
1809 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1810 | channel_writel(dwc, LLP, 0); | |
1811 | } | |
3bfb1d20 HS |
1812 | } |
1813 | ||
11f932ec | 1814 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1815 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1816 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1817 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1818 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1819 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1820 | ||
3bfb1d20 HS |
1821 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1822 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1823 | if (pdata->is_private) |
1824 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1825 | dw->dma.dev = &pdev->dev; |
1826 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1827 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1828 | ||
1829 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1830 | ||
1831 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1832 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1833 | |
07934481 | 1834 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1835 | dw->dma.device_issue_pending = dwc_issue_pending; |
1836 | ||
1837 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1838 | ||
21d43f49 AS |
1839 | dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", |
1840 | nr_channels); | |
3bfb1d20 HS |
1841 | |
1842 | dma_async_device_register(&dw->dma); | |
1843 | ||
f9c6a655 AB |
1844 | if (pdev->dev.of_node) { |
1845 | err = of_dma_controller_register(pdev->dev.of_node, | |
1846 | dw_dma_xlate, dw); | |
1847 | if (err && err != -ENODEV) | |
1848 | dev_err(&pdev->dev, | |
1849 | "could not register of_dma_controller\n"); | |
1850 | } | |
1851 | ||
3bfb1d20 | 1852 | return 0; |
3bfb1d20 HS |
1853 | } |
1854 | ||
4bf27b8b | 1855 | static int dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1856 | { |
1857 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1858 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 | 1859 | |
f9c6a655 AB |
1860 | if (pdev->dev.of_node) |
1861 | of_dma_controller_free(pdev->dev.of_node); | |
3bfb1d20 HS |
1862 | dw_dma_off(dw); |
1863 | dma_async_device_unregister(&dw->dma); | |
1864 | ||
3bfb1d20 HS |
1865 | tasklet_kill(&dw->tasklet); |
1866 | ||
1867 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1868 | chan.device_node) { | |
1869 | list_del(&dwc->chan.device_node); | |
1870 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1871 | } | |
1872 | ||
3bfb1d20 HS |
1873 | return 0; |
1874 | } | |
1875 | ||
1876 | static void dw_shutdown(struct platform_device *pdev) | |
1877 | { | |
1878 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1879 | ||
6168d567 | 1880 | dw_dma_off(dw); |
3075528d | 1881 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1882 | } |
1883 | ||
4a256b5f | 1884 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1885 | { |
4a256b5f | 1886 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1887 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1888 | ||
6168d567 | 1889 | dw_dma_off(dw); |
3075528d | 1890 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1891 | |
3bfb1d20 HS |
1892 | return 0; |
1893 | } | |
1894 | ||
4a256b5f | 1895 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1896 | { |
4a256b5f | 1897 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1898 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1899 | ||
3075528d | 1900 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1901 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1902 | |
3bfb1d20 | 1903 | return 0; |
3bfb1d20 HS |
1904 | } |
1905 | ||
47145210 | 1906 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1907 | .suspend_noirq = dw_suspend_noirq, |
1908 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1909 | .freeze_noirq = dw_suspend_noirq, |
1910 | .thaw_noirq = dw_resume_noirq, | |
1911 | .restore_noirq = dw_resume_noirq, | |
1912 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1913 | }; |
1914 | ||
d3f797d9 VK |
1915 | #ifdef CONFIG_OF |
1916 | static const struct of_device_id dw_dma_id_table[] = { | |
1917 | { .compatible = "snps,dma-spear1340" }, | |
1918 | {} | |
1919 | }; | |
1920 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1921 | #endif | |
1922 | ||
cfdf5b6c | 1923 | static const struct platform_device_id dw_dma_ids[] = { |
bce95c63 AS |
1924 | /* Name, Request Line Base */ |
1925 | { "INTL9C60", (kernel_ulong_t)16 }, | |
cfdf5b6c MW |
1926 | { } |
1927 | }; | |
1928 | ||
3bfb1d20 | 1929 | static struct platform_driver dw_driver = { |
01126856 | 1930 | .probe = dw_probe, |
a7d6e3ec | 1931 | .remove = dw_remove, |
3bfb1d20 | 1932 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1933 | .driver = { |
1934 | .name = "dw_dmac", | |
4a256b5f | 1935 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1936 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 | 1937 | }, |
cfdf5b6c | 1938 | .id_table = dw_dma_ids, |
3bfb1d20 HS |
1939 | }; |
1940 | ||
1941 | static int __init dw_init(void) | |
1942 | { | |
01126856 | 1943 | return platform_driver_register(&dw_driver); |
3bfb1d20 | 1944 | } |
cb689a70 | 1945 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1946 | |
1947 | static void __exit dw_exit(void) | |
1948 | { | |
1949 | platform_driver_unregister(&dw_driver); | |
1950 | } | |
1951 | module_exit(dw_exit); | |
1952 | ||
1953 | MODULE_LICENSE("GPL v2"); | |
1954 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1955 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1956 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |