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Commit | Line | Data |
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3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | ||
23 | #include "dw_dmac_regs.h" | |
24 | ||
25 | /* | |
26 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
27 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
28 | * of which use ARM any more). See the "Databook" from Synopsys for | |
29 | * information beyond what licensees probably provide. | |
30 | * | |
31 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
32 | * which does not support descriptor writeback. | |
33 | */ | |
34 | ||
f301c062 JI |
35 | #define DWC_DEFAULT_CTLLO(private) ({ \ |
36 | struct dw_dma_slave *__slave = (private); \ | |
37 | int dms = __slave ? __slave->dst_master : 0; \ | |
38 | int sms = __slave ? __slave->src_master : 1; \ | |
e51dc53b VK |
39 | u8 smsize = __slave ? __slave->src_msize : DW_DMA_MSIZE_16; \ |
40 | u8 dmsize = __slave ? __slave->dst_msize : DW_DMA_MSIZE_16; \ | |
f301c062 | 41 | \ |
ee66509d VK |
42 | (DWC_CTLL_DST_MSIZE(dmsize) \ |
43 | | DWC_CTLL_SRC_MSIZE(smsize) \ | |
f301c062 JI |
44 | | DWC_CTLL_LLP_D_EN \ |
45 | | DWC_CTLL_LLP_S_EN \ | |
46 | | DWC_CTLL_DMS(dms) \ | |
47 | | DWC_CTLL_SMS(sms)); \ | |
48 | }) | |
3bfb1d20 HS |
49 | |
50 | /* | |
51 | * This is configuration-dependent and usually a funny size like 4095. | |
3bfb1d20 HS |
52 | * |
53 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
418e7407 | 54 | * words, we can do 16380 bytes per descriptor. |
3bfb1d20 HS |
55 | * |
56 | * This parameter is also system-specific. | |
57 | */ | |
418e7407 | 58 | #define DWC_MAX_COUNT 4095U |
3bfb1d20 HS |
59 | |
60 | /* | |
61 | * Number of descriptors to allocate for each channel. This should be | |
62 | * made configurable somehow; preferably, the clients (at least the | |
63 | * ones using slave transfers) should be able to give us a hint. | |
64 | */ | |
65 | #define NR_DESCS_PER_CHANNEL 64 | |
66 | ||
67 | /*----------------------------------------------------------------------*/ | |
68 | ||
69 | /* | |
70 | * Because we're not relying on writeback from the controller (it may not | |
71 | * even be configured into the core!) we don't need to use dma_pool. These | |
72 | * descriptors -- and associated data -- are cacheable. We do need to make | |
73 | * sure their dcache entries are written back before handing them off to | |
74 | * the controller, though. | |
75 | */ | |
76 | ||
41d5e59c DW |
77 | static struct device *chan2dev(struct dma_chan *chan) |
78 | { | |
79 | return &chan->dev->device; | |
80 | } | |
81 | static struct device *chan2parent(struct dma_chan *chan) | |
82 | { | |
83 | return chan->dev->device.parent; | |
84 | } | |
85 | ||
3bfb1d20 HS |
86 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
87 | { | |
88 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
89 | } | |
90 | ||
3bfb1d20 HS |
91 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
92 | { | |
93 | struct dw_desc *desc, *_desc; | |
94 | struct dw_desc *ret = NULL; | |
95 | unsigned int i = 0; | |
96 | ||
97 | spin_lock_bh(&dwc->lock); | |
98 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { | |
99 | if (async_tx_test_ack(&desc->txd)) { | |
100 | list_del(&desc->desc_node); | |
101 | ret = desc; | |
102 | break; | |
103 | } | |
41d5e59c | 104 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 HS |
105 | i++; |
106 | } | |
107 | spin_unlock_bh(&dwc->lock); | |
108 | ||
41d5e59c | 109 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
110 | |
111 | return ret; | |
112 | } | |
113 | ||
114 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
115 | { | |
116 | struct dw_desc *child; | |
117 | ||
e0bd0f8c | 118 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 119 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
120 | child->txd.phys, sizeof(child->lli), |
121 | DMA_TO_DEVICE); | |
41d5e59c | 122 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
123 | desc->txd.phys, sizeof(desc->lli), |
124 | DMA_TO_DEVICE); | |
125 | } | |
126 | ||
127 | /* | |
128 | * Move a descriptor, including any children, to the free list. | |
129 | * `desc' must not be on any lists. | |
130 | */ | |
131 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
132 | { | |
133 | if (desc) { | |
134 | struct dw_desc *child; | |
135 | ||
136 | dwc_sync_desc_for_cpu(dwc, desc); | |
137 | ||
138 | spin_lock_bh(&dwc->lock); | |
e0bd0f8c | 139 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 140 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
141 | "moving child desc %p to freelist\n", |
142 | child); | |
e0bd0f8c | 143 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 144 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 HS |
145 | list_add(&desc->desc_node, &dwc->free_list); |
146 | spin_unlock_bh(&dwc->lock); | |
147 | } | |
148 | } | |
149 | ||
150 | /* Called with dwc->lock held and bh disabled */ | |
151 | static dma_cookie_t | |
152 | dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
153 | { | |
154 | dma_cookie_t cookie = dwc->chan.cookie; | |
155 | ||
156 | if (++cookie < 0) | |
157 | cookie = 1; | |
158 | ||
159 | dwc->chan.cookie = cookie; | |
160 | desc->txd.cookie = cookie; | |
161 | ||
162 | return cookie; | |
163 | } | |
164 | ||
165 | /*----------------------------------------------------------------------*/ | |
166 | ||
167 | /* Called with dwc->lock held and bh disabled */ | |
168 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
169 | { | |
170 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
171 | ||
172 | /* ASSERT: channel is idle */ | |
173 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 174 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 175 | "BUG: Attempted to start non-idle channel\n"); |
41d5e59c | 176 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
177 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
178 | channel_readl(dwc, SAR), | |
179 | channel_readl(dwc, DAR), | |
180 | channel_readl(dwc, LLP), | |
181 | channel_readl(dwc, CTL_HI), | |
182 | channel_readl(dwc, CTL_LO)); | |
183 | ||
184 | /* The tasklet will hopefully advance the queue... */ | |
185 | return; | |
186 | } | |
187 | ||
188 | channel_writel(dwc, LLP, first->txd.phys); | |
189 | channel_writel(dwc, CTL_LO, | |
190 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
191 | channel_writel(dwc, CTL_HI, 0); | |
192 | channel_set_bit(dw, CH_EN, dwc->mask); | |
193 | } | |
194 | ||
195 | /*----------------------------------------------------------------------*/ | |
196 | ||
197 | static void | |
5fedefb8 VK |
198 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
199 | bool callback_required) | |
3bfb1d20 | 200 | { |
5fedefb8 VK |
201 | dma_async_tx_callback callback = NULL; |
202 | void *param = NULL; | |
3bfb1d20 | 203 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 204 | struct dw_desc *child; |
3bfb1d20 | 205 | |
41d5e59c | 206 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 HS |
207 | |
208 | dwc->completed = txd->cookie; | |
5fedefb8 VK |
209 | if (callback_required) { |
210 | callback = txd->callback; | |
211 | param = txd->callback_param; | |
212 | } | |
3bfb1d20 HS |
213 | |
214 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
215 | |
216 | /* async_tx_ack */ | |
217 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
218 | async_tx_ack(&child->txd); | |
219 | async_tx_ack(&desc->txd); | |
220 | ||
e0bd0f8c | 221 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
222 | list_move(&desc->desc_node, &dwc->free_list); |
223 | ||
657a77fa AN |
224 | if (!dwc->chan.private) { |
225 | struct device *parent = chan2parent(&dwc->chan); | |
226 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
227 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
228 | dma_unmap_single(parent, desc->lli.dar, | |
229 | desc->len, DMA_FROM_DEVICE); | |
230 | else | |
231 | dma_unmap_page(parent, desc->lli.dar, | |
232 | desc->len, DMA_FROM_DEVICE); | |
233 | } | |
234 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
235 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
236 | dma_unmap_single(parent, desc->lli.sar, | |
237 | desc->len, DMA_TO_DEVICE); | |
238 | else | |
239 | dma_unmap_page(parent, desc->lli.sar, | |
240 | desc->len, DMA_TO_DEVICE); | |
241 | } | |
242 | } | |
3bfb1d20 | 243 | |
5fedefb8 | 244 | if (callback_required && callback) |
3bfb1d20 HS |
245 | callback(param); |
246 | } | |
247 | ||
248 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
249 | { | |
250 | struct dw_desc *desc, *_desc; | |
251 | LIST_HEAD(list); | |
252 | ||
253 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 254 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
255 | "BUG: XFER bit set, but channel not idle!\n"); |
256 | ||
257 | /* Try to continue after resetting the channel... */ | |
258 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
259 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
260 | cpu_relax(); | |
261 | } | |
262 | ||
263 | /* | |
264 | * Submit queued descriptors ASAP, i.e. before we go through | |
265 | * the completed ones. | |
266 | */ | |
3bfb1d20 | 267 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
268 | if (!list_empty(&dwc->queue)) { |
269 | list_move(dwc->queue.next, &dwc->active_list); | |
270 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
271 | } | |
3bfb1d20 HS |
272 | |
273 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
5fedefb8 | 274 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
275 | } |
276 | ||
277 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
278 | { | |
279 | dma_addr_t llp; | |
280 | struct dw_desc *desc, *_desc; | |
281 | struct dw_desc *child; | |
282 | u32 status_xfer; | |
283 | ||
284 | /* | |
285 | * Clear block interrupt flag before scanning so that we don't | |
286 | * miss any, and read LLP before RAW_XFER to ensure it is | |
287 | * valid if we decide to scan the list. | |
288 | */ | |
289 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
290 | llp = channel_readl(dwc, LLP); | |
291 | status_xfer = dma_readl(dw, RAW.XFER); | |
292 | ||
293 | if (status_xfer & dwc->mask) { | |
294 | /* Everything we've submitted is done */ | |
295 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
296 | dwc_complete_all(dw, dwc); | |
297 | return; | |
298 | } | |
299 | ||
087809fc JI |
300 | if (list_empty(&dwc->active_list)) |
301 | return; | |
302 | ||
41d5e59c | 303 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); |
3bfb1d20 HS |
304 | |
305 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb VK |
306 | /* check first descriptors addr */ |
307 | if (desc->txd.phys == llp) | |
308 | return; | |
309 | ||
310 | /* check first descriptors llp */ | |
3bfb1d20 HS |
311 | if (desc->lli.llp == llp) |
312 | /* This one is currently in progress */ | |
313 | return; | |
314 | ||
e0bd0f8c | 315 | list_for_each_entry(child, &desc->tx_list, desc_node) |
3bfb1d20 HS |
316 | if (child->lli.llp == llp) |
317 | /* Currently in progress */ | |
318 | return; | |
319 | ||
320 | /* | |
321 | * No descriptors so far seem to be in progress, i.e. | |
322 | * this one must be done. | |
323 | */ | |
5fedefb8 | 324 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
325 | } |
326 | ||
41d5e59c | 327 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
328 | "BUG: All descriptors done, but channel not idle!\n"); |
329 | ||
330 | /* Try to continue after resetting the channel... */ | |
331 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
332 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
333 | cpu_relax(); | |
334 | ||
335 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
336 | list_move(dwc->queue.next, &dwc->active_list); |
337 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 HS |
338 | } |
339 | } | |
340 | ||
341 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
342 | { | |
41d5e59c | 343 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
344 | " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
345 | lli->sar, lli->dar, lli->llp, | |
346 | lli->ctlhi, lli->ctllo); | |
347 | } | |
348 | ||
349 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
350 | { | |
351 | struct dw_desc *bad_desc; | |
352 | struct dw_desc *child; | |
353 | ||
354 | dwc_scan_descriptors(dw, dwc); | |
355 | ||
356 | /* | |
357 | * The descriptor currently at the head of the active list is | |
358 | * borked. Since we don't have any way to report errors, we'll | |
359 | * just have to scream loudly and try to carry on. | |
360 | */ | |
361 | bad_desc = dwc_first_active(dwc); | |
362 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 363 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
364 | |
365 | /* Clear the error flag and try to restart the controller */ | |
366 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
367 | if (!list_empty(&dwc->active_list)) | |
368 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
369 | ||
370 | /* | |
371 | * KERN_CRITICAL may seem harsh, but since this only happens | |
372 | * when someone submits a bad physical address in a | |
373 | * descriptor, we should consider ourselves lucky that the | |
374 | * controller flagged an error instead of scribbling over | |
375 | * random memory locations. | |
376 | */ | |
41d5e59c | 377 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 378 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 379 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
380 | " cookie: %d\n", bad_desc->txd.cookie); |
381 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 382 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
383 | dwc_dump_lli(dwc, &child->lli); |
384 | ||
385 | /* Pretend the descriptor completed successfully */ | |
5fedefb8 | 386 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
387 | } |
388 | ||
d9de4519 HCE |
389 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
390 | ||
391 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
392 | { | |
393 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
394 | return channel_readl(dwc, SAR); | |
395 | } | |
396 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
397 | ||
398 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
399 | { | |
400 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
401 | return channel_readl(dwc, DAR); | |
402 | } | |
403 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
404 | ||
405 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
406 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
407 | u32 status_block, u32 status_err, u32 status_xfer) | |
408 | { | |
409 | if (status_block & dwc->mask) { | |
410 | void (*callback)(void *param); | |
411 | void *callback_param; | |
412 | ||
413 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
414 | channel_readl(dwc, LLP)); | |
415 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
416 | ||
417 | callback = dwc->cdesc->period_callback; | |
418 | callback_param = dwc->cdesc->period_callback_param; | |
419 | if (callback) { | |
420 | spin_unlock(&dwc->lock); | |
421 | callback(callback_param); | |
422 | spin_lock(&dwc->lock); | |
423 | } | |
424 | } | |
425 | ||
426 | /* | |
427 | * Error and transfer complete are highly unlikely, and will most | |
428 | * likely be due to a configuration error by the user. | |
429 | */ | |
430 | if (unlikely(status_err & dwc->mask) || | |
431 | unlikely(status_xfer & dwc->mask)) { | |
432 | int i; | |
433 | ||
434 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
435 | "interrupt, stopping DMA transfer\n", | |
436 | status_xfer ? "xfer" : "error"); | |
437 | dev_err(chan2dev(&dwc->chan), | |
438 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
439 | channel_readl(dwc, SAR), | |
440 | channel_readl(dwc, DAR), | |
441 | channel_readl(dwc, LLP), | |
442 | channel_readl(dwc, CTL_HI), | |
443 | channel_readl(dwc, CTL_LO)); | |
444 | ||
445 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
446 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
447 | cpu_relax(); | |
448 | ||
449 | /* make sure DMA does not restart by loading a new list */ | |
450 | channel_writel(dwc, LLP, 0); | |
451 | channel_writel(dwc, CTL_LO, 0); | |
452 | channel_writel(dwc, CTL_HI, 0); | |
453 | ||
454 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
455 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
456 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
457 | ||
458 | for (i = 0; i < dwc->cdesc->periods; i++) | |
459 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
460 | } | |
461 | } | |
462 | ||
463 | /* ------------------------------------------------------------------------- */ | |
464 | ||
3bfb1d20 HS |
465 | static void dw_dma_tasklet(unsigned long data) |
466 | { | |
467 | struct dw_dma *dw = (struct dw_dma *)data; | |
468 | struct dw_dma_chan *dwc; | |
469 | u32 status_block; | |
470 | u32 status_xfer; | |
471 | u32 status_err; | |
472 | int i; | |
473 | ||
474 | status_block = dma_readl(dw, RAW.BLOCK); | |
7fe7b2f4 | 475 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
476 | status_err = dma_readl(dw, RAW.ERROR); |
477 | ||
478 | dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n", | |
479 | status_block, status_err); | |
480 | ||
481 | for (i = 0; i < dw->dma.chancnt; i++) { | |
482 | dwc = &dw->chan[i]; | |
483 | spin_lock(&dwc->lock); | |
d9de4519 HCE |
484 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
485 | dwc_handle_cyclic(dw, dwc, status_block, status_err, | |
486 | status_xfer); | |
487 | else if (status_err & (1 << i)) | |
3bfb1d20 HS |
488 | dwc_handle_error(dw, dwc); |
489 | else if ((status_block | status_xfer) & (1 << i)) | |
490 | dwc_scan_descriptors(dw, dwc); | |
491 | spin_unlock(&dwc->lock); | |
492 | } | |
493 | ||
494 | /* | |
495 | * Re-enable interrupts. Block Complete interrupts are only | |
496 | * enabled if the INT_EN bit in the descriptor is set. This | |
497 | * will trigger a scan before the whole list is done. | |
498 | */ | |
499 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
500 | channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
501 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
502 | } | |
503 | ||
504 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
505 | { | |
506 | struct dw_dma *dw = dev_id; | |
507 | u32 status; | |
508 | ||
509 | dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n", | |
510 | dma_readl(dw, STATUS_INT)); | |
511 | ||
512 | /* | |
513 | * Just disable the interrupts. We'll turn them back on in the | |
514 | * softirq handler. | |
515 | */ | |
516 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
517 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
518 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
519 | ||
520 | status = dma_readl(dw, STATUS_INT); | |
521 | if (status) { | |
522 | dev_err(dw->dma.dev, | |
523 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
524 | status); | |
525 | ||
526 | /* Try to recover */ | |
527 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
528 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); | |
529 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); | |
530 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
531 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
532 | } | |
533 | ||
534 | tasklet_schedule(&dw->tasklet); | |
535 | ||
536 | return IRQ_HANDLED; | |
537 | } | |
538 | ||
539 | /*----------------------------------------------------------------------*/ | |
540 | ||
541 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
542 | { | |
543 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
544 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
545 | dma_cookie_t cookie; | |
546 | ||
547 | spin_lock_bh(&dwc->lock); | |
548 | cookie = dwc_assign_cookie(dwc, desc); | |
549 | ||
550 | /* | |
551 | * REVISIT: We should attempt to chain as many descriptors as | |
552 | * possible, perhaps even appending to those already submitted | |
553 | * for DMA. But this is hard to do in a race-free manner. | |
554 | */ | |
555 | if (list_empty(&dwc->active_list)) { | |
41d5e59c | 556 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", |
3bfb1d20 | 557 | desc->txd.cookie); |
3bfb1d20 | 558 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 559 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 560 | } else { |
41d5e59c | 561 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", |
3bfb1d20 HS |
562 | desc->txd.cookie); |
563 | ||
564 | list_add_tail(&desc->desc_node, &dwc->queue); | |
565 | } | |
566 | ||
567 | spin_unlock_bh(&dwc->lock); | |
568 | ||
569 | return cookie; | |
570 | } | |
571 | ||
572 | static struct dma_async_tx_descriptor * | |
573 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
574 | size_t len, unsigned long flags) | |
575 | { | |
576 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
577 | struct dw_desc *desc; | |
578 | struct dw_desc *first; | |
579 | struct dw_desc *prev; | |
580 | size_t xfer_count; | |
581 | size_t offset; | |
582 | unsigned int src_width; | |
583 | unsigned int dst_width; | |
584 | u32 ctllo; | |
585 | ||
41d5e59c | 586 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n", |
3bfb1d20 HS |
587 | dest, src, len, flags); |
588 | ||
589 | if (unlikely(!len)) { | |
41d5e59c | 590 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
3bfb1d20 HS |
591 | return NULL; |
592 | } | |
593 | ||
594 | /* | |
595 | * We can be a lot more clever here, but this should take care | |
596 | * of the most common optimization. | |
597 | */ | |
a0227456 VK |
598 | if (!((src | dest | len) & 7)) |
599 | src_width = dst_width = 3; | |
600 | else if (!((src | dest | len) & 3)) | |
3bfb1d20 HS |
601 | src_width = dst_width = 2; |
602 | else if (!((src | dest | len) & 1)) | |
603 | src_width = dst_width = 1; | |
604 | else | |
605 | src_width = dst_width = 0; | |
606 | ||
f301c062 | 607 | ctllo = DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
608 | | DWC_CTLL_DST_WIDTH(dst_width) |
609 | | DWC_CTLL_SRC_WIDTH(src_width) | |
610 | | DWC_CTLL_DST_INC | |
611 | | DWC_CTLL_SRC_INC | |
612 | | DWC_CTLL_FC_M2M; | |
613 | prev = first = NULL; | |
614 | ||
615 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
616 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
617 | DWC_MAX_COUNT); | |
618 | ||
619 | desc = dwc_desc_get(dwc); | |
620 | if (!desc) | |
621 | goto err_desc_get; | |
622 | ||
623 | desc->lli.sar = src + offset; | |
624 | desc->lli.dar = dest + offset; | |
625 | desc->lli.ctllo = ctllo; | |
626 | desc->lli.ctlhi = xfer_count; | |
627 | ||
628 | if (!first) { | |
629 | first = desc; | |
630 | } else { | |
631 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 632 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
633 | prev->txd.phys, sizeof(prev->lli), |
634 | DMA_TO_DEVICE); | |
635 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 636 | &first->tx_list); |
3bfb1d20 HS |
637 | } |
638 | prev = desc; | |
639 | } | |
640 | ||
641 | ||
642 | if (flags & DMA_PREP_INTERRUPT) | |
643 | /* Trigger interrupt after last block */ | |
644 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
645 | ||
646 | prev->lli.llp = 0; | |
41d5e59c | 647 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
648 | prev->txd.phys, sizeof(prev->lli), |
649 | DMA_TO_DEVICE); | |
650 | ||
651 | first->txd.flags = flags; | |
652 | first->len = len; | |
653 | ||
654 | return &first->txd; | |
655 | ||
656 | err_desc_get: | |
657 | dwc_desc_put(dwc, first); | |
658 | return NULL; | |
659 | } | |
660 | ||
661 | static struct dma_async_tx_descriptor * | |
662 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
663 | unsigned int sg_len, enum dma_data_direction direction, | |
664 | unsigned long flags) | |
665 | { | |
666 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 667 | struct dw_dma_slave *dws = chan->private; |
3bfb1d20 HS |
668 | struct dw_desc *prev; |
669 | struct dw_desc *first; | |
670 | u32 ctllo; | |
671 | dma_addr_t reg; | |
672 | unsigned int reg_width; | |
673 | unsigned int mem_width; | |
674 | unsigned int i; | |
675 | struct scatterlist *sg; | |
676 | size_t total_len = 0; | |
677 | ||
41d5e59c | 678 | dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); |
3bfb1d20 HS |
679 | |
680 | if (unlikely(!dws || !sg_len)) | |
681 | return NULL; | |
682 | ||
74465b4f | 683 | reg_width = dws->reg_width; |
3bfb1d20 HS |
684 | prev = first = NULL; |
685 | ||
3bfb1d20 HS |
686 | switch (direction) { |
687 | case DMA_TO_DEVICE: | |
f301c062 | 688 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
689 | | DWC_CTLL_DST_WIDTH(reg_width) |
690 | | DWC_CTLL_DST_FIX | |
691 | | DWC_CTLL_SRC_INC | |
ee66509d | 692 | | DWC_CTLL_FC(dws->fc)); |
74465b4f | 693 | reg = dws->tx_reg; |
3bfb1d20 HS |
694 | for_each_sg(sgl, sg, sg_len, i) { |
695 | struct dw_desc *desc; | |
696 | u32 len; | |
697 | u32 mem; | |
698 | ||
699 | desc = dwc_desc_get(dwc); | |
700 | if (!desc) { | |
41d5e59c | 701 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
702 | "not enough descriptors available\n"); |
703 | goto err_desc_get; | |
704 | } | |
705 | ||
706 | mem = sg_phys(sg); | |
707 | len = sg_dma_len(sg); | |
708 | mem_width = 2; | |
709 | if (unlikely(mem & 3 || len & 3)) | |
710 | mem_width = 0; | |
711 | ||
712 | desc->lli.sar = mem; | |
713 | desc->lli.dar = reg; | |
714 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
715 | desc->lli.ctlhi = len >> mem_width; | |
716 | ||
717 | if (!first) { | |
718 | first = desc; | |
719 | } else { | |
720 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 721 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
722 | prev->txd.phys, |
723 | sizeof(prev->lli), | |
724 | DMA_TO_DEVICE); | |
725 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 726 | &first->tx_list); |
3bfb1d20 HS |
727 | } |
728 | prev = desc; | |
729 | total_len += len; | |
730 | } | |
731 | break; | |
732 | case DMA_FROM_DEVICE: | |
f301c062 | 733 | ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
3bfb1d20 HS |
734 | | DWC_CTLL_SRC_WIDTH(reg_width) |
735 | | DWC_CTLL_DST_INC | |
736 | | DWC_CTLL_SRC_FIX | |
ee66509d | 737 | | DWC_CTLL_FC(dws->fc)); |
3bfb1d20 | 738 | |
74465b4f | 739 | reg = dws->rx_reg; |
3bfb1d20 HS |
740 | for_each_sg(sgl, sg, sg_len, i) { |
741 | struct dw_desc *desc; | |
742 | u32 len; | |
743 | u32 mem; | |
744 | ||
745 | desc = dwc_desc_get(dwc); | |
746 | if (!desc) { | |
41d5e59c | 747 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
748 | "not enough descriptors available\n"); |
749 | goto err_desc_get; | |
750 | } | |
751 | ||
752 | mem = sg_phys(sg); | |
753 | len = sg_dma_len(sg); | |
754 | mem_width = 2; | |
755 | if (unlikely(mem & 3 || len & 3)) | |
756 | mem_width = 0; | |
757 | ||
758 | desc->lli.sar = reg; | |
759 | desc->lli.dar = mem; | |
760 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
761 | desc->lli.ctlhi = len >> reg_width; | |
762 | ||
763 | if (!first) { | |
764 | first = desc; | |
765 | } else { | |
766 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 767 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
768 | prev->txd.phys, |
769 | sizeof(prev->lli), | |
770 | DMA_TO_DEVICE); | |
771 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 772 | &first->tx_list); |
3bfb1d20 HS |
773 | } |
774 | prev = desc; | |
775 | total_len += len; | |
776 | } | |
777 | break; | |
778 | default: | |
779 | return NULL; | |
780 | } | |
781 | ||
782 | if (flags & DMA_PREP_INTERRUPT) | |
783 | /* Trigger interrupt after last block */ | |
784 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
785 | ||
786 | prev->lli.llp = 0; | |
41d5e59c | 787 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
788 | prev->txd.phys, sizeof(prev->lli), |
789 | DMA_TO_DEVICE); | |
790 | ||
791 | first->len = total_len; | |
792 | ||
793 | return &first->txd; | |
794 | ||
795 | err_desc_get: | |
796 | dwc_desc_put(dwc, first); | |
797 | return NULL; | |
798 | } | |
799 | ||
05827630 LW |
800 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
801 | unsigned long arg) | |
3bfb1d20 HS |
802 | { |
803 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
804 | struct dw_dma *dw = to_dw_dma(chan->device); | |
805 | struct dw_desc *desc, *_desc; | |
806 | LIST_HEAD(list); | |
807 | ||
c3635c78 LW |
808 | /* Only supports DMA_TERMINATE_ALL */ |
809 | if (cmd != DMA_TERMINATE_ALL) | |
810 | return -ENXIO; | |
811 | ||
3bfb1d20 HS |
812 | /* |
813 | * This is only called when something went wrong elsewhere, so | |
814 | * we don't really care about the data. Just disable the | |
815 | * channel. We still have to poll the channel enable bit due | |
816 | * to AHB/HSB limitations. | |
817 | */ | |
818 | spin_lock_bh(&dwc->lock); | |
819 | ||
820 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
821 | ||
822 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
823 | cpu_relax(); | |
824 | ||
825 | /* active_list entries will end up before queued entries */ | |
826 | list_splice_init(&dwc->queue, &list); | |
827 | list_splice_init(&dwc->active_list, &list); | |
828 | ||
829 | spin_unlock_bh(&dwc->lock); | |
830 | ||
831 | /* Flush all pending and queued descriptors */ | |
832 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
5fedefb8 | 833 | dwc_descriptor_complete(dwc, desc, false); |
c3635c78 LW |
834 | |
835 | return 0; | |
3bfb1d20 HS |
836 | } |
837 | ||
838 | static enum dma_status | |
07934481 LW |
839 | dwc_tx_status(struct dma_chan *chan, |
840 | dma_cookie_t cookie, | |
841 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
842 | { |
843 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
844 | dma_cookie_t last_used; | |
845 | dma_cookie_t last_complete; | |
846 | int ret; | |
847 | ||
848 | last_complete = dwc->completed; | |
849 | last_used = chan->cookie; | |
850 | ||
851 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
852 | if (ret != DMA_SUCCESS) { | |
569432ef | 853 | spin_lock_bh(&dwc->lock); |
3bfb1d20 | 854 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
569432ef | 855 | spin_unlock_bh(&dwc->lock); |
3bfb1d20 HS |
856 | |
857 | last_complete = dwc->completed; | |
858 | last_used = chan->cookie; | |
859 | ||
860 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
861 | } | |
862 | ||
abf53902 VK |
863 | if (ret != DMA_SUCCESS) |
864 | dma_set_tx_state(txstate, last_complete, last_used, | |
865 | dwc_first_active(dwc)->len); | |
866 | else | |
867 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
3bfb1d20 HS |
868 | |
869 | return ret; | |
870 | } | |
871 | ||
872 | static void dwc_issue_pending(struct dma_chan *chan) | |
873 | { | |
874 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
875 | ||
876 | spin_lock_bh(&dwc->lock); | |
877 | if (!list_empty(&dwc->queue)) | |
878 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
879 | spin_unlock_bh(&dwc->lock); | |
880 | } | |
881 | ||
aa1e6f1a | 882 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
883 | { |
884 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
885 | struct dw_dma *dw = to_dw_dma(chan->device); | |
886 | struct dw_desc *desc; | |
3bfb1d20 HS |
887 | struct dw_dma_slave *dws; |
888 | int i; | |
889 | u32 cfghi; | |
890 | u32 cfglo; | |
891 | ||
41d5e59c | 892 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); |
3bfb1d20 | 893 | |
3bfb1d20 HS |
894 | /* ASSERT: channel is idle */ |
895 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 896 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
897 | return -EIO; |
898 | } | |
899 | ||
900 | dwc->completed = chan->cookie = 1; | |
901 | ||
902 | cfghi = DWC_CFGH_FIFO_MODE; | |
903 | cfglo = 0; | |
904 | ||
287d8592 | 905 | dws = chan->private; |
74465b4f | 906 | if (dws) { |
3bfb1d20 HS |
907 | /* |
908 | * We need controller-specific data to set up slave | |
909 | * transfers. | |
910 | */ | |
74465b4f | 911 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
3bfb1d20 | 912 | |
3bfb1d20 | 913 | cfghi = dws->cfg_hi; |
93317e8e | 914 | cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; |
3bfb1d20 | 915 | } |
93317e8e VK |
916 | |
917 | cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority); | |
918 | ||
3bfb1d20 HS |
919 | channel_writel(dwc, CFG_LO, cfglo); |
920 | channel_writel(dwc, CFG_HI, cfghi); | |
921 | ||
922 | /* | |
923 | * NOTE: some controllers may have additional features that we | |
924 | * need to initialize here, like "scatter-gather" (which | |
925 | * doesn't mean what you think it means), and status writeback. | |
926 | */ | |
927 | ||
928 | spin_lock_bh(&dwc->lock); | |
929 | i = dwc->descs_allocated; | |
930 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
931 | spin_unlock_bh(&dwc->lock); | |
932 | ||
933 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
934 | if (!desc) { | |
41d5e59c | 935 | dev_info(chan2dev(chan), |
3bfb1d20 HS |
936 | "only allocated %d descriptors\n", i); |
937 | spin_lock_bh(&dwc->lock); | |
938 | break; | |
939 | } | |
940 | ||
e0bd0f8c | 941 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
942 | dma_async_tx_descriptor_init(&desc->txd, chan); |
943 | desc->txd.tx_submit = dwc_tx_submit; | |
944 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 945 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
946 | sizeof(desc->lli), DMA_TO_DEVICE); |
947 | dwc_desc_put(dwc, desc); | |
948 | ||
949 | spin_lock_bh(&dwc->lock); | |
950 | i = ++dwc->descs_allocated; | |
951 | } | |
952 | ||
953 | /* Enable interrupts */ | |
954 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
955 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
956 | channel_set_bit(dw, MASK.ERROR, dwc->mask); | |
957 | ||
958 | spin_unlock_bh(&dwc->lock); | |
959 | ||
41d5e59c | 960 | dev_dbg(chan2dev(chan), |
3bfb1d20 HS |
961 | "alloc_chan_resources allocated %d descriptors\n", i); |
962 | ||
963 | return i; | |
964 | } | |
965 | ||
966 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
967 | { | |
968 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
969 | struct dw_dma *dw = to_dw_dma(chan->device); | |
970 | struct dw_desc *desc, *_desc; | |
971 | LIST_HEAD(list); | |
972 | ||
41d5e59c | 973 | dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", |
3bfb1d20 HS |
974 | dwc->descs_allocated); |
975 | ||
976 | /* ASSERT: channel is idle */ | |
977 | BUG_ON(!list_empty(&dwc->active_list)); | |
978 | BUG_ON(!list_empty(&dwc->queue)); | |
979 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
980 | ||
981 | spin_lock_bh(&dwc->lock); | |
982 | list_splice_init(&dwc->free_list, &list); | |
983 | dwc->descs_allocated = 0; | |
3bfb1d20 HS |
984 | |
985 | /* Disable interrupts */ | |
986 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
987 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); | |
988 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); | |
989 | ||
990 | spin_unlock_bh(&dwc->lock); | |
991 | ||
992 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
993 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
994 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
995 | sizeof(desc->lli), DMA_TO_DEVICE); |
996 | kfree(desc); | |
997 | } | |
998 | ||
41d5e59c | 999 | dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); |
3bfb1d20 HS |
1000 | } |
1001 | ||
d9de4519 HCE |
1002 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1003 | ||
1004 | /** | |
1005 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1006 | * @chan: the DMA channel to start | |
1007 | * | |
1008 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1009 | * -errno on failure. | |
1010 | */ | |
1011 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1012 | { | |
1013 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1014 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1015 | ||
1016 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1017 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1018 | return -ENODEV; | |
1019 | } | |
1020 | ||
1021 | spin_lock(&dwc->lock); | |
1022 | ||
1023 | /* assert channel is idle */ | |
1024 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1025 | dev_err(chan2dev(&dwc->chan), | |
1026 | "BUG: Attempted to start non-idle channel\n"); | |
1027 | dev_err(chan2dev(&dwc->chan), | |
1028 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
1029 | channel_readl(dwc, SAR), | |
1030 | channel_readl(dwc, DAR), | |
1031 | channel_readl(dwc, LLP), | |
1032 | channel_readl(dwc, CTL_HI), | |
1033 | channel_readl(dwc, CTL_LO)); | |
1034 | spin_unlock(&dwc->lock); | |
1035 | return -EBUSY; | |
1036 | } | |
1037 | ||
1038 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1039 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1040 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1041 | ||
1042 | /* setup DMAC channel registers */ | |
1043 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1044 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1045 | channel_writel(dwc, CTL_HI, 0); | |
1046 | ||
1047 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1048 | ||
1049 | spin_unlock(&dwc->lock); | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1054 | ||
1055 | /** | |
1056 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1057 | * @chan: the DMA channel to stop | |
1058 | * | |
1059 | * Must be called with soft interrupts disabled. | |
1060 | */ | |
1061 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1062 | { | |
1063 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1064 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1065 | ||
1066 | spin_lock(&dwc->lock); | |
1067 | ||
1068 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1069 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1070 | cpu_relax(); | |
1071 | ||
1072 | spin_unlock(&dwc->lock); | |
1073 | } | |
1074 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1075 | ||
1076 | /** | |
1077 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1078 | * @chan: the DMA channel to prepare | |
1079 | * @buf_addr: physical DMA address where the buffer starts | |
1080 | * @buf_len: total number of bytes for the entire buffer | |
1081 | * @period_len: number of bytes for each period | |
1082 | * @direction: transfer direction, to or from device | |
1083 | * | |
1084 | * Must be called before trying to start the transfer. Returns a valid struct | |
1085 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1086 | */ | |
1087 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1088 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
1089 | enum dma_data_direction direction) | |
1090 | { | |
1091 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1092 | struct dw_cyclic_desc *cdesc; | |
1093 | struct dw_cyclic_desc *retval = NULL; | |
1094 | struct dw_desc *desc; | |
1095 | struct dw_desc *last = NULL; | |
1096 | struct dw_dma_slave *dws = chan->private; | |
1097 | unsigned long was_cyclic; | |
1098 | unsigned int reg_width; | |
1099 | unsigned int periods; | |
1100 | unsigned int i; | |
1101 | ||
1102 | spin_lock_bh(&dwc->lock); | |
1103 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { | |
1104 | spin_unlock_bh(&dwc->lock); | |
1105 | dev_dbg(chan2dev(&dwc->chan), | |
1106 | "queue and/or active list are not empty\n"); | |
1107 | return ERR_PTR(-EBUSY); | |
1108 | } | |
1109 | ||
1110 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1111 | spin_unlock_bh(&dwc->lock); | |
1112 | if (was_cyclic) { | |
1113 | dev_dbg(chan2dev(&dwc->chan), | |
1114 | "channel already prepared for cyclic DMA\n"); | |
1115 | return ERR_PTR(-EBUSY); | |
1116 | } | |
1117 | ||
1118 | retval = ERR_PTR(-EINVAL); | |
1119 | reg_width = dws->reg_width; | |
1120 | periods = buf_len / period_len; | |
1121 | ||
1122 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
1123 | if (period_len > (DWC_MAX_COUNT << reg_width)) | |
1124 | goto out_err; | |
1125 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1126 | goto out_err; | |
1127 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1128 | goto out_err; | |
1129 | if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) | |
1130 | goto out_err; | |
1131 | ||
1132 | retval = ERR_PTR(-ENOMEM); | |
1133 | ||
1134 | if (periods > NR_DESCS_PER_CHANNEL) | |
1135 | goto out_err; | |
1136 | ||
1137 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1138 | if (!cdesc) | |
1139 | goto out_err; | |
1140 | ||
1141 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1142 | if (!cdesc->desc) | |
1143 | goto out_err_alloc; | |
1144 | ||
1145 | for (i = 0; i < periods; i++) { | |
1146 | desc = dwc_desc_get(dwc); | |
1147 | if (!desc) | |
1148 | goto out_err_desc_get; | |
1149 | ||
1150 | switch (direction) { | |
1151 | case DMA_TO_DEVICE: | |
1152 | desc->lli.dar = dws->tx_reg; | |
1153 | desc->lli.sar = buf_addr + (period_len * i); | |
f301c062 | 1154 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
d9de4519 HCE |
1155 | | DWC_CTLL_DST_WIDTH(reg_width) |
1156 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1157 | | DWC_CTLL_DST_FIX | |
1158 | | DWC_CTLL_SRC_INC | |
ee66509d | 1159 | | DWC_CTLL_FC(dws->fc) |
d9de4519 HCE |
1160 | | DWC_CTLL_INT_EN); |
1161 | break; | |
1162 | case DMA_FROM_DEVICE: | |
1163 | desc->lli.dar = buf_addr + (period_len * i); | |
1164 | desc->lli.sar = dws->rx_reg; | |
f301c062 | 1165 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) |
d9de4519 HCE |
1166 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1167 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1168 | | DWC_CTLL_DST_INC | |
1169 | | DWC_CTLL_SRC_FIX | |
ee66509d | 1170 | | DWC_CTLL_FC(dws->fc) |
d9de4519 HCE |
1171 | | DWC_CTLL_INT_EN); |
1172 | break; | |
1173 | default: | |
1174 | break; | |
1175 | } | |
1176 | ||
1177 | desc->lli.ctlhi = (period_len >> reg_width); | |
1178 | cdesc->desc[i] = desc; | |
1179 | ||
1180 | if (last) { | |
1181 | last->lli.llp = desc->txd.phys; | |
1182 | dma_sync_single_for_device(chan2parent(chan), | |
1183 | last->txd.phys, sizeof(last->lli), | |
1184 | DMA_TO_DEVICE); | |
1185 | } | |
1186 | ||
1187 | last = desc; | |
1188 | } | |
1189 | ||
1190 | /* lets make a cyclic list */ | |
1191 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1192 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1193 | sizeof(last->lli), DMA_TO_DEVICE); | |
1194 | ||
1195 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu " | |
1196 | "period %zu periods %d\n", buf_addr, buf_len, | |
1197 | period_len, periods); | |
1198 | ||
1199 | cdesc->periods = periods; | |
1200 | dwc->cdesc = cdesc; | |
1201 | ||
1202 | return cdesc; | |
1203 | ||
1204 | out_err_desc_get: | |
1205 | while (i--) | |
1206 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1207 | out_err_alloc: | |
1208 | kfree(cdesc); | |
1209 | out_err: | |
1210 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1211 | return (struct dw_cyclic_desc *)retval; | |
1212 | } | |
1213 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1214 | ||
1215 | /** | |
1216 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1217 | * @chan: the DMA channel to free | |
1218 | */ | |
1219 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1220 | { | |
1221 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1222 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1223 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1224 | int i; | |
1225 | ||
1226 | dev_dbg(chan2dev(&dwc->chan), "cyclic free\n"); | |
1227 | ||
1228 | if (!cdesc) | |
1229 | return; | |
1230 | ||
1231 | spin_lock_bh(&dwc->lock); | |
1232 | ||
1233 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1234 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1235 | cpu_relax(); | |
1236 | ||
1237 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1238 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1239 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1240 | ||
1241 | spin_unlock_bh(&dwc->lock); | |
1242 | ||
1243 | for (i = 0; i < cdesc->periods; i++) | |
1244 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1245 | ||
1246 | kfree(cdesc->desc); | |
1247 | kfree(cdesc); | |
1248 | ||
1249 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1250 | } | |
1251 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1252 | ||
3bfb1d20 HS |
1253 | /*----------------------------------------------------------------------*/ |
1254 | ||
1255 | static void dw_dma_off(struct dw_dma *dw) | |
1256 | { | |
1257 | dma_writel(dw, CFG, 0); | |
1258 | ||
1259 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1260 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1261 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1262 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1263 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1264 | ||
1265 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1266 | cpu_relax(); | |
1267 | } | |
1268 | ||
1269 | static int __init dw_probe(struct platform_device *pdev) | |
1270 | { | |
1271 | struct dw_dma_platform_data *pdata; | |
1272 | struct resource *io; | |
1273 | struct dw_dma *dw; | |
1274 | size_t size; | |
1275 | int irq; | |
1276 | int err; | |
1277 | int i; | |
1278 | ||
1279 | pdata = pdev->dev.platform_data; | |
1280 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1281 | return -EINVAL; | |
1282 | ||
1283 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1284 | if (!io) | |
1285 | return -EINVAL; | |
1286 | ||
1287 | irq = platform_get_irq(pdev, 0); | |
1288 | if (irq < 0) | |
1289 | return irq; | |
1290 | ||
1291 | size = sizeof(struct dw_dma); | |
1292 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
1293 | dw = kzalloc(size, GFP_KERNEL); | |
1294 | if (!dw) | |
1295 | return -ENOMEM; | |
1296 | ||
1297 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
1298 | err = -EBUSY; | |
1299 | goto err_kfree; | |
1300 | } | |
1301 | ||
3bfb1d20 HS |
1302 | dw->regs = ioremap(io->start, DW_REGLEN); |
1303 | if (!dw->regs) { | |
1304 | err = -ENOMEM; | |
1305 | goto err_release_r; | |
1306 | } | |
1307 | ||
1308 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
1309 | if (IS_ERR(dw->clk)) { | |
1310 | err = PTR_ERR(dw->clk); | |
1311 | goto err_clk; | |
1312 | } | |
1313 | clk_enable(dw->clk); | |
1314 | ||
1315 | /* force dma off, just in case */ | |
1316 | dw_dma_off(dw); | |
1317 | ||
1318 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); | |
1319 | if (err) | |
1320 | goto err_irq; | |
1321 | ||
1322 | platform_set_drvdata(pdev, dw); | |
1323 | ||
1324 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1325 | ||
1326 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1327 | ||
1328 | INIT_LIST_HEAD(&dw->dma.channels); | |
1329 | for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) { | |
1330 | struct dw_dma_chan *dwc = &dw->chan[i]; | |
1331 | ||
1332 | dwc->chan.device = &dw->dma; | |
1333 | dwc->chan.cookie = dwc->completed = 1; | |
1334 | dwc->chan.chan_id = i; | |
b0c3130d VK |
1335 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1336 | list_add_tail(&dwc->chan.device_node, | |
1337 | &dw->dma.channels); | |
1338 | else | |
1339 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1340 | |
93317e8e VK |
1341 | /* 7 is highest priority & 0 is lowest. */ |
1342 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
1343 | dwc->priority = 7 - i; | |
1344 | else | |
1345 | dwc->priority = i; | |
1346 | ||
3bfb1d20 HS |
1347 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1348 | spin_lock_init(&dwc->lock); | |
1349 | dwc->mask = 1 << i; | |
1350 | ||
1351 | INIT_LIST_HEAD(&dwc->active_list); | |
1352 | INIT_LIST_HEAD(&dwc->queue); | |
1353 | INIT_LIST_HEAD(&dwc->free_list); | |
1354 | ||
1355 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1356 | } | |
1357 | ||
1358 | /* Clear/disable all interrupts on all channels. */ | |
1359 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); | |
1360 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); | |
1361 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); | |
1362 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1363 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1364 | ||
1365 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1366 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1367 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1368 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1369 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1370 | ||
1371 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1372 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1373 | if (pdata->is_private) |
1374 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1375 | dw->dma.dev = &pdev->dev; |
1376 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1377 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1378 | ||
1379 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1380 | ||
1381 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1382 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1383 | |
07934481 | 1384 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1385 | dw->dma.device_issue_pending = dwc_issue_pending; |
1386 | ||
1387 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1388 | ||
1389 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
dfbc9019 | 1390 | dev_name(&pdev->dev), dw->dma.chancnt); |
3bfb1d20 HS |
1391 | |
1392 | dma_async_device_register(&dw->dma); | |
1393 | ||
1394 | return 0; | |
1395 | ||
1396 | err_irq: | |
1397 | clk_disable(dw->clk); | |
1398 | clk_put(dw->clk); | |
1399 | err_clk: | |
1400 | iounmap(dw->regs); | |
1401 | dw->regs = NULL; | |
1402 | err_release_r: | |
1403 | release_resource(io); | |
1404 | err_kfree: | |
1405 | kfree(dw); | |
1406 | return err; | |
1407 | } | |
1408 | ||
1409 | static int __exit dw_remove(struct platform_device *pdev) | |
1410 | { | |
1411 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1412 | struct dw_dma_chan *dwc, *_dwc; | |
1413 | struct resource *io; | |
1414 | ||
1415 | dw_dma_off(dw); | |
1416 | dma_async_device_unregister(&dw->dma); | |
1417 | ||
1418 | free_irq(platform_get_irq(pdev, 0), dw); | |
1419 | tasklet_kill(&dw->tasklet); | |
1420 | ||
1421 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1422 | chan.device_node) { | |
1423 | list_del(&dwc->chan.device_node); | |
1424 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1425 | } | |
1426 | ||
1427 | clk_disable(dw->clk); | |
1428 | clk_put(dw->clk); | |
1429 | ||
1430 | iounmap(dw->regs); | |
1431 | dw->regs = NULL; | |
1432 | ||
1433 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1434 | release_mem_region(io->start, DW_REGLEN); | |
1435 | ||
1436 | kfree(dw); | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | static void dw_shutdown(struct platform_device *pdev) | |
1442 | { | |
1443 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1444 | ||
1445 | dw_dma_off(platform_get_drvdata(pdev)); | |
1446 | clk_disable(dw->clk); | |
1447 | } | |
1448 | ||
4a256b5f | 1449 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1450 | { |
4a256b5f | 1451 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1452 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1453 | ||
1454 | dw_dma_off(platform_get_drvdata(pdev)); | |
1455 | clk_disable(dw->clk); | |
1456 | return 0; | |
1457 | } | |
1458 | ||
4a256b5f | 1459 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1460 | { |
4a256b5f | 1461 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1462 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1463 | ||
1464 | clk_enable(dw->clk); | |
1465 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1466 | return 0; | |
3bfb1d20 HS |
1467 | } |
1468 | ||
47145210 | 1469 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1470 | .suspend_noirq = dw_suspend_noirq, |
1471 | .resume_noirq = dw_resume_noirq, | |
1472 | }; | |
1473 | ||
3bfb1d20 HS |
1474 | static struct platform_driver dw_driver = { |
1475 | .remove = __exit_p(dw_remove), | |
1476 | .shutdown = dw_shutdown, | |
3bfb1d20 HS |
1477 | .driver = { |
1478 | .name = "dw_dmac", | |
4a256b5f | 1479 | .pm = &dw_dev_pm_ops, |
3bfb1d20 HS |
1480 | }, |
1481 | }; | |
1482 | ||
1483 | static int __init dw_init(void) | |
1484 | { | |
1485 | return platform_driver_probe(&dw_driver, dw_probe); | |
1486 | } | |
cb689a70 | 1487 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1488 | |
1489 | static void __exit dw_exit(void) | |
1490 | { | |
1491 | platform_driver_unregister(&dw_driver); | |
1492 | } | |
1493 | module_exit(dw_exit); | |
1494 | ||
1495 | MODULE_LICENSE("GPL v2"); | |
1496 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
1497 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); |