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Commit | Line | Data |
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3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
b801479b | 11 | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
d3f797d9 | 20 | #include <linux/of.h> |
3bfb1d20 HS |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | ||
26 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 27 | #include "dmaengine.h" |
3bfb1d20 HS |
28 | |
29 | /* | |
30 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
31 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
32 | * of which use ARM any more). See the "Databook" from Synopsys for | |
33 | * information beyond what licensees probably provide. | |
34 | * | |
35 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
36 | * which does not support descriptor writeback. | |
37 | */ | |
38 | ||
a0982004 AS |
39 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
40 | { | |
41 | return slave ? slave->dst_master : 0; | |
42 | } | |
43 | ||
44 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
45 | { | |
46 | return slave ? slave->src_master : 1; | |
47 | } | |
48 | ||
327e6970 VK |
49 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
50 | struct dw_dma_slave *__slave = (_chan->private); \ | |
51 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ | |
52 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
a0982004 AS |
53 | int _dms = dwc_get_dms(__slave); \ |
54 | int _sms = dwc_get_sms(__slave); \ | |
327e6970 VK |
55 | u8 _smsize = __slave ? _sconfig->src_maxburst : \ |
56 | DW_DMA_MSIZE_16; \ | |
57 | u8 _dmsize = __slave ? _sconfig->dst_maxburst : \ | |
58 | DW_DMA_MSIZE_16; \ | |
f301c062 | 59 | \ |
327e6970 VK |
60 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
61 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
62 | | DWC_CTLL_LLP_D_EN \ |
63 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
64 | | DWC_CTLL_DMS(_dms) \ |
65 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 66 | }) |
3bfb1d20 | 67 | |
3bfb1d20 HS |
68 | /* |
69 | * Number of descriptors to allocate for each channel. This should be | |
70 | * made configurable somehow; preferably, the clients (at least the | |
71 | * ones using slave transfers) should be able to give us a hint. | |
72 | */ | |
73 | #define NR_DESCS_PER_CHANNEL 64 | |
74 | ||
75 | /*----------------------------------------------------------------------*/ | |
76 | ||
77 | /* | |
78 | * Because we're not relying on writeback from the controller (it may not | |
79 | * even be configured into the core!) we don't need to use dma_pool. These | |
80 | * descriptors -- and associated data -- are cacheable. We do need to make | |
81 | * sure their dcache entries are written back before handing them off to | |
82 | * the controller, though. | |
83 | */ | |
84 | ||
41d5e59c DW |
85 | static struct device *chan2dev(struct dma_chan *chan) |
86 | { | |
87 | return &chan->dev->device; | |
88 | } | |
89 | static struct device *chan2parent(struct dma_chan *chan) | |
90 | { | |
91 | return chan->dev->device.parent; | |
92 | } | |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
95 | { | |
e63a47a3 | 96 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
97 | } |
98 | ||
3bfb1d20 HS |
99 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
100 | { | |
101 | struct dw_desc *desc, *_desc; | |
102 | struct dw_desc *ret = NULL; | |
103 | unsigned int i = 0; | |
69cea5a0 | 104 | unsigned long flags; |
3bfb1d20 | 105 | |
69cea5a0 | 106 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 107 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 108 | i++; |
3bfb1d20 HS |
109 | if (async_tx_test_ack(&desc->txd)) { |
110 | list_del(&desc->desc_node); | |
111 | ret = desc; | |
112 | break; | |
113 | } | |
41d5e59c | 114 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 115 | } |
69cea5a0 | 116 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 117 | |
41d5e59c | 118 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
119 | |
120 | return ret; | |
121 | } | |
122 | ||
123 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
124 | { | |
125 | struct dw_desc *child; | |
126 | ||
e0bd0f8c | 127 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 128 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
129 | child->txd.phys, sizeof(child->lli), |
130 | DMA_TO_DEVICE); | |
41d5e59c | 131 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
132 | desc->txd.phys, sizeof(desc->lli), |
133 | DMA_TO_DEVICE); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Move a descriptor, including any children, to the free list. | |
138 | * `desc' must not be on any lists. | |
139 | */ | |
140 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
141 | { | |
69cea5a0 VK |
142 | unsigned long flags; |
143 | ||
3bfb1d20 HS |
144 | if (desc) { |
145 | struct dw_desc *child; | |
146 | ||
147 | dwc_sync_desc_for_cpu(dwc, desc); | |
148 | ||
69cea5a0 | 149 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 150 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 151 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
152 | "moving child desc %p to freelist\n", |
153 | child); | |
e0bd0f8c | 154 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 155 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 156 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 157 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
158 | } |
159 | } | |
160 | ||
61e183f8 VK |
161 | static void dwc_initialize(struct dw_dma_chan *dwc) |
162 | { | |
163 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
164 | struct dw_dma_slave *dws = dwc->chan.private; | |
165 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
166 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
167 | ||
168 | if (dwc->initialized == true) | |
169 | return; | |
170 | ||
171 | if (dws) { | |
172 | /* | |
173 | * We need controller-specific data to set up slave | |
174 | * transfers. | |
175 | */ | |
176 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
177 | ||
178 | cfghi = dws->cfg_hi; | |
179 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf AS |
180 | } else { |
181 | if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) | |
182 | cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); | |
183 | else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) | |
184 | cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); | |
61e183f8 VK |
185 | } |
186 | ||
187 | channel_writel(dwc, CFG_LO, cfglo); | |
188 | channel_writel(dwc, CFG_HI, cfghi); | |
189 | ||
190 | /* Enable interrupts */ | |
191 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
192 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
193 | ||
194 | dwc->initialized = true; | |
195 | } | |
196 | ||
3bfb1d20 HS |
197 | /*----------------------------------------------------------------------*/ |
198 | ||
4c2d56c5 AS |
199 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
200 | { | |
201 | /* | |
202 | * We can be a lot more clever here, but this should take care | |
203 | * of the most common optimization. | |
204 | */ | |
205 | if (!(v & 7)) | |
206 | return 3; | |
207 | else if (!(v & 3)) | |
208 | return 2; | |
209 | else if (!(v & 1)) | |
210 | return 1; | |
211 | return 0; | |
212 | } | |
213 | ||
f52b36d2 | 214 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
215 | { |
216 | dev_err(chan2dev(&dwc->chan), | |
217 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
218 | channel_readl(dwc, SAR), | |
219 | channel_readl(dwc, DAR), | |
220 | channel_readl(dwc, LLP), | |
221 | channel_readl(dwc, CTL_HI), | |
222 | channel_readl(dwc, CTL_LO)); | |
223 | } | |
224 | ||
3f936207 AS |
225 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
226 | { | |
227 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
228 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
229 | cpu_relax(); | |
230 | } | |
231 | ||
1d455437 AS |
232 | /*----------------------------------------------------------------------*/ |
233 | ||
fed2574b AS |
234 | /* Perform single block transfer */ |
235 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
236 | struct dw_desc *desc) | |
237 | { | |
238 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
239 | u32 ctllo; | |
240 | ||
241 | /* Software emulation of LLP mode relies on interrupts to continue | |
242 | * multi block transfer. */ | |
243 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
244 | ||
245 | channel_writel(dwc, SAR, desc->lli.sar); | |
246 | channel_writel(dwc, DAR, desc->lli.dar); | |
247 | channel_writel(dwc, CTL_LO, ctllo); | |
248 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
249 | channel_set_bit(dw, CH_EN, dwc->mask); | |
f5c6a7df AS |
250 | |
251 | /* Move pointer to next descriptor */ | |
252 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
253 | } |
254 | ||
3bfb1d20 HS |
255 | /* Called with dwc->lock held and bh disabled */ |
256 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
257 | { | |
258 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 259 | unsigned long was_soft_llp; |
3bfb1d20 HS |
260 | |
261 | /* ASSERT: channel is idle */ | |
262 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 263 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 264 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 265 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
266 | |
267 | /* The tasklet will hopefully advance the queue... */ | |
268 | return; | |
269 | } | |
270 | ||
fed2574b AS |
271 | if (dwc->nollp) { |
272 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
273 | &dwc->flags); | |
274 | if (was_soft_llp) { | |
275 | dev_err(chan2dev(&dwc->chan), | |
276 | "BUG: Attempted to start new LLP transfer " | |
277 | "inside ongoing one\n"); | |
278 | return; | |
279 | } | |
280 | ||
281 | dwc_initialize(dwc); | |
282 | ||
283 | dwc->tx_list = &first->tx_list; | |
f5c6a7df | 284 | dwc->tx_node_active = &first->tx_list; |
fed2574b AS |
285 | |
286 | dwc_do_single_block(dwc, first); | |
287 | ||
288 | return; | |
289 | } | |
290 | ||
61e183f8 VK |
291 | dwc_initialize(dwc); |
292 | ||
3bfb1d20 HS |
293 | channel_writel(dwc, LLP, first->txd.phys); |
294 | channel_writel(dwc, CTL_LO, | |
295 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
296 | channel_writel(dwc, CTL_HI, 0); | |
297 | channel_set_bit(dw, CH_EN, dwc->mask); | |
298 | } | |
299 | ||
300 | /*----------------------------------------------------------------------*/ | |
301 | ||
302 | static void | |
5fedefb8 VK |
303 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
304 | bool callback_required) | |
3bfb1d20 | 305 | { |
5fedefb8 VK |
306 | dma_async_tx_callback callback = NULL; |
307 | void *param = NULL; | |
3bfb1d20 | 308 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 309 | struct dw_desc *child; |
69cea5a0 | 310 | unsigned long flags; |
3bfb1d20 | 311 | |
41d5e59c | 312 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 313 | |
69cea5a0 | 314 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 315 | dma_cookie_complete(txd); |
5fedefb8 VK |
316 | if (callback_required) { |
317 | callback = txd->callback; | |
318 | param = txd->callback_param; | |
319 | } | |
3bfb1d20 HS |
320 | |
321 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
322 | |
323 | /* async_tx_ack */ | |
324 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
325 | async_tx_ack(&child->txd); | |
326 | async_tx_ack(&desc->txd); | |
327 | ||
e0bd0f8c | 328 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
329 | list_move(&desc->desc_node, &dwc->free_list); |
330 | ||
657a77fa AN |
331 | if (!dwc->chan.private) { |
332 | struct device *parent = chan2parent(&dwc->chan); | |
333 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
334 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
335 | dma_unmap_single(parent, desc->lli.dar, | |
336 | desc->len, DMA_FROM_DEVICE); | |
337 | else | |
338 | dma_unmap_page(parent, desc->lli.dar, | |
339 | desc->len, DMA_FROM_DEVICE); | |
340 | } | |
341 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
342 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
343 | dma_unmap_single(parent, desc->lli.sar, | |
344 | desc->len, DMA_TO_DEVICE); | |
345 | else | |
346 | dma_unmap_page(parent, desc->lli.sar, | |
347 | desc->len, DMA_TO_DEVICE); | |
348 | } | |
349 | } | |
3bfb1d20 | 350 | |
69cea5a0 VK |
351 | spin_unlock_irqrestore(&dwc->lock, flags); |
352 | ||
21e93c1e | 353 | if (callback) |
3bfb1d20 HS |
354 | callback(param); |
355 | } | |
356 | ||
357 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
358 | { | |
359 | struct dw_desc *desc, *_desc; | |
360 | LIST_HEAD(list); | |
69cea5a0 | 361 | unsigned long flags; |
3bfb1d20 | 362 | |
69cea5a0 | 363 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 364 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 365 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
366 | "BUG: XFER bit set, but channel not idle!\n"); |
367 | ||
368 | /* Try to continue after resetting the channel... */ | |
3f936207 | 369 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
370 | } |
371 | ||
372 | /* | |
373 | * Submit queued descriptors ASAP, i.e. before we go through | |
374 | * the completed ones. | |
375 | */ | |
3bfb1d20 | 376 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
377 | if (!list_empty(&dwc->queue)) { |
378 | list_move(dwc->queue.next, &dwc->active_list); | |
379 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
380 | } | |
3bfb1d20 | 381 | |
69cea5a0 VK |
382 | spin_unlock_irqrestore(&dwc->lock, flags); |
383 | ||
3bfb1d20 | 384 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 385 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
386 | } |
387 | ||
388 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
389 | { | |
390 | dma_addr_t llp; | |
391 | struct dw_desc *desc, *_desc; | |
392 | struct dw_desc *child; | |
393 | u32 status_xfer; | |
69cea5a0 | 394 | unsigned long flags; |
3bfb1d20 | 395 | |
69cea5a0 | 396 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
397 | llp = channel_readl(dwc, LLP); |
398 | status_xfer = dma_readl(dw, RAW.XFER); | |
399 | ||
400 | if (status_xfer & dwc->mask) { | |
401 | /* Everything we've submitted is done */ | |
402 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
69cea5a0 VK |
403 | spin_unlock_irqrestore(&dwc->lock, flags); |
404 | ||
3bfb1d20 HS |
405 | dwc_complete_all(dw, dwc); |
406 | return; | |
407 | } | |
408 | ||
69cea5a0 VK |
409 | if (list_empty(&dwc->active_list)) { |
410 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 411 | return; |
69cea5a0 | 412 | } |
087809fc | 413 | |
2e4c364e | 414 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 415 | (unsigned long long)llp); |
3bfb1d20 HS |
416 | |
417 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb | 418 | /* check first descriptors addr */ |
69cea5a0 VK |
419 | if (desc->txd.phys == llp) { |
420 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 421 | return; |
69cea5a0 | 422 | } |
84adccfb VK |
423 | |
424 | /* check first descriptors llp */ | |
69cea5a0 | 425 | if (desc->lli.llp == llp) { |
3bfb1d20 | 426 | /* This one is currently in progress */ |
69cea5a0 | 427 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 428 | return; |
69cea5a0 | 429 | } |
3bfb1d20 | 430 | |
e0bd0f8c | 431 | list_for_each_entry(child, &desc->tx_list, desc_node) |
69cea5a0 | 432 | if (child->lli.llp == llp) { |
3bfb1d20 | 433 | /* Currently in progress */ |
69cea5a0 | 434 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 435 | return; |
69cea5a0 | 436 | } |
3bfb1d20 HS |
437 | |
438 | /* | |
439 | * No descriptors so far seem to be in progress, i.e. | |
440 | * this one must be done. | |
441 | */ | |
69cea5a0 | 442 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 443 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 444 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
445 | } |
446 | ||
41d5e59c | 447 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
448 | "BUG: All descriptors done, but channel not idle!\n"); |
449 | ||
450 | /* Try to continue after resetting the channel... */ | |
3f936207 | 451 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
452 | |
453 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
454 | list_move(dwc->queue.next, &dwc->active_list); |
455 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 456 | } |
69cea5a0 | 457 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
458 | } |
459 | ||
93aad1bc | 460 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 461 | { |
21d43f49 AS |
462 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
463 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); | |
3bfb1d20 HS |
464 | } |
465 | ||
466 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
467 | { | |
468 | struct dw_desc *bad_desc; | |
469 | struct dw_desc *child; | |
69cea5a0 | 470 | unsigned long flags; |
3bfb1d20 HS |
471 | |
472 | dwc_scan_descriptors(dw, dwc); | |
473 | ||
69cea5a0 VK |
474 | spin_lock_irqsave(&dwc->lock, flags); |
475 | ||
3bfb1d20 HS |
476 | /* |
477 | * The descriptor currently at the head of the active list is | |
478 | * borked. Since we don't have any way to report errors, we'll | |
479 | * just have to scream loudly and try to carry on. | |
480 | */ | |
481 | bad_desc = dwc_first_active(dwc); | |
482 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 483 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
484 | |
485 | /* Clear the error flag and try to restart the controller */ | |
486 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
487 | if (!list_empty(&dwc->active_list)) | |
488 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
489 | ||
490 | /* | |
ba84bd71 | 491 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
492 | * when someone submits a bad physical address in a |
493 | * descriptor, we should consider ourselves lucky that the | |
494 | * controller flagged an error instead of scribbling over | |
495 | * random memory locations. | |
496 | */ | |
ba84bd71 AS |
497 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
498 | " cookie: %d\n", bad_desc->txd.cookie); | |
3bfb1d20 | 499 | dwc_dump_lli(dwc, &bad_desc->lli); |
e0bd0f8c | 500 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
501 | dwc_dump_lli(dwc, &child->lli); |
502 | ||
69cea5a0 VK |
503 | spin_unlock_irqrestore(&dwc->lock, flags); |
504 | ||
3bfb1d20 | 505 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 506 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
507 | } |
508 | ||
d9de4519 HCE |
509 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
510 | ||
511 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
512 | { | |
513 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
514 | return channel_readl(dwc, SAR); | |
515 | } | |
516 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
517 | ||
518 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
519 | { | |
520 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
521 | return channel_readl(dwc, DAR); | |
522 | } | |
523 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
524 | ||
525 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
526 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 527 | u32 status_err, u32 status_xfer) |
d9de4519 | 528 | { |
69cea5a0 VK |
529 | unsigned long flags; |
530 | ||
ff7b05f2 | 531 | if (dwc->mask) { |
d9de4519 HCE |
532 | void (*callback)(void *param); |
533 | void *callback_param; | |
534 | ||
535 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
536 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
537 | |
538 | callback = dwc->cdesc->period_callback; | |
539 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
540 | |
541 | if (callback) | |
d9de4519 | 542 | callback(callback_param); |
d9de4519 HCE |
543 | } |
544 | ||
545 | /* | |
546 | * Error and transfer complete are highly unlikely, and will most | |
547 | * likely be due to a configuration error by the user. | |
548 | */ | |
549 | if (unlikely(status_err & dwc->mask) || | |
550 | unlikely(status_xfer & dwc->mask)) { | |
551 | int i; | |
552 | ||
553 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
554 | "interrupt, stopping DMA transfer\n", | |
555 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
556 | |
557 | spin_lock_irqsave(&dwc->lock, flags); | |
558 | ||
1d455437 | 559 | dwc_dump_chan_regs(dwc); |
d9de4519 | 560 | |
3f936207 | 561 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
562 | |
563 | /* make sure DMA does not restart by loading a new list */ | |
564 | channel_writel(dwc, LLP, 0); | |
565 | channel_writel(dwc, CTL_LO, 0); | |
566 | channel_writel(dwc, CTL_HI, 0); | |
567 | ||
d9de4519 HCE |
568 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
569 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
570 | ||
571 | for (i = 0; i < dwc->cdesc->periods; i++) | |
572 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
573 | |
574 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
575 | } |
576 | } | |
577 | ||
578 | /* ------------------------------------------------------------------------- */ | |
579 | ||
3bfb1d20 HS |
580 | static void dw_dma_tasklet(unsigned long data) |
581 | { | |
582 | struct dw_dma *dw = (struct dw_dma *)data; | |
583 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
584 | u32 status_xfer; |
585 | u32 status_err; | |
586 | int i; | |
587 | ||
7fe7b2f4 | 588 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
589 | status_err = dma_readl(dw, RAW.ERROR); |
590 | ||
2e4c364e | 591 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
592 | |
593 | for (i = 0; i < dw->dma.chancnt; i++) { | |
594 | dwc = &dw->chan[i]; | |
d9de4519 | 595 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 596 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 597 | else if (status_err & (1 << i)) |
3bfb1d20 | 598 | dwc_handle_error(dw, dwc); |
fed2574b AS |
599 | else if (status_xfer & (1 << i)) { |
600 | unsigned long flags; | |
601 | ||
602 | spin_lock_irqsave(&dwc->lock, flags); | |
603 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
604 | if (dwc->tx_node_active != dwc->tx_list) { | |
605 | struct dw_desc *desc = | |
e63a47a3 | 606 | to_dw_desc(dwc->tx_node_active); |
fed2574b AS |
607 | |
608 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
609 | ||
fed2574b AS |
610 | dwc_do_single_block(dwc, desc); |
611 | ||
612 | spin_unlock_irqrestore(&dwc->lock, flags); | |
613 | continue; | |
fed2574b | 614 | } |
f5c6a7df AS |
615 | /* we are done here */ |
616 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
fed2574b AS |
617 | } |
618 | spin_unlock_irqrestore(&dwc->lock, flags); | |
619 | ||
3bfb1d20 | 620 | dwc_scan_descriptors(dw, dwc); |
fed2574b | 621 | } |
3bfb1d20 HS |
622 | } |
623 | ||
624 | /* | |
ff7b05f2 | 625 | * Re-enable interrupts. |
3bfb1d20 HS |
626 | */ |
627 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
628 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
629 | } | |
630 | ||
631 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
632 | { | |
633 | struct dw_dma *dw = dev_id; | |
634 | u32 status; | |
635 | ||
2e4c364e | 636 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
637 | dma_readl(dw, STATUS_INT)); |
638 | ||
639 | /* | |
640 | * Just disable the interrupts. We'll turn them back on in the | |
641 | * softirq handler. | |
642 | */ | |
643 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
644 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
645 | ||
646 | status = dma_readl(dw, STATUS_INT); | |
647 | if (status) { | |
648 | dev_err(dw->dma.dev, | |
649 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
650 | status); | |
651 | ||
652 | /* Try to recover */ | |
653 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
654 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
655 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
656 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
657 | } | |
658 | ||
659 | tasklet_schedule(&dw->tasklet); | |
660 | ||
661 | return IRQ_HANDLED; | |
662 | } | |
663 | ||
664 | /*----------------------------------------------------------------------*/ | |
665 | ||
666 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
667 | { | |
668 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
669 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
670 | dma_cookie_t cookie; | |
69cea5a0 | 671 | unsigned long flags; |
3bfb1d20 | 672 | |
69cea5a0 | 673 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 674 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
675 | |
676 | /* | |
677 | * REVISIT: We should attempt to chain as many descriptors as | |
678 | * possible, perhaps even appending to those already submitted | |
679 | * for DMA. But this is hard to do in a race-free manner. | |
680 | */ | |
681 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 682 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 683 | desc->txd.cookie); |
3bfb1d20 | 684 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 685 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 686 | } else { |
2e4c364e | 687 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
688 | desc->txd.cookie); |
689 | ||
690 | list_add_tail(&desc->desc_node, &dwc->queue); | |
691 | } | |
692 | ||
69cea5a0 | 693 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
694 | |
695 | return cookie; | |
696 | } | |
697 | ||
698 | static struct dma_async_tx_descriptor * | |
699 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
700 | size_t len, unsigned long flags) | |
701 | { | |
702 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
a0982004 | 703 | struct dw_dma_slave *dws = chan->private; |
3bfb1d20 HS |
704 | struct dw_desc *desc; |
705 | struct dw_desc *first; | |
706 | struct dw_desc *prev; | |
707 | size_t xfer_count; | |
708 | size_t offset; | |
709 | unsigned int src_width; | |
710 | unsigned int dst_width; | |
3d4f8605 | 711 | unsigned int data_width; |
3bfb1d20 HS |
712 | u32 ctllo; |
713 | ||
2f45d613 | 714 | dev_vdbg(chan2dev(chan), |
2e4c364e | 715 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
716 | (unsigned long long)dest, (unsigned long long)src, |
717 | len, flags); | |
3bfb1d20 HS |
718 | |
719 | if (unlikely(!len)) { | |
2e4c364e | 720 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
721 | return NULL; |
722 | } | |
723 | ||
3d4f8605 AS |
724 | data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)], |
725 | dwc->dw->data_width[dwc_get_dms(dws)]); | |
a0982004 | 726 | |
3d4f8605 AS |
727 | src_width = dst_width = min_t(unsigned int, data_width, |
728 | dwc_fast_fls(src | dest | len)); | |
3bfb1d20 | 729 | |
327e6970 | 730 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
731 | | DWC_CTLL_DST_WIDTH(dst_width) |
732 | | DWC_CTLL_SRC_WIDTH(src_width) | |
733 | | DWC_CTLL_DST_INC | |
734 | | DWC_CTLL_SRC_INC | |
735 | | DWC_CTLL_FC_M2M; | |
736 | prev = first = NULL; | |
737 | ||
738 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
739 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 740 | dwc->block_size); |
3bfb1d20 HS |
741 | |
742 | desc = dwc_desc_get(dwc); | |
743 | if (!desc) | |
744 | goto err_desc_get; | |
745 | ||
746 | desc->lli.sar = src + offset; | |
747 | desc->lli.dar = dest + offset; | |
748 | desc->lli.ctllo = ctllo; | |
749 | desc->lli.ctlhi = xfer_count; | |
750 | ||
751 | if (!first) { | |
752 | first = desc; | |
753 | } else { | |
754 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 755 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
756 | prev->txd.phys, sizeof(prev->lli), |
757 | DMA_TO_DEVICE); | |
758 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 759 | &first->tx_list); |
3bfb1d20 HS |
760 | } |
761 | prev = desc; | |
762 | } | |
763 | ||
764 | ||
765 | if (flags & DMA_PREP_INTERRUPT) | |
766 | /* Trigger interrupt after last block */ | |
767 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
768 | ||
769 | prev->lli.llp = 0; | |
41d5e59c | 770 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
771 | prev->txd.phys, sizeof(prev->lli), |
772 | DMA_TO_DEVICE); | |
773 | ||
774 | first->txd.flags = flags; | |
775 | first->len = len; | |
776 | ||
777 | return &first->txd; | |
778 | ||
779 | err_desc_get: | |
780 | dwc_desc_put(dwc, first); | |
781 | return NULL; | |
782 | } | |
783 | ||
784 | static struct dma_async_tx_descriptor * | |
785 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 786 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 787 | unsigned long flags, void *context) |
3bfb1d20 HS |
788 | { |
789 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 790 | struct dw_dma_slave *dws = chan->private; |
327e6970 | 791 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
792 | struct dw_desc *prev; |
793 | struct dw_desc *first; | |
794 | u32 ctllo; | |
795 | dma_addr_t reg; | |
796 | unsigned int reg_width; | |
797 | unsigned int mem_width; | |
a0982004 | 798 | unsigned int data_width; |
3bfb1d20 HS |
799 | unsigned int i; |
800 | struct scatterlist *sg; | |
801 | size_t total_len = 0; | |
802 | ||
2e4c364e | 803 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 HS |
804 | |
805 | if (unlikely(!dws || !sg_len)) | |
806 | return NULL; | |
807 | ||
3bfb1d20 HS |
808 | prev = first = NULL; |
809 | ||
3bfb1d20 | 810 | switch (direction) { |
db8196df | 811 | case DMA_MEM_TO_DEV: |
327e6970 VK |
812 | reg_width = __fls(sconfig->dst_addr_width); |
813 | reg = sconfig->dst_addr; | |
814 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
815 | | DWC_CTLL_DST_WIDTH(reg_width) |
816 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
817 | | DWC_CTLL_SRC_INC); |
818 | ||
819 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
820 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
821 | ||
a0982004 AS |
822 | data_width = dwc->dw->data_width[dwc_get_sms(dws)]; |
823 | ||
3bfb1d20 HS |
824 | for_each_sg(sgl, sg, sg_len, i) { |
825 | struct dw_desc *desc; | |
69dc14b5 | 826 | u32 len, dlen, mem; |
3bfb1d20 | 827 | |
cbb796cc | 828 | mem = sg_dma_address(sg); |
69dc14b5 | 829 | len = sg_dma_len(sg); |
6bc711f6 | 830 | |
a0982004 AS |
831 | mem_width = min_t(unsigned int, |
832 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 833 | |
69dc14b5 | 834 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
835 | desc = dwc_desc_get(dwc); |
836 | if (!desc) { | |
41d5e59c | 837 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
838 | "not enough descriptors available\n"); |
839 | goto err_desc_get; | |
840 | } | |
841 | ||
3bfb1d20 HS |
842 | desc->lli.sar = mem; |
843 | desc->lli.dar = reg; | |
844 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
845 | if ((len >> mem_width) > dwc->block_size) { |
846 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
847 | mem += dlen; |
848 | len -= dlen; | |
849 | } else { | |
850 | dlen = len; | |
851 | len = 0; | |
852 | } | |
853 | ||
854 | desc->lli.ctlhi = dlen >> mem_width; | |
3bfb1d20 HS |
855 | |
856 | if (!first) { | |
857 | first = desc; | |
858 | } else { | |
859 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 860 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
861 | prev->txd.phys, |
862 | sizeof(prev->lli), | |
863 | DMA_TO_DEVICE); | |
864 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 865 | &first->tx_list); |
3bfb1d20 HS |
866 | } |
867 | prev = desc; | |
69dc14b5 VK |
868 | total_len += dlen; |
869 | ||
870 | if (len) | |
871 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
872 | } |
873 | break; | |
db8196df | 874 | case DMA_DEV_TO_MEM: |
327e6970 VK |
875 | reg_width = __fls(sconfig->src_addr_width); |
876 | reg = sconfig->src_addr; | |
877 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
878 | | DWC_CTLL_SRC_WIDTH(reg_width) |
879 | | DWC_CTLL_DST_INC | |
327e6970 VK |
880 | | DWC_CTLL_SRC_FIX); |
881 | ||
882 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
883 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 884 | |
a0982004 AS |
885 | data_width = dwc->dw->data_width[dwc_get_dms(dws)]; |
886 | ||
3bfb1d20 HS |
887 | for_each_sg(sgl, sg, sg_len, i) { |
888 | struct dw_desc *desc; | |
69dc14b5 | 889 | u32 len, dlen, mem; |
3bfb1d20 | 890 | |
cbb796cc | 891 | mem = sg_dma_address(sg); |
3bfb1d20 | 892 | len = sg_dma_len(sg); |
6bc711f6 | 893 | |
a0982004 AS |
894 | mem_width = min_t(unsigned int, |
895 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 896 | |
69dc14b5 VK |
897 | slave_sg_fromdev_fill_desc: |
898 | desc = dwc_desc_get(dwc); | |
899 | if (!desc) { | |
900 | dev_err(chan2dev(chan), | |
901 | "not enough descriptors available\n"); | |
902 | goto err_desc_get; | |
903 | } | |
904 | ||
3bfb1d20 HS |
905 | desc->lli.sar = reg; |
906 | desc->lli.dar = mem; | |
907 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
908 | if ((len >> reg_width) > dwc->block_size) { |
909 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
910 | mem += dlen; |
911 | len -= dlen; | |
912 | } else { | |
913 | dlen = len; | |
914 | len = 0; | |
915 | } | |
916 | desc->lli.ctlhi = dlen >> reg_width; | |
3bfb1d20 HS |
917 | |
918 | if (!first) { | |
919 | first = desc; | |
920 | } else { | |
921 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 922 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
923 | prev->txd.phys, |
924 | sizeof(prev->lli), | |
925 | DMA_TO_DEVICE); | |
926 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 927 | &first->tx_list); |
3bfb1d20 HS |
928 | } |
929 | prev = desc; | |
69dc14b5 VK |
930 | total_len += dlen; |
931 | ||
932 | if (len) | |
933 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
934 | } |
935 | break; | |
936 | default: | |
937 | return NULL; | |
938 | } | |
939 | ||
940 | if (flags & DMA_PREP_INTERRUPT) | |
941 | /* Trigger interrupt after last block */ | |
942 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
943 | ||
944 | prev->lli.llp = 0; | |
41d5e59c | 945 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
946 | prev->txd.phys, sizeof(prev->lli), |
947 | DMA_TO_DEVICE); | |
948 | ||
949 | first->len = total_len; | |
950 | ||
951 | return &first->txd; | |
952 | ||
953 | err_desc_get: | |
954 | dwc_desc_put(dwc, first); | |
955 | return NULL; | |
956 | } | |
957 | ||
327e6970 VK |
958 | /* |
959 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
960 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
961 | * | |
962 | * NOTE: burst size 2 is not supported by controller. | |
963 | * | |
964 | * This can be done by finding least significant bit set: n & (n - 1) | |
965 | */ | |
966 | static inline void convert_burst(u32 *maxburst) | |
967 | { | |
968 | if (*maxburst > 1) | |
969 | *maxburst = fls(*maxburst) - 2; | |
970 | else | |
971 | *maxburst = 0; | |
972 | } | |
973 | ||
974 | static int | |
975 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
976 | { | |
977 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
978 | ||
979 | /* Check if it is chan is configured for slave transfers */ | |
980 | if (!chan->private) | |
981 | return -EINVAL; | |
982 | ||
983 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
984 | ||
985 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
986 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
05827630 LW |
991 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
992 | unsigned long arg) | |
3bfb1d20 HS |
993 | { |
994 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
995 | struct dw_dma *dw = to_dw_dma(chan->device); | |
996 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 997 | unsigned long flags; |
a7c57cf7 | 998 | u32 cfglo; |
3bfb1d20 HS |
999 | LIST_HEAD(list); |
1000 | ||
a7c57cf7 LW |
1001 | if (cmd == DMA_PAUSE) { |
1002 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1003 | |
a7c57cf7 LW |
1004 | cfglo = channel_readl(dwc, CFG_LO); |
1005 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
1006 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
1007 | cpu_relax(); | |
3bfb1d20 | 1008 | |
a7c57cf7 LW |
1009 | dwc->paused = true; |
1010 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1011 | } else if (cmd == DMA_RESUME) { | |
1012 | if (!dwc->paused) | |
1013 | return 0; | |
3bfb1d20 | 1014 | |
a7c57cf7 | 1015 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1016 | |
a7c57cf7 LW |
1017 | cfglo = channel_readl(dwc, CFG_LO); |
1018 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1019 | dwc->paused = false; | |
3bfb1d20 | 1020 | |
a7c57cf7 LW |
1021 | spin_unlock_irqrestore(&dwc->lock, flags); |
1022 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1023 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1024 | |
fed2574b AS |
1025 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1026 | ||
3f936207 | 1027 | dwc_chan_disable(dw, dwc); |
a7c57cf7 LW |
1028 | |
1029 | dwc->paused = false; | |
1030 | ||
1031 | /* active_list entries will end up before queued entries */ | |
1032 | list_splice_init(&dwc->queue, &list); | |
1033 | list_splice_init(&dwc->active_list, &list); | |
1034 | ||
1035 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1036 | ||
1037 | /* Flush all pending and queued descriptors */ | |
1038 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1039 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1040 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1041 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1042 | } else { | |
a7c57cf7 | 1043 | return -ENXIO; |
327e6970 | 1044 | } |
c3635c78 LW |
1045 | |
1046 | return 0; | |
3bfb1d20 HS |
1047 | } |
1048 | ||
1049 | static enum dma_status | |
07934481 LW |
1050 | dwc_tx_status(struct dma_chan *chan, |
1051 | dma_cookie_t cookie, | |
1052 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1053 | { |
1054 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1055 | enum dma_status ret; |
3bfb1d20 | 1056 | |
96a2af41 | 1057 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1058 | if (ret != DMA_SUCCESS) { |
1059 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1060 | ||
96a2af41 | 1061 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1062 | } |
1063 | ||
abf53902 | 1064 | if (ret != DMA_SUCCESS) |
96a2af41 | 1065 | dma_set_residue(txstate, dwc_first_active(dwc)->len); |
3bfb1d20 | 1066 | |
a7c57cf7 LW |
1067 | if (dwc->paused) |
1068 | return DMA_PAUSED; | |
3bfb1d20 HS |
1069 | |
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | static void dwc_issue_pending(struct dma_chan *chan) | |
1074 | { | |
1075 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1076 | ||
3bfb1d20 HS |
1077 | if (!list_empty(&dwc->queue)) |
1078 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1079 | } |
1080 | ||
aa1e6f1a | 1081 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1082 | { |
1083 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1084 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1085 | struct dw_desc *desc; | |
3bfb1d20 | 1086 | int i; |
69cea5a0 | 1087 | unsigned long flags; |
cbd65312 | 1088 | int ret; |
3bfb1d20 | 1089 | |
2e4c364e | 1090 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1091 | |
3bfb1d20 HS |
1092 | /* ASSERT: channel is idle */ |
1093 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1094 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1095 | return -EIO; |
1096 | } | |
1097 | ||
d3ee98cd | 1098 | dma_cookie_init(chan); |
3bfb1d20 | 1099 | |
3bfb1d20 HS |
1100 | /* |
1101 | * NOTE: some controllers may have additional features that we | |
1102 | * need to initialize here, like "scatter-gather" (which | |
1103 | * doesn't mean what you think it means), and status writeback. | |
1104 | */ | |
1105 | ||
69cea5a0 | 1106 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1107 | i = dwc->descs_allocated; |
1108 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
69cea5a0 | 1109 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1110 | |
1111 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
cbd65312 AS |
1112 | if (!desc) |
1113 | goto err_desc_alloc; | |
3bfb1d20 | 1114 | |
e0bd0f8c | 1115 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1116 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1117 | desc->txd.tx_submit = dwc_tx_submit; | |
1118 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 1119 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 | 1120 | sizeof(desc->lli), DMA_TO_DEVICE); |
cbd65312 AS |
1121 | ret = dma_mapping_error(chan2parent(chan), desc->txd.phys); |
1122 | if (ret) | |
1123 | goto err_desc_alloc; | |
1124 | ||
3bfb1d20 HS |
1125 | dwc_desc_put(dwc, desc); |
1126 | ||
69cea5a0 | 1127 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1128 | i = ++dwc->descs_allocated; |
1129 | } | |
1130 | ||
69cea5a0 | 1131 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1132 | |
2e4c364e | 1133 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 | 1134 | |
cbd65312 AS |
1135 | return i; |
1136 | ||
1137 | err_desc_alloc: | |
1138 | kfree(desc); | |
1139 | ||
1140 | dev_info(chan2dev(chan), "only allocated %d descriptors\n", i); | |
1141 | ||
3bfb1d20 HS |
1142 | return i; |
1143 | } | |
1144 | ||
1145 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1146 | { | |
1147 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1148 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1149 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1150 | unsigned long flags; |
3bfb1d20 HS |
1151 | LIST_HEAD(list); |
1152 | ||
2e4c364e | 1153 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1154 | dwc->descs_allocated); |
1155 | ||
1156 | /* ASSERT: channel is idle */ | |
1157 | BUG_ON(!list_empty(&dwc->active_list)); | |
1158 | BUG_ON(!list_empty(&dwc->queue)); | |
1159 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1160 | ||
69cea5a0 | 1161 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1162 | list_splice_init(&dwc->free_list, &list); |
1163 | dwc->descs_allocated = 0; | |
61e183f8 | 1164 | dwc->initialized = false; |
3bfb1d20 HS |
1165 | |
1166 | /* Disable interrupts */ | |
1167 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1168 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1169 | ||
69cea5a0 | 1170 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1171 | |
1172 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
1173 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
1174 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
1175 | sizeof(desc->lli), DMA_TO_DEVICE); |
1176 | kfree(desc); | |
1177 | } | |
1178 | ||
2e4c364e | 1179 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1180 | } |
1181 | ||
a9ddb575 VK |
1182 | bool dw_dma_generic_filter(struct dma_chan *chan, void *param) |
1183 | { | |
1184 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1185 | static struct dw_dma *last_dw; | |
1186 | static char *last_bus_id; | |
1187 | int i = -1; | |
1188 | ||
1189 | /* | |
1190 | * dmaengine framework calls this routine for all channels of all dma | |
1191 | * controller, until true is returned. If 'param' bus_id is not | |
1192 | * registered with a dma controller (dw), then there is no need of | |
1193 | * running below function for all channels of dw. | |
1194 | * | |
1195 | * This block of code does this by saving the parameters of last | |
1196 | * failure. If dw and param are same, i.e. trying on same dw with | |
1197 | * different channel, return false. | |
1198 | */ | |
1199 | if ((last_dw == dw) && (last_bus_id == param)) | |
1200 | return false; | |
1201 | /* | |
1202 | * Return true: | |
1203 | * - If dw_dma's platform data is not filled with slave info, then all | |
1204 | * dma controllers are fine for transfer. | |
1205 | * - Or if param is NULL | |
1206 | */ | |
1207 | if (!dw->sd || !param) | |
1208 | return true; | |
1209 | ||
1210 | while (++i < dw->sd_count) { | |
1211 | if (!strcmp(dw->sd[i].bus_id, param)) { | |
1212 | chan->private = &dw->sd[i]; | |
1213 | last_dw = NULL; | |
1214 | last_bus_id = NULL; | |
1215 | ||
1216 | return true; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | last_dw = dw; | |
1221 | last_bus_id = param; | |
1222 | return false; | |
1223 | } | |
1224 | EXPORT_SYMBOL(dw_dma_generic_filter); | |
1225 | ||
d9de4519 HCE |
1226 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1227 | ||
1228 | /** | |
1229 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1230 | * @chan: the DMA channel to start | |
1231 | * | |
1232 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1233 | * -errno on failure. | |
1234 | */ | |
1235 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1236 | { | |
1237 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1238 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1239 | unsigned long flags; |
d9de4519 HCE |
1240 | |
1241 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1242 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1243 | return -ENODEV; | |
1244 | } | |
1245 | ||
69cea5a0 | 1246 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1247 | |
1248 | /* assert channel is idle */ | |
1249 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1250 | dev_err(chan2dev(&dwc->chan), | |
1251 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1252 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1253 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1254 | return -EBUSY; |
1255 | } | |
1256 | ||
d9de4519 HCE |
1257 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1258 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1259 | ||
1260 | /* setup DMAC channel registers */ | |
1261 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1262 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1263 | channel_writel(dwc, CTL_HI, 0); | |
1264 | ||
1265 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1266 | ||
69cea5a0 | 1267 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1268 | |
1269 | return 0; | |
1270 | } | |
1271 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1272 | ||
1273 | /** | |
1274 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1275 | * @chan: the DMA channel to stop | |
1276 | * | |
1277 | * Must be called with soft interrupts disabled. | |
1278 | */ | |
1279 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1280 | { | |
1281 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1282 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1283 | unsigned long flags; |
d9de4519 | 1284 | |
69cea5a0 | 1285 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1286 | |
3f936207 | 1287 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1288 | |
69cea5a0 | 1289 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1290 | } |
1291 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1292 | ||
1293 | /** | |
1294 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1295 | * @chan: the DMA channel to prepare | |
1296 | * @buf_addr: physical DMA address where the buffer starts | |
1297 | * @buf_len: total number of bytes for the entire buffer | |
1298 | * @period_len: number of bytes for each period | |
1299 | * @direction: transfer direction, to or from device | |
1300 | * | |
1301 | * Must be called before trying to start the transfer. Returns a valid struct | |
1302 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1303 | */ | |
1304 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1305 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1306 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1307 | { |
1308 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1309 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1310 | struct dw_cyclic_desc *cdesc; |
1311 | struct dw_cyclic_desc *retval = NULL; | |
1312 | struct dw_desc *desc; | |
1313 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1314 | unsigned long was_cyclic; |
1315 | unsigned int reg_width; | |
1316 | unsigned int periods; | |
1317 | unsigned int i; | |
69cea5a0 | 1318 | unsigned long flags; |
d9de4519 | 1319 | |
69cea5a0 | 1320 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1321 | if (dwc->nollp) { |
1322 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1323 | dev_dbg(chan2dev(&dwc->chan), | |
1324 | "channel doesn't support LLP transfers\n"); | |
1325 | return ERR_PTR(-EINVAL); | |
1326 | } | |
1327 | ||
d9de4519 | 1328 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1329 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1330 | dev_dbg(chan2dev(&dwc->chan), |
1331 | "queue and/or active list are not empty\n"); | |
1332 | return ERR_PTR(-EBUSY); | |
1333 | } | |
1334 | ||
1335 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1336 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1337 | if (was_cyclic) { |
1338 | dev_dbg(chan2dev(&dwc->chan), | |
1339 | "channel already prepared for cyclic DMA\n"); | |
1340 | return ERR_PTR(-EBUSY); | |
1341 | } | |
1342 | ||
1343 | retval = ERR_PTR(-EINVAL); | |
327e6970 VK |
1344 | |
1345 | if (direction == DMA_MEM_TO_DEV) | |
1346 | reg_width = __ffs(sconfig->dst_addr_width); | |
1347 | else | |
1348 | reg_width = __ffs(sconfig->src_addr_width); | |
1349 | ||
d9de4519 HCE |
1350 | periods = buf_len / period_len; |
1351 | ||
1352 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1353 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1354 | goto out_err; |
1355 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1356 | goto out_err; | |
1357 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1358 | goto out_err; | |
db8196df | 1359 | if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM)))) |
d9de4519 HCE |
1360 | goto out_err; |
1361 | ||
1362 | retval = ERR_PTR(-ENOMEM); | |
1363 | ||
1364 | if (periods > NR_DESCS_PER_CHANNEL) | |
1365 | goto out_err; | |
1366 | ||
1367 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1368 | if (!cdesc) | |
1369 | goto out_err; | |
1370 | ||
1371 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1372 | if (!cdesc->desc) | |
1373 | goto out_err_alloc; | |
1374 | ||
1375 | for (i = 0; i < periods; i++) { | |
1376 | desc = dwc_desc_get(dwc); | |
1377 | if (!desc) | |
1378 | goto out_err_desc_get; | |
1379 | ||
1380 | switch (direction) { | |
db8196df | 1381 | case DMA_MEM_TO_DEV: |
327e6970 | 1382 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1383 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1384 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1385 | | DWC_CTLL_DST_WIDTH(reg_width) |
1386 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1387 | | DWC_CTLL_DST_FIX | |
1388 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1389 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1390 | |
1391 | desc->lli.ctllo |= sconfig->device_fc ? | |
1392 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1393 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1394 | ||
d9de4519 | 1395 | break; |
db8196df | 1396 | case DMA_DEV_TO_MEM: |
d9de4519 | 1397 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1398 | desc->lli.sar = sconfig->src_addr; |
1399 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1400 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1401 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1402 | | DWC_CTLL_DST_INC | |
1403 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1404 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1405 | |
1406 | desc->lli.ctllo |= sconfig->device_fc ? | |
1407 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1408 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1409 | ||
d9de4519 HCE |
1410 | break; |
1411 | default: | |
1412 | break; | |
1413 | } | |
1414 | ||
1415 | desc->lli.ctlhi = (period_len >> reg_width); | |
1416 | cdesc->desc[i] = desc; | |
1417 | ||
1418 | if (last) { | |
1419 | last->lli.llp = desc->txd.phys; | |
1420 | dma_sync_single_for_device(chan2parent(chan), | |
1421 | last->txd.phys, sizeof(last->lli), | |
1422 | DMA_TO_DEVICE); | |
1423 | } | |
1424 | ||
1425 | last = desc; | |
1426 | } | |
1427 | ||
1428 | /* lets make a cyclic list */ | |
1429 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1430 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1431 | sizeof(last->lli), DMA_TO_DEVICE); | |
1432 | ||
2f45d613 AS |
1433 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1434 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1435 | buf_len, period_len, periods); | |
d9de4519 HCE |
1436 | |
1437 | cdesc->periods = periods; | |
1438 | dwc->cdesc = cdesc; | |
1439 | ||
1440 | return cdesc; | |
1441 | ||
1442 | out_err_desc_get: | |
1443 | while (i--) | |
1444 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1445 | out_err_alloc: | |
1446 | kfree(cdesc); | |
1447 | out_err: | |
1448 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1449 | return (struct dw_cyclic_desc *)retval; | |
1450 | } | |
1451 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1452 | ||
1453 | /** | |
1454 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1455 | * @chan: the DMA channel to free | |
1456 | */ | |
1457 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1458 | { | |
1459 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1460 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1461 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1462 | int i; | |
69cea5a0 | 1463 | unsigned long flags; |
d9de4519 | 1464 | |
2e4c364e | 1465 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1466 | |
1467 | if (!cdesc) | |
1468 | return; | |
1469 | ||
69cea5a0 | 1470 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1471 | |
3f936207 | 1472 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1473 | |
d9de4519 HCE |
1474 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1475 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1476 | ||
69cea5a0 | 1477 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1478 | |
1479 | for (i = 0; i < cdesc->periods; i++) | |
1480 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1481 | ||
1482 | kfree(cdesc->desc); | |
1483 | kfree(cdesc); | |
1484 | ||
1485 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1486 | } | |
1487 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1488 | ||
3bfb1d20 HS |
1489 | /*----------------------------------------------------------------------*/ |
1490 | ||
1491 | static void dw_dma_off(struct dw_dma *dw) | |
1492 | { | |
61e183f8 VK |
1493 | int i; |
1494 | ||
3bfb1d20 HS |
1495 | dma_writel(dw, CFG, 0); |
1496 | ||
1497 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1498 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1499 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1500 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1501 | ||
1502 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1503 | cpu_relax(); | |
61e183f8 VK |
1504 | |
1505 | for (i = 0; i < dw->dma.chancnt; i++) | |
1506 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1507 | } |
1508 | ||
a9ddb575 VK |
1509 | #ifdef CONFIG_OF |
1510 | static struct dw_dma_platform_data * | |
1511 | dw_dma_parse_dt(struct platform_device *pdev) | |
1512 | { | |
1513 | struct device_node *sn, *cn, *np = pdev->dev.of_node; | |
1514 | struct dw_dma_platform_data *pdata; | |
1515 | struct dw_dma_slave *sd; | |
1516 | u32 tmp, arr[4]; | |
1517 | ||
1518 | if (!np) { | |
1519 | dev_err(&pdev->dev, "Missing DT data\n"); | |
1520 | return NULL; | |
1521 | } | |
1522 | ||
1523 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1524 | if (!pdata) | |
1525 | return NULL; | |
1526 | ||
1527 | if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels)) | |
1528 | return NULL; | |
1529 | ||
1530 | if (of_property_read_bool(np, "is_private")) | |
1531 | pdata->is_private = true; | |
1532 | ||
1533 | if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) | |
1534 | pdata->chan_allocation_order = (unsigned char)tmp; | |
1535 | ||
1536 | if (!of_property_read_u32(np, "chan_priority", &tmp)) | |
1537 | pdata->chan_priority = tmp; | |
1538 | ||
1539 | if (!of_property_read_u32(np, "block_size", &tmp)) | |
1540 | pdata->block_size = tmp; | |
1541 | ||
1542 | if (!of_property_read_u32(np, "nr_masters", &tmp)) { | |
1543 | if (tmp > 4) | |
1544 | return NULL; | |
1545 | ||
1546 | pdata->nr_masters = tmp; | |
1547 | } | |
1548 | ||
1549 | if (!of_property_read_u32_array(np, "data_width", arr, | |
1550 | pdata->nr_masters)) | |
1551 | for (tmp = 0; tmp < pdata->nr_masters; tmp++) | |
1552 | pdata->data_width[tmp] = arr[tmp]; | |
1553 | ||
1554 | /* parse slave data */ | |
1555 | sn = of_find_node_by_name(np, "slave_info"); | |
1556 | if (!sn) | |
1557 | return pdata; | |
1558 | ||
1559 | /* calculate number of slaves */ | |
1560 | tmp = of_get_child_count(sn); | |
1561 | if (!tmp) | |
1562 | return NULL; | |
1563 | ||
1564 | sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL); | |
1565 | if (!sd) | |
1566 | return NULL; | |
1567 | ||
1568 | pdata->sd = sd; | |
1569 | pdata->sd_count = tmp; | |
1570 | ||
1571 | for_each_child_of_node(sn, cn) { | |
1572 | sd->dma_dev = &pdev->dev; | |
1573 | of_property_read_string(cn, "bus_id", &sd->bus_id); | |
1574 | of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi); | |
1575 | of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo); | |
1576 | if (!of_property_read_u32(cn, "src_master", &tmp)) | |
1577 | sd->src_master = tmp; | |
1578 | ||
1579 | if (!of_property_read_u32(cn, "dst_master", &tmp)) | |
1580 | sd->dst_master = tmp; | |
1581 | sd++; | |
1582 | } | |
1583 | ||
1584 | return pdata; | |
1585 | } | |
1586 | #else | |
1587 | static inline struct dw_dma_platform_data * | |
1588 | dw_dma_parse_dt(struct platform_device *pdev) | |
1589 | { | |
1590 | return NULL; | |
1591 | } | |
1592 | #endif | |
1593 | ||
463a1f8b | 1594 | static int dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1595 | { |
1596 | struct dw_dma_platform_data *pdata; | |
1597 | struct resource *io; | |
1598 | struct dw_dma *dw; | |
1599 | size_t size; | |
482c67ea AS |
1600 | void __iomem *regs; |
1601 | bool autocfg; | |
1602 | unsigned int dw_params; | |
1603 | unsigned int nr_channels; | |
4a63a8b3 | 1604 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1605 | int irq; |
1606 | int err; | |
1607 | int i; | |
1608 | ||
3bfb1d20 HS |
1609 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1610 | if (!io) | |
1611 | return -EINVAL; | |
1612 | ||
1613 | irq = platform_get_irq(pdev, 0); | |
1614 | if (irq < 0) | |
1615 | return irq; | |
1616 | ||
482c67ea AS |
1617 | regs = devm_request_and_ioremap(&pdev->dev, io); |
1618 | if (!regs) | |
1619 | return -EBUSY; | |
1620 | ||
1621 | dw_params = dma_read_byaddr(regs, DW_PARAMS); | |
1622 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1623 | ||
123de543 AS |
1624 | pdata = dev_get_platdata(&pdev->dev); |
1625 | if (!pdata) | |
1626 | pdata = dw_dma_parse_dt(pdev); | |
1627 | ||
1628 | if (!pdata && autocfg) { | |
1629 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1630 | if (!pdata) | |
1631 | return -ENOMEM; | |
1632 | ||
1633 | /* Fill platform data with the default values */ | |
1634 | pdata->is_private = true; | |
1635 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; | |
1636 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
1637 | } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1638 | return -EINVAL; | |
1639 | ||
482c67ea AS |
1640 | if (autocfg) |
1641 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1642 | else | |
1643 | nr_channels = pdata->nr_channels; | |
1644 | ||
1645 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1646 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1647 | if (!dw) |
1648 | return -ENOMEM; | |
1649 | ||
dbde5c29 AS |
1650 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1651 | if (IS_ERR(dw->clk)) | |
1652 | return PTR_ERR(dw->clk); | |
3075528d | 1653 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1654 | |
482c67ea | 1655 | dw->regs = regs; |
a9ddb575 VK |
1656 | dw->sd = pdata->sd; |
1657 | dw->sd_count = pdata->sd_count; | |
482c67ea | 1658 | |
4a63a8b3 | 1659 | /* get hardware configuration parameters */ |
a0982004 | 1660 | if (autocfg) { |
4a63a8b3 AS |
1661 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1662 | ||
a0982004 AS |
1663 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1664 | for (i = 0; i < dw->nr_masters; i++) { | |
1665 | dw->data_width[i] = | |
1666 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1667 | } | |
1668 | } else { | |
1669 | dw->nr_masters = pdata->nr_masters; | |
1670 | memcpy(dw->data_width, pdata->data_width, 4); | |
1671 | } | |
1672 | ||
11f932ec | 1673 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1674 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1675 | |
3bfb1d20 HS |
1676 | /* force dma off, just in case */ |
1677 | dw_dma_off(dw); | |
1678 | ||
236b106f AS |
1679 | /* disable BLOCK interrupts as well */ |
1680 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1681 | ||
dbde5c29 AS |
1682 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1683 | "dw_dmac", dw); | |
3bfb1d20 | 1684 | if (err) |
dbde5c29 | 1685 | return err; |
3bfb1d20 HS |
1686 | |
1687 | platform_set_drvdata(pdev, dw); | |
1688 | ||
1689 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1690 | ||
3bfb1d20 | 1691 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1692 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1693 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1694 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1695 | |
1696 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1697 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1698 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1699 | list_add_tail(&dwc->chan.device_node, | |
1700 | &dw->dma.channels); | |
1701 | else | |
1702 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1703 | |
93317e8e VK |
1704 | /* 7 is highest priority & 0 is lowest. */ |
1705 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1706 | dwc->priority = r; |
93317e8e VK |
1707 | else |
1708 | dwc->priority = i; | |
1709 | ||
3bfb1d20 HS |
1710 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1711 | spin_lock_init(&dwc->lock); | |
1712 | dwc->mask = 1 << i; | |
1713 | ||
1714 | INIT_LIST_HEAD(&dwc->active_list); | |
1715 | INIT_LIST_HEAD(&dwc->queue); | |
1716 | INIT_LIST_HEAD(&dwc->free_list); | |
1717 | ||
1718 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1719 | |
a0982004 AS |
1720 | dwc->dw = dw; |
1721 | ||
4a63a8b3 | 1722 | /* hardware configuration */ |
fed2574b AS |
1723 | if (autocfg) { |
1724 | unsigned int dwc_params; | |
1725 | ||
1726 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1727 | DWC_PARAMS); | |
1728 | ||
4a63a8b3 AS |
1729 | /* Decode maximum block size for given channel. The |
1730 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1731 | * up to 0x0a for 4095. */ | |
1732 | dwc->block_size = | |
1733 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1734 | dwc->nollp = |
1735 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1736 | } else { | |
4a63a8b3 | 1737 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1738 | |
1739 | /* Check if channel supports multi block transfer */ | |
1740 | channel_writel(dwc, LLP, 0xfffffffc); | |
1741 | dwc->nollp = | |
1742 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1743 | channel_writel(dwc, LLP, 0); | |
1744 | } | |
3bfb1d20 HS |
1745 | } |
1746 | ||
11f932ec | 1747 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1748 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1749 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1750 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1751 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1752 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1753 | ||
3bfb1d20 HS |
1754 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1755 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1756 | if (pdata->is_private) |
1757 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1758 | dw->dma.dev = &pdev->dev; |
1759 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1760 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1761 | ||
1762 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1763 | ||
1764 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1765 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1766 | |
07934481 | 1767 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1768 | dw->dma.device_issue_pending = dwc_issue_pending; |
1769 | ||
1770 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1771 | ||
21d43f49 AS |
1772 | dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n", |
1773 | nr_channels); | |
3bfb1d20 HS |
1774 | |
1775 | dma_async_device_register(&dw->dma); | |
1776 | ||
1777 | return 0; | |
3bfb1d20 HS |
1778 | } |
1779 | ||
0272e93f | 1780 | static int __devexit dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1781 | { |
1782 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1783 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 HS |
1784 | |
1785 | dw_dma_off(dw); | |
1786 | dma_async_device_unregister(&dw->dma); | |
1787 | ||
3bfb1d20 HS |
1788 | tasklet_kill(&dw->tasklet); |
1789 | ||
1790 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1791 | chan.device_node) { | |
1792 | list_del(&dwc->chan.device_node); | |
1793 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1794 | } | |
1795 | ||
3bfb1d20 HS |
1796 | return 0; |
1797 | } | |
1798 | ||
1799 | static void dw_shutdown(struct platform_device *pdev) | |
1800 | { | |
1801 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1802 | ||
6168d567 | 1803 | dw_dma_off(dw); |
3075528d | 1804 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1805 | } |
1806 | ||
4a256b5f | 1807 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1808 | { |
4a256b5f | 1809 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1810 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1811 | ||
6168d567 | 1812 | dw_dma_off(dw); |
3075528d | 1813 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1814 | |
3bfb1d20 HS |
1815 | return 0; |
1816 | } | |
1817 | ||
4a256b5f | 1818 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1819 | { |
4a256b5f | 1820 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1821 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1822 | ||
3075528d | 1823 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1824 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
b801479b | 1825 | |
3bfb1d20 | 1826 | return 0; |
3bfb1d20 HS |
1827 | } |
1828 | ||
47145210 | 1829 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1830 | .suspend_noirq = dw_suspend_noirq, |
1831 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1832 | .freeze_noirq = dw_suspend_noirq, |
1833 | .thaw_noirq = dw_resume_noirq, | |
1834 | .restore_noirq = dw_resume_noirq, | |
1835 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1836 | }; |
1837 | ||
d3f797d9 VK |
1838 | #ifdef CONFIG_OF |
1839 | static const struct of_device_id dw_dma_id_table[] = { | |
1840 | { .compatible = "snps,dma-spear1340" }, | |
1841 | {} | |
1842 | }; | |
1843 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1844 | #endif | |
1845 | ||
3bfb1d20 | 1846 | static struct platform_driver dw_driver = { |
a7d6e3ec | 1847 | .remove = dw_remove, |
3bfb1d20 | 1848 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1849 | .driver = { |
1850 | .name = "dw_dmac", | |
4a256b5f | 1851 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1852 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 HS |
1853 | }, |
1854 | }; | |
1855 | ||
1856 | static int __init dw_init(void) | |
1857 | { | |
1858 | return platform_driver_probe(&dw_driver, dw_probe); | |
1859 | } | |
cb689a70 | 1860 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1861 | |
1862 | static void __exit dw_exit(void) | |
1863 | { | |
1864 | platform_driver_unregister(&dw_driver); | |
1865 | } | |
1866 | module_exit(dw_exit); | |
1867 | ||
1868 | MODULE_LICENSE("GPL v2"); | |
1869 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1870 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1871 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |