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Commit | Line | Data |
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3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
327e6970 | 12 | #include <linux/bitops.h> |
3bfb1d20 HS |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/io.h> | |
d3f797d9 | 20 | #include <linux/of.h> |
3bfb1d20 HS |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | ||
26 | #include "dw_dmac_regs.h" | |
d2ebfb33 | 27 | #include "dmaengine.h" |
3bfb1d20 HS |
28 | |
29 | /* | |
30 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
31 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
32 | * of which use ARM any more). See the "Databook" from Synopsys for | |
33 | * information beyond what licensees probably provide. | |
34 | * | |
35 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
36 | * which does not support descriptor writeback. | |
37 | */ | |
38 | ||
a0982004 AS |
39 | static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave) |
40 | { | |
41 | return slave ? slave->dst_master : 0; | |
42 | } | |
43 | ||
44 | static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave) | |
45 | { | |
46 | return slave ? slave->src_master : 1; | |
47 | } | |
48 | ||
327e6970 VK |
49 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
50 | struct dw_dma_slave *__slave = (_chan->private); \ | |
51 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ | |
52 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
a0982004 AS |
53 | int _dms = dwc_get_dms(__slave); \ |
54 | int _sms = dwc_get_sms(__slave); \ | |
327e6970 VK |
55 | u8 _smsize = __slave ? _sconfig->src_maxburst : \ |
56 | DW_DMA_MSIZE_16; \ | |
57 | u8 _dmsize = __slave ? _sconfig->dst_maxburst : \ | |
58 | DW_DMA_MSIZE_16; \ | |
f301c062 | 59 | \ |
327e6970 VK |
60 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
61 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
62 | | DWC_CTLL_LLP_D_EN \ |
63 | | DWC_CTLL_LLP_S_EN \ | |
327e6970 VK |
64 | | DWC_CTLL_DMS(_dms) \ |
65 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 66 | }) |
3bfb1d20 | 67 | |
3bfb1d20 HS |
68 | /* |
69 | * Number of descriptors to allocate for each channel. This should be | |
70 | * made configurable somehow; preferably, the clients (at least the | |
71 | * ones using slave transfers) should be able to give us a hint. | |
72 | */ | |
73 | #define NR_DESCS_PER_CHANNEL 64 | |
74 | ||
75 | /*----------------------------------------------------------------------*/ | |
76 | ||
77 | /* | |
78 | * Because we're not relying on writeback from the controller (it may not | |
79 | * even be configured into the core!) we don't need to use dma_pool. These | |
80 | * descriptors -- and associated data -- are cacheable. We do need to make | |
81 | * sure their dcache entries are written back before handing them off to | |
82 | * the controller, though. | |
83 | */ | |
84 | ||
41d5e59c DW |
85 | static struct device *chan2dev(struct dma_chan *chan) |
86 | { | |
87 | return &chan->dev->device; | |
88 | } | |
89 | static struct device *chan2parent(struct dma_chan *chan) | |
90 | { | |
91 | return chan->dev->device.parent; | |
92 | } | |
93 | ||
3bfb1d20 HS |
94 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
95 | { | |
96 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
97 | } | |
98 | ||
3bfb1d20 HS |
99 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
100 | { | |
101 | struct dw_desc *desc, *_desc; | |
102 | struct dw_desc *ret = NULL; | |
103 | unsigned int i = 0; | |
69cea5a0 | 104 | unsigned long flags; |
3bfb1d20 | 105 | |
69cea5a0 | 106 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 107 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { |
2ab37276 | 108 | i++; |
3bfb1d20 HS |
109 | if (async_tx_test_ack(&desc->txd)) { |
110 | list_del(&desc->desc_node); | |
111 | ret = desc; | |
112 | break; | |
113 | } | |
41d5e59c | 114 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 | 115 | } |
69cea5a0 | 116 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 117 | |
41d5e59c | 118 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
119 | |
120 | return ret; | |
121 | } | |
122 | ||
123 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
124 | { | |
125 | struct dw_desc *child; | |
126 | ||
e0bd0f8c | 127 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 128 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
129 | child->txd.phys, sizeof(child->lli), |
130 | DMA_TO_DEVICE); | |
41d5e59c | 131 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
132 | desc->txd.phys, sizeof(desc->lli), |
133 | DMA_TO_DEVICE); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Move a descriptor, including any children, to the free list. | |
138 | * `desc' must not be on any lists. | |
139 | */ | |
140 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
141 | { | |
69cea5a0 VK |
142 | unsigned long flags; |
143 | ||
3bfb1d20 HS |
144 | if (desc) { |
145 | struct dw_desc *child; | |
146 | ||
147 | dwc_sync_desc_for_cpu(dwc, desc); | |
148 | ||
69cea5a0 | 149 | spin_lock_irqsave(&dwc->lock, flags); |
e0bd0f8c | 150 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 151 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
152 | "moving child desc %p to freelist\n", |
153 | child); | |
e0bd0f8c | 154 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 155 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 | 156 | list_add(&desc->desc_node, &dwc->free_list); |
69cea5a0 | 157 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
158 | } |
159 | } | |
160 | ||
61e183f8 VK |
161 | static void dwc_initialize(struct dw_dma_chan *dwc) |
162 | { | |
163 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
164 | struct dw_dma_slave *dws = dwc->chan.private; | |
165 | u32 cfghi = DWC_CFGH_FIFO_MODE; | |
166 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
167 | ||
168 | if (dwc->initialized == true) | |
169 | return; | |
170 | ||
171 | if (dws) { | |
172 | /* | |
173 | * We need controller-specific data to set up slave | |
174 | * transfers. | |
175 | */ | |
176 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); | |
177 | ||
178 | cfghi = dws->cfg_hi; | |
179 | cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK; | |
8fccc5bf AS |
180 | } else { |
181 | if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) | |
182 | cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id); | |
183 | else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) | |
184 | cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id); | |
61e183f8 VK |
185 | } |
186 | ||
187 | channel_writel(dwc, CFG_LO, cfglo); | |
188 | channel_writel(dwc, CFG_HI, cfghi); | |
189 | ||
190 | /* Enable interrupts */ | |
191 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
192 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
193 | ||
194 | dwc->initialized = true; | |
195 | } | |
196 | ||
3bfb1d20 HS |
197 | /*----------------------------------------------------------------------*/ |
198 | ||
4c2d56c5 AS |
199 | static inline unsigned int dwc_fast_fls(unsigned long long v) |
200 | { | |
201 | /* | |
202 | * We can be a lot more clever here, but this should take care | |
203 | * of the most common optimization. | |
204 | */ | |
205 | if (!(v & 7)) | |
206 | return 3; | |
207 | else if (!(v & 3)) | |
208 | return 2; | |
209 | else if (!(v & 1)) | |
210 | return 1; | |
211 | return 0; | |
212 | } | |
213 | ||
f52b36d2 | 214 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
215 | { |
216 | dev_err(chan2dev(&dwc->chan), | |
217 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
218 | channel_readl(dwc, SAR), | |
219 | channel_readl(dwc, DAR), | |
220 | channel_readl(dwc, LLP), | |
221 | channel_readl(dwc, CTL_HI), | |
222 | channel_readl(dwc, CTL_LO)); | |
223 | } | |
224 | ||
3f936207 AS |
225 | |
226 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
227 | { | |
228 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
229 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
230 | cpu_relax(); | |
231 | } | |
232 | ||
1d455437 AS |
233 | /*----------------------------------------------------------------------*/ |
234 | ||
fed2574b AS |
235 | /* Perform single block transfer */ |
236 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
237 | struct dw_desc *desc) | |
238 | { | |
239 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
240 | u32 ctllo; | |
241 | ||
242 | /* Software emulation of LLP mode relies on interrupts to continue | |
243 | * multi block transfer. */ | |
244 | ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN; | |
245 | ||
246 | channel_writel(dwc, SAR, desc->lli.sar); | |
247 | channel_writel(dwc, DAR, desc->lli.dar); | |
248 | channel_writel(dwc, CTL_LO, ctllo); | |
249 | channel_writel(dwc, CTL_HI, desc->lli.ctlhi); | |
250 | channel_set_bit(dw, CH_EN, dwc->mask); | |
251 | } | |
252 | ||
3bfb1d20 HS |
253 | /* Called with dwc->lock held and bh disabled */ |
254 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
255 | { | |
256 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
fed2574b | 257 | unsigned long was_soft_llp; |
3bfb1d20 HS |
258 | |
259 | /* ASSERT: channel is idle */ | |
260 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 261 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 262 | "BUG: Attempted to start non-idle channel\n"); |
1d455437 | 263 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
264 | |
265 | /* The tasklet will hopefully advance the queue... */ | |
266 | return; | |
267 | } | |
268 | ||
fed2574b AS |
269 | if (dwc->nollp) { |
270 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
271 | &dwc->flags); | |
272 | if (was_soft_llp) { | |
273 | dev_err(chan2dev(&dwc->chan), | |
274 | "BUG: Attempted to start new LLP transfer " | |
275 | "inside ongoing one\n"); | |
276 | return; | |
277 | } | |
278 | ||
279 | dwc_initialize(dwc); | |
280 | ||
281 | dwc->tx_list = &first->tx_list; | |
282 | dwc->tx_node_active = first->tx_list.next; | |
283 | ||
284 | dwc_do_single_block(dwc, first); | |
285 | ||
286 | return; | |
287 | } | |
288 | ||
61e183f8 VK |
289 | dwc_initialize(dwc); |
290 | ||
3bfb1d20 HS |
291 | channel_writel(dwc, LLP, first->txd.phys); |
292 | channel_writel(dwc, CTL_LO, | |
293 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
294 | channel_writel(dwc, CTL_HI, 0); | |
295 | channel_set_bit(dw, CH_EN, dwc->mask); | |
296 | } | |
297 | ||
298 | /*----------------------------------------------------------------------*/ | |
299 | ||
300 | static void | |
5fedefb8 VK |
301 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
302 | bool callback_required) | |
3bfb1d20 | 303 | { |
5fedefb8 VK |
304 | dma_async_tx_callback callback = NULL; |
305 | void *param = NULL; | |
3bfb1d20 | 306 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 307 | struct dw_desc *child; |
69cea5a0 | 308 | unsigned long flags; |
3bfb1d20 | 309 | |
41d5e59c | 310 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 311 | |
69cea5a0 | 312 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 313 | dma_cookie_complete(txd); |
5fedefb8 VK |
314 | if (callback_required) { |
315 | callback = txd->callback; | |
316 | param = txd->callback_param; | |
317 | } | |
3bfb1d20 HS |
318 | |
319 | dwc_sync_desc_for_cpu(dwc, desc); | |
e518076e VK |
320 | |
321 | /* async_tx_ack */ | |
322 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
323 | async_tx_ack(&child->txd); | |
324 | async_tx_ack(&desc->txd); | |
325 | ||
e0bd0f8c | 326 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
327 | list_move(&desc->desc_node, &dwc->free_list); |
328 | ||
657a77fa AN |
329 | if (!dwc->chan.private) { |
330 | struct device *parent = chan2parent(&dwc->chan); | |
331 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
332 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
333 | dma_unmap_single(parent, desc->lli.dar, | |
334 | desc->len, DMA_FROM_DEVICE); | |
335 | else | |
336 | dma_unmap_page(parent, desc->lli.dar, | |
337 | desc->len, DMA_FROM_DEVICE); | |
338 | } | |
339 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
340 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
341 | dma_unmap_single(parent, desc->lli.sar, | |
342 | desc->len, DMA_TO_DEVICE); | |
343 | else | |
344 | dma_unmap_page(parent, desc->lli.sar, | |
345 | desc->len, DMA_TO_DEVICE); | |
346 | } | |
347 | } | |
3bfb1d20 | 348 | |
69cea5a0 VK |
349 | spin_unlock_irqrestore(&dwc->lock, flags); |
350 | ||
5fedefb8 | 351 | if (callback_required && callback) |
3bfb1d20 HS |
352 | callback(param); |
353 | } | |
354 | ||
355 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
356 | { | |
357 | struct dw_desc *desc, *_desc; | |
358 | LIST_HEAD(list); | |
69cea5a0 | 359 | unsigned long flags; |
3bfb1d20 | 360 | |
69cea5a0 | 361 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 362 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 363 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
364 | "BUG: XFER bit set, but channel not idle!\n"); |
365 | ||
366 | /* Try to continue after resetting the channel... */ | |
3f936207 | 367 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
368 | } |
369 | ||
370 | /* | |
371 | * Submit queued descriptors ASAP, i.e. before we go through | |
372 | * the completed ones. | |
373 | */ | |
3bfb1d20 | 374 | list_splice_init(&dwc->active_list, &list); |
f336e42f VK |
375 | if (!list_empty(&dwc->queue)) { |
376 | list_move(dwc->queue.next, &dwc->active_list); | |
377 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
378 | } | |
3bfb1d20 | 379 | |
69cea5a0 VK |
380 | spin_unlock_irqrestore(&dwc->lock, flags); |
381 | ||
3bfb1d20 | 382 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 383 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
384 | } |
385 | ||
386 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
387 | { | |
388 | dma_addr_t llp; | |
389 | struct dw_desc *desc, *_desc; | |
390 | struct dw_desc *child; | |
391 | u32 status_xfer; | |
69cea5a0 | 392 | unsigned long flags; |
3bfb1d20 | 393 | |
69cea5a0 | 394 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
395 | llp = channel_readl(dwc, LLP); |
396 | status_xfer = dma_readl(dw, RAW.XFER); | |
397 | ||
398 | if (status_xfer & dwc->mask) { | |
399 | /* Everything we've submitted is done */ | |
400 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
69cea5a0 VK |
401 | spin_unlock_irqrestore(&dwc->lock, flags); |
402 | ||
3bfb1d20 HS |
403 | dwc_complete_all(dw, dwc); |
404 | return; | |
405 | } | |
406 | ||
69cea5a0 VK |
407 | if (list_empty(&dwc->active_list)) { |
408 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 409 | return; |
69cea5a0 | 410 | } |
087809fc | 411 | |
2e4c364e | 412 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__, |
2f45d613 | 413 | (unsigned long long)llp); |
3bfb1d20 HS |
414 | |
415 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
84adccfb | 416 | /* check first descriptors addr */ |
69cea5a0 VK |
417 | if (desc->txd.phys == llp) { |
418 | spin_unlock_irqrestore(&dwc->lock, flags); | |
84adccfb | 419 | return; |
69cea5a0 | 420 | } |
84adccfb VK |
421 | |
422 | /* check first descriptors llp */ | |
69cea5a0 | 423 | if (desc->lli.llp == llp) { |
3bfb1d20 | 424 | /* This one is currently in progress */ |
69cea5a0 | 425 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 426 | return; |
69cea5a0 | 427 | } |
3bfb1d20 | 428 | |
e0bd0f8c | 429 | list_for_each_entry(child, &desc->tx_list, desc_node) |
69cea5a0 | 430 | if (child->lli.llp == llp) { |
3bfb1d20 | 431 | /* Currently in progress */ |
69cea5a0 | 432 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 433 | return; |
69cea5a0 | 434 | } |
3bfb1d20 HS |
435 | |
436 | /* | |
437 | * No descriptors so far seem to be in progress, i.e. | |
438 | * this one must be done. | |
439 | */ | |
69cea5a0 | 440 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 441 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 442 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
443 | } |
444 | ||
41d5e59c | 445 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
446 | "BUG: All descriptors done, but channel not idle!\n"); |
447 | ||
448 | /* Try to continue after resetting the channel... */ | |
3f936207 | 449 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
450 | |
451 | if (!list_empty(&dwc->queue)) { | |
f336e42f VK |
452 | list_move(dwc->queue.next, &dwc->active_list); |
453 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
3bfb1d20 | 454 | } |
69cea5a0 | 455 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
456 | } |
457 | ||
93aad1bc | 458 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) |
3bfb1d20 | 459 | { |
41d5e59c | 460 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 461 | " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
f8609c2b | 462 | lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); |
3bfb1d20 HS |
463 | } |
464 | ||
465 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
466 | { | |
467 | struct dw_desc *bad_desc; | |
468 | struct dw_desc *child; | |
69cea5a0 | 469 | unsigned long flags; |
3bfb1d20 HS |
470 | |
471 | dwc_scan_descriptors(dw, dwc); | |
472 | ||
69cea5a0 VK |
473 | spin_lock_irqsave(&dwc->lock, flags); |
474 | ||
3bfb1d20 HS |
475 | /* |
476 | * The descriptor currently at the head of the active list is | |
477 | * borked. Since we don't have any way to report errors, we'll | |
478 | * just have to scream loudly and try to carry on. | |
479 | */ | |
480 | bad_desc = dwc_first_active(dwc); | |
481 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 482 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
483 | |
484 | /* Clear the error flag and try to restart the controller */ | |
485 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
486 | if (!list_empty(&dwc->active_list)) | |
487 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
488 | ||
489 | /* | |
490 | * KERN_CRITICAL may seem harsh, but since this only happens | |
491 | * when someone submits a bad physical address in a | |
492 | * descriptor, we should consider ourselves lucky that the | |
493 | * controller flagged an error instead of scribbling over | |
494 | * random memory locations. | |
495 | */ | |
41d5e59c | 496 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 497 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 498 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
499 | " cookie: %d\n", bad_desc->txd.cookie); |
500 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 501 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
502 | dwc_dump_lli(dwc, &child->lli); |
503 | ||
69cea5a0 VK |
504 | spin_unlock_irqrestore(&dwc->lock, flags); |
505 | ||
3bfb1d20 | 506 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 507 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
508 | } |
509 | ||
d9de4519 HCE |
510 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
511 | ||
512 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
513 | { | |
514 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
515 | return channel_readl(dwc, SAR); | |
516 | } | |
517 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
518 | ||
519 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
520 | { | |
521 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
522 | return channel_readl(dwc, DAR); | |
523 | } | |
524 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
525 | ||
526 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
527 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
ff7b05f2 | 528 | u32 status_err, u32 status_xfer) |
d9de4519 | 529 | { |
69cea5a0 VK |
530 | unsigned long flags; |
531 | ||
ff7b05f2 | 532 | if (dwc->mask) { |
d9de4519 HCE |
533 | void (*callback)(void *param); |
534 | void *callback_param; | |
535 | ||
536 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
537 | channel_readl(dwc, LLP)); | |
d9de4519 HCE |
538 | |
539 | callback = dwc->cdesc->period_callback; | |
540 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
541 | |
542 | if (callback) | |
d9de4519 | 543 | callback(callback_param); |
d9de4519 HCE |
544 | } |
545 | ||
546 | /* | |
547 | * Error and transfer complete are highly unlikely, and will most | |
548 | * likely be due to a configuration error by the user. | |
549 | */ | |
550 | if (unlikely(status_err & dwc->mask) || | |
551 | unlikely(status_xfer & dwc->mask)) { | |
552 | int i; | |
553 | ||
554 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
555 | "interrupt, stopping DMA transfer\n", | |
556 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
557 | |
558 | spin_lock_irqsave(&dwc->lock, flags); | |
559 | ||
1d455437 | 560 | dwc_dump_chan_regs(dwc); |
d9de4519 | 561 | |
3f936207 | 562 | dwc_chan_disable(dw, dwc); |
d9de4519 HCE |
563 | |
564 | /* make sure DMA does not restart by loading a new list */ | |
565 | channel_writel(dwc, LLP, 0); | |
566 | channel_writel(dwc, CTL_LO, 0); | |
567 | channel_writel(dwc, CTL_HI, 0); | |
568 | ||
d9de4519 HCE |
569 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
570 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
571 | ||
572 | for (i = 0; i < dwc->cdesc->periods; i++) | |
573 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
69cea5a0 VK |
574 | |
575 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 HCE |
576 | } |
577 | } | |
578 | ||
579 | /* ------------------------------------------------------------------------- */ | |
580 | ||
3bfb1d20 HS |
581 | static void dw_dma_tasklet(unsigned long data) |
582 | { | |
583 | struct dw_dma *dw = (struct dw_dma *)data; | |
584 | struct dw_dma_chan *dwc; | |
3bfb1d20 HS |
585 | u32 status_xfer; |
586 | u32 status_err; | |
587 | int i; | |
588 | ||
7fe7b2f4 | 589 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
590 | status_err = dma_readl(dw, RAW.ERROR); |
591 | ||
2e4c364e | 592 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
593 | |
594 | for (i = 0; i < dw->dma.chancnt; i++) { | |
595 | dwc = &dw->chan[i]; | |
d9de4519 | 596 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
ff7b05f2 | 597 | dwc_handle_cyclic(dw, dwc, status_err, status_xfer); |
d9de4519 | 598 | else if (status_err & (1 << i)) |
3bfb1d20 | 599 | dwc_handle_error(dw, dwc); |
fed2574b AS |
600 | else if (status_xfer & (1 << i)) { |
601 | unsigned long flags; | |
602 | ||
603 | spin_lock_irqsave(&dwc->lock, flags); | |
604 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
605 | if (dwc->tx_node_active != dwc->tx_list) { | |
606 | struct dw_desc *desc = | |
607 | list_entry(dwc->tx_node_active, | |
608 | struct dw_desc, | |
609 | desc_node); | |
610 | ||
611 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
612 | ||
613 | /* move pointer to next descriptor */ | |
614 | dwc->tx_node_active = | |
615 | dwc->tx_node_active->next; | |
616 | ||
617 | dwc_do_single_block(dwc, desc); | |
618 | ||
619 | spin_unlock_irqrestore(&dwc->lock, flags); | |
620 | continue; | |
621 | } else { | |
622 | /* we are done here */ | |
623 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
624 | } | |
625 | } | |
626 | spin_unlock_irqrestore(&dwc->lock, flags); | |
627 | ||
3bfb1d20 | 628 | dwc_scan_descriptors(dw, dwc); |
fed2574b | 629 | } |
3bfb1d20 HS |
630 | } |
631 | ||
632 | /* | |
ff7b05f2 | 633 | * Re-enable interrupts. |
3bfb1d20 HS |
634 | */ |
635 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
636 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
637 | } | |
638 | ||
639 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
640 | { | |
641 | struct dw_dma *dw = dev_id; | |
642 | u32 status; | |
643 | ||
2e4c364e | 644 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, |
3bfb1d20 HS |
645 | dma_readl(dw, STATUS_INT)); |
646 | ||
647 | /* | |
648 | * Just disable the interrupts. We'll turn them back on in the | |
649 | * softirq handler. | |
650 | */ | |
651 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
652 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
653 | ||
654 | status = dma_readl(dw, STATUS_INT); | |
655 | if (status) { | |
656 | dev_err(dw->dma.dev, | |
657 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
658 | status); | |
659 | ||
660 | /* Try to recover */ | |
661 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
3bfb1d20 HS |
662 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
663 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
664 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
665 | } | |
666 | ||
667 | tasklet_schedule(&dw->tasklet); | |
668 | ||
669 | return IRQ_HANDLED; | |
670 | } | |
671 | ||
672 | /*----------------------------------------------------------------------*/ | |
673 | ||
674 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
675 | { | |
676 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
677 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
678 | dma_cookie_t cookie; | |
69cea5a0 | 679 | unsigned long flags; |
3bfb1d20 | 680 | |
69cea5a0 | 681 | spin_lock_irqsave(&dwc->lock, flags); |
884485e1 | 682 | cookie = dma_cookie_assign(tx); |
3bfb1d20 HS |
683 | |
684 | /* | |
685 | * REVISIT: We should attempt to chain as many descriptors as | |
686 | * possible, perhaps even appending to those already submitted | |
687 | * for DMA. But this is hard to do in a race-free manner. | |
688 | */ | |
689 | if (list_empty(&dwc->active_list)) { | |
2e4c364e | 690 | dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, |
3bfb1d20 | 691 | desc->txd.cookie); |
3bfb1d20 | 692 | list_add_tail(&desc->desc_node, &dwc->active_list); |
f336e42f | 693 | dwc_dostart(dwc, dwc_first_active(dwc)); |
3bfb1d20 | 694 | } else { |
2e4c364e | 695 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, |
3bfb1d20 HS |
696 | desc->txd.cookie); |
697 | ||
698 | list_add_tail(&desc->desc_node, &dwc->queue); | |
699 | } | |
700 | ||
69cea5a0 | 701 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
702 | |
703 | return cookie; | |
704 | } | |
705 | ||
706 | static struct dma_async_tx_descriptor * | |
707 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
708 | size_t len, unsigned long flags) | |
709 | { | |
710 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
a0982004 | 711 | struct dw_dma_slave *dws = chan->private; |
3bfb1d20 HS |
712 | struct dw_desc *desc; |
713 | struct dw_desc *first; | |
714 | struct dw_desc *prev; | |
715 | size_t xfer_count; | |
716 | size_t offset; | |
717 | unsigned int src_width; | |
718 | unsigned int dst_width; | |
719 | u32 ctllo; | |
720 | ||
2f45d613 | 721 | dev_vdbg(chan2dev(chan), |
2e4c364e | 722 | "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, |
2f45d613 AS |
723 | (unsigned long long)dest, (unsigned long long)src, |
724 | len, flags); | |
3bfb1d20 HS |
725 | |
726 | if (unlikely(!len)) { | |
2e4c364e | 727 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
728 | return NULL; |
729 | } | |
730 | ||
a0982004 AS |
731 | src_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)], |
732 | dwc_fast_fls(src | len)); | |
733 | ||
734 | dst_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_dms(dws)], | |
735 | dwc_fast_fls(dest | len)); | |
3bfb1d20 | 736 | |
327e6970 | 737 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
738 | | DWC_CTLL_DST_WIDTH(dst_width) |
739 | | DWC_CTLL_SRC_WIDTH(src_width) | |
740 | | DWC_CTLL_DST_INC | |
741 | | DWC_CTLL_SRC_INC | |
742 | | DWC_CTLL_FC_M2M; | |
743 | prev = first = NULL; | |
744 | ||
745 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
746 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 747 | dwc->block_size); |
3bfb1d20 HS |
748 | |
749 | desc = dwc_desc_get(dwc); | |
750 | if (!desc) | |
751 | goto err_desc_get; | |
752 | ||
753 | desc->lli.sar = src + offset; | |
754 | desc->lli.dar = dest + offset; | |
755 | desc->lli.ctllo = ctllo; | |
756 | desc->lli.ctlhi = xfer_count; | |
757 | ||
758 | if (!first) { | |
759 | first = desc; | |
760 | } else { | |
761 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 762 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
763 | prev->txd.phys, sizeof(prev->lli), |
764 | DMA_TO_DEVICE); | |
765 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 766 | &first->tx_list); |
3bfb1d20 HS |
767 | } |
768 | prev = desc; | |
769 | } | |
770 | ||
771 | ||
772 | if (flags & DMA_PREP_INTERRUPT) | |
773 | /* Trigger interrupt after last block */ | |
774 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
775 | ||
776 | prev->lli.llp = 0; | |
41d5e59c | 777 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
778 | prev->txd.phys, sizeof(prev->lli), |
779 | DMA_TO_DEVICE); | |
780 | ||
781 | first->txd.flags = flags; | |
782 | first->len = len; | |
783 | ||
784 | return &first->txd; | |
785 | ||
786 | err_desc_get: | |
787 | dwc_desc_put(dwc, first); | |
788 | return NULL; | |
789 | } | |
790 | ||
791 | static struct dma_async_tx_descriptor * | |
792 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 793 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 794 | unsigned long flags, void *context) |
3bfb1d20 HS |
795 | { |
796 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 797 | struct dw_dma_slave *dws = chan->private; |
327e6970 | 798 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
799 | struct dw_desc *prev; |
800 | struct dw_desc *first; | |
801 | u32 ctllo; | |
802 | dma_addr_t reg; | |
803 | unsigned int reg_width; | |
804 | unsigned int mem_width; | |
a0982004 | 805 | unsigned int data_width; |
3bfb1d20 HS |
806 | unsigned int i; |
807 | struct scatterlist *sg; | |
808 | size_t total_len = 0; | |
809 | ||
2e4c364e | 810 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 HS |
811 | |
812 | if (unlikely(!dws || !sg_len)) | |
813 | return NULL; | |
814 | ||
3bfb1d20 HS |
815 | prev = first = NULL; |
816 | ||
3bfb1d20 | 817 | switch (direction) { |
db8196df | 818 | case DMA_MEM_TO_DEV: |
327e6970 VK |
819 | reg_width = __fls(sconfig->dst_addr_width); |
820 | reg = sconfig->dst_addr; | |
821 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
822 | | DWC_CTLL_DST_WIDTH(reg_width) |
823 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
824 | | DWC_CTLL_SRC_INC); |
825 | ||
826 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
827 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
828 | ||
a0982004 AS |
829 | data_width = dwc->dw->data_width[dwc_get_sms(dws)]; |
830 | ||
3bfb1d20 HS |
831 | for_each_sg(sgl, sg, sg_len, i) { |
832 | struct dw_desc *desc; | |
69dc14b5 | 833 | u32 len, dlen, mem; |
3bfb1d20 | 834 | |
cbb796cc | 835 | mem = sg_dma_address(sg); |
69dc14b5 | 836 | len = sg_dma_len(sg); |
6bc711f6 | 837 | |
a0982004 AS |
838 | mem_width = min_t(unsigned int, |
839 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 840 | |
69dc14b5 | 841 | slave_sg_todev_fill_desc: |
3bfb1d20 HS |
842 | desc = dwc_desc_get(dwc); |
843 | if (!desc) { | |
41d5e59c | 844 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
845 | "not enough descriptors available\n"); |
846 | goto err_desc_get; | |
847 | } | |
848 | ||
3bfb1d20 HS |
849 | desc->lli.sar = mem; |
850 | desc->lli.dar = reg; | |
851 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
4a63a8b3 AS |
852 | if ((len >> mem_width) > dwc->block_size) { |
853 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
854 | mem += dlen; |
855 | len -= dlen; | |
856 | } else { | |
857 | dlen = len; | |
858 | len = 0; | |
859 | } | |
860 | ||
861 | desc->lli.ctlhi = dlen >> mem_width; | |
3bfb1d20 HS |
862 | |
863 | if (!first) { | |
864 | first = desc; | |
865 | } else { | |
866 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 867 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
868 | prev->txd.phys, |
869 | sizeof(prev->lli), | |
870 | DMA_TO_DEVICE); | |
871 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 872 | &first->tx_list); |
3bfb1d20 HS |
873 | } |
874 | prev = desc; | |
69dc14b5 VK |
875 | total_len += dlen; |
876 | ||
877 | if (len) | |
878 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
879 | } |
880 | break; | |
db8196df | 881 | case DMA_DEV_TO_MEM: |
327e6970 VK |
882 | reg_width = __fls(sconfig->src_addr_width); |
883 | reg = sconfig->src_addr; | |
884 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
885 | | DWC_CTLL_SRC_WIDTH(reg_width) |
886 | | DWC_CTLL_DST_INC | |
327e6970 VK |
887 | | DWC_CTLL_SRC_FIX); |
888 | ||
889 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
890 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 891 | |
a0982004 AS |
892 | data_width = dwc->dw->data_width[dwc_get_dms(dws)]; |
893 | ||
3bfb1d20 HS |
894 | for_each_sg(sgl, sg, sg_len, i) { |
895 | struct dw_desc *desc; | |
69dc14b5 | 896 | u32 len, dlen, mem; |
3bfb1d20 | 897 | |
cbb796cc | 898 | mem = sg_dma_address(sg); |
3bfb1d20 | 899 | len = sg_dma_len(sg); |
6bc711f6 | 900 | |
a0982004 AS |
901 | mem_width = min_t(unsigned int, |
902 | data_width, dwc_fast_fls(mem | len)); | |
3bfb1d20 | 903 | |
69dc14b5 VK |
904 | slave_sg_fromdev_fill_desc: |
905 | desc = dwc_desc_get(dwc); | |
906 | if (!desc) { | |
907 | dev_err(chan2dev(chan), | |
908 | "not enough descriptors available\n"); | |
909 | goto err_desc_get; | |
910 | } | |
911 | ||
3bfb1d20 HS |
912 | desc->lli.sar = reg; |
913 | desc->lli.dar = mem; | |
914 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
4a63a8b3 AS |
915 | if ((len >> reg_width) > dwc->block_size) { |
916 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
917 | mem += dlen; |
918 | len -= dlen; | |
919 | } else { | |
920 | dlen = len; | |
921 | len = 0; | |
922 | } | |
923 | desc->lli.ctlhi = dlen >> reg_width; | |
3bfb1d20 HS |
924 | |
925 | if (!first) { | |
926 | first = desc; | |
927 | } else { | |
928 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 929 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
930 | prev->txd.phys, |
931 | sizeof(prev->lli), | |
932 | DMA_TO_DEVICE); | |
933 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 934 | &first->tx_list); |
3bfb1d20 HS |
935 | } |
936 | prev = desc; | |
69dc14b5 VK |
937 | total_len += dlen; |
938 | ||
939 | if (len) | |
940 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
941 | } |
942 | break; | |
943 | default: | |
944 | return NULL; | |
945 | } | |
946 | ||
947 | if (flags & DMA_PREP_INTERRUPT) | |
948 | /* Trigger interrupt after last block */ | |
949 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
950 | ||
951 | prev->lli.llp = 0; | |
41d5e59c | 952 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
953 | prev->txd.phys, sizeof(prev->lli), |
954 | DMA_TO_DEVICE); | |
955 | ||
956 | first->len = total_len; | |
957 | ||
958 | return &first->txd; | |
959 | ||
960 | err_desc_get: | |
961 | dwc_desc_put(dwc, first); | |
962 | return NULL; | |
963 | } | |
964 | ||
327e6970 VK |
965 | /* |
966 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
967 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
968 | * | |
969 | * NOTE: burst size 2 is not supported by controller. | |
970 | * | |
971 | * This can be done by finding least significant bit set: n & (n - 1) | |
972 | */ | |
973 | static inline void convert_burst(u32 *maxburst) | |
974 | { | |
975 | if (*maxburst > 1) | |
976 | *maxburst = fls(*maxburst) - 2; | |
977 | else | |
978 | *maxburst = 0; | |
979 | } | |
980 | ||
981 | static int | |
982 | set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) | |
983 | { | |
984 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
985 | ||
986 | /* Check if it is chan is configured for slave transfers */ | |
987 | if (!chan->private) | |
988 | return -EINVAL; | |
989 | ||
990 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
991 | ||
992 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
993 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
05827630 LW |
998 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
999 | unsigned long arg) | |
3bfb1d20 HS |
1000 | { |
1001 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1002 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1003 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1004 | unsigned long flags; |
a7c57cf7 | 1005 | u32 cfglo; |
3bfb1d20 HS |
1006 | LIST_HEAD(list); |
1007 | ||
a7c57cf7 LW |
1008 | if (cmd == DMA_PAUSE) { |
1009 | spin_lock_irqsave(&dwc->lock, flags); | |
c3635c78 | 1010 | |
a7c57cf7 LW |
1011 | cfglo = channel_readl(dwc, CFG_LO); |
1012 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); | |
1013 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY)) | |
1014 | cpu_relax(); | |
3bfb1d20 | 1015 | |
a7c57cf7 LW |
1016 | dwc->paused = true; |
1017 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1018 | } else if (cmd == DMA_RESUME) { | |
1019 | if (!dwc->paused) | |
1020 | return 0; | |
3bfb1d20 | 1021 | |
a7c57cf7 | 1022 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 1023 | |
a7c57cf7 LW |
1024 | cfglo = channel_readl(dwc, CFG_LO); |
1025 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
1026 | dwc->paused = false; | |
3bfb1d20 | 1027 | |
a7c57cf7 LW |
1028 | spin_unlock_irqrestore(&dwc->lock, flags); |
1029 | } else if (cmd == DMA_TERMINATE_ALL) { | |
1030 | spin_lock_irqsave(&dwc->lock, flags); | |
3bfb1d20 | 1031 | |
fed2574b AS |
1032 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
1033 | ||
3f936207 | 1034 | dwc_chan_disable(dw, dwc); |
a7c57cf7 LW |
1035 | |
1036 | dwc->paused = false; | |
1037 | ||
1038 | /* active_list entries will end up before queued entries */ | |
1039 | list_splice_init(&dwc->queue, &list); | |
1040 | list_splice_init(&dwc->active_list, &list); | |
1041 | ||
1042 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1043 | ||
1044 | /* Flush all pending and queued descriptors */ | |
1045 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1046 | dwc_descriptor_complete(dwc, desc, false); | |
327e6970 VK |
1047 | } else if (cmd == DMA_SLAVE_CONFIG) { |
1048 | return set_runtime_config(chan, (struct dma_slave_config *)arg); | |
1049 | } else { | |
a7c57cf7 | 1050 | return -ENXIO; |
327e6970 | 1051 | } |
c3635c78 LW |
1052 | |
1053 | return 0; | |
3bfb1d20 HS |
1054 | } |
1055 | ||
1056 | static enum dma_status | |
07934481 LW |
1057 | dwc_tx_status(struct dma_chan *chan, |
1058 | dma_cookie_t cookie, | |
1059 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1060 | { |
1061 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1062 | enum dma_status ret; |
3bfb1d20 | 1063 | |
96a2af41 | 1064 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1065 | if (ret != DMA_SUCCESS) { |
1066 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
1067 | ||
96a2af41 | 1068 | ret = dma_cookie_status(chan, cookie, txstate); |
3bfb1d20 HS |
1069 | } |
1070 | ||
abf53902 | 1071 | if (ret != DMA_SUCCESS) |
96a2af41 | 1072 | dma_set_residue(txstate, dwc_first_active(dwc)->len); |
3bfb1d20 | 1073 | |
a7c57cf7 LW |
1074 | if (dwc->paused) |
1075 | return DMA_PAUSED; | |
3bfb1d20 HS |
1076 | |
1077 | return ret; | |
1078 | } | |
1079 | ||
1080 | static void dwc_issue_pending(struct dma_chan *chan) | |
1081 | { | |
1082 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1083 | ||
3bfb1d20 HS |
1084 | if (!list_empty(&dwc->queue)) |
1085 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
3bfb1d20 HS |
1086 | } |
1087 | ||
aa1e6f1a | 1088 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1089 | { |
1090 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1091 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1092 | struct dw_desc *desc; | |
3bfb1d20 | 1093 | int i; |
69cea5a0 | 1094 | unsigned long flags; |
3bfb1d20 | 1095 | |
2e4c364e | 1096 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1097 | |
3bfb1d20 HS |
1098 | /* ASSERT: channel is idle */ |
1099 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1100 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1101 | return -EIO; |
1102 | } | |
1103 | ||
d3ee98cd | 1104 | dma_cookie_init(chan); |
3bfb1d20 | 1105 | |
3bfb1d20 HS |
1106 | /* |
1107 | * NOTE: some controllers may have additional features that we | |
1108 | * need to initialize here, like "scatter-gather" (which | |
1109 | * doesn't mean what you think it means), and status writeback. | |
1110 | */ | |
1111 | ||
69cea5a0 | 1112 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1113 | i = dwc->descs_allocated; |
1114 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
69cea5a0 | 1115 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1116 | |
1117 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
1118 | if (!desc) { | |
41d5e59c | 1119 | dev_info(chan2dev(chan), |
3bfb1d20 | 1120 | "only allocated %d descriptors\n", i); |
69cea5a0 | 1121 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1122 | break; |
1123 | } | |
1124 | ||
e0bd0f8c | 1125 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
1126 | dma_async_tx_descriptor_init(&desc->txd, chan); |
1127 | desc->txd.tx_submit = dwc_tx_submit; | |
1128 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 1129 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
1130 | sizeof(desc->lli), DMA_TO_DEVICE); |
1131 | dwc_desc_put(dwc, desc); | |
1132 | ||
69cea5a0 | 1133 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1134 | i = ++dwc->descs_allocated; |
1135 | } | |
1136 | ||
69cea5a0 | 1137 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1138 | |
2e4c364e | 1139 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
3bfb1d20 HS |
1140 | |
1141 | return i; | |
1142 | } | |
1143 | ||
1144 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1145 | { | |
1146 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1147 | struct dw_dma *dw = to_dw_dma(chan->device); | |
1148 | struct dw_desc *desc, *_desc; | |
69cea5a0 | 1149 | unsigned long flags; |
3bfb1d20 HS |
1150 | LIST_HEAD(list); |
1151 | ||
2e4c364e | 1152 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1153 | dwc->descs_allocated); |
1154 | ||
1155 | /* ASSERT: channel is idle */ | |
1156 | BUG_ON(!list_empty(&dwc->active_list)); | |
1157 | BUG_ON(!list_empty(&dwc->queue)); | |
1158 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1159 | ||
69cea5a0 | 1160 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
1161 | list_splice_init(&dwc->free_list, &list); |
1162 | dwc->descs_allocated = 0; | |
61e183f8 | 1163 | dwc->initialized = false; |
3bfb1d20 HS |
1164 | |
1165 | /* Disable interrupts */ | |
1166 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
3bfb1d20 HS |
1167 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1168 | ||
69cea5a0 | 1169 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
1170 | |
1171 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
1172 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
1173 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
1174 | sizeof(desc->lli), DMA_TO_DEVICE); |
1175 | kfree(desc); | |
1176 | } | |
1177 | ||
2e4c364e | 1178 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1179 | } |
1180 | ||
d9de4519 HCE |
1181 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1182 | ||
1183 | /** | |
1184 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1185 | * @chan: the DMA channel to start | |
1186 | * | |
1187 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1188 | * -errno on failure. | |
1189 | */ | |
1190 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1191 | { | |
1192 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1193 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1194 | unsigned long flags; |
d9de4519 HCE |
1195 | |
1196 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1197 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1198 | return -ENODEV; | |
1199 | } | |
1200 | ||
69cea5a0 | 1201 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 HCE |
1202 | |
1203 | /* assert channel is idle */ | |
1204 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1205 | dev_err(chan2dev(&dwc->chan), | |
1206 | "BUG: Attempted to start non-idle channel\n"); | |
1d455437 | 1207 | dwc_dump_chan_regs(dwc); |
69cea5a0 | 1208 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1209 | return -EBUSY; |
1210 | } | |
1211 | ||
d9de4519 HCE |
1212 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1213 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1214 | ||
1215 | /* setup DMAC channel registers */ | |
1216 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1217 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1218 | channel_writel(dwc, CTL_HI, 0); | |
1219 | ||
1220 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1221 | ||
69cea5a0 | 1222 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1223 | |
1224 | return 0; | |
1225 | } | |
1226 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1227 | ||
1228 | /** | |
1229 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1230 | * @chan: the DMA channel to stop | |
1231 | * | |
1232 | * Must be called with soft interrupts disabled. | |
1233 | */ | |
1234 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1235 | { | |
1236 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1237 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1238 | unsigned long flags; |
d9de4519 | 1239 | |
69cea5a0 | 1240 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1241 | |
3f936207 | 1242 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1243 | |
69cea5a0 | 1244 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1245 | } |
1246 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1247 | ||
1248 | /** | |
1249 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1250 | * @chan: the DMA channel to prepare | |
1251 | * @buf_addr: physical DMA address where the buffer starts | |
1252 | * @buf_len: total number of bytes for the entire buffer | |
1253 | * @period_len: number of bytes for each period | |
1254 | * @direction: transfer direction, to or from device | |
1255 | * | |
1256 | * Must be called before trying to start the transfer. Returns a valid struct | |
1257 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1258 | */ | |
1259 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1260 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1261 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1262 | { |
1263 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1264 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1265 | struct dw_cyclic_desc *cdesc; |
1266 | struct dw_cyclic_desc *retval = NULL; | |
1267 | struct dw_desc *desc; | |
1268 | struct dw_desc *last = NULL; | |
d9de4519 HCE |
1269 | unsigned long was_cyclic; |
1270 | unsigned int reg_width; | |
1271 | unsigned int periods; | |
1272 | unsigned int i; | |
69cea5a0 | 1273 | unsigned long flags; |
d9de4519 | 1274 | |
69cea5a0 | 1275 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1276 | if (dwc->nollp) { |
1277 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1278 | dev_dbg(chan2dev(&dwc->chan), | |
1279 | "channel doesn't support LLP transfers\n"); | |
1280 | return ERR_PTR(-EINVAL); | |
1281 | } | |
1282 | ||
d9de4519 | 1283 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1284 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1285 | dev_dbg(chan2dev(&dwc->chan), |
1286 | "queue and/or active list are not empty\n"); | |
1287 | return ERR_PTR(-EBUSY); | |
1288 | } | |
1289 | ||
1290 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1291 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1292 | if (was_cyclic) { |
1293 | dev_dbg(chan2dev(&dwc->chan), | |
1294 | "channel already prepared for cyclic DMA\n"); | |
1295 | return ERR_PTR(-EBUSY); | |
1296 | } | |
1297 | ||
1298 | retval = ERR_PTR(-EINVAL); | |
327e6970 VK |
1299 | |
1300 | if (direction == DMA_MEM_TO_DEV) | |
1301 | reg_width = __ffs(sconfig->dst_addr_width); | |
1302 | else | |
1303 | reg_width = __ffs(sconfig->src_addr_width); | |
1304 | ||
d9de4519 HCE |
1305 | periods = buf_len / period_len; |
1306 | ||
1307 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1308 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1309 | goto out_err; |
1310 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1311 | goto out_err; | |
1312 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1313 | goto out_err; | |
db8196df | 1314 | if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM)))) |
d9de4519 HCE |
1315 | goto out_err; |
1316 | ||
1317 | retval = ERR_PTR(-ENOMEM); | |
1318 | ||
1319 | if (periods > NR_DESCS_PER_CHANNEL) | |
1320 | goto out_err; | |
1321 | ||
1322 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1323 | if (!cdesc) | |
1324 | goto out_err; | |
1325 | ||
1326 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1327 | if (!cdesc->desc) | |
1328 | goto out_err_alloc; | |
1329 | ||
1330 | for (i = 0; i < periods; i++) { | |
1331 | desc = dwc_desc_get(dwc); | |
1332 | if (!desc) | |
1333 | goto out_err_desc_get; | |
1334 | ||
1335 | switch (direction) { | |
db8196df | 1336 | case DMA_MEM_TO_DEV: |
327e6970 | 1337 | desc->lli.dar = sconfig->dst_addr; |
d9de4519 | 1338 | desc->lli.sar = buf_addr + (period_len * i); |
327e6970 | 1339 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) |
d9de4519 HCE |
1340 | | DWC_CTLL_DST_WIDTH(reg_width) |
1341 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1342 | | DWC_CTLL_DST_FIX | |
1343 | | DWC_CTLL_SRC_INC | |
d9de4519 | 1344 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1345 | |
1346 | desc->lli.ctllo |= sconfig->device_fc ? | |
1347 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1348 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
1349 | ||
d9de4519 | 1350 | break; |
db8196df | 1351 | case DMA_DEV_TO_MEM: |
d9de4519 | 1352 | desc->lli.dar = buf_addr + (period_len * i); |
327e6970 VK |
1353 | desc->lli.sar = sconfig->src_addr; |
1354 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan) | |
d9de4519 HCE |
1355 | | DWC_CTLL_SRC_WIDTH(reg_width) |
1356 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1357 | | DWC_CTLL_DST_INC | |
1358 | | DWC_CTLL_SRC_FIX | |
d9de4519 | 1359 | | DWC_CTLL_INT_EN); |
327e6970 VK |
1360 | |
1361 | desc->lli.ctllo |= sconfig->device_fc ? | |
1362 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1363 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
1364 | ||
d9de4519 HCE |
1365 | break; |
1366 | default: | |
1367 | break; | |
1368 | } | |
1369 | ||
1370 | desc->lli.ctlhi = (period_len >> reg_width); | |
1371 | cdesc->desc[i] = desc; | |
1372 | ||
1373 | if (last) { | |
1374 | last->lli.llp = desc->txd.phys; | |
1375 | dma_sync_single_for_device(chan2parent(chan), | |
1376 | last->txd.phys, sizeof(last->lli), | |
1377 | DMA_TO_DEVICE); | |
1378 | } | |
1379 | ||
1380 | last = desc; | |
1381 | } | |
1382 | ||
1383 | /* lets make a cyclic list */ | |
1384 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1385 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1386 | sizeof(last->lli), DMA_TO_DEVICE); | |
1387 | ||
2f45d613 AS |
1388 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu " |
1389 | "period %zu periods %d\n", (unsigned long long)buf_addr, | |
1390 | buf_len, period_len, periods); | |
d9de4519 HCE |
1391 | |
1392 | cdesc->periods = periods; | |
1393 | dwc->cdesc = cdesc; | |
1394 | ||
1395 | return cdesc; | |
1396 | ||
1397 | out_err_desc_get: | |
1398 | while (i--) | |
1399 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1400 | out_err_alloc: | |
1401 | kfree(cdesc); | |
1402 | out_err: | |
1403 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1404 | return (struct dw_cyclic_desc *)retval; | |
1405 | } | |
1406 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1407 | ||
1408 | /** | |
1409 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1410 | * @chan: the DMA channel to free | |
1411 | */ | |
1412 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1413 | { | |
1414 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1415 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1416 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1417 | int i; | |
69cea5a0 | 1418 | unsigned long flags; |
d9de4519 | 1419 | |
2e4c364e | 1420 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1421 | |
1422 | if (!cdesc) | |
1423 | return; | |
1424 | ||
69cea5a0 | 1425 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1426 | |
3f936207 | 1427 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1428 | |
d9de4519 HCE |
1429 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1430 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1431 | ||
69cea5a0 | 1432 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1433 | |
1434 | for (i = 0; i < cdesc->periods; i++) | |
1435 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1436 | ||
1437 | kfree(cdesc->desc); | |
1438 | kfree(cdesc); | |
1439 | ||
1440 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1441 | } | |
1442 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1443 | ||
3bfb1d20 HS |
1444 | /*----------------------------------------------------------------------*/ |
1445 | ||
1446 | static void dw_dma_off(struct dw_dma *dw) | |
1447 | { | |
61e183f8 VK |
1448 | int i; |
1449 | ||
3bfb1d20 HS |
1450 | dma_writel(dw, CFG, 0); |
1451 | ||
1452 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
3bfb1d20 HS |
1453 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1454 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1455 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1456 | ||
1457 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1458 | cpu_relax(); | |
61e183f8 VK |
1459 | |
1460 | for (i = 0; i < dw->dma.chancnt; i++) | |
1461 | dw->chan[i].initialized = false; | |
3bfb1d20 HS |
1462 | } |
1463 | ||
0272e93f | 1464 | static int __devinit dw_probe(struct platform_device *pdev) |
3bfb1d20 HS |
1465 | { |
1466 | struct dw_dma_platform_data *pdata; | |
1467 | struct resource *io; | |
1468 | struct dw_dma *dw; | |
1469 | size_t size; | |
482c67ea AS |
1470 | void __iomem *regs; |
1471 | bool autocfg; | |
1472 | unsigned int dw_params; | |
1473 | unsigned int nr_channels; | |
4a63a8b3 | 1474 | unsigned int max_blk_size = 0; |
3bfb1d20 HS |
1475 | int irq; |
1476 | int err; | |
1477 | int i; | |
1478 | ||
6c618c9d | 1479 | pdata = dev_get_platdata(&pdev->dev); |
3bfb1d20 HS |
1480 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) |
1481 | return -EINVAL; | |
1482 | ||
1483 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1484 | if (!io) | |
1485 | return -EINVAL; | |
1486 | ||
1487 | irq = platform_get_irq(pdev, 0); | |
1488 | if (irq < 0) | |
1489 | return irq; | |
1490 | ||
482c67ea AS |
1491 | regs = devm_request_and_ioremap(&pdev->dev, io); |
1492 | if (!regs) | |
1493 | return -EBUSY; | |
1494 | ||
1495 | dw_params = dma_read_byaddr(regs, DW_PARAMS); | |
1496 | autocfg = dw_params >> DW_PARAMS_EN & 0x1; | |
1497 | ||
1498 | if (autocfg) | |
1499 | nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; | |
1500 | else | |
1501 | nr_channels = pdata->nr_channels; | |
1502 | ||
1503 | size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan); | |
dbde5c29 | 1504 | dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
3bfb1d20 HS |
1505 | if (!dw) |
1506 | return -ENOMEM; | |
1507 | ||
dbde5c29 AS |
1508 | dw->clk = devm_clk_get(&pdev->dev, "hclk"); |
1509 | if (IS_ERR(dw->clk)) | |
1510 | return PTR_ERR(dw->clk); | |
3075528d | 1511 | clk_prepare_enable(dw->clk); |
3bfb1d20 | 1512 | |
482c67ea AS |
1513 | dw->regs = regs; |
1514 | ||
4a63a8b3 | 1515 | /* get hardware configuration parameters */ |
a0982004 | 1516 | if (autocfg) { |
4a63a8b3 AS |
1517 | max_blk_size = dma_readl(dw, MAX_BLK_SIZE); |
1518 | ||
a0982004 AS |
1519 | dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
1520 | for (i = 0; i < dw->nr_masters; i++) { | |
1521 | dw->data_width[i] = | |
1522 | (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; | |
1523 | } | |
1524 | } else { | |
1525 | dw->nr_masters = pdata->nr_masters; | |
1526 | memcpy(dw->data_width, pdata->data_width, 4); | |
1527 | } | |
1528 | ||
11f932ec | 1529 | /* Calculate all channel mask before DMA setup */ |
482c67ea | 1530 | dw->all_chan_mask = (1 << nr_channels) - 1; |
11f932ec | 1531 | |
3bfb1d20 HS |
1532 | /* force dma off, just in case */ |
1533 | dw_dma_off(dw); | |
1534 | ||
236b106f AS |
1535 | /* disable BLOCK interrupts as well */ |
1536 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1537 | ||
dbde5c29 AS |
1538 | err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0, |
1539 | "dw_dmac", dw); | |
3bfb1d20 | 1540 | if (err) |
dbde5c29 | 1541 | return err; |
3bfb1d20 HS |
1542 | |
1543 | platform_set_drvdata(pdev, dw); | |
1544 | ||
1545 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1546 | ||
3bfb1d20 | 1547 | INIT_LIST_HEAD(&dw->dma.channels); |
482c67ea | 1548 | for (i = 0; i < nr_channels; i++) { |
3bfb1d20 | 1549 | struct dw_dma_chan *dwc = &dw->chan[i]; |
fed2574b | 1550 | int r = nr_channels - i - 1; |
3bfb1d20 HS |
1551 | |
1552 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1553 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1554 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1555 | list_add_tail(&dwc->chan.device_node, | |
1556 | &dw->dma.channels); | |
1557 | else | |
1558 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1559 | |
93317e8e VK |
1560 | /* 7 is highest priority & 0 is lowest. */ |
1561 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
fed2574b | 1562 | dwc->priority = r; |
93317e8e VK |
1563 | else |
1564 | dwc->priority = i; | |
1565 | ||
3bfb1d20 HS |
1566 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1567 | spin_lock_init(&dwc->lock); | |
1568 | dwc->mask = 1 << i; | |
1569 | ||
1570 | INIT_LIST_HEAD(&dwc->active_list); | |
1571 | INIT_LIST_HEAD(&dwc->queue); | |
1572 | INIT_LIST_HEAD(&dwc->free_list); | |
1573 | ||
1574 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1575 | |
a0982004 AS |
1576 | dwc->dw = dw; |
1577 | ||
4a63a8b3 | 1578 | /* hardware configuration */ |
fed2574b AS |
1579 | if (autocfg) { |
1580 | unsigned int dwc_params; | |
1581 | ||
1582 | dwc_params = dma_read_byaddr(regs + r * sizeof(u32), | |
1583 | DWC_PARAMS); | |
1584 | ||
4a63a8b3 AS |
1585 | /* Decode maximum block size for given channel. The |
1586 | * stored 4 bit value represents blocks from 0x00 for 3 | |
1587 | * up to 0x0a for 4095. */ | |
1588 | dwc->block_size = | |
1589 | (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; | |
fed2574b AS |
1590 | dwc->nollp = |
1591 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1592 | } else { | |
4a63a8b3 | 1593 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1594 | |
1595 | /* Check if channel supports multi block transfer */ | |
1596 | channel_writel(dwc, LLP, 0xfffffffc); | |
1597 | dwc->nollp = | |
1598 | (channel_readl(dwc, LLP) & 0xfffffffc) == 0; | |
1599 | channel_writel(dwc, LLP, 0); | |
1600 | } | |
3bfb1d20 HS |
1601 | } |
1602 | ||
11f932ec | 1603 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1604 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1605 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1606 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1607 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1608 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1609 | ||
3bfb1d20 HS |
1610 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
1611 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
95ea759e JI |
1612 | if (pdata->is_private) |
1613 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
3bfb1d20 HS |
1614 | dw->dma.dev = &pdev->dev; |
1615 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1616 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1617 | ||
1618 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1619 | ||
1620 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1621 | dw->dma.device_control = dwc_control; |
3bfb1d20 | 1622 | |
07934481 | 1623 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1624 | dw->dma.device_issue_pending = dwc_issue_pending; |
1625 | ||
1626 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1627 | ||
1628 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
482c67ea | 1629 | dev_name(&pdev->dev), nr_channels); |
3bfb1d20 HS |
1630 | |
1631 | dma_async_device_register(&dw->dma); | |
1632 | ||
1633 | return 0; | |
3bfb1d20 HS |
1634 | } |
1635 | ||
0272e93f | 1636 | static int __devexit dw_remove(struct platform_device *pdev) |
3bfb1d20 HS |
1637 | { |
1638 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1639 | struct dw_dma_chan *dwc, *_dwc; | |
3bfb1d20 HS |
1640 | |
1641 | dw_dma_off(dw); | |
1642 | dma_async_device_unregister(&dw->dma); | |
1643 | ||
3bfb1d20 HS |
1644 | tasklet_kill(&dw->tasklet); |
1645 | ||
1646 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1647 | chan.device_node) { | |
1648 | list_del(&dwc->chan.device_node); | |
1649 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1650 | } | |
1651 | ||
3bfb1d20 HS |
1652 | return 0; |
1653 | } | |
1654 | ||
1655 | static void dw_shutdown(struct platform_device *pdev) | |
1656 | { | |
1657 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1658 | ||
1659 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1660 | clk_disable_unprepare(dw->clk); |
3bfb1d20 HS |
1661 | } |
1662 | ||
4a256b5f | 1663 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1664 | { |
4a256b5f | 1665 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1666 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1667 | ||
1668 | dw_dma_off(platform_get_drvdata(pdev)); | |
3075528d | 1669 | clk_disable_unprepare(dw->clk); |
61e183f8 | 1670 | |
3bfb1d20 HS |
1671 | return 0; |
1672 | } | |
1673 | ||
4a256b5f | 1674 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1675 | { |
4a256b5f | 1676 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1677 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1678 | ||
3075528d | 1679 | clk_prepare_enable(dw->clk); |
3bfb1d20 HS |
1680 | dma_writel(dw, CFG, DW_CFG_DMA_EN); |
1681 | return 0; | |
3bfb1d20 HS |
1682 | } |
1683 | ||
47145210 | 1684 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1685 | .suspend_noirq = dw_suspend_noirq, |
1686 | .resume_noirq = dw_resume_noirq, | |
7414a1b8 RK |
1687 | .freeze_noirq = dw_suspend_noirq, |
1688 | .thaw_noirq = dw_resume_noirq, | |
1689 | .restore_noirq = dw_resume_noirq, | |
1690 | .poweroff_noirq = dw_suspend_noirq, | |
4a256b5f MD |
1691 | }; |
1692 | ||
d3f797d9 VK |
1693 | #ifdef CONFIG_OF |
1694 | static const struct of_device_id dw_dma_id_table[] = { | |
1695 | { .compatible = "snps,dma-spear1340" }, | |
1696 | {} | |
1697 | }; | |
1698 | MODULE_DEVICE_TABLE(of, dw_dma_id_table); | |
1699 | #endif | |
1700 | ||
3bfb1d20 | 1701 | static struct platform_driver dw_driver = { |
0272e93f | 1702 | .remove = __devexit_p(dw_remove), |
3bfb1d20 | 1703 | .shutdown = dw_shutdown, |
3bfb1d20 HS |
1704 | .driver = { |
1705 | .name = "dw_dmac", | |
4a256b5f | 1706 | .pm = &dw_dev_pm_ops, |
d3f797d9 | 1707 | .of_match_table = of_match_ptr(dw_dma_id_table), |
3bfb1d20 HS |
1708 | }, |
1709 | }; | |
1710 | ||
1711 | static int __init dw_init(void) | |
1712 | { | |
1713 | return platform_driver_probe(&dw_driver, dw_probe); | |
1714 | } | |
cb689a70 | 1715 | subsys_initcall(dw_init); |
3bfb1d20 HS |
1716 | |
1717 | static void __exit dw_exit(void) | |
1718 | { | |
1719 | platform_driver_unregister(&dw_driver); | |
1720 | } | |
1721 | module_exit(dw_exit); | |
1722 | ||
1723 | MODULE_LICENSE("GPL v2"); | |
1724 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
e05503ef | 1725 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
10d8935f | 1726 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |