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Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
3ad7a42d | 27 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
28 | |
29 | #include "dmaengine.h" | |
30 | #include "virt-dma.h" | |
31 | ||
32 | /* | |
33 | * This will go away when the private EDMA API is folded | |
34 | * into this driver and the platform device(s) are | |
35 | * instantiated in the arch code. We can only get away | |
36 | * with this simplification because DA8XX may not be built | |
37 | * in the same kernel image with other DaVinci parts. This | |
38 | * avoids having to sprinkle dmaengine driver platform devices | |
39 | * and data throughout all the existing board files. | |
40 | */ | |
41 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
42 | #define EDMA_CTLRS 2 | |
43 | #define EDMA_CHANS 32 | |
44 | #else | |
45 | #define EDMA_CTLRS 1 | |
46 | #define EDMA_CHANS 64 | |
47 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
48 | ||
49 | /* Max of 16 segments per channel to conserve PaRAM slots */ | |
50 | #define MAX_NR_SG 16 | |
51 | #define EDMA_MAX_SLOTS MAX_NR_SG | |
52 | #define EDMA_DESCRIPTORS 16 | |
53 | ||
54 | struct edma_desc { | |
55 | struct virt_dma_desc vdesc; | |
56 | struct list_head node; | |
57 | int absync; | |
58 | int pset_nr; | |
53407062 | 59 | int processed; |
c2dde5f8 MP |
60 | struct edmacc_param pset[0]; |
61 | }; | |
62 | ||
63 | struct edma_cc; | |
64 | ||
65 | struct edma_chan { | |
66 | struct virt_dma_chan vchan; | |
67 | struct list_head node; | |
68 | struct edma_desc *edesc; | |
69 | struct edma_cc *ecc; | |
70 | int ch_num; | |
71 | bool alloced; | |
72 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 73 | int missed; |
661f7cb5 | 74 | struct dma_slave_config cfg; |
c2dde5f8 MP |
75 | }; |
76 | ||
77 | struct edma_cc { | |
78 | int ctlr; | |
79 | struct dma_device dma_slave; | |
80 | struct edma_chan slave_chans[EDMA_CHANS]; | |
81 | int num_slave_chans; | |
82 | int dummy_slot; | |
83 | }; | |
84 | ||
85 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
86 | { | |
87 | return container_of(d, struct edma_cc, dma_slave); | |
88 | } | |
89 | ||
90 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
91 | { | |
92 | return container_of(c, struct edma_chan, vchan.chan); | |
93 | } | |
94 | ||
95 | static inline struct edma_desc | |
96 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
97 | { | |
98 | return container_of(tx, struct edma_desc, vdesc.tx); | |
99 | } | |
100 | ||
101 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
102 | { | |
103 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
104 | } | |
105 | ||
106 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
107 | static void edma_execute(struct edma_chan *echan) | |
108 | { | |
53407062 | 109 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 110 | struct edma_desc *edesc; |
53407062 JF |
111 | struct device *dev = echan->vchan.chan.device->dev; |
112 | int i, j, left, nslots; | |
113 | ||
114 | /* If either we processed all psets or we're still not started */ | |
115 | if (!echan->edesc || | |
116 | echan->edesc->pset_nr == echan->edesc->processed) { | |
117 | /* Get next vdesc */ | |
118 | vdesc = vchan_next_desc(&echan->vchan); | |
119 | if (!vdesc) { | |
120 | echan->edesc = NULL; | |
121 | return; | |
122 | } | |
123 | list_del(&vdesc->node); | |
124 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
125 | } |
126 | ||
53407062 | 127 | edesc = echan->edesc; |
c2dde5f8 | 128 | |
53407062 JF |
129 | /* Find out how many left */ |
130 | left = edesc->pset_nr - edesc->processed; | |
131 | nslots = min(MAX_NR_SG, left); | |
c2dde5f8 MP |
132 | |
133 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
134 | for (i = 0; i < nslots; i++) { |
135 | j = i + edesc->processed; | |
136 | edma_write_slot(echan->slot[i], &edesc->pset[j]); | |
c2dde5f8 MP |
137 | dev_dbg(echan->vchan.chan.device->dev, |
138 | "\n pset[%d]:\n" | |
139 | " chnum\t%d\n" | |
140 | " slot\t%d\n" | |
141 | " opt\t%08x\n" | |
142 | " src\t%08x\n" | |
143 | " dst\t%08x\n" | |
144 | " abcnt\t%08x\n" | |
145 | " ccnt\t%08x\n" | |
146 | " bidx\t%08x\n" | |
147 | " cidx\t%08x\n" | |
148 | " lkrld\t%08x\n", | |
53407062 JF |
149 | j, echan->ch_num, echan->slot[i], |
150 | edesc->pset[j].opt, | |
151 | edesc->pset[j].src, | |
152 | edesc->pset[j].dst, | |
153 | edesc->pset[j].a_b_cnt, | |
154 | edesc->pset[j].ccnt, | |
155 | edesc->pset[j].src_dst_bidx, | |
156 | edesc->pset[j].src_dst_cidx, | |
157 | edesc->pset[j].link_bcntrld); | |
c2dde5f8 | 158 | /* Link to the previous slot if not the last set */ |
53407062 | 159 | if (i != (nslots - 1)) |
c2dde5f8 | 160 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
161 | } |
162 | ||
53407062 JF |
163 | edesc->processed += nslots; |
164 | ||
b267b3bc JF |
165 | /* |
166 | * If this is either the last set in a set of SG-list transactions | |
167 | * then setup a link to the dummy slot, this results in all future | |
168 | * events being absorbed and that's OK because we're done | |
169 | */ | |
170 | if (edesc->processed == edesc->pset_nr) | |
171 | edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot); | |
172 | ||
53407062 JF |
173 | edma_resume(echan->ch_num); |
174 | ||
175 | if (edesc->processed <= MAX_NR_SG) { | |
176 | dev_dbg(dev, "first transfer starting %d\n", echan->ch_num); | |
177 | edma_start(echan->ch_num); | |
178 | } | |
c5f47990 JF |
179 | |
180 | /* | |
181 | * This happens due to setup times between intermediate transfers | |
182 | * in long SG lists which have to be broken up into transfers of | |
183 | * MAX_NR_SG | |
184 | */ | |
185 | if (echan->missed) { | |
186 | dev_dbg(dev, "missed event in execute detected\n"); | |
187 | edma_clean_channel(echan->ch_num); | |
188 | edma_stop(echan->ch_num); | |
189 | edma_start(echan->ch_num); | |
190 | edma_trigger_channel(echan->ch_num); | |
191 | echan->missed = 0; | |
192 | } | |
c2dde5f8 MP |
193 | } |
194 | ||
195 | static int edma_terminate_all(struct edma_chan *echan) | |
196 | { | |
197 | unsigned long flags; | |
198 | LIST_HEAD(head); | |
199 | ||
200 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
201 | ||
202 | /* | |
203 | * Stop DMA activity: we assume the callback will not be called | |
204 | * after edma_dma() returns (even if it does, it will see | |
205 | * echan->edesc is NULL and exit.) | |
206 | */ | |
207 | if (echan->edesc) { | |
208 | echan->edesc = NULL; | |
209 | edma_stop(echan->ch_num); | |
210 | } | |
211 | ||
212 | vchan_get_all_descriptors(&echan->vchan, &head); | |
213 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
214 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
c2dde5f8 | 219 | static int edma_slave_config(struct edma_chan *echan, |
661f7cb5 | 220 | struct dma_slave_config *cfg) |
c2dde5f8 | 221 | { |
661f7cb5 MP |
222 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
223 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
224 | return -EINVAL; |
225 | ||
661f7cb5 | 226 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
231 | static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
232 | unsigned long arg) | |
233 | { | |
234 | int ret = 0; | |
235 | struct dma_slave_config *config; | |
236 | struct edma_chan *echan = to_edma_chan(chan); | |
237 | ||
238 | switch (cmd) { | |
239 | case DMA_TERMINATE_ALL: | |
240 | edma_terminate_all(echan); | |
241 | break; | |
242 | case DMA_SLAVE_CONFIG: | |
243 | config = (struct dma_slave_config *)arg; | |
244 | ret = edma_slave_config(echan, config); | |
245 | break; | |
246 | default: | |
247 | ret = -ENOSYS; | |
248 | } | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
253 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( | |
254 | struct dma_chan *chan, struct scatterlist *sgl, | |
255 | unsigned int sg_len, enum dma_transfer_direction direction, | |
256 | unsigned long tx_flags, void *context) | |
257 | { | |
258 | struct edma_chan *echan = to_edma_chan(chan); | |
259 | struct device *dev = chan->device->dev; | |
260 | struct edma_desc *edesc; | |
661f7cb5 MP |
261 | dma_addr_t dev_addr; |
262 | enum dma_slave_buswidth dev_width; | |
263 | u32 burst; | |
c2dde5f8 | 264 | struct scatterlist *sg; |
c2dde5f8 MP |
265 | int acnt, bcnt, ccnt, src, dst, cidx; |
266 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
6fbe24da | 267 | int i, nslots; |
c2dde5f8 MP |
268 | |
269 | if (unlikely(!echan || !sgl || !sg_len)) | |
270 | return NULL; | |
271 | ||
661f7cb5 MP |
272 | if (direction == DMA_DEV_TO_MEM) { |
273 | dev_addr = echan->cfg.src_addr; | |
274 | dev_width = echan->cfg.src_addr_width; | |
275 | burst = echan->cfg.src_maxburst; | |
276 | } else if (direction == DMA_MEM_TO_DEV) { | |
277 | dev_addr = echan->cfg.dst_addr; | |
278 | dev_width = echan->cfg.dst_addr_width; | |
279 | burst = echan->cfg.dst_maxburst; | |
280 | } else { | |
281 | dev_err(dev, "%s: bad direction?\n", __func__); | |
282 | return NULL; | |
283 | } | |
284 | ||
285 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c2dde5f8 MP |
286 | dev_err(dev, "Undefined slave buswidth\n"); |
287 | return NULL; | |
288 | } | |
289 | ||
c2dde5f8 MP |
290 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
291 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
292 | if (!edesc) { | |
293 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
294 | return NULL; | |
295 | } | |
296 | ||
297 | edesc->pset_nr = sg_len; | |
298 | ||
6fbe24da JF |
299 | /* Allocate a PaRAM slot, if needed */ |
300 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
301 | ||
302 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
303 | if (echan->slot[i] < 0) { |
304 | echan->slot[i] = | |
305 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
306 | EDMA_SLOT_ANY); | |
307 | if (echan->slot[i] < 0) { | |
308 | dev_err(dev, "Failed to allocate slot\n"); | |
309 | return NULL; | |
310 | } | |
311 | } | |
6fbe24da JF |
312 | } |
313 | ||
314 | /* Configure PaRAM sets for each SG */ | |
315 | for_each_sg(sgl, sg, sg_len, i) { | |
c2dde5f8 | 316 | |
661f7cb5 | 317 | acnt = dev_width; |
c2dde5f8 MP |
318 | |
319 | /* | |
320 | * If the maxburst is equal to the fifo width, use | |
321 | * A-synced transfers. This allows for large contiguous | |
322 | * buffer transfers using only one PaRAM set. | |
323 | */ | |
661f7cb5 | 324 | if (burst == 1) { |
c2dde5f8 MP |
325 | edesc->absync = false; |
326 | ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1); | |
327 | bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1); | |
328 | if (bcnt) | |
329 | ccnt++; | |
330 | else | |
331 | bcnt = SZ_64K - 1; | |
332 | cidx = acnt; | |
333 | /* | |
334 | * If maxburst is greater than the fifo address_width, | |
335 | * use AB-synced transfers where A count is the fifo | |
336 | * address_width and B count is the maxburst. In this | |
337 | * case, we are limited to transfers of C count frames | |
338 | * of (address_width * maxburst) where C count is limited | |
339 | * to SZ_64K-1. This places an upper bound on the length | |
340 | * of an SG segment that can be handled. | |
341 | */ | |
342 | } else { | |
343 | edesc->absync = true; | |
661f7cb5 | 344 | bcnt = burst; |
c2dde5f8 MP |
345 | ccnt = sg_dma_len(sg) / (acnt * bcnt); |
346 | if (ccnt > (SZ_64K - 1)) { | |
347 | dev_err(dev, "Exceeded max SG segment size\n"); | |
348 | return NULL; | |
349 | } | |
350 | cidx = acnt * bcnt; | |
351 | } | |
352 | ||
353 | if (direction == DMA_MEM_TO_DEV) { | |
354 | src = sg_dma_address(sg); | |
661f7cb5 | 355 | dst = dev_addr; |
c2dde5f8 MP |
356 | src_bidx = acnt; |
357 | src_cidx = cidx; | |
358 | dst_bidx = 0; | |
359 | dst_cidx = 0; | |
360 | } else { | |
661f7cb5 | 361 | src = dev_addr; |
c2dde5f8 MP |
362 | dst = sg_dma_address(sg); |
363 | src_bidx = 0; | |
364 | src_cidx = 0; | |
365 | dst_bidx = acnt; | |
366 | dst_cidx = cidx; | |
367 | } | |
368 | ||
369 | edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); | |
370 | /* Configure A or AB synchronized transfers */ | |
371 | if (edesc->absync) | |
372 | edesc->pset[i].opt |= SYNCDIM; | |
6fbe24da JF |
373 | |
374 | /* If this is the last in a current SG set of transactions, | |
375 | enable interrupts so that next set is processed */ | |
376 | if (!((i+1) % MAX_NR_SG)) | |
377 | edesc->pset[i].opt |= TCINTEN; | |
378 | ||
c2dde5f8 MP |
379 | /* If this is the last set, enable completion interrupt flag */ |
380 | if (i == sg_len - 1) | |
381 | edesc->pset[i].opt |= TCINTEN; | |
382 | ||
383 | edesc->pset[i].src = src; | |
384 | edesc->pset[i].dst = dst; | |
385 | ||
386 | edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx; | |
387 | edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
388 | ||
389 | edesc->pset[i].a_b_cnt = bcnt << 16 | acnt; | |
390 | edesc->pset[i].ccnt = ccnt; | |
391 | edesc->pset[i].link_bcntrld = 0xffffffff; | |
392 | ||
393 | } | |
394 | ||
395 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
396 | } | |
397 | ||
398 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
399 | { | |
400 | struct edma_chan *echan = data; | |
401 | struct device *dev = echan->vchan.chan.device->dev; | |
402 | struct edma_desc *edesc; | |
403 | unsigned long flags; | |
c5f47990 | 404 | struct edmacc_param p; |
c2dde5f8 | 405 | |
53407062 JF |
406 | /* Pause the channel */ |
407 | edma_pause(echan->ch_num); | |
c2dde5f8 MP |
408 | |
409 | switch (ch_status) { | |
410 | case DMA_COMPLETE: | |
c2dde5f8 MP |
411 | spin_lock_irqsave(&echan->vchan.lock, flags); |
412 | ||
413 | edesc = echan->edesc; | |
414 | if (edesc) { | |
53407062 JF |
415 | if (edesc->processed == edesc->pset_nr) { |
416 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); | |
417 | edma_stop(echan->ch_num); | |
418 | vchan_cookie_complete(&edesc->vdesc); | |
419 | } else { | |
420 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
421 | } | |
422 | ||
c2dde5f8 | 423 | edma_execute(echan); |
c2dde5f8 MP |
424 | } |
425 | ||
426 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
427 | ||
428 | break; | |
429 | case DMA_CC_ERROR: | |
c5f47990 JF |
430 | spin_lock_irqsave(&echan->vchan.lock, flags); |
431 | ||
432 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); | |
433 | ||
434 | /* | |
435 | * Issue later based on missed flag which will be sure | |
436 | * to happen as: | |
437 | * (1) we finished transmitting an intermediate slot and | |
438 | * edma_execute is coming up. | |
439 | * (2) or we finished current transfer and issue will | |
440 | * call edma_execute. | |
441 | * | |
442 | * Important note: issuing can be dangerous here and | |
443 | * lead to some nasty recursion when we are in a NULL | |
444 | * slot. So we avoid doing so and set the missed flag. | |
445 | */ | |
446 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
447 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
448 | echan->missed = 1; | |
449 | } else { | |
450 | /* | |
451 | * The slot is already programmed but the event got | |
452 | * missed, so its safe to issue it here. | |
453 | */ | |
454 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
455 | edma_clean_channel(echan->ch_num); | |
456 | edma_stop(echan->ch_num); | |
457 | edma_start(echan->ch_num); | |
458 | edma_trigger_channel(echan->ch_num); | |
459 | } | |
460 | ||
461 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
462 | ||
c2dde5f8 MP |
463 | break; |
464 | default: | |
465 | break; | |
466 | } | |
467 | } | |
468 | ||
469 | /* Alloc channel resources */ | |
470 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
471 | { | |
472 | struct edma_chan *echan = to_edma_chan(chan); | |
473 | struct device *dev = chan->device->dev; | |
474 | int ret; | |
475 | int a_ch_num; | |
476 | LIST_HEAD(descs); | |
477 | ||
478 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
479 | chan, EVENTQ_DEFAULT); | |
480 | ||
481 | if (a_ch_num < 0) { | |
482 | ret = -ENODEV; | |
483 | goto err_no_chan; | |
484 | } | |
485 | ||
486 | if (a_ch_num != echan->ch_num) { | |
487 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
488 | EDMA_CTLR(echan->ch_num), | |
489 | EDMA_CHAN_SLOT(echan->ch_num)); | |
490 | ret = -ENODEV; | |
491 | goto err_wrong_chan; | |
492 | } | |
493 | ||
494 | echan->alloced = true; | |
495 | echan->slot[0] = echan->ch_num; | |
496 | ||
497 | dev_info(dev, "allocated channel for %u:%u\n", | |
498 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); | |
499 | ||
500 | return 0; | |
501 | ||
502 | err_wrong_chan: | |
503 | edma_free_channel(a_ch_num); | |
504 | err_no_chan: | |
505 | return ret; | |
506 | } | |
507 | ||
508 | /* Free channel resources */ | |
509 | static void edma_free_chan_resources(struct dma_chan *chan) | |
510 | { | |
511 | struct edma_chan *echan = to_edma_chan(chan); | |
512 | struct device *dev = chan->device->dev; | |
513 | int i; | |
514 | ||
515 | /* Terminate transfers */ | |
516 | edma_stop(echan->ch_num); | |
517 | ||
518 | vchan_free_chan_resources(&echan->vchan); | |
519 | ||
520 | /* Free EDMA PaRAM slots */ | |
521 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
522 | if (echan->slot[i] >= 0) { | |
523 | edma_free_slot(echan->slot[i]); | |
524 | echan->slot[i] = -1; | |
525 | } | |
526 | } | |
527 | ||
528 | /* Free EDMA channel */ | |
529 | if (echan->alloced) { | |
530 | edma_free_channel(echan->ch_num); | |
531 | echan->alloced = false; | |
532 | } | |
533 | ||
534 | dev_info(dev, "freeing channel for %u\n", echan->ch_num); | |
535 | } | |
536 | ||
537 | /* Send pending descriptor to hardware */ | |
538 | static void edma_issue_pending(struct dma_chan *chan) | |
539 | { | |
540 | struct edma_chan *echan = to_edma_chan(chan); | |
541 | unsigned long flags; | |
542 | ||
543 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
544 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
545 | edma_execute(echan); | |
546 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
547 | } | |
548 | ||
549 | static size_t edma_desc_size(struct edma_desc *edesc) | |
550 | { | |
551 | int i; | |
552 | size_t size; | |
553 | ||
554 | if (edesc->absync) | |
555 | for (size = i = 0; i < edesc->pset_nr; i++) | |
556 | size += (edesc->pset[i].a_b_cnt & 0xffff) * | |
557 | (edesc->pset[i].a_b_cnt >> 16) * | |
558 | edesc->pset[i].ccnt; | |
559 | else | |
560 | size = (edesc->pset[0].a_b_cnt & 0xffff) * | |
561 | (edesc->pset[0].a_b_cnt >> 16) + | |
562 | (edesc->pset[0].a_b_cnt & 0xffff) * | |
563 | (SZ_64K - 1) * edesc->pset[0].ccnt; | |
564 | ||
565 | return size; | |
566 | } | |
567 | ||
568 | /* Check request completion status */ | |
569 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
570 | dma_cookie_t cookie, | |
571 | struct dma_tx_state *txstate) | |
572 | { | |
573 | struct edma_chan *echan = to_edma_chan(chan); | |
574 | struct virt_dma_desc *vdesc; | |
575 | enum dma_status ret; | |
576 | unsigned long flags; | |
577 | ||
578 | ret = dma_cookie_status(chan, cookie, txstate); | |
579 | if (ret == DMA_SUCCESS || !txstate) | |
580 | return ret; | |
581 | ||
582 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
583 | vdesc = vchan_find_desc(&echan->vchan, cookie); | |
584 | if (vdesc) { | |
585 | txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx)); | |
586 | } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) { | |
587 | struct edma_desc *edesc = echan->edesc; | |
588 | txstate->residue = edma_desc_size(edesc); | |
c2dde5f8 MP |
589 | } |
590 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | static void __init edma_chan_init(struct edma_cc *ecc, | |
596 | struct dma_device *dma, | |
597 | struct edma_chan *echans) | |
598 | { | |
599 | int i, j; | |
600 | ||
601 | for (i = 0; i < EDMA_CHANS; i++) { | |
602 | struct edma_chan *echan = &echans[i]; | |
603 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
604 | echan->ecc = ecc; | |
605 | echan->vchan.desc_free = edma_desc_free; | |
606 | ||
607 | vchan_init(&echan->vchan, dma); | |
608 | ||
609 | INIT_LIST_HEAD(&echan->node); | |
610 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
611 | echan->slot[j] = -1; | |
612 | } | |
613 | } | |
614 | ||
615 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, | |
616 | struct device *dev) | |
617 | { | |
618 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
619 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; | |
620 | dma->device_free_chan_resources = edma_free_chan_resources; | |
621 | dma->device_issue_pending = edma_issue_pending; | |
622 | dma->device_tx_status = edma_tx_status; | |
623 | dma->device_control = edma_control; | |
624 | dma->dev = dev; | |
625 | ||
626 | INIT_LIST_HEAD(&dma->channels); | |
627 | } | |
628 | ||
463a1f8b | 629 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
630 | { |
631 | struct edma_cc *ecc; | |
632 | int ret; | |
633 | ||
634 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); | |
635 | if (!ecc) { | |
636 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
637 | return -ENOMEM; | |
638 | } | |
639 | ||
640 | ecc->ctlr = pdev->id; | |
641 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
642 | if (ecc->dummy_slot < 0) { | |
643 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
644 | return -EIO; | |
645 | } | |
646 | ||
647 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
648 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
649 | ||
650 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
651 | ||
652 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
653 | ||
654 | ret = dma_async_device_register(&ecc->dma_slave); | |
655 | if (ret) | |
656 | goto err_reg1; | |
657 | ||
658 | platform_set_drvdata(pdev, ecc); | |
659 | ||
660 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
661 | ||
662 | return 0; | |
663 | ||
664 | err_reg1: | |
665 | edma_free_slot(ecc->dummy_slot); | |
666 | return ret; | |
667 | } | |
668 | ||
4bf27b8b | 669 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
670 | { |
671 | struct device *dev = &pdev->dev; | |
672 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
673 | ||
674 | dma_async_device_unregister(&ecc->dma_slave); | |
675 | edma_free_slot(ecc->dummy_slot); | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | static struct platform_driver edma_driver = { | |
681 | .probe = edma_probe, | |
a7d6e3ec | 682 | .remove = edma_remove, |
c2dde5f8 MP |
683 | .driver = { |
684 | .name = "edma-dma-engine", | |
685 | .owner = THIS_MODULE, | |
686 | }, | |
687 | }; | |
688 | ||
689 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
690 | { | |
691 | if (chan->device->dev->driver == &edma_driver.driver) { | |
692 | struct edma_chan *echan = to_edma_chan(chan); | |
693 | unsigned ch_req = *(unsigned *)param; | |
694 | return ch_req == echan->ch_num; | |
695 | } | |
696 | return false; | |
697 | } | |
698 | EXPORT_SYMBOL(edma_filter_fn); | |
699 | ||
700 | static struct platform_device *pdev0, *pdev1; | |
701 | ||
702 | static const struct platform_device_info edma_dev_info0 = { | |
703 | .name = "edma-dma-engine", | |
704 | .id = 0, | |
c2dde5f8 MP |
705 | }; |
706 | ||
707 | static const struct platform_device_info edma_dev_info1 = { | |
708 | .name = "edma-dma-engine", | |
709 | .id = 1, | |
c2dde5f8 MP |
710 | }; |
711 | ||
712 | static int edma_init(void) | |
713 | { | |
714 | int ret = platform_driver_register(&edma_driver); | |
715 | ||
716 | if (ret == 0) { | |
717 | pdev0 = platform_device_register_full(&edma_dev_info0); | |
718 | if (IS_ERR(pdev0)) { | |
719 | platform_driver_unregister(&edma_driver); | |
720 | ret = PTR_ERR(pdev0); | |
721 | goto out; | |
722 | } | |
373459ee AS |
723 | pdev0->dev.dma_mask = &pdev0->dev.coherent_dma_mask; |
724 | pdev0->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
c2dde5f8 MP |
725 | } |
726 | ||
727 | if (EDMA_CTLRS == 2) { | |
728 | pdev1 = platform_device_register_full(&edma_dev_info1); | |
729 | if (IS_ERR(pdev1)) { | |
730 | platform_driver_unregister(&edma_driver); | |
731 | platform_device_unregister(pdev0); | |
732 | ret = PTR_ERR(pdev1); | |
733 | } | |
373459ee AS |
734 | pdev1->dev.dma_mask = &pdev1->dev.coherent_dma_mask; |
735 | pdev1->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
c2dde5f8 MP |
736 | } |
737 | ||
738 | out: | |
739 | return ret; | |
740 | } | |
741 | subsys_initcall(edma_init); | |
742 | ||
743 | static void __exit edma_exit(void) | |
744 | { | |
745 | platform_device_unregister(pdev0); | |
746 | if (pdev1) | |
747 | platform_device_unregister(pdev1); | |
748 | platform_driver_unregister(&edma_driver); | |
749 | } | |
750 | module_exit(edma_exit); | |
751 | ||
d71505b6 | 752 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
753 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
754 | MODULE_LICENSE("GPL v2"); |