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Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
b7a4fd53 | 18 | #include <linux/edma.h> |
c2dde5f8 MP |
19 | #include <linux/err.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
ed64610f | 27 | #include <linux/of.h> |
dc9b6055 | 28 | #include <linux/of_dma.h> |
2b6b3b74 PU |
29 | #include <linux/of_irq.h> |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_device.h> | |
32 | #include <linux/pm_runtime.h> | |
c2dde5f8 | 33 | |
3ad7a42d | 34 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
35 | |
36 | #include "dmaengine.h" | |
37 | #include "virt-dma.h" | |
38 | ||
2b6b3b74 PU |
39 | /* Offsets matching "struct edmacc_param" */ |
40 | #define PARM_OPT 0x00 | |
41 | #define PARM_SRC 0x04 | |
42 | #define PARM_A_B_CNT 0x08 | |
43 | #define PARM_DST 0x0c | |
44 | #define PARM_SRC_DST_BIDX 0x10 | |
45 | #define PARM_LINK_BCNTRLD 0x14 | |
46 | #define PARM_SRC_DST_CIDX 0x18 | |
47 | #define PARM_CCNT 0x1c | |
48 | ||
49 | #define PARM_SIZE 0x20 | |
50 | ||
51 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
52 | #define SH_ER 0x00 /* 64 bits */ | |
53 | #define SH_ECR 0x08 /* 64 bits */ | |
54 | #define SH_ESR 0x10 /* 64 bits */ | |
55 | #define SH_CER 0x18 /* 64 bits */ | |
56 | #define SH_EER 0x20 /* 64 bits */ | |
57 | #define SH_EECR 0x28 /* 64 bits */ | |
58 | #define SH_EESR 0x30 /* 64 bits */ | |
59 | #define SH_SER 0x38 /* 64 bits */ | |
60 | #define SH_SECR 0x40 /* 64 bits */ | |
61 | #define SH_IER 0x50 /* 64 bits */ | |
62 | #define SH_IECR 0x58 /* 64 bits */ | |
63 | #define SH_IESR 0x60 /* 64 bits */ | |
64 | #define SH_IPR 0x68 /* 64 bits */ | |
65 | #define SH_ICR 0x70 /* 64 bits */ | |
66 | #define SH_IEVAL 0x78 | |
67 | #define SH_QER 0x80 | |
68 | #define SH_QEER 0x84 | |
69 | #define SH_QEECR 0x88 | |
70 | #define SH_QEESR 0x8c | |
71 | #define SH_QSER 0x90 | |
72 | #define SH_QSECR 0x94 | |
73 | #define SH_SIZE 0x200 | |
74 | ||
75 | /* Offsets for EDMA CC global registers */ | |
76 | #define EDMA_REV 0x0000 | |
77 | #define EDMA_CCCFG 0x0004 | |
78 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
79 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
80 | #define EDMA_QDMAQNUM 0x0260 | |
81 | #define EDMA_QUETCMAP 0x0280 | |
82 | #define EDMA_QUEPRI 0x0284 | |
83 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
84 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
85 | #define EDMA_QEMR 0x0310 | |
86 | #define EDMA_QEMCR 0x0314 | |
87 | #define EDMA_CCERR 0x0318 | |
88 | #define EDMA_CCERRCLR 0x031c | |
89 | #define EDMA_EEVAL 0x0320 | |
90 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
91 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
92 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
93 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
94 | #define EDMA_QWMTHRA 0x0620 | |
95 | #define EDMA_QWMTHRB 0x0624 | |
96 | #define EDMA_CCSTAT 0x0640 | |
97 | ||
98 | #define EDMA_M 0x1000 /* global channel registers */ | |
99 | #define EDMA_ECR 0x1008 | |
100 | #define EDMA_ECRH 0x100C | |
101 | #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */ | |
102 | #define EDMA_PARM 0x4000 /* PaRAM entries */ | |
103 | ||
104 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) | |
105 | ||
106 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ | |
107 | ||
108 | /* CCCFG register */ | |
109 | #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ | |
633e42b8 | 110 | #define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */ |
2b6b3b74 PU |
111 | #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ |
112 | #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ | |
113 | #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ | |
114 | #define CHMAP_EXIST BIT(24) | |
115 | ||
2abd5f1b JF |
116 | /* |
117 | * Max of 20 segments per channel to conserve PaRAM slots | |
118 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
119 | * that are required for ASoC, otherwise DMA prep calls will | |
120 | * fail. Today davinci-pcm is the only user of this driver and | |
121 | * requires atleast 17 slots, so we setup the default to 20. | |
122 | */ | |
123 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
124 | #define EDMA_MAX_SLOTS MAX_NR_SG |
125 | #define EDMA_DESCRIPTORS 16 | |
126 | ||
2b6b3b74 PU |
127 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ |
128 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ | |
129 | #define EDMA_CONT_PARAMS_ANY 1001 | |
130 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 | |
131 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 | |
132 | ||
2b6b3b74 PU |
133 | /* PaRAM slots are laid out like this */ |
134 | struct edmacc_param { | |
135 | u32 opt; | |
136 | u32 src; | |
137 | u32 a_b_cnt; | |
138 | u32 dst; | |
139 | u32 src_dst_bidx; | |
140 | u32 link_bcntrld; | |
141 | u32 src_dst_cidx; | |
142 | u32 ccnt; | |
143 | } __packed; | |
144 | ||
145 | /* fields in edmacc_param.opt */ | |
146 | #define SAM BIT(0) | |
147 | #define DAM BIT(1) | |
148 | #define SYNCDIM BIT(2) | |
149 | #define STATIC BIT(3) | |
150 | #define EDMA_FWID (0x07 << 8) | |
151 | #define TCCMODE BIT(11) | |
152 | #define EDMA_TCC(t) ((t) << 12) | |
153 | #define TCINTEN BIT(20) | |
154 | #define ITCINTEN BIT(21) | |
155 | #define TCCHEN BIT(22) | |
156 | #define ITCCHEN BIT(23) | |
157 | ||
b5088ad9 | 158 | struct edma_pset { |
c2da2340 TG |
159 | u32 len; |
160 | dma_addr_t addr; | |
b5088ad9 TG |
161 | struct edmacc_param param; |
162 | }; | |
163 | ||
c2dde5f8 MP |
164 | struct edma_desc { |
165 | struct virt_dma_desc vdesc; | |
166 | struct list_head node; | |
c2da2340 | 167 | enum dma_transfer_direction direction; |
50a9c707 | 168 | int cyclic; |
c2dde5f8 MP |
169 | int absync; |
170 | int pset_nr; | |
04361d88 | 171 | struct edma_chan *echan; |
53407062 | 172 | int processed; |
04361d88 JF |
173 | |
174 | /* | |
175 | * The following 4 elements are used for residue accounting. | |
176 | * | |
177 | * - processed_stat: the number of SG elements we have traversed | |
178 | * so far to cover accounting. This is updated directly to processed | |
179 | * during edma_callback and is always <= processed, because processed | |
180 | * refers to the number of pending transfer (programmed to EDMA | |
181 | * controller), where as processed_stat tracks number of transfers | |
182 | * accounted for so far. | |
183 | * | |
184 | * - residue: The amount of bytes we have left to transfer for this desc | |
185 | * | |
186 | * - residue_stat: The residue in bytes of data we have covered | |
187 | * so far for accounting. This is updated directly to residue | |
188 | * during callbacks to keep it current. | |
189 | * | |
190 | * - sg_len: Tracks the length of the current intermediate transfer, | |
191 | * this is required to update the residue during intermediate transfer | |
192 | * completion callback. | |
193 | */ | |
740b41f7 | 194 | int processed_stat; |
740b41f7 | 195 | u32 sg_len; |
04361d88 | 196 | u32 residue; |
740b41f7 | 197 | u32 residue_stat; |
04361d88 | 198 | |
b5088ad9 | 199 | struct edma_pset pset[0]; |
c2dde5f8 MP |
200 | }; |
201 | ||
202 | struct edma_cc; | |
203 | ||
1be5336b PU |
204 | struct edma_tc { |
205 | struct device_node *node; | |
206 | u16 id; | |
207 | }; | |
208 | ||
c2dde5f8 MP |
209 | struct edma_chan { |
210 | struct virt_dma_chan vchan; | |
211 | struct list_head node; | |
212 | struct edma_desc *edesc; | |
213 | struct edma_cc *ecc; | |
1be5336b | 214 | struct edma_tc *tc; |
c2dde5f8 MP |
215 | int ch_num; |
216 | bool alloced; | |
1be5336b | 217 | bool hw_triggered; |
c2dde5f8 | 218 | int slot[EDMA_MAX_SLOTS]; |
c5f47990 | 219 | int missed; |
661f7cb5 | 220 | struct dma_slave_config cfg; |
c2dde5f8 MP |
221 | }; |
222 | ||
223 | struct edma_cc { | |
2b6b3b74 PU |
224 | struct device *dev; |
225 | struct edma_soc_info *info; | |
226 | void __iomem *base; | |
227 | int id; | |
1be5336b | 228 | bool legacy_mode; |
2b6b3b74 PU |
229 | |
230 | /* eDMA3 resource information */ | |
231 | unsigned num_channels; | |
633e42b8 | 232 | unsigned num_qchannels; |
2b6b3b74 PU |
233 | unsigned num_region; |
234 | unsigned num_slots; | |
235 | unsigned num_tc; | |
4ab54f69 | 236 | bool chmap_exist; |
2b6b3b74 PU |
237 | enum dma_event_q default_queue; |
238 | ||
1be5336b PU |
239 | /* |
240 | * The slot_inuse bit for each PaRAM slot is clear unless the slot is | |
241 | * in use by Linux or if it is allocated to be used by DSP. | |
2b6b3b74 | 242 | */ |
7a73b135 | 243 | unsigned long *slot_inuse; |
2b6b3b74 | 244 | |
c2dde5f8 | 245 | struct dma_device dma_slave; |
1be5336b | 246 | struct dma_device *dma_memcpy; |
cb782059 | 247 | struct edma_chan *slave_chans; |
1be5336b | 248 | struct edma_tc *tc_list; |
c2dde5f8 MP |
249 | int dummy_slot; |
250 | }; | |
251 | ||
2b6b3b74 PU |
252 | /* dummy param set used to (re)initialize parameter RAM slots */ |
253 | static const struct edmacc_param dummy_paramset = { | |
254 | .link_bcntrld = 0xffff, | |
255 | .ccnt = 1, | |
256 | }; | |
257 | ||
1be5336b PU |
258 | #define EDMA_BINDING_LEGACY 0 |
259 | #define EDMA_BINDING_TPCC 1 | |
2b6b3b74 | 260 | static const struct of_device_id edma_of_ids[] = { |
1be5336b PU |
261 | { |
262 | .compatible = "ti,edma3", | |
263 | .data = (void *)EDMA_BINDING_LEGACY, | |
264 | }, | |
265 | { | |
266 | .compatible = "ti,edma3-tpcc", | |
267 | .data = (void *)EDMA_BINDING_TPCC, | |
268 | }, | |
2b6b3b74 PU |
269 | {} |
270 | }; | |
271 | ||
272 | static inline unsigned int edma_read(struct edma_cc *ecc, int offset) | |
273 | { | |
274 | return (unsigned int)__raw_readl(ecc->base + offset); | |
275 | } | |
276 | ||
277 | static inline void edma_write(struct edma_cc *ecc, int offset, int val) | |
278 | { | |
279 | __raw_writel(val, ecc->base + offset); | |
280 | } | |
281 | ||
282 | static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, | |
283 | unsigned or) | |
284 | { | |
285 | unsigned val = edma_read(ecc, offset); | |
286 | ||
287 | val &= and; | |
288 | val |= or; | |
289 | edma_write(ecc, offset, val); | |
290 | } | |
291 | ||
292 | static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) | |
293 | { | |
294 | unsigned val = edma_read(ecc, offset); | |
295 | ||
296 | val &= and; | |
297 | edma_write(ecc, offset, val); | |
298 | } | |
299 | ||
300 | static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) | |
301 | { | |
302 | unsigned val = edma_read(ecc, offset); | |
303 | ||
304 | val |= or; | |
305 | edma_write(ecc, offset, val); | |
306 | } | |
307 | ||
308 | static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, | |
309 | int i) | |
310 | { | |
311 | return edma_read(ecc, offset + (i << 2)); | |
312 | } | |
313 | ||
314 | static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, | |
315 | unsigned val) | |
316 | { | |
317 | edma_write(ecc, offset + (i << 2), val); | |
318 | } | |
319 | ||
320 | static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, | |
321 | unsigned and, unsigned or) | |
322 | { | |
323 | edma_modify(ecc, offset + (i << 2), and, or); | |
324 | } | |
325 | ||
326 | static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, | |
327 | unsigned or) | |
328 | { | |
329 | edma_or(ecc, offset + (i << 2), or); | |
330 | } | |
331 | ||
332 | static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, | |
333 | unsigned or) | |
334 | { | |
335 | edma_or(ecc, offset + ((i * 2 + j) << 2), or); | |
336 | } | |
337 | ||
338 | static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, | |
339 | int j, unsigned val) | |
340 | { | |
341 | edma_write(ecc, offset + ((i * 2 + j) << 2), val); | |
342 | } | |
343 | ||
344 | static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) | |
345 | { | |
346 | return edma_read(ecc, EDMA_SHADOW0 + offset); | |
347 | } | |
348 | ||
349 | static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, | |
350 | int offset, int i) | |
351 | { | |
352 | return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); | |
353 | } | |
354 | ||
355 | static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, | |
356 | unsigned val) | |
357 | { | |
358 | edma_write(ecc, EDMA_SHADOW0 + offset, val); | |
359 | } | |
360 | ||
361 | static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, | |
362 | int i, unsigned val) | |
363 | { | |
364 | edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); | |
365 | } | |
366 | ||
d9c345d1 PU |
367 | static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, |
368 | int param_no) | |
2b6b3b74 PU |
369 | { |
370 | return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); | |
371 | } | |
372 | ||
d9c345d1 PU |
373 | static inline void edma_param_write(struct edma_cc *ecc, int offset, |
374 | int param_no, unsigned val) | |
2b6b3b74 PU |
375 | { |
376 | edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); | |
377 | } | |
378 | ||
d9c345d1 PU |
379 | static inline void edma_param_modify(struct edma_cc *ecc, int offset, |
380 | int param_no, unsigned and, unsigned or) | |
2b6b3b74 PU |
381 | { |
382 | edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); | |
383 | } | |
384 | ||
d9c345d1 PU |
385 | static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, |
386 | unsigned and) | |
2b6b3b74 PU |
387 | { |
388 | edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); | |
389 | } | |
390 | ||
d9c345d1 PU |
391 | static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, |
392 | unsigned or) | |
2b6b3b74 PU |
393 | { |
394 | edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); | |
395 | } | |
396 | ||
397 | static inline void set_bits(int offset, int len, unsigned long *p) | |
398 | { | |
399 | for (; len > 0; len--) | |
400 | set_bit(offset + (len - 1), p); | |
401 | } | |
402 | ||
403 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
404 | { | |
405 | for (; len > 0; len--) | |
406 | clear_bit(offset + (len - 1), p); | |
407 | } | |
408 | ||
2b6b3b74 PU |
409 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, |
410 | int priority) | |
411 | { | |
412 | int bit = queue_no * 4; | |
413 | ||
414 | edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); | |
415 | } | |
416 | ||
34cf3011 | 417 | static void edma_set_chmap(struct edma_chan *echan, int slot) |
2b6b3b74 | 418 | { |
34cf3011 PU |
419 | struct edma_cc *ecc = echan->ecc; |
420 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
421 | ||
e4e886c6 | 422 | if (ecc->chmap_exist) { |
e4e886c6 PU |
423 | slot = EDMA_CHAN_SLOT(slot); |
424 | edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); | |
425 | } | |
2b6b3b74 PU |
426 | } |
427 | ||
34cf3011 | 428 | static void edma_setup_interrupt(struct edma_chan *echan, bool enable) |
2b6b3b74 | 429 | { |
34cf3011 PU |
430 | struct edma_cc *ecc = echan->ecc; |
431 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
2b6b3b74 | 432 | |
79ad2e38 | 433 | if (enable) { |
34cf3011 PU |
434 | edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, |
435 | BIT(channel & 0x1f)); | |
436 | edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, | |
437 | BIT(channel & 0x1f)); | |
79ad2e38 | 438 | } else { |
34cf3011 PU |
439 | edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, |
440 | BIT(channel & 0x1f)); | |
2b6b3b74 PU |
441 | } |
442 | } | |
443 | ||
444 | /* | |
11c15733 | 445 | * paRAM slot management functions |
2b6b3b74 PU |
446 | */ |
447 | static void edma_write_slot(struct edma_cc *ecc, unsigned slot, | |
448 | const struct edmacc_param *param) | |
449 | { | |
450 | slot = EDMA_CHAN_SLOT(slot); | |
451 | if (slot >= ecc->num_slots) | |
452 | return; | |
453 | memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); | |
454 | } | |
455 | ||
2b6b3b74 PU |
456 | static void edma_read_slot(struct edma_cc *ecc, unsigned slot, |
457 | struct edmacc_param *param) | |
458 | { | |
459 | slot = EDMA_CHAN_SLOT(slot); | |
460 | if (slot >= ecc->num_slots) | |
461 | return; | |
462 | memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); | |
463 | } | |
464 | ||
465 | /** | |
466 | * edma_alloc_slot - allocate DMA parameter RAM | |
467 | * @ecc: pointer to edma_cc struct | |
468 | * @slot: specific slot to allocate; negative for "any unused slot" | |
469 | * | |
470 | * This allocates a parameter RAM slot, initializing it to hold a | |
471 | * dummy transfer. Slots allocated using this routine have not been | |
472 | * mapped to a hardware DMA channel, and will normally be used by | |
473 | * linking to them from a slot associated with a DMA channel. | |
474 | * | |
475 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
476 | * slots may be allocated on behalf of DSP firmware. | |
477 | * | |
478 | * Returns the number of the slot, else negative errno. | |
479 | */ | |
480 | static int edma_alloc_slot(struct edma_cc *ecc, int slot) | |
481 | { | |
e4e886c6 | 482 | if (slot > 0) { |
2b6b3b74 | 483 | slot = EDMA_CHAN_SLOT(slot); |
e4e886c6 PU |
484 | /* Requesting entry paRAM slot for a HW triggered channel. */ |
485 | if (ecc->chmap_exist && slot < ecc->num_channels) | |
486 | slot = EDMA_SLOT_ANY; | |
487 | } | |
488 | ||
2b6b3b74 | 489 | if (slot < 0) { |
e4e886c6 PU |
490 | if (ecc->chmap_exist) |
491 | slot = 0; | |
492 | else | |
493 | slot = ecc->num_channels; | |
2b6b3b74 | 494 | for (;;) { |
7a73b135 | 495 | slot = find_next_zero_bit(ecc->slot_inuse, |
2b6b3b74 PU |
496 | ecc->num_slots, |
497 | slot); | |
498 | if (slot == ecc->num_slots) | |
499 | return -ENOMEM; | |
7a73b135 | 500 | if (!test_and_set_bit(slot, ecc->slot_inuse)) |
2b6b3b74 PU |
501 | break; |
502 | } | |
e4e886c6 | 503 | } else if (slot >= ecc->num_slots) { |
2b6b3b74 | 504 | return -EINVAL; |
7a73b135 | 505 | } else if (test_and_set_bit(slot, ecc->slot_inuse)) { |
2b6b3b74 PU |
506 | return -EBUSY; |
507 | } | |
508 | ||
509 | edma_write_slot(ecc, slot, &dummy_paramset); | |
510 | ||
511 | return EDMA_CTLR_CHAN(ecc->id, slot); | |
512 | } | |
513 | ||
2b6b3b74 PU |
514 | static void edma_free_slot(struct edma_cc *ecc, unsigned slot) |
515 | { | |
516 | slot = EDMA_CHAN_SLOT(slot); | |
e4e886c6 | 517 | if (slot >= ecc->num_slots) |
2b6b3b74 PU |
518 | return; |
519 | ||
520 | edma_write_slot(ecc, slot, &dummy_paramset); | |
7a73b135 | 521 | clear_bit(slot, ecc->slot_inuse); |
2b6b3b74 PU |
522 | } |
523 | ||
524 | /** | |
525 | * edma_link - link one parameter RAM slot to another | |
526 | * @ecc: pointer to edma_cc struct | |
527 | * @from: parameter RAM slot originating the link | |
528 | * @to: parameter RAM slot which is the link target | |
529 | * | |
530 | * The originating slot should not be part of any active DMA transfer. | |
531 | */ | |
532 | static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) | |
533 | { | |
fc014095 PU |
534 | if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to))) |
535 | dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); | |
536 | ||
2b6b3b74 PU |
537 | from = EDMA_CHAN_SLOT(from); |
538 | to = EDMA_CHAN_SLOT(to); | |
539 | if (from >= ecc->num_slots || to >= ecc->num_slots) | |
540 | return; | |
541 | ||
d9c345d1 PU |
542 | edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, |
543 | PARM_OFFSET(to)); | |
2b6b3b74 PU |
544 | } |
545 | ||
546 | /** | |
547 | * edma_get_position - returns the current transfer point | |
548 | * @ecc: pointer to edma_cc struct | |
549 | * @slot: parameter RAM slot being examined | |
550 | * @dst: true selects the dest position, false the source | |
551 | * | |
552 | * Returns the position of the current active slot | |
553 | */ | |
554 | static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, | |
555 | bool dst) | |
556 | { | |
557 | u32 offs; | |
558 | ||
559 | slot = EDMA_CHAN_SLOT(slot); | |
560 | offs = PARM_OFFSET(slot); | |
561 | offs += dst ? PARM_DST : PARM_SRC; | |
562 | ||
563 | return edma_read(ecc, offs); | |
564 | } | |
565 | ||
34cf3011 | 566 | /* |
2b6b3b74 PU |
567 | * Channels with event associations will be triggered by their hardware |
568 | * events, and channels without such associations will be triggered by | |
569 | * software. (At this writing there is no interface for using software | |
570 | * triggers except with channels that don't support hardware triggers.) | |
2b6b3b74 | 571 | */ |
34cf3011 | 572 | static void edma_start(struct edma_chan *echan) |
2b6b3b74 | 573 | { |
34cf3011 PU |
574 | struct edma_cc *ecc = echan->ecc; |
575 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
576 | int j = (channel >> 5); | |
577 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 578 | |
1be5336b | 579 | if (!echan->hw_triggered) { |
2b6b3b74 | 580 | /* EDMA channels without event association */ |
34cf3011 PU |
581 | dev_dbg(ecc->dev, "ESR%d %08x\n", j, |
582 | edma_shadow0_read_array(ecc, SH_ESR, j)); | |
583 | edma_shadow0_write_array(ecc, SH_ESR, j, mask); | |
584 | } else { | |
2b6b3b74 | 585 | /* EDMA channel with event association */ |
3287fb4d PU |
586 | dev_dbg(ecc->dev, "ER%d %08x\n", j, |
587 | edma_shadow0_read_array(ecc, SH_ER, j)); | |
2b6b3b74 PU |
588 | /* Clear any pending event or error */ |
589 | edma_write_array(ecc, EDMA_ECR, j, mask); | |
590 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
591 | /* Clear any SER */ | |
592 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
593 | edma_shadow0_write_array(ecc, SH_EESR, j, mask); | |
3287fb4d PU |
594 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
595 | edma_shadow0_read_array(ecc, SH_EER, j)); | |
2b6b3b74 | 596 | } |
2b6b3b74 PU |
597 | } |
598 | ||
34cf3011 | 599 | static void edma_stop(struct edma_chan *echan) |
2b6b3b74 | 600 | { |
34cf3011 PU |
601 | struct edma_cc *ecc = echan->ecc; |
602 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
603 | int j = (channel >> 5); | |
604 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 605 | |
34cf3011 PU |
606 | edma_shadow0_write_array(ecc, SH_EECR, j, mask); |
607 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); | |
608 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
609 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
2b6b3b74 | 610 | |
34cf3011 PU |
611 | /* clear possibly pending completion interrupt */ |
612 | edma_shadow0_write_array(ecc, SH_ICR, j, mask); | |
2b6b3b74 | 613 | |
34cf3011 PU |
614 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
615 | edma_shadow0_read_array(ecc, SH_EER, j)); | |
2b6b3b74 | 616 | |
34cf3011 PU |
617 | /* REVISIT: consider guarding against inappropriate event |
618 | * chaining by overwriting with dummy_paramset. | |
619 | */ | |
2b6b3b74 PU |
620 | } |
621 | ||
11c15733 PU |
622 | /* |
623 | * Temporarily disable EDMA hardware events on the specified channel, | |
624 | * preventing them from triggering new transfers | |
2b6b3b74 | 625 | */ |
34cf3011 | 626 | static void edma_pause(struct edma_chan *echan) |
2b6b3b74 | 627 | { |
34cf3011 PU |
628 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
629 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 630 | |
34cf3011 | 631 | edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); |
2b6b3b74 PU |
632 | } |
633 | ||
11c15733 | 634 | /* Re-enable EDMA hardware events on the specified channel. */ |
34cf3011 | 635 | static void edma_resume(struct edma_chan *echan) |
2b6b3b74 | 636 | { |
34cf3011 PU |
637 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
638 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 639 | |
34cf3011 | 640 | edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); |
2b6b3b74 PU |
641 | } |
642 | ||
34cf3011 | 643 | static void edma_trigger_channel(struct edma_chan *echan) |
2b6b3b74 | 644 | { |
34cf3011 PU |
645 | struct edma_cc *ecc = echan->ecc; |
646 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
647 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 PU |
648 | |
649 | edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); | |
650 | ||
3287fb4d PU |
651 | dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), |
652 | edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); | |
2b6b3b74 PU |
653 | } |
654 | ||
34cf3011 | 655 | static void edma_clean_channel(struct edma_chan *echan) |
2b6b3b74 | 656 | { |
34cf3011 PU |
657 | struct edma_cc *ecc = echan->ecc; |
658 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
659 | int j = (channel >> 5); | |
660 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 661 | |
34cf3011 PU |
662 | dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); |
663 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); | |
664 | /* Clear the corresponding EMR bits */ | |
665 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
666 | /* Clear any SER */ | |
667 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
668 | edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); | |
2b6b3b74 PU |
669 | } |
670 | ||
f9425deb PU |
671 | /* Move channel to a specific event queue */ |
672 | static void edma_assign_channel_eventq(struct edma_chan *echan, | |
673 | enum dma_event_q eventq_no) | |
674 | { | |
675 | struct edma_cc *ecc = echan->ecc; | |
676 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
677 | int bit = (channel & 0x7) * 4; | |
678 | ||
679 | /* default to low priority queue */ | |
680 | if (eventq_no == EVENTQ_DEFAULT) | |
681 | eventq_no = ecc->default_queue; | |
682 | if (eventq_no >= ecc->num_tc) | |
683 | return; | |
684 | ||
685 | eventq_no &= 7; | |
686 | edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), | |
687 | eventq_no << bit); | |
688 | } | |
689 | ||
34cf3011 | 690 | static int edma_alloc_channel(struct edma_chan *echan, |
79ad2e38 | 691 | enum dma_event_q eventq_no) |
2b6b3b74 | 692 | { |
34cf3011 PU |
693 | struct edma_cc *ecc = echan->ecc; |
694 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
2b6b3b74 | 695 | |
2b6b3b74 PU |
696 | /* ensure access through shadow region 0 */ |
697 | edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); | |
698 | ||
699 | /* ensure no events are pending */ | |
34cf3011 | 700 | edma_stop(echan); |
2b6b3b74 | 701 | |
34cf3011 | 702 | edma_setup_interrupt(echan, true); |
2b6b3b74 | 703 | |
f9425deb | 704 | edma_assign_channel_eventq(echan, eventq_no); |
2b6b3b74 | 705 | |
34cf3011 | 706 | return 0; |
2b6b3b74 PU |
707 | } |
708 | ||
34cf3011 | 709 | static void edma_free_channel(struct edma_chan *echan) |
2b6b3b74 | 710 | { |
34cf3011 PU |
711 | /* ensure no events are pending */ |
712 | edma_stop(echan); | |
2b6b3b74 | 713 | /* REVISIT should probably take out of shadow region 0 */ |
34cf3011 | 714 | edma_setup_interrupt(echan, false); |
2b6b3b74 PU |
715 | } |
716 | ||
c2dde5f8 MP |
717 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) |
718 | { | |
719 | return container_of(d, struct edma_cc, dma_slave); | |
720 | } | |
721 | ||
722 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
723 | { | |
724 | return container_of(c, struct edma_chan, vchan.chan); | |
725 | } | |
726 | ||
2b6b3b74 | 727 | static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) |
c2dde5f8 MP |
728 | { |
729 | return container_of(tx, struct edma_desc, vdesc.tx); | |
730 | } | |
731 | ||
732 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
733 | { | |
734 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
735 | } | |
736 | ||
737 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
738 | static void edma_execute(struct edma_chan *echan) | |
739 | { | |
2b6b3b74 | 740 | struct edma_cc *ecc = echan->ecc; |
53407062 | 741 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 742 | struct edma_desc *edesc; |
53407062 JF |
743 | struct device *dev = echan->vchan.chan.device->dev; |
744 | int i, j, left, nslots; | |
745 | ||
8fa7ff4f PU |
746 | if (!echan->edesc) { |
747 | /* Setup is needed for the first transfer */ | |
53407062 | 748 | vdesc = vchan_next_desc(&echan->vchan); |
8fa7ff4f | 749 | if (!vdesc) |
53407062 | 750 | return; |
53407062 JF |
751 | list_del(&vdesc->node); |
752 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
753 | } |
754 | ||
53407062 | 755 | edesc = echan->edesc; |
c2dde5f8 | 756 | |
53407062 JF |
757 | /* Find out how many left */ |
758 | left = edesc->pset_nr - edesc->processed; | |
759 | nslots = min(MAX_NR_SG, left); | |
740b41f7 | 760 | edesc->sg_len = 0; |
c2dde5f8 MP |
761 | |
762 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
763 | for (i = 0; i < nslots; i++) { |
764 | j = i + edesc->processed; | |
2b6b3b74 | 765 | edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); |
740b41f7 | 766 | edesc->sg_len += edesc->pset[j].len; |
907f74a0 PU |
767 | dev_vdbg(dev, |
768 | "\n pset[%d]:\n" | |
769 | " chnum\t%d\n" | |
770 | " slot\t%d\n" | |
771 | " opt\t%08x\n" | |
772 | " src\t%08x\n" | |
773 | " dst\t%08x\n" | |
774 | " abcnt\t%08x\n" | |
775 | " ccnt\t%08x\n" | |
776 | " bidx\t%08x\n" | |
777 | " cidx\t%08x\n" | |
778 | " lkrld\t%08x\n", | |
779 | j, echan->ch_num, echan->slot[i], | |
780 | edesc->pset[j].param.opt, | |
781 | edesc->pset[j].param.src, | |
782 | edesc->pset[j].param.dst, | |
783 | edesc->pset[j].param.a_b_cnt, | |
784 | edesc->pset[j].param.ccnt, | |
785 | edesc->pset[j].param.src_dst_bidx, | |
786 | edesc->pset[j].param.src_dst_cidx, | |
787 | edesc->pset[j].param.link_bcntrld); | |
c2dde5f8 | 788 | /* Link to the previous slot if not the last set */ |
53407062 | 789 | if (i != (nslots - 1)) |
2b6b3b74 | 790 | edma_link(ecc, echan->slot[i], echan->slot[i + 1]); |
c2dde5f8 MP |
791 | } |
792 | ||
53407062 JF |
793 | edesc->processed += nslots; |
794 | ||
b267b3bc JF |
795 | /* |
796 | * If this is either the last set in a set of SG-list transactions | |
797 | * then setup a link to the dummy slot, this results in all future | |
798 | * events being absorbed and that's OK because we're done | |
799 | */ | |
50a9c707 JF |
800 | if (edesc->processed == edesc->pset_nr) { |
801 | if (edesc->cyclic) | |
2b6b3b74 | 802 | edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); |
50a9c707 | 803 | else |
2b6b3b74 | 804 | edma_link(ecc, echan->slot[nslots - 1], |
50a9c707 JF |
805 | echan->ecc->dummy_slot); |
806 | } | |
b267b3bc | 807 | |
c5f47990 | 808 | if (echan->missed) { |
8fa7ff4f PU |
809 | /* |
810 | * This happens due to setup times between intermediate | |
811 | * transfers in long SG lists which have to be broken up into | |
812 | * transfers of MAX_NR_SG | |
813 | */ | |
9aac9096 | 814 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
34cf3011 PU |
815 | edma_clean_channel(echan); |
816 | edma_stop(echan); | |
817 | edma_start(echan); | |
818 | edma_trigger_channel(echan); | |
c5f47990 | 819 | echan->missed = 0; |
8fa7ff4f PU |
820 | } else if (edesc->processed <= MAX_NR_SG) { |
821 | dev_dbg(dev, "first transfer starting on channel %d\n", | |
822 | echan->ch_num); | |
34cf3011 | 823 | edma_start(echan); |
8fa7ff4f PU |
824 | } else { |
825 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
826 | echan->ch_num, edesc->processed); | |
34cf3011 | 827 | edma_resume(echan); |
c5f47990 | 828 | } |
c2dde5f8 MP |
829 | } |
830 | ||
aa7c09b6 | 831 | static int edma_terminate_all(struct dma_chan *chan) |
c2dde5f8 | 832 | { |
aa7c09b6 | 833 | struct edma_chan *echan = to_edma_chan(chan); |
c2dde5f8 MP |
834 | unsigned long flags; |
835 | LIST_HEAD(head); | |
836 | ||
837 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
838 | ||
839 | /* | |
840 | * Stop DMA activity: we assume the callback will not be called | |
841 | * after edma_dma() returns (even if it does, it will see | |
842 | * echan->edesc is NULL and exit.) | |
843 | */ | |
844 | if (echan->edesc) { | |
34cf3011 | 845 | edma_stop(echan); |
8fa7ff4f | 846 | /* Move the cyclic channel back to default queue */ |
1be5336b | 847 | if (!echan->tc && echan->edesc->cyclic) |
34cf3011 | 848 | edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); |
5ca9e7ce PK |
849 | /* |
850 | * free the running request descriptor | |
851 | * since it is not in any of the vdesc lists | |
852 | */ | |
853 | edma_desc_free(&echan->edesc->vdesc); | |
c2dde5f8 | 854 | echan->edesc = NULL; |
c2dde5f8 MP |
855 | } |
856 | ||
857 | vchan_get_all_descriptors(&echan->vchan, &head); | |
858 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
859 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
aa7c09b6 | 864 | static int edma_slave_config(struct dma_chan *chan, |
661f7cb5 | 865 | struct dma_slave_config *cfg) |
c2dde5f8 | 866 | { |
aa7c09b6 MR |
867 | struct edma_chan *echan = to_edma_chan(chan); |
868 | ||
661f7cb5 MP |
869 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
870 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
871 | return -EINVAL; |
872 | ||
661f7cb5 | 873 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
aa7c09b6 | 878 | static int edma_dma_pause(struct dma_chan *chan) |
72c7b67a | 879 | { |
aa7c09b6 MR |
880 | struct edma_chan *echan = to_edma_chan(chan); |
881 | ||
02ec6041 | 882 | if (!echan->edesc) |
72c7b67a PU |
883 | return -EINVAL; |
884 | ||
34cf3011 | 885 | edma_pause(echan); |
72c7b67a PU |
886 | return 0; |
887 | } | |
888 | ||
aa7c09b6 | 889 | static int edma_dma_resume(struct dma_chan *chan) |
72c7b67a | 890 | { |
aa7c09b6 MR |
891 | struct edma_chan *echan = to_edma_chan(chan); |
892 | ||
34cf3011 | 893 | edma_resume(echan); |
72c7b67a PU |
894 | return 0; |
895 | } | |
896 | ||
fd009035 JF |
897 | /* |
898 | * A PaRAM set configuration abstraction used by other modes | |
899 | * @chan: Channel who's PaRAM set we're configuring | |
900 | * @pset: PaRAM set to initialize and setup. | |
901 | * @src_addr: Source address of the DMA | |
902 | * @dst_addr: Destination address of the DMA | |
903 | * @burst: In units of dev_width, how much to send | |
904 | * @dev_width: How much is the dev_width | |
905 | * @dma_length: Total length of the DMA transfer | |
906 | * @direction: Direction of the transfer | |
907 | */ | |
b5088ad9 | 908 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
2b6b3b74 | 909 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
df6694f8 | 910 | unsigned int acnt, unsigned int dma_length, |
2b6b3b74 | 911 | enum dma_transfer_direction direction) |
fd009035 JF |
912 | { |
913 | struct edma_chan *echan = to_edma_chan(chan); | |
914 | struct device *dev = chan->device->dev; | |
b5088ad9 | 915 | struct edmacc_param *param = &epset->param; |
df6694f8 | 916 | int bcnt, ccnt, cidx; |
fd009035 JF |
917 | int src_bidx, dst_bidx, src_cidx, dst_cidx; |
918 | int absync; | |
919 | ||
b2b617de PU |
920 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ |
921 | if (!burst) | |
922 | burst = 1; | |
fd009035 JF |
923 | /* |
924 | * If the maxburst is equal to the fifo width, use | |
925 | * A-synced transfers. This allows for large contiguous | |
926 | * buffer transfers using only one PaRAM set. | |
927 | */ | |
928 | if (burst == 1) { | |
929 | /* | |
930 | * For the A-sync case, bcnt and ccnt are the remainder | |
931 | * and quotient respectively of the division of: | |
932 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
933 | * that in case bcnt over flows, we have ccnt to use. | |
934 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
935 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
936 | * In this case, the best way adopted is- bccnt for the | |
937 | * first frame will be the remainder below. Then for | |
938 | * every successive frame, bcnt will be SZ_64K-1. This | |
939 | * is assured as bcntrld = 0xffff in end of function. | |
940 | */ | |
941 | absync = false; | |
942 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
943 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
944 | /* | |
945 | * If bcnt is non-zero, we have a remainder and hence an | |
946 | * extra frame to transfer, so increment ccnt. | |
947 | */ | |
948 | if (bcnt) | |
949 | ccnt++; | |
950 | else | |
951 | bcnt = SZ_64K - 1; | |
952 | cidx = acnt; | |
953 | } else { | |
954 | /* | |
955 | * If maxburst is greater than the fifo address_width, | |
956 | * use AB-synced transfers where A count is the fifo | |
957 | * address_width and B count is the maxburst. In this | |
958 | * case, we are limited to transfers of C count frames | |
959 | * of (address_width * maxburst) where C count is limited | |
960 | * to SZ_64K-1. This places an upper bound on the length | |
961 | * of an SG segment that can be handled. | |
962 | */ | |
963 | absync = true; | |
964 | bcnt = burst; | |
965 | ccnt = dma_length / (acnt * bcnt); | |
966 | if (ccnt > (SZ_64K - 1)) { | |
967 | dev_err(dev, "Exceeded max SG segment size\n"); | |
968 | return -EINVAL; | |
969 | } | |
970 | cidx = acnt * bcnt; | |
971 | } | |
972 | ||
c2da2340 TG |
973 | epset->len = dma_length; |
974 | ||
fd009035 JF |
975 | if (direction == DMA_MEM_TO_DEV) { |
976 | src_bidx = acnt; | |
977 | src_cidx = cidx; | |
978 | dst_bidx = 0; | |
979 | dst_cidx = 0; | |
c2da2340 | 980 | epset->addr = src_addr; |
fd009035 JF |
981 | } else if (direction == DMA_DEV_TO_MEM) { |
982 | src_bidx = 0; | |
983 | src_cidx = 0; | |
984 | dst_bidx = acnt; | |
985 | dst_cidx = cidx; | |
c2da2340 | 986 | epset->addr = dst_addr; |
8cc3e30b JF |
987 | } else if (direction == DMA_MEM_TO_MEM) { |
988 | src_bidx = acnt; | |
989 | src_cidx = cidx; | |
990 | dst_bidx = acnt; | |
991 | dst_cidx = cidx; | |
fd009035 JF |
992 | } else { |
993 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
994 | return -EINVAL; | |
995 | } | |
996 | ||
b5088ad9 | 997 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
fd009035 JF |
998 | /* Configure A or AB synchronized transfers */ |
999 | if (absync) | |
b5088ad9 | 1000 | param->opt |= SYNCDIM; |
fd009035 | 1001 | |
b5088ad9 TG |
1002 | param->src = src_addr; |
1003 | param->dst = dst_addr; | |
fd009035 | 1004 | |
b5088ad9 TG |
1005 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
1006 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
fd009035 | 1007 | |
b5088ad9 TG |
1008 | param->a_b_cnt = bcnt << 16 | acnt; |
1009 | param->ccnt = ccnt; | |
fd009035 JF |
1010 | /* |
1011 | * Only time when (bcntrld) auto reload is required is for | |
1012 | * A-sync case, and in this case, a requirement of reload value | |
1013 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
1014 | * and then later will be populated by edma_execute. | |
1015 | */ | |
b5088ad9 | 1016 | param->link_bcntrld = 0xffffffff; |
fd009035 JF |
1017 | return absync; |
1018 | } | |
1019 | ||
c2dde5f8 MP |
1020 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
1021 | struct dma_chan *chan, struct scatterlist *sgl, | |
1022 | unsigned int sg_len, enum dma_transfer_direction direction, | |
1023 | unsigned long tx_flags, void *context) | |
1024 | { | |
1025 | struct edma_chan *echan = to_edma_chan(chan); | |
1026 | struct device *dev = chan->device->dev; | |
1027 | struct edma_desc *edesc; | |
fd009035 | 1028 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
1029 | enum dma_slave_buswidth dev_width; |
1030 | u32 burst; | |
c2dde5f8 | 1031 | struct scatterlist *sg; |
fd009035 | 1032 | int i, nslots, ret; |
c2dde5f8 MP |
1033 | |
1034 | if (unlikely(!echan || !sgl || !sg_len)) | |
1035 | return NULL; | |
1036 | ||
661f7cb5 | 1037 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 1038 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
1039 | dev_width = echan->cfg.src_addr_width; |
1040 | burst = echan->cfg.src_maxburst; | |
1041 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 1042 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
1043 | dev_width = echan->cfg.dst_addr_width; |
1044 | burst = echan->cfg.dst_maxburst; | |
1045 | } else { | |
e6fad592 | 1046 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
661f7cb5 MP |
1047 | return NULL; |
1048 | } | |
1049 | ||
1050 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 1051 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
1052 | return NULL; |
1053 | } | |
1054 | ||
2b6b3b74 PU |
1055 | edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]), |
1056 | GFP_ATOMIC); | |
c2dde5f8 | 1057 | if (!edesc) { |
c594c891 | 1058 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
c2dde5f8 MP |
1059 | return NULL; |
1060 | } | |
1061 | ||
1062 | edesc->pset_nr = sg_len; | |
b6205c39 | 1063 | edesc->residue = 0; |
c2da2340 | 1064 | edesc->direction = direction; |
740b41f7 | 1065 | edesc->echan = echan; |
c2dde5f8 | 1066 | |
6fbe24da JF |
1067 | /* Allocate a PaRAM slot, if needed */ |
1068 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
1069 | ||
1070 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
1071 | if (echan->slot[i] < 0) { |
1072 | echan->slot[i] = | |
2b6b3b74 | 1073 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
c2dde5f8 | 1074 | if (echan->slot[i] < 0) { |
4b6271a6 | 1075 | kfree(edesc); |
c594c891 PU |
1076 | dev_err(dev, "%s: Failed to allocate slot\n", |
1077 | __func__); | |
c2dde5f8 MP |
1078 | return NULL; |
1079 | } | |
1080 | } | |
6fbe24da JF |
1081 | } |
1082 | ||
1083 | /* Configure PaRAM sets for each SG */ | |
1084 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
1085 | /* Get address for each SG */ |
1086 | if (direction == DMA_DEV_TO_MEM) | |
1087 | dst_addr = sg_dma_address(sg); | |
1088 | else | |
1089 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 1090 | |
fd009035 JF |
1091 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
1092 | dst_addr, burst, dev_width, | |
1093 | sg_dma_len(sg), direction); | |
b967aecf VK |
1094 | if (ret < 0) { |
1095 | kfree(edesc); | |
fd009035 | 1096 | return NULL; |
c2dde5f8 MP |
1097 | } |
1098 | ||
fd009035 | 1099 | edesc->absync = ret; |
b6205c39 | 1100 | edesc->residue += sg_dma_len(sg); |
6fbe24da JF |
1101 | |
1102 | /* If this is the last in a current SG set of transactions, | |
1103 | enable interrupts so that next set is processed */ | |
1104 | if (!((i+1) % MAX_NR_SG)) | |
b5088ad9 | 1105 | edesc->pset[i].param.opt |= TCINTEN; |
6fbe24da | 1106 | |
c2dde5f8 MP |
1107 | /* If this is the last set, enable completion interrupt flag */ |
1108 | if (i == sg_len - 1) | |
b5088ad9 | 1109 | edesc->pset[i].param.opt |= TCINTEN; |
c2dde5f8 | 1110 | } |
740b41f7 | 1111 | edesc->residue_stat = edesc->residue; |
c2dde5f8 | 1112 | |
c2dde5f8 MP |
1113 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
1114 | } | |
c2dde5f8 | 1115 | |
b7a4fd53 | 1116 | static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
8cc3e30b JF |
1117 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
1118 | size_t len, unsigned long tx_flags) | |
1119 | { | |
df6694f8 | 1120 | int ret, nslots; |
8cc3e30b JF |
1121 | struct edma_desc *edesc; |
1122 | struct device *dev = chan->device->dev; | |
1123 | struct edma_chan *echan = to_edma_chan(chan); | |
df6694f8 | 1124 | unsigned int width, pset_len; |
8cc3e30b JF |
1125 | |
1126 | if (unlikely(!echan || !len)) | |
1127 | return NULL; | |
1128 | ||
df6694f8 PU |
1129 | if (len < SZ_64K) { |
1130 | /* | |
1131 | * Transfer size less than 64K can be handled with one paRAM | |
1132 | * slot and with one burst. | |
1133 | * ACNT = length | |
1134 | */ | |
1135 | width = len; | |
1136 | pset_len = len; | |
1137 | nslots = 1; | |
1138 | } else { | |
1139 | /* | |
1140 | * Transfer size bigger than 64K will be handled with maximum of | |
1141 | * two paRAM slots. | |
1142 | * slot1: (full_length / 32767) times 32767 bytes bursts. | |
1143 | * ACNT = 32767, length1: (full_length / 32767) * 32767 | |
1144 | * slot2: the remaining amount of data after slot1. | |
1145 | * ACNT = full_length - length1, length2 = ACNT | |
1146 | * | |
1147 | * When the full_length is multibple of 32767 one slot can be | |
1148 | * used to complete the transfer. | |
1149 | */ | |
1150 | width = SZ_32K - 1; | |
1151 | pset_len = rounddown(len, width); | |
1152 | /* One slot is enough for lengths multiple of (SZ_32K -1) */ | |
1153 | if (unlikely(pset_len == len)) | |
1154 | nslots = 1; | |
1155 | else | |
1156 | nslots = 2; | |
1157 | } | |
1158 | ||
1159 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), | |
1160 | GFP_ATOMIC); | |
8cc3e30b JF |
1161 | if (!edesc) { |
1162 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
1163 | return NULL; | |
1164 | } | |
1165 | ||
df6694f8 PU |
1166 | edesc->pset_nr = nslots; |
1167 | edesc->residue = edesc->residue_stat = len; | |
1168 | edesc->direction = DMA_MEM_TO_MEM; | |
1169 | edesc->echan = echan; | |
21a31846 | 1170 | |
8cc3e30b | 1171 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, |
df6694f8 PU |
1172 | width, pset_len, DMA_MEM_TO_MEM); |
1173 | if (ret < 0) { | |
1174 | kfree(edesc); | |
8cc3e30b | 1175 | return NULL; |
df6694f8 | 1176 | } |
8cc3e30b JF |
1177 | |
1178 | edesc->absync = ret; | |
1179 | ||
b0cce4ca | 1180 | edesc->pset[0].param.opt |= ITCCHEN; |
df6694f8 PU |
1181 | if (nslots == 1) { |
1182 | /* Enable transfer complete interrupt */ | |
1183 | edesc->pset[0].param.opt |= TCINTEN; | |
1184 | } else { | |
1185 | /* Enable transfer complete chaining for the first slot */ | |
1186 | edesc->pset[0].param.opt |= TCCHEN; | |
1187 | ||
1188 | if (echan->slot[1] < 0) { | |
1189 | echan->slot[1] = edma_alloc_slot(echan->ecc, | |
1190 | EDMA_SLOT_ANY); | |
1191 | if (echan->slot[1] < 0) { | |
1192 | kfree(edesc); | |
1193 | dev_err(dev, "%s: Failed to allocate slot\n", | |
1194 | __func__); | |
1195 | return NULL; | |
1196 | } | |
1197 | } | |
1198 | dest += pset_len; | |
1199 | src += pset_len; | |
1200 | pset_len = width = len % (SZ_32K - 1); | |
1201 | ||
1202 | ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, | |
1203 | width, pset_len, DMA_MEM_TO_MEM); | |
1204 | if (ret < 0) { | |
1205 | kfree(edesc); | |
1206 | return NULL; | |
1207 | } | |
1208 | ||
1209 | edesc->pset[1].param.opt |= ITCCHEN; | |
1210 | edesc->pset[1].param.opt |= TCINTEN; | |
1211 | } | |
8cc3e30b JF |
1212 | |
1213 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
1214 | } | |
1215 | ||
50a9c707 JF |
1216 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
1217 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
1218 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 1219 | unsigned long tx_flags) |
50a9c707 JF |
1220 | { |
1221 | struct edma_chan *echan = to_edma_chan(chan); | |
1222 | struct device *dev = chan->device->dev; | |
1223 | struct edma_desc *edesc; | |
1224 | dma_addr_t src_addr, dst_addr; | |
1225 | enum dma_slave_buswidth dev_width; | |
1226 | u32 burst; | |
1227 | int i, ret, nslots; | |
1228 | ||
1229 | if (unlikely(!echan || !buf_len || !period_len)) | |
1230 | return NULL; | |
1231 | ||
1232 | if (direction == DMA_DEV_TO_MEM) { | |
1233 | src_addr = echan->cfg.src_addr; | |
1234 | dst_addr = buf_addr; | |
1235 | dev_width = echan->cfg.src_addr_width; | |
1236 | burst = echan->cfg.src_maxburst; | |
1237 | } else if (direction == DMA_MEM_TO_DEV) { | |
1238 | src_addr = buf_addr; | |
1239 | dst_addr = echan->cfg.dst_addr; | |
1240 | dev_width = echan->cfg.dst_addr_width; | |
1241 | burst = echan->cfg.dst_maxburst; | |
1242 | } else { | |
e6fad592 | 1243 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
50a9c707 JF |
1244 | return NULL; |
1245 | } | |
1246 | ||
1247 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 1248 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
1249 | return NULL; |
1250 | } | |
1251 | ||
1252 | if (unlikely(buf_len % period_len)) { | |
1253 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
1254 | return NULL; | |
1255 | } | |
1256 | ||
1257 | nslots = (buf_len / period_len) + 1; | |
1258 | ||
1259 | /* | |
1260 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
1261 | * by cases where the number of periods is more than the maximum | |
1262 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
1263 | * such as Slave SGs, such delays are tolerable and synchronized, | |
1264 | * but the synchronization is difficult to achieve with Cyclic and | |
1265 | * cannot be guaranteed, so we error out early. | |
1266 | */ | |
1267 | if (nslots > MAX_NR_SG) | |
1268 | return NULL; | |
1269 | ||
2b6b3b74 PU |
1270 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), |
1271 | GFP_ATOMIC); | |
50a9c707 | 1272 | if (!edesc) { |
c594c891 | 1273 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
50a9c707 JF |
1274 | return NULL; |
1275 | } | |
1276 | ||
1277 | edesc->cyclic = 1; | |
1278 | edesc->pset_nr = nslots; | |
740b41f7 | 1279 | edesc->residue = edesc->residue_stat = buf_len; |
c2da2340 | 1280 | edesc->direction = direction; |
740b41f7 | 1281 | edesc->echan = echan; |
50a9c707 | 1282 | |
83bb3126 PU |
1283 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
1284 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
1285 | |
1286 | for (i = 0; i < nslots; i++) { | |
1287 | /* Allocate a PaRAM slot, if needed */ | |
1288 | if (echan->slot[i] < 0) { | |
1289 | echan->slot[i] = | |
2b6b3b74 | 1290 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
50a9c707 | 1291 | if (echan->slot[i] < 0) { |
e3ddc979 | 1292 | kfree(edesc); |
c594c891 PU |
1293 | dev_err(dev, "%s: Failed to allocate slot\n", |
1294 | __func__); | |
50a9c707 JF |
1295 | return NULL; |
1296 | } | |
1297 | } | |
1298 | ||
1299 | if (i == nslots - 1) { | |
1300 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
1301 | sizeof(edesc->pset[0])); | |
1302 | break; | |
1303 | } | |
1304 | ||
1305 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
1306 | dst_addr, burst, dev_width, period_len, | |
1307 | direction); | |
e3ddc979 CE |
1308 | if (ret < 0) { |
1309 | kfree(edesc); | |
50a9c707 | 1310 | return NULL; |
e3ddc979 | 1311 | } |
c2dde5f8 | 1312 | |
50a9c707 JF |
1313 | if (direction == DMA_DEV_TO_MEM) |
1314 | dst_addr += period_len; | |
1315 | else | |
1316 | src_addr += period_len; | |
c2dde5f8 | 1317 | |
83bb3126 PU |
1318 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
1319 | dev_vdbg(dev, | |
50a9c707 JF |
1320 | "\n pset[%d]:\n" |
1321 | " chnum\t%d\n" | |
1322 | " slot\t%d\n" | |
1323 | " opt\t%08x\n" | |
1324 | " src\t%08x\n" | |
1325 | " dst\t%08x\n" | |
1326 | " abcnt\t%08x\n" | |
1327 | " ccnt\t%08x\n" | |
1328 | " bidx\t%08x\n" | |
1329 | " cidx\t%08x\n" | |
1330 | " lkrld\t%08x\n", | |
1331 | i, echan->ch_num, echan->slot[i], | |
b5088ad9 TG |
1332 | edesc->pset[i].param.opt, |
1333 | edesc->pset[i].param.src, | |
1334 | edesc->pset[i].param.dst, | |
1335 | edesc->pset[i].param.a_b_cnt, | |
1336 | edesc->pset[i].param.ccnt, | |
1337 | edesc->pset[i].param.src_dst_bidx, | |
1338 | edesc->pset[i].param.src_dst_cidx, | |
1339 | edesc->pset[i].param.link_bcntrld); | |
50a9c707 JF |
1340 | |
1341 | edesc->absync = ret; | |
1342 | ||
1343 | /* | |
a1f146f3 | 1344 | * Enable period interrupt only if it is requested |
50a9c707 | 1345 | */ |
a1f146f3 PU |
1346 | if (tx_flags & DMA_PREP_INTERRUPT) |
1347 | edesc->pset[i].param.opt |= TCINTEN; | |
c2dde5f8 MP |
1348 | } |
1349 | ||
8e8805d5 | 1350 | /* Place the cyclic channel to highest priority queue */ |
1be5336b PU |
1351 | if (!echan->tc) |
1352 | edma_assign_channel_eventq(echan, EVENTQ_0); | |
8e8805d5 | 1353 | |
c2dde5f8 MP |
1354 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
1355 | } | |
1356 | ||
79ad2e38 | 1357 | static void edma_completion_handler(struct edma_chan *echan) |
c2dde5f8 | 1358 | { |
c2dde5f8 | 1359 | struct device *dev = echan->vchan.chan.device->dev; |
79ad2e38 | 1360 | struct edma_desc *edesc = echan->edesc; |
c2dde5f8 | 1361 | |
79ad2e38 PU |
1362 | if (!edesc) |
1363 | return; | |
50a9c707 | 1364 | |
8fa7ff4f | 1365 | spin_lock(&echan->vchan.lock); |
79ad2e38 PU |
1366 | if (edesc->cyclic) { |
1367 | vchan_cyclic_callback(&edesc->vdesc); | |
1368 | spin_unlock(&echan->vchan.lock); | |
1369 | return; | |
1370 | } else if (edesc->processed == edesc->pset_nr) { | |
1371 | edesc->residue = 0; | |
34cf3011 | 1372 | edma_stop(echan); |
79ad2e38 PU |
1373 | vchan_cookie_complete(&edesc->vdesc); |
1374 | echan->edesc = NULL; | |
1375 | ||
1376 | dev_dbg(dev, "Transfer completed on channel %d\n", | |
1377 | echan->ch_num); | |
1378 | } else { | |
1379 | dev_dbg(dev, "Sub transfer completed on channel %d\n", | |
1380 | echan->ch_num); | |
1381 | ||
34cf3011 | 1382 | edma_pause(echan); |
79ad2e38 PU |
1383 | |
1384 | /* Update statistics for tx_status */ | |
1385 | edesc->residue -= edesc->sg_len; | |
1386 | edesc->residue_stat = edesc->residue; | |
1387 | edesc->processed_stat = edesc->processed; | |
1388 | } | |
1389 | edma_execute(echan); | |
1390 | ||
1391 | spin_unlock(&echan->vchan.lock); | |
1392 | } | |
1393 | ||
1394 | /* eDMA interrupt handler */ | |
1395 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
1396 | { | |
1397 | struct edma_cc *ecc = data; | |
1398 | int ctlr; | |
1399 | u32 sh_ier; | |
1400 | u32 sh_ipr; | |
1401 | u32 bank; | |
1402 | ||
1403 | ctlr = ecc->id; | |
1404 | if (ctlr < 0) | |
1405 | return IRQ_NONE; | |
1406 | ||
1407 | dev_vdbg(ecc->dev, "dma_irq_handler\n"); | |
1408 | ||
1409 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); | |
1410 | if (!sh_ipr) { | |
1411 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); | |
1412 | if (!sh_ipr) | |
1413 | return IRQ_NONE; | |
1414 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); | |
1415 | bank = 1; | |
1416 | } else { | |
1417 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); | |
1418 | bank = 0; | |
1419 | } | |
1420 | ||
1421 | do { | |
1422 | u32 slot; | |
1423 | u32 channel; | |
1424 | ||
1425 | slot = __ffs(sh_ipr); | |
1426 | sh_ipr &= ~(BIT(slot)); | |
1427 | ||
1428 | if (sh_ier & BIT(slot)) { | |
1429 | channel = (bank << 5) | slot; | |
1430 | /* Clear the corresponding IPR bits */ | |
1431 | edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); | |
1432 | edma_completion_handler(&ecc->slave_chans[channel]); | |
c2dde5f8 | 1433 | } |
79ad2e38 PU |
1434 | } while (sh_ipr); |
1435 | ||
1436 | edma_shadow0_write(ecc, SH_IEVAL, 1); | |
1437 | return IRQ_HANDLED; | |
1438 | } | |
1439 | ||
1440 | static void edma_error_handler(struct edma_chan *echan) | |
1441 | { | |
1442 | struct edma_cc *ecc = echan->ecc; | |
1443 | struct device *dev = echan->vchan.chan.device->dev; | |
1444 | struct edmacc_param p; | |
1445 | ||
1446 | if (!echan->edesc) | |
1447 | return; | |
1448 | ||
1449 | spin_lock(&echan->vchan.lock); | |
c5f47990 | 1450 | |
79ad2e38 PU |
1451 | edma_read_slot(ecc, echan->slot[0], &p); |
1452 | /* | |
1453 | * Issue later based on missed flag which will be sure | |
1454 | * to happen as: | |
1455 | * (1) we finished transmitting an intermediate slot and | |
1456 | * edma_execute is coming up. | |
1457 | * (2) or we finished current transfer and issue will | |
1458 | * call edma_execute. | |
1459 | * | |
1460 | * Important note: issuing can be dangerous here and | |
1461 | * lead to some nasty recursion when we are in a NULL | |
1462 | * slot. So we avoid doing so and set the missed flag. | |
1463 | */ | |
1464 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
1465 | dev_dbg(dev, "Error on null slot, setting miss\n"); | |
1466 | echan->missed = 1; | |
1467 | } else { | |
c5f47990 | 1468 | /* |
79ad2e38 PU |
1469 | * The slot is already programmed but the event got |
1470 | * missed, so its safe to issue it here. | |
c5f47990 | 1471 | */ |
79ad2e38 | 1472 | dev_dbg(dev, "Missed event, TRIGGERING\n"); |
34cf3011 PU |
1473 | edma_clean_channel(echan); |
1474 | edma_stop(echan); | |
1475 | edma_start(echan); | |
1476 | edma_trigger_channel(echan); | |
79ad2e38 PU |
1477 | } |
1478 | spin_unlock(&echan->vchan.lock); | |
1479 | } | |
1480 | ||
7c3b8b3d PU |
1481 | static inline bool edma_error_pending(struct edma_cc *ecc) |
1482 | { | |
1483 | if (edma_read_array(ecc, EDMA_EMR, 0) || | |
1484 | edma_read_array(ecc, EDMA_EMR, 1) || | |
1485 | edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) | |
1486 | return true; | |
1487 | ||
1488 | return false; | |
1489 | } | |
1490 | ||
79ad2e38 PU |
1491 | /* eDMA error interrupt handler */ |
1492 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
1493 | { | |
1494 | struct edma_cc *ecc = data; | |
e4402a12 | 1495 | int i, j; |
79ad2e38 PU |
1496 | int ctlr; |
1497 | unsigned int cnt = 0; | |
e4402a12 | 1498 | unsigned int val; |
79ad2e38 PU |
1499 | |
1500 | ctlr = ecc->id; | |
1501 | if (ctlr < 0) | |
1502 | return IRQ_NONE; | |
1503 | ||
1504 | dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); | |
1505 | ||
7c3b8b3d | 1506 | if (!edma_error_pending(ecc)) |
79ad2e38 PU |
1507 | return IRQ_NONE; |
1508 | ||
1509 | while (1) { | |
e4402a12 PU |
1510 | /* Event missed register(s) */ |
1511 | for (j = 0; j < 2; j++) { | |
1512 | unsigned long emr; | |
1513 | ||
1514 | val = edma_read_array(ecc, EDMA_EMR, j); | |
1515 | if (!val) | |
1516 | continue; | |
1517 | ||
1518 | dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); | |
1519 | emr = val; | |
1520 | for (i = find_next_bit(&emr, 32, 0); i < 32; | |
1521 | i = find_next_bit(&emr, 32, i + 1)) { | |
79ad2e38 PU |
1522 | int k = (j << 5) + i; |
1523 | ||
e4402a12 PU |
1524 | /* Clear the corresponding EMR bits */ |
1525 | edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); | |
1526 | /* Clear any SER */ | |
1527 | edma_shadow0_write_array(ecc, SH_SECR, j, | |
79ad2e38 | 1528 | BIT(i)); |
e4402a12 | 1529 | edma_error_handler(&ecc->slave_chans[k]); |
79ad2e38 | 1530 | } |
c5f47990 | 1531 | } |
e4402a12 PU |
1532 | |
1533 | val = edma_read(ecc, EDMA_QEMR); | |
1534 | if (val) { | |
1535 | dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); | |
1536 | /* Not reported, just clear the interrupt reason. */ | |
1537 | edma_write(ecc, EDMA_QEMCR, val); | |
1538 | edma_shadow0_write(ecc, SH_QSECR, val); | |
1539 | } | |
1540 | ||
1541 | val = edma_read(ecc, EDMA_CCERR); | |
1542 | if (val) { | |
1543 | dev_warn(ecc->dev, "CCERR 0x%08x\n", val); | |
1544 | /* Not reported, just clear the interrupt reason. */ | |
1545 | edma_write(ecc, EDMA_CCERRCLR, val); | |
1546 | } | |
1547 | ||
7c3b8b3d | 1548 | if (!edma_error_pending(ecc)) |
79ad2e38 PU |
1549 | break; |
1550 | cnt++; | |
1551 | if (cnt > 10) | |
1552 | break; | |
c2dde5f8 | 1553 | } |
79ad2e38 PU |
1554 | edma_write(ecc, EDMA_EEVAL, 1); |
1555 | return IRQ_HANDLED; | |
c2dde5f8 MP |
1556 | } |
1557 | ||
1be5336b PU |
1558 | static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable) |
1559 | { | |
1560 | struct platform_device *tc_pdev; | |
1561 | int ret; | |
1562 | ||
1563 | if (!tc) | |
1564 | return; | |
1565 | ||
1566 | tc_pdev = of_find_device_by_node(tc->node); | |
1567 | if (!tc_pdev) { | |
1568 | pr_err("%s: TPTC device is not found\n", __func__); | |
1569 | return; | |
1570 | } | |
1571 | if (!pm_runtime_enabled(&tc_pdev->dev)) | |
1572 | pm_runtime_enable(&tc_pdev->dev); | |
1573 | ||
1574 | if (enable) | |
1575 | ret = pm_runtime_get_sync(&tc_pdev->dev); | |
1576 | else | |
1577 | ret = pm_runtime_put_sync(&tc_pdev->dev); | |
1578 | ||
1579 | if (ret < 0) | |
1580 | pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__, | |
1581 | enable ? "get" : "put", dev_name(&tc_pdev->dev)); | |
1582 | } | |
1583 | ||
c2dde5f8 MP |
1584 | /* Alloc channel resources */ |
1585 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
1586 | { | |
1587 | struct edma_chan *echan = to_edma_chan(chan); | |
1be5336b PU |
1588 | struct edma_cc *ecc = echan->ecc; |
1589 | struct device *dev = ecc->dev; | |
1590 | enum dma_event_q eventq_no = EVENTQ_DEFAULT; | |
c2dde5f8 | 1591 | int ret; |
c2dde5f8 | 1592 | |
1be5336b PU |
1593 | if (echan->tc) { |
1594 | eventq_no = echan->tc->id; | |
1595 | } else if (ecc->tc_list) { | |
1596 | /* memcpy channel */ | |
1597 | echan->tc = &ecc->tc_list[ecc->info->default_queue]; | |
1598 | eventq_no = echan->tc->id; | |
1599 | } | |
1600 | ||
1601 | ret = edma_alloc_channel(echan, eventq_no); | |
34cf3011 PU |
1602 | if (ret) |
1603 | return ret; | |
c2dde5f8 | 1604 | |
1be5336b | 1605 | echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); |
e4e886c6 PU |
1606 | if (echan->slot[0] < 0) { |
1607 | dev_err(dev, "Entry slot allocation failed for channel %u\n", | |
1608 | EDMA_CHAN_SLOT(echan->ch_num)); | |
34cf3011 | 1609 | goto err_slot; |
e4e886c6 PU |
1610 | } |
1611 | ||
1612 | /* Set up channel -> slot mapping for the entry slot */ | |
34cf3011 PU |
1613 | edma_set_chmap(echan, echan->slot[0]); |
1614 | echan->alloced = true; | |
c2dde5f8 | 1615 | |
1be5336b PU |
1616 | dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", |
1617 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, | |
1618 | echan->hw_triggered ? "HW" : "SW"); | |
1619 | ||
1620 | edma_tc_set_pm_state(echan->tc, true); | |
c2dde5f8 MP |
1621 | |
1622 | return 0; | |
1623 | ||
34cf3011 PU |
1624 | err_slot: |
1625 | edma_free_channel(echan); | |
c2dde5f8 MP |
1626 | return ret; |
1627 | } | |
1628 | ||
1629 | /* Free channel resources */ | |
1630 | static void edma_free_chan_resources(struct dma_chan *chan) | |
1631 | { | |
1632 | struct edma_chan *echan = to_edma_chan(chan); | |
1be5336b | 1633 | struct device *dev = echan->ecc->dev; |
c2dde5f8 MP |
1634 | int i; |
1635 | ||
1636 | /* Terminate transfers */ | |
34cf3011 | 1637 | edma_stop(echan); |
c2dde5f8 MP |
1638 | |
1639 | vchan_free_chan_resources(&echan->vchan); | |
1640 | ||
1641 | /* Free EDMA PaRAM slots */ | |
e4e886c6 | 1642 | for (i = 0; i < EDMA_MAX_SLOTS; i++) { |
c2dde5f8 | 1643 | if (echan->slot[i] >= 0) { |
2b6b3b74 | 1644 | edma_free_slot(echan->ecc, echan->slot[i]); |
c2dde5f8 MP |
1645 | echan->slot[i] = -1; |
1646 | } | |
1647 | } | |
1648 | ||
e4e886c6 | 1649 | /* Set entry slot to the dummy slot */ |
34cf3011 | 1650 | edma_set_chmap(echan, echan->ecc->dummy_slot); |
e4e886c6 | 1651 | |
c2dde5f8 MP |
1652 | /* Free EDMA channel */ |
1653 | if (echan->alloced) { | |
34cf3011 | 1654 | edma_free_channel(echan); |
c2dde5f8 MP |
1655 | echan->alloced = false; |
1656 | } | |
1657 | ||
1be5336b PU |
1658 | edma_tc_set_pm_state(echan->tc, false); |
1659 | echan->tc = NULL; | |
1660 | echan->hw_triggered = false; | |
1661 | ||
1662 | dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", | |
1663 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); | |
c2dde5f8 MP |
1664 | } |
1665 | ||
1666 | /* Send pending descriptor to hardware */ | |
1667 | static void edma_issue_pending(struct dma_chan *chan) | |
1668 | { | |
1669 | struct edma_chan *echan = to_edma_chan(chan); | |
1670 | unsigned long flags; | |
1671 | ||
1672 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
1673 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
1674 | edma_execute(echan); | |
1675 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
1676 | } | |
1677 | ||
740b41f7 TG |
1678 | static u32 edma_residue(struct edma_desc *edesc) |
1679 | { | |
1680 | bool dst = edesc->direction == DMA_DEV_TO_MEM; | |
1681 | struct edma_pset *pset = edesc->pset; | |
1682 | dma_addr_t done, pos; | |
1683 | int i; | |
1684 | ||
1685 | /* | |
1686 | * We always read the dst/src position from the first RamPar | |
1687 | * pset. That's the one which is active now. | |
1688 | */ | |
2b6b3b74 | 1689 | pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); |
740b41f7 TG |
1690 | |
1691 | /* | |
1692 | * Cyclic is simple. Just subtract pset[0].addr from pos. | |
1693 | * | |
1694 | * We never update edesc->residue in the cyclic case, so we | |
1695 | * can tell the remaining room to the end of the circular | |
1696 | * buffer. | |
1697 | */ | |
1698 | if (edesc->cyclic) { | |
1699 | done = pos - pset->addr; | |
1700 | edesc->residue_stat = edesc->residue - done; | |
1701 | return edesc->residue_stat; | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * For SG operation we catch up with the last processed | |
1706 | * status. | |
1707 | */ | |
1708 | pset += edesc->processed_stat; | |
1709 | ||
1710 | for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { | |
1711 | /* | |
1712 | * If we are inside this pset address range, we know | |
1713 | * this is the active one. Get the current delta and | |
1714 | * stop walking the psets. | |
1715 | */ | |
1716 | if (pos >= pset->addr && pos < pset->addr + pset->len) | |
1717 | return edesc->residue_stat - (pos - pset->addr); | |
1718 | ||
1719 | /* Otherwise mark it done and update residue_stat. */ | |
1720 | edesc->processed_stat++; | |
1721 | edesc->residue_stat -= pset->len; | |
1722 | } | |
1723 | return edesc->residue_stat; | |
1724 | } | |
1725 | ||
c2dde5f8 MP |
1726 | /* Check request completion status */ |
1727 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
1728 | dma_cookie_t cookie, | |
1729 | struct dma_tx_state *txstate) | |
1730 | { | |
1731 | struct edma_chan *echan = to_edma_chan(chan); | |
1732 | struct virt_dma_desc *vdesc; | |
1733 | enum dma_status ret; | |
1734 | unsigned long flags; | |
1735 | ||
1736 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 1737 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
1738 | return ret; |
1739 | ||
1740 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
de135939 | 1741 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
740b41f7 | 1742 | txstate->residue = edma_residue(echan->edesc); |
de135939 TG |
1743 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
1744 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; | |
c2dde5f8 MP |
1745 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
1746 | ||
1747 | return ret; | |
1748 | } | |
1749 | ||
1be5336b PU |
1750 | static bool edma_is_memcpy_channel(int ch_num, u16 *memcpy_channels) |
1751 | { | |
1752 | s16 *memcpy_ch = memcpy_channels; | |
1753 | ||
1754 | if (!memcpy_channels) | |
1755 | return false; | |
1756 | while (*memcpy_ch != -1) { | |
1757 | if (*memcpy_ch == ch_num) | |
1758 | return true; | |
1759 | memcpy_ch++; | |
1760 | } | |
1761 | return false; | |
1762 | } | |
1763 | ||
02f77ef1 PU |
1764 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
1765 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
1766 | BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ | |
1767 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
1768 | ||
1be5336b | 1769 | static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) |
c2dde5f8 | 1770 | { |
1be5336b PU |
1771 | struct dma_device *s_ddev = &ecc->dma_slave; |
1772 | struct dma_device *m_ddev = NULL; | |
1773 | s16 *memcpy_channels = ecc->info->memcpy_channels; | |
c2dde5f8 MP |
1774 | int i, j; |
1775 | ||
1be5336b PU |
1776 | dma_cap_zero(s_ddev->cap_mask); |
1777 | dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); | |
1778 | dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); | |
1779 | if (ecc->legacy_mode && !memcpy_channels) { | |
1780 | dev_warn(ecc->dev, | |
1781 | "Legacy memcpy is enabled, things might not work\n"); | |
02f77ef1 | 1782 | |
1be5336b PU |
1783 | dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); |
1784 | s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; | |
1785 | s_ddev->directions = BIT(DMA_MEM_TO_MEM); | |
1786 | } | |
02f77ef1 | 1787 | |
1be5336b PU |
1788 | s_ddev->device_prep_slave_sg = edma_prep_slave_sg; |
1789 | s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; | |
1790 | s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; | |
1791 | s_ddev->device_free_chan_resources = edma_free_chan_resources; | |
1792 | s_ddev->device_issue_pending = edma_issue_pending; | |
1793 | s_ddev->device_tx_status = edma_tx_status; | |
1794 | s_ddev->device_config = edma_slave_config; | |
1795 | s_ddev->device_pause = edma_dma_pause; | |
1796 | s_ddev->device_resume = edma_dma_resume; | |
1797 | s_ddev->device_terminate_all = edma_terminate_all; | |
1798 | ||
1799 | s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1800 | s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1801 | s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); | |
1802 | s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1803 | ||
1804 | s_ddev->dev = ecc->dev; | |
1805 | INIT_LIST_HEAD(&s_ddev->channels); | |
1806 | ||
1807 | if (memcpy_channels) { | |
1808 | m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); | |
1809 | ecc->dma_memcpy = m_ddev; | |
1810 | ||
1811 | dma_cap_zero(m_ddev->cap_mask); | |
1812 | dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); | |
1813 | ||
1814 | m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; | |
1815 | m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; | |
1816 | m_ddev->device_free_chan_resources = edma_free_chan_resources; | |
1817 | m_ddev->device_issue_pending = edma_issue_pending; | |
1818 | m_ddev->device_tx_status = edma_tx_status; | |
1819 | m_ddev->device_config = edma_slave_config; | |
1820 | m_ddev->device_pause = edma_dma_pause; | |
1821 | m_ddev->device_resume = edma_dma_resume; | |
1822 | m_ddev->device_terminate_all = edma_terminate_all; | |
1823 | ||
1824 | m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1825 | m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1826 | m_ddev->directions = BIT(DMA_MEM_TO_MEM); | |
1827 | m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1828 | ||
1829 | m_ddev->dev = ecc->dev; | |
1830 | INIT_LIST_HEAD(&m_ddev->channels); | |
1831 | } else if (!ecc->legacy_mode) { | |
1832 | dev_info(ecc->dev, "memcpy is disabled\n"); | |
1833 | } | |
02f77ef1 | 1834 | |
cb782059 | 1835 | for (i = 0; i < ecc->num_channels; i++) { |
02f77ef1 | 1836 | struct edma_chan *echan = &ecc->slave_chans[i]; |
2b6b3b74 | 1837 | echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); |
c2dde5f8 MP |
1838 | echan->ecc = ecc; |
1839 | echan->vchan.desc_free = edma_desc_free; | |
1840 | ||
1be5336b PU |
1841 | if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels)) |
1842 | vchan_init(&echan->vchan, m_ddev); | |
1843 | else | |
1844 | vchan_init(&echan->vchan, s_ddev); | |
c2dde5f8 MP |
1845 | |
1846 | INIT_LIST_HEAD(&echan->node); | |
1847 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
1848 | echan->slot[j] = -1; | |
1849 | } | |
1850 | } | |
1851 | ||
2b6b3b74 PU |
1852 | static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, |
1853 | struct edma_cc *ecc) | |
1854 | { | |
1855 | int i; | |
1856 | u32 value, cccfg; | |
1857 | s8 (*queue_priority_map)[2]; | |
1858 | ||
1859 | /* Decode the eDMA3 configuration from CCCFG register */ | |
1860 | cccfg = edma_read(ecc, EDMA_CCCFG); | |
1861 | ||
1862 | value = GET_NUM_REGN(cccfg); | |
1863 | ecc->num_region = BIT(value); | |
1864 | ||
1865 | value = GET_NUM_DMACH(cccfg); | |
1866 | ecc->num_channels = BIT(value + 1); | |
1867 | ||
633e42b8 PU |
1868 | value = GET_NUM_QDMACH(cccfg); |
1869 | ecc->num_qchannels = value * 2; | |
1870 | ||
2b6b3b74 PU |
1871 | value = GET_NUM_PAENTRY(cccfg); |
1872 | ecc->num_slots = BIT(value + 4); | |
1873 | ||
1874 | value = GET_NUM_EVQUE(cccfg); | |
1875 | ecc->num_tc = value + 1; | |
1876 | ||
4ab54f69 PU |
1877 | ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; |
1878 | ||
2b6b3b74 PU |
1879 | dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); |
1880 | dev_dbg(dev, "num_region: %u\n", ecc->num_region); | |
1881 | dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); | |
633e42b8 | 1882 | dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); |
2b6b3b74 PU |
1883 | dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); |
1884 | dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); | |
4ab54f69 | 1885 | dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); |
2b6b3b74 PU |
1886 | |
1887 | /* Nothing need to be done if queue priority is provided */ | |
1888 | if (pdata->queue_priority_mapping) | |
1889 | return 0; | |
1890 | ||
1891 | /* | |
1892 | * Configure TC/queue priority as follows: | |
1893 | * Q0 - priority 0 | |
1894 | * Q1 - priority 1 | |
1895 | * Q2 - priority 2 | |
1896 | * ... | |
1897 | * The meaning of priority numbers: 0 highest priority, 7 lowest | |
1898 | * priority. So Q0 is the highest priority queue and the last queue has | |
1899 | * the lowest priority. | |
1900 | */ | |
547c6e27 | 1901 | queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), |
2b6b3b74 PU |
1902 | GFP_KERNEL); |
1903 | if (!queue_priority_map) | |
1904 | return -ENOMEM; | |
1905 | ||
1906 | for (i = 0; i < ecc->num_tc; i++) { | |
1907 | queue_priority_map[i][0] = i; | |
1908 | queue_priority_map[i][1] = i; | |
1909 | } | |
1910 | queue_priority_map[i][0] = -1; | |
1911 | queue_priority_map[i][1] = -1; | |
1912 | ||
1913 | pdata->queue_priority_mapping = queue_priority_map; | |
1914 | /* Default queue has the lowest priority */ | |
1915 | pdata->default_queue = i - 1; | |
1916 | ||
1917 | return 0; | |
1918 | } | |
1919 | ||
1920 | #if IS_ENABLED(CONFIG_OF) | |
1921 | static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, | |
1922 | size_t sz) | |
1923 | { | |
1924 | const char pname[] = "ti,edma-xbar-event-map"; | |
1925 | struct resource res; | |
1926 | void __iomem *xbar; | |
1927 | s16 (*xbar_chans)[2]; | |
1928 | size_t nelm = sz / sizeof(s16); | |
1929 | u32 shift, offset, mux; | |
1930 | int ret, i; | |
1931 | ||
547c6e27 | 1932 | xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); |
2b6b3b74 PU |
1933 | if (!xbar_chans) |
1934 | return -ENOMEM; | |
1935 | ||
1936 | ret = of_address_to_resource(dev->of_node, 1, &res); | |
1937 | if (ret) | |
1938 | return -ENOMEM; | |
1939 | ||
1940 | xbar = devm_ioremap(dev, res.start, resource_size(&res)); | |
1941 | if (!xbar) | |
1942 | return -ENOMEM; | |
1943 | ||
1944 | ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, | |
1945 | nelm); | |
1946 | if (ret) | |
1947 | return -EIO; | |
1948 | ||
1949 | /* Invalidate last entry for the other user of this mess */ | |
1950 | nelm >>= 1; | |
1951 | xbar_chans[nelm][0] = -1; | |
1952 | xbar_chans[nelm][1] = -1; | |
1953 | ||
1954 | for (i = 0; i < nelm; i++) { | |
1955 | shift = (xbar_chans[i][1] & 0x03) << 3; | |
1956 | offset = xbar_chans[i][1] & 0xfffffffc; | |
1957 | mux = readl(xbar + offset); | |
1958 | mux &= ~(0xff << shift); | |
1959 | mux |= xbar_chans[i][0] << shift; | |
1960 | writel(mux, (xbar + offset)); | |
1961 | } | |
1962 | ||
1963 | pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; | |
1964 | return 0; | |
1965 | } | |
1966 | ||
1be5336b PU |
1967 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
1968 | bool legacy_mode) | |
2b6b3b74 PU |
1969 | { |
1970 | struct edma_soc_info *info; | |
966a87b5 PU |
1971 | struct property *prop; |
1972 | size_t sz; | |
2b6b3b74 PU |
1973 | int ret; |
1974 | ||
1975 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | |
1976 | if (!info) | |
1977 | return ERR_PTR(-ENOMEM); | |
1978 | ||
1be5336b PU |
1979 | if (legacy_mode) { |
1980 | prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", | |
1981 | &sz); | |
1982 | if (prop) { | |
1983 | ret = edma_xbar_event_map(dev, info, sz); | |
1984 | if (ret) | |
1985 | return ERR_PTR(ret); | |
1986 | } | |
1987 | return info; | |
1988 | } | |
1989 | ||
1990 | /* Get the list of channels allocated to be used for memcpy */ | |
1991 | prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); | |
1992 | if (prop) { | |
1993 | const char pname[] = "ti,edma-memcpy-channels"; | |
1994 | size_t nelm = sz / sizeof(s16); | |
1995 | s16 *memcpy_ch; | |
1996 | ||
1997 | memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s16), | |
1998 | GFP_KERNEL); | |
1999 | if (!memcpy_ch) | |
2000 | return ERR_PTR(-ENOMEM); | |
2001 | ||
2002 | ret = of_property_read_u16_array(dev->of_node, pname, | |
2003 | (u16 *)memcpy_ch, nelm); | |
2004 | if (ret) | |
2005 | return ERR_PTR(ret); | |
2006 | ||
2007 | memcpy_ch[nelm] = -1; | |
2008 | info->memcpy_channels = memcpy_ch; | |
2009 | } | |
2010 | ||
2011 | prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", | |
2012 | &sz); | |
966a87b5 | 2013 | if (prop) { |
1be5336b PU |
2014 | const char pname[] = "ti,edma-reserved-slot-ranges"; |
2015 | s16 (*rsv_slots)[2]; | |
2016 | size_t nelm = sz / sizeof(*rsv_slots); | |
2017 | struct edma_rsv_info *rsv_info; | |
2018 | ||
2019 | if (!nelm) | |
2020 | return info; | |
2021 | ||
2022 | rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); | |
2023 | if (!rsv_info) | |
2024 | return ERR_PTR(-ENOMEM); | |
2025 | ||
2026 | rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), | |
2027 | GFP_KERNEL); | |
2028 | if (!rsv_slots) | |
2029 | return ERR_PTR(-ENOMEM); | |
2030 | ||
2031 | ret = of_property_read_u16_array(dev->of_node, pname, | |
2032 | (u16 *)rsv_slots, nelm * 2); | |
966a87b5 PU |
2033 | if (ret) |
2034 | return ERR_PTR(ret); | |
1be5336b PU |
2035 | |
2036 | rsv_slots[nelm][0] = -1; | |
2037 | rsv_slots[nelm][1] = -1; | |
2038 | info->rsv = rsv_info; | |
2039 | info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; | |
966a87b5 | 2040 | } |
2b6b3b74 PU |
2041 | |
2042 | return info; | |
2043 | } | |
1be5336b PU |
2044 | |
2045 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, | |
2046 | struct of_dma *ofdma) | |
2047 | { | |
2048 | struct edma_cc *ecc = ofdma->of_dma_data; | |
2049 | struct dma_chan *chan = NULL; | |
2050 | struct edma_chan *echan; | |
2051 | int i; | |
2052 | ||
2053 | if (!ecc || dma_spec->args_count < 1) | |
2054 | return NULL; | |
2055 | ||
2056 | for (i = 0; i < ecc->num_channels; i++) { | |
2057 | echan = &ecc->slave_chans[i]; | |
2058 | if (echan->ch_num == dma_spec->args[0]) { | |
2059 | chan = &echan->vchan.chan; | |
2060 | break; | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | if (!chan) | |
2065 | return NULL; | |
2066 | ||
2067 | if (echan->ecc->legacy_mode && dma_spec->args_count == 1) | |
2068 | goto out; | |
2069 | ||
2070 | if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && | |
2071 | dma_spec->args[1] < echan->ecc->num_tc) { | |
2072 | echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; | |
2073 | goto out; | |
2074 | } | |
2075 | ||
2076 | return NULL; | |
2077 | out: | |
2078 | /* The channel is going to be used as HW synchronized */ | |
2079 | echan->hw_triggered = true; | |
2080 | return dma_get_slave_channel(chan); | |
2081 | } | |
2b6b3b74 | 2082 | #else |
1be5336b PU |
2083 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
2084 | bool legacy_mode) | |
2b6b3b74 PU |
2085 | { |
2086 | return ERR_PTR(-EINVAL); | |
2087 | } | |
1be5336b PU |
2088 | |
2089 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, | |
2090 | struct of_dma *ofdma) | |
2091 | { | |
2092 | return NULL; | |
2093 | } | |
2b6b3b74 PU |
2094 | #endif |
2095 | ||
463a1f8b | 2096 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 | 2097 | { |
2b6b3b74 PU |
2098 | struct edma_soc_info *info = pdev->dev.platform_data; |
2099 | s8 (*queue_priority_mapping)[2]; | |
2100 | int i, off, ln; | |
2b6b3b74 PU |
2101 | const s16 (*rsv_slots)[2]; |
2102 | const s16 (*xbar_chans)[2]; | |
2103 | int irq; | |
2104 | char *irq_name; | |
2105 | struct resource *mem; | |
2106 | struct device_node *node = pdev->dev.of_node; | |
2107 | struct device *dev = &pdev->dev; | |
2108 | struct edma_cc *ecc; | |
1be5336b | 2109 | bool legacy_mode = true; |
c2dde5f8 MP |
2110 | int ret; |
2111 | ||
2b6b3b74 | 2112 | if (node) { |
1be5336b PU |
2113 | const struct of_device_id *match; |
2114 | ||
2115 | match = of_match_node(edma_of_ids, node); | |
2116 | if (match && (u32)match->data == EDMA_BINDING_TPCC) | |
2117 | legacy_mode = false; | |
2118 | ||
2119 | info = edma_setup_info_from_dt(dev, legacy_mode); | |
2b6b3b74 PU |
2120 | if (IS_ERR(info)) { |
2121 | dev_err(dev, "failed to get DT data\n"); | |
2122 | return PTR_ERR(info); | |
2123 | } | |
2124 | } | |
2125 | ||
2126 | if (!info) | |
2127 | return -ENODEV; | |
2128 | ||
2129 | pm_runtime_enable(dev); | |
2130 | ret = pm_runtime_get_sync(dev); | |
2131 | if (ret < 0) { | |
2132 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
2133 | return ret; | |
2134 | } | |
2135 | ||
907f74a0 | 2136 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
94cb0e79 RK |
2137 | if (ret) |
2138 | return ret; | |
2139 | ||
907f74a0 | 2140 | ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); |
c2dde5f8 | 2141 | if (!ecc) { |
907f74a0 | 2142 | dev_err(dev, "Can't allocate controller\n"); |
c2dde5f8 MP |
2143 | return -ENOMEM; |
2144 | } | |
2145 | ||
2b6b3b74 PU |
2146 | ecc->dev = dev; |
2147 | ecc->id = pdev->id; | |
1be5336b | 2148 | ecc->legacy_mode = legacy_mode; |
2b6b3b74 PU |
2149 | /* When booting with DT the pdev->id is -1 */ |
2150 | if (ecc->id < 0) | |
2151 | ecc->id = 0; | |
2152 | ||
2153 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); | |
2154 | if (!mem) { | |
2155 | dev_dbg(dev, "mem resource not found, using index 0\n"); | |
2156 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2157 | if (!mem) { | |
2158 | dev_err(dev, "no mem resource?\n"); | |
2159 | return -ENODEV; | |
2160 | } | |
2161 | } | |
2162 | ecc->base = devm_ioremap_resource(dev, mem); | |
2163 | if (IS_ERR(ecc->base)) | |
2164 | return PTR_ERR(ecc->base); | |
2165 | ||
2166 | platform_set_drvdata(pdev, ecc); | |
2167 | ||
2168 | /* Get eDMA3 configuration from IP */ | |
2169 | ret = edma_setup_from_hw(dev, info, ecc); | |
2170 | if (ret) | |
2171 | return ret; | |
2172 | ||
cb782059 PU |
2173 | /* Allocate memory based on the information we got from the IP */ |
2174 | ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, | |
2175 | sizeof(*ecc->slave_chans), GFP_KERNEL); | |
2176 | if (!ecc->slave_chans) | |
2177 | return -ENOMEM; | |
2178 | ||
7a73b135 | 2179 | ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), |
cb782059 | 2180 | sizeof(unsigned long), GFP_KERNEL); |
7a73b135 | 2181 | if (!ecc->slot_inuse) |
cb782059 PU |
2182 | return -ENOMEM; |
2183 | ||
2b6b3b74 PU |
2184 | ecc->default_queue = info->default_queue; |
2185 | ||
2186 | for (i = 0; i < ecc->num_slots; i++) | |
2187 | edma_write_slot(ecc, i, &dummy_paramset); | |
2188 | ||
2b6b3b74 | 2189 | if (info->rsv) { |
2b6b3b74 PU |
2190 | /* Set the reserved slots in inuse list */ |
2191 | rsv_slots = info->rsv->rsv_slots; | |
2192 | if (rsv_slots) { | |
2193 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
2194 | off = rsv_slots[i][0]; | |
2195 | ln = rsv_slots[i][1]; | |
7a73b135 | 2196 | set_bits(off, ln, ecc->slot_inuse); |
2b6b3b74 PU |
2197 | } |
2198 | } | |
2199 | } | |
2200 | ||
2201 | /* Clear the xbar mapped channels in unused list */ | |
2202 | xbar_chans = info->xbar_chans; | |
2203 | if (xbar_chans) { | |
2204 | for (i = 0; xbar_chans[i][1] != -1; i++) { | |
2205 | off = xbar_chans[i][1]; | |
2b6b3b74 PU |
2206 | } |
2207 | } | |
2208 | ||
2209 | irq = platform_get_irq_byname(pdev, "edma3_ccint"); | |
2210 | if (irq < 0 && node) | |
2211 | irq = irq_of_parse_and_map(node, 0); | |
2212 | ||
2213 | if (irq >= 0) { | |
2214 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", | |
2215 | dev_name(dev)); | |
2216 | ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, | |
2217 | ecc); | |
2218 | if (ret) { | |
2219 | dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); | |
2220 | return ret; | |
2221 | } | |
2222 | } | |
2223 | ||
2224 | irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); | |
2225 | if (irq < 0 && node) | |
2226 | irq = irq_of_parse_and_map(node, 2); | |
2227 | ||
2228 | if (irq >= 0) { | |
2229 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", | |
2230 | dev_name(dev)); | |
2231 | ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, | |
2232 | ecc); | |
2233 | if (ret) { | |
2234 | dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); | |
2235 | return ret; | |
2236 | } | |
2237 | } | |
2238 | ||
e4e886c6 PU |
2239 | ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); |
2240 | if (ecc->dummy_slot < 0) { | |
2241 | dev_err(dev, "Can't allocate PaRAM dummy slot\n"); | |
2242 | return ecc->dummy_slot; | |
2243 | } | |
2244 | ||
2b6b3b74 PU |
2245 | queue_priority_mapping = info->queue_priority_mapping; |
2246 | ||
1be5336b PU |
2247 | if (!ecc->legacy_mode) { |
2248 | int lowest_priority = 0; | |
2249 | struct of_phandle_args tc_args; | |
2250 | ||
2251 | ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, | |
2252 | sizeof(*ecc->tc_list), GFP_KERNEL); | |
2253 | if (!ecc->tc_list) | |
2254 | return -ENOMEM; | |
2255 | ||
2256 | for (i = 0;; i++) { | |
2257 | ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs", | |
2258 | 1, i, &tc_args); | |
2259 | if (ret || i == ecc->num_tc) | |
2260 | break; | |
2261 | ||
2262 | ecc->tc_list[i].node = tc_args.np; | |
2263 | ecc->tc_list[i].id = i; | |
2264 | queue_priority_mapping[i][1] = tc_args.args[0]; | |
2265 | if (queue_priority_mapping[i][1] > lowest_priority) { | |
2266 | lowest_priority = queue_priority_mapping[i][1]; | |
2267 | info->default_queue = i; | |
2268 | } | |
2269 | } | |
2270 | } | |
2271 | ||
2b6b3b74 PU |
2272 | /* Event queue priority mapping */ |
2273 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
2274 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], | |
2275 | queue_priority_mapping[i][1]); | |
ca304fa9 | 2276 | |
2b6b3b74 PU |
2277 | for (i = 0; i < ecc->num_region; i++) { |
2278 | edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); | |
2279 | edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); | |
2280 | edma_write_array(ecc, EDMA_QRAE, i, 0x0); | |
2281 | } | |
2282 | ecc->info = info; | |
2283 | ||
02f77ef1 | 2284 | /* Init the dma device and channels */ |
1be5336b | 2285 | edma_dma_init(ecc, legacy_mode); |
c2dde5f8 | 2286 | |
34cf3011 PU |
2287 | for (i = 0; i < ecc->num_channels; i++) { |
2288 | /* Assign all channels to the default queue */ | |
f9425deb PU |
2289 | edma_assign_channel_eventq(&ecc->slave_chans[i], |
2290 | info->default_queue); | |
34cf3011 PU |
2291 | /* Set entry slot to the dummy slot */ |
2292 | edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); | |
2293 | } | |
2294 | ||
c2dde5f8 | 2295 | ret = dma_async_device_register(&ecc->dma_slave); |
1be5336b PU |
2296 | if (ret) { |
2297 | dev_err(dev, "slave ddev registration failed (%d)\n", ret); | |
c2dde5f8 | 2298 | goto err_reg1; |
1be5336b PU |
2299 | } |
2300 | ||
2301 | if (ecc->dma_memcpy) { | |
2302 | ret = dma_async_device_register(ecc->dma_memcpy); | |
2303 | if (ret) { | |
2304 | dev_err(dev, "memcpy ddev registration failed (%d)\n", | |
2305 | ret); | |
2306 | dma_async_device_unregister(&ecc->dma_slave); | |
2307 | goto err_reg1; | |
2308 | } | |
2309 | } | |
c2dde5f8 | 2310 | |
2b6b3b74 | 2311 | if (node) |
1be5336b | 2312 | of_dma_controller_register(node, of_edma_xlate, ecc); |
dc9b6055 | 2313 | |
907f74a0 | 2314 | dev_info(dev, "TI EDMA DMA engine driver\n"); |
c2dde5f8 MP |
2315 | |
2316 | return 0; | |
2317 | ||
2318 | err_reg1: | |
2b6b3b74 | 2319 | edma_free_slot(ecc, ecc->dummy_slot); |
c2dde5f8 MP |
2320 | return ret; |
2321 | } | |
2322 | ||
4bf27b8b | 2323 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
2324 | { |
2325 | struct device *dev = &pdev->dev; | |
2326 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
2327 | ||
907f74a0 PU |
2328 | if (dev->of_node) |
2329 | of_dma_controller_free(dev->of_node); | |
c2dde5f8 | 2330 | dma_async_device_unregister(&ecc->dma_slave); |
1be5336b PU |
2331 | if (ecc->dma_memcpy) |
2332 | dma_async_device_unregister(ecc->dma_memcpy); | |
2b6b3b74 | 2333 | edma_free_slot(ecc, ecc->dummy_slot); |
c2dde5f8 MP |
2334 | |
2335 | return 0; | |
2336 | } | |
2337 | ||
2b6b3b74 | 2338 | #ifdef CONFIG_PM_SLEEP |
1be5336b PU |
2339 | static int edma_pm_suspend(struct device *dev) |
2340 | { | |
2341 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
2342 | struct edma_chan *echan = ecc->slave_chans; | |
2343 | int i; | |
2344 | ||
2345 | for (i = 0; i < ecc->num_channels; i++) { | |
2346 | if (echan[i].alloced) { | |
2347 | edma_setup_interrupt(&echan[i], false); | |
2348 | edma_tc_set_pm_state(echan[i].tc, false); | |
2349 | } | |
2350 | } | |
2351 | ||
2352 | return 0; | |
2353 | } | |
2354 | ||
2b6b3b74 PU |
2355 | static int edma_pm_resume(struct device *dev) |
2356 | { | |
2357 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
e4e886c6 | 2358 | struct edma_chan *echan = ecc->slave_chans; |
2b6b3b74 PU |
2359 | int i; |
2360 | s8 (*queue_priority_mapping)[2]; | |
2361 | ||
2362 | queue_priority_mapping = ecc->info->queue_priority_mapping; | |
2363 | ||
2364 | /* Event queue priority mapping */ | |
2365 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
2366 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], | |
2367 | queue_priority_mapping[i][1]); | |
2368 | ||
2b6b3b74 | 2369 | for (i = 0; i < ecc->num_channels; i++) { |
e4e886c6 | 2370 | if (echan[i].alloced) { |
2b6b3b74 PU |
2371 | /* ensure access through shadow region 0 */ |
2372 | edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, | |
2373 | BIT(i & 0x1f)); | |
2374 | ||
34cf3011 | 2375 | edma_setup_interrupt(&echan[i], true); |
e4e886c6 PU |
2376 | |
2377 | /* Set up channel -> slot mapping for the entry slot */ | |
34cf3011 | 2378 | edma_set_chmap(&echan[i], echan[i].slot[0]); |
1be5336b PU |
2379 | |
2380 | edma_tc_set_pm_state(echan[i].tc, true); | |
2b6b3b74 PU |
2381 | } |
2382 | } | |
2383 | ||
2384 | return 0; | |
2385 | } | |
2386 | #endif | |
2387 | ||
2388 | static const struct dev_pm_ops edma_pm_ops = { | |
1be5336b | 2389 | SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume) |
2b6b3b74 PU |
2390 | }; |
2391 | ||
c2dde5f8 MP |
2392 | static struct platform_driver edma_driver = { |
2393 | .probe = edma_probe, | |
a7d6e3ec | 2394 | .remove = edma_remove, |
c2dde5f8 | 2395 | .driver = { |
2b6b3b74 PU |
2396 | .name = "edma", |
2397 | .pm = &edma_pm_ops, | |
2398 | .of_match_table = edma_of_ids, | |
c2dde5f8 MP |
2399 | }, |
2400 | }; | |
2401 | ||
2402 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
2403 | { | |
1be5336b PU |
2404 | bool match = false; |
2405 | ||
c2dde5f8 MP |
2406 | if (chan->device->dev->driver == &edma_driver.driver) { |
2407 | struct edma_chan *echan = to_edma_chan(chan); | |
2408 | unsigned ch_req = *(unsigned *)param; | |
1be5336b PU |
2409 | if (ch_req == echan->ch_num) { |
2410 | /* The channel is going to be used as HW synchronized */ | |
2411 | echan->hw_triggered = true; | |
2412 | match = true; | |
2413 | } | |
c2dde5f8 | 2414 | } |
1be5336b | 2415 | return match; |
c2dde5f8 MP |
2416 | } |
2417 | EXPORT_SYMBOL(edma_filter_fn); | |
2418 | ||
c2dde5f8 MP |
2419 | static int edma_init(void) |
2420 | { | |
5305e4d6 | 2421 | return platform_driver_register(&edma_driver); |
c2dde5f8 MP |
2422 | } |
2423 | subsys_initcall(edma_init); | |
2424 | ||
2425 | static void __exit edma_exit(void) | |
2426 | { | |
c2dde5f8 MP |
2427 | platform_driver_unregister(&edma_driver); |
2428 | } | |
2429 | module_exit(edma_exit); | |
2430 | ||
d71505b6 | 2431 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
2432 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
2433 | MODULE_LICENSE("GPL v2"); |