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Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
b7a4fd53 | 18 | #include <linux/edma.h> |
c2dde5f8 MP |
19 | #include <linux/err.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
ed64610f | 27 | #include <linux/of.h> |
dc9b6055 | 28 | #include <linux/of_dma.h> |
2b6b3b74 PU |
29 | #include <linux/of_irq.h> |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_device.h> | |
32 | #include <linux/pm_runtime.h> | |
c2dde5f8 | 33 | |
3ad7a42d | 34 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
35 | |
36 | #include "dmaengine.h" | |
37 | #include "virt-dma.h" | |
38 | ||
2b6b3b74 PU |
39 | /* Offsets matching "struct edmacc_param" */ |
40 | #define PARM_OPT 0x00 | |
41 | #define PARM_SRC 0x04 | |
42 | #define PARM_A_B_CNT 0x08 | |
43 | #define PARM_DST 0x0c | |
44 | #define PARM_SRC_DST_BIDX 0x10 | |
45 | #define PARM_LINK_BCNTRLD 0x14 | |
46 | #define PARM_SRC_DST_CIDX 0x18 | |
47 | #define PARM_CCNT 0x1c | |
48 | ||
49 | #define PARM_SIZE 0x20 | |
50 | ||
51 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
52 | #define SH_ER 0x00 /* 64 bits */ | |
53 | #define SH_ECR 0x08 /* 64 bits */ | |
54 | #define SH_ESR 0x10 /* 64 bits */ | |
55 | #define SH_CER 0x18 /* 64 bits */ | |
56 | #define SH_EER 0x20 /* 64 bits */ | |
57 | #define SH_EECR 0x28 /* 64 bits */ | |
58 | #define SH_EESR 0x30 /* 64 bits */ | |
59 | #define SH_SER 0x38 /* 64 bits */ | |
60 | #define SH_SECR 0x40 /* 64 bits */ | |
61 | #define SH_IER 0x50 /* 64 bits */ | |
62 | #define SH_IECR 0x58 /* 64 bits */ | |
63 | #define SH_IESR 0x60 /* 64 bits */ | |
64 | #define SH_IPR 0x68 /* 64 bits */ | |
65 | #define SH_ICR 0x70 /* 64 bits */ | |
66 | #define SH_IEVAL 0x78 | |
67 | #define SH_QER 0x80 | |
68 | #define SH_QEER 0x84 | |
69 | #define SH_QEECR 0x88 | |
70 | #define SH_QEESR 0x8c | |
71 | #define SH_QSER 0x90 | |
72 | #define SH_QSECR 0x94 | |
73 | #define SH_SIZE 0x200 | |
74 | ||
75 | /* Offsets for EDMA CC global registers */ | |
76 | #define EDMA_REV 0x0000 | |
77 | #define EDMA_CCCFG 0x0004 | |
78 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
79 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
80 | #define EDMA_QDMAQNUM 0x0260 | |
81 | #define EDMA_QUETCMAP 0x0280 | |
82 | #define EDMA_QUEPRI 0x0284 | |
83 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
84 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
85 | #define EDMA_QEMR 0x0310 | |
86 | #define EDMA_QEMCR 0x0314 | |
87 | #define EDMA_CCERR 0x0318 | |
88 | #define EDMA_CCERRCLR 0x031c | |
89 | #define EDMA_EEVAL 0x0320 | |
90 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
91 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
92 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
93 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
94 | #define EDMA_QWMTHRA 0x0620 | |
95 | #define EDMA_QWMTHRB 0x0624 | |
96 | #define EDMA_CCSTAT 0x0640 | |
97 | ||
98 | #define EDMA_M 0x1000 /* global channel registers */ | |
99 | #define EDMA_ECR 0x1008 | |
100 | #define EDMA_ECRH 0x100C | |
101 | #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */ | |
102 | #define EDMA_PARM 0x4000 /* PaRAM entries */ | |
103 | ||
104 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) | |
105 | ||
106 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ | |
107 | ||
108 | /* CCCFG register */ | |
109 | #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ | |
f5ea7ad2 | 110 | #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */ |
2b6b3b74 PU |
111 | #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ |
112 | #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ | |
113 | #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ | |
114 | #define CHMAP_EXIST BIT(24) | |
115 | ||
4ac31d18 JO |
116 | /* CCSTAT register */ |
117 | #define EDMA_CCSTAT_ACTV BIT(4) | |
118 | ||
2abd5f1b JF |
119 | /* |
120 | * Max of 20 segments per channel to conserve PaRAM slots | |
121 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
122 | * that are required for ASoC, otherwise DMA prep calls will | |
123 | * fail. Today davinci-pcm is the only user of this driver and | |
124 | * requires atleast 17 slots, so we setup the default to 20. | |
125 | */ | |
126 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
127 | #define EDMA_MAX_SLOTS MAX_NR_SG |
128 | #define EDMA_DESCRIPTORS 16 | |
129 | ||
2b6b3b74 PU |
130 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ |
131 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ | |
132 | #define EDMA_CONT_PARAMS_ANY 1001 | |
133 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 | |
134 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 | |
135 | ||
2b6b3b74 PU |
136 | /* PaRAM slots are laid out like this */ |
137 | struct edmacc_param { | |
138 | u32 opt; | |
139 | u32 src; | |
140 | u32 a_b_cnt; | |
141 | u32 dst; | |
142 | u32 src_dst_bidx; | |
143 | u32 link_bcntrld; | |
144 | u32 src_dst_cidx; | |
145 | u32 ccnt; | |
146 | } __packed; | |
147 | ||
148 | /* fields in edmacc_param.opt */ | |
149 | #define SAM BIT(0) | |
150 | #define DAM BIT(1) | |
151 | #define SYNCDIM BIT(2) | |
152 | #define STATIC BIT(3) | |
153 | #define EDMA_FWID (0x07 << 8) | |
154 | #define TCCMODE BIT(11) | |
155 | #define EDMA_TCC(t) ((t) << 12) | |
156 | #define TCINTEN BIT(20) | |
157 | #define ITCINTEN BIT(21) | |
158 | #define TCCHEN BIT(22) | |
159 | #define ITCCHEN BIT(23) | |
160 | ||
b5088ad9 | 161 | struct edma_pset { |
c2da2340 TG |
162 | u32 len; |
163 | dma_addr_t addr; | |
b5088ad9 TG |
164 | struct edmacc_param param; |
165 | }; | |
166 | ||
c2dde5f8 MP |
167 | struct edma_desc { |
168 | struct virt_dma_desc vdesc; | |
169 | struct list_head node; | |
c2da2340 | 170 | enum dma_transfer_direction direction; |
50a9c707 | 171 | int cyclic; |
c2dde5f8 MP |
172 | int absync; |
173 | int pset_nr; | |
04361d88 | 174 | struct edma_chan *echan; |
53407062 | 175 | int processed; |
04361d88 JF |
176 | |
177 | /* | |
178 | * The following 4 elements are used for residue accounting. | |
179 | * | |
180 | * - processed_stat: the number of SG elements we have traversed | |
181 | * so far to cover accounting. This is updated directly to processed | |
182 | * during edma_callback and is always <= processed, because processed | |
183 | * refers to the number of pending transfer (programmed to EDMA | |
184 | * controller), where as processed_stat tracks number of transfers | |
185 | * accounted for so far. | |
186 | * | |
187 | * - residue: The amount of bytes we have left to transfer for this desc | |
188 | * | |
189 | * - residue_stat: The residue in bytes of data we have covered | |
190 | * so far for accounting. This is updated directly to residue | |
191 | * during callbacks to keep it current. | |
192 | * | |
193 | * - sg_len: Tracks the length of the current intermediate transfer, | |
194 | * this is required to update the residue during intermediate transfer | |
195 | * completion callback. | |
196 | */ | |
740b41f7 | 197 | int processed_stat; |
740b41f7 | 198 | u32 sg_len; |
04361d88 | 199 | u32 residue; |
740b41f7 | 200 | u32 residue_stat; |
04361d88 | 201 | |
b5088ad9 | 202 | struct edma_pset pset[0]; |
c2dde5f8 MP |
203 | }; |
204 | ||
205 | struct edma_cc; | |
206 | ||
1be5336b PU |
207 | struct edma_tc { |
208 | struct device_node *node; | |
209 | u16 id; | |
210 | }; | |
211 | ||
c2dde5f8 MP |
212 | struct edma_chan { |
213 | struct virt_dma_chan vchan; | |
214 | struct list_head node; | |
215 | struct edma_desc *edesc; | |
216 | struct edma_cc *ecc; | |
1be5336b | 217 | struct edma_tc *tc; |
c2dde5f8 MP |
218 | int ch_num; |
219 | bool alloced; | |
1be5336b | 220 | bool hw_triggered; |
c2dde5f8 | 221 | int slot[EDMA_MAX_SLOTS]; |
c5f47990 | 222 | int missed; |
661f7cb5 | 223 | struct dma_slave_config cfg; |
c2dde5f8 MP |
224 | }; |
225 | ||
226 | struct edma_cc { | |
2b6b3b74 PU |
227 | struct device *dev; |
228 | struct edma_soc_info *info; | |
229 | void __iomem *base; | |
230 | int id; | |
1be5336b | 231 | bool legacy_mode; |
2b6b3b74 PU |
232 | |
233 | /* eDMA3 resource information */ | |
234 | unsigned num_channels; | |
633e42b8 | 235 | unsigned num_qchannels; |
2b6b3b74 PU |
236 | unsigned num_region; |
237 | unsigned num_slots; | |
238 | unsigned num_tc; | |
4ab54f69 | 239 | bool chmap_exist; |
2b6b3b74 PU |
240 | enum dma_event_q default_queue; |
241 | ||
638001e0 VK |
242 | unsigned int ccint; |
243 | unsigned int ccerrint; | |
244 | ||
1be5336b PU |
245 | /* |
246 | * The slot_inuse bit for each PaRAM slot is clear unless the slot is | |
247 | * in use by Linux or if it is allocated to be used by DSP. | |
2b6b3b74 | 248 | */ |
7a73b135 | 249 | unsigned long *slot_inuse; |
2b6b3b74 | 250 | |
c2dde5f8 | 251 | struct dma_device dma_slave; |
1be5336b | 252 | struct dma_device *dma_memcpy; |
cb782059 | 253 | struct edma_chan *slave_chans; |
1be5336b | 254 | struct edma_tc *tc_list; |
c2dde5f8 MP |
255 | int dummy_slot; |
256 | }; | |
257 | ||
2b6b3b74 PU |
258 | /* dummy param set used to (re)initialize parameter RAM slots */ |
259 | static const struct edmacc_param dummy_paramset = { | |
260 | .link_bcntrld = 0xffff, | |
261 | .ccnt = 1, | |
262 | }; | |
263 | ||
1be5336b PU |
264 | #define EDMA_BINDING_LEGACY 0 |
265 | #define EDMA_BINDING_TPCC 1 | |
2b6b3b74 | 266 | static const struct of_device_id edma_of_ids[] = { |
1be5336b PU |
267 | { |
268 | .compatible = "ti,edma3", | |
269 | .data = (void *)EDMA_BINDING_LEGACY, | |
270 | }, | |
271 | { | |
272 | .compatible = "ti,edma3-tpcc", | |
273 | .data = (void *)EDMA_BINDING_TPCC, | |
274 | }, | |
2b6b3b74 PU |
275 | {} |
276 | }; | |
86737510 | 277 | MODULE_DEVICE_TABLE(of, edma_of_ids); |
2b6b3b74 | 278 | |
34635b1a PU |
279 | static const struct of_device_id edma_tptc_of_ids[] = { |
280 | { .compatible = "ti,edma3-tptc", }, | |
281 | {} | |
282 | }; | |
86737510 | 283 | MODULE_DEVICE_TABLE(of, edma_tptc_of_ids); |
34635b1a | 284 | |
2b6b3b74 PU |
285 | static inline unsigned int edma_read(struct edma_cc *ecc, int offset) |
286 | { | |
287 | return (unsigned int)__raw_readl(ecc->base + offset); | |
288 | } | |
289 | ||
290 | static inline void edma_write(struct edma_cc *ecc, int offset, int val) | |
291 | { | |
292 | __raw_writel(val, ecc->base + offset); | |
293 | } | |
294 | ||
295 | static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, | |
296 | unsigned or) | |
297 | { | |
298 | unsigned val = edma_read(ecc, offset); | |
299 | ||
300 | val &= and; | |
301 | val |= or; | |
302 | edma_write(ecc, offset, val); | |
303 | } | |
304 | ||
305 | static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) | |
306 | { | |
307 | unsigned val = edma_read(ecc, offset); | |
308 | ||
309 | val &= and; | |
310 | edma_write(ecc, offset, val); | |
311 | } | |
312 | ||
313 | static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) | |
314 | { | |
315 | unsigned val = edma_read(ecc, offset); | |
316 | ||
317 | val |= or; | |
318 | edma_write(ecc, offset, val); | |
319 | } | |
320 | ||
321 | static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, | |
322 | int i) | |
323 | { | |
324 | return edma_read(ecc, offset + (i << 2)); | |
325 | } | |
326 | ||
327 | static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, | |
328 | unsigned val) | |
329 | { | |
330 | edma_write(ecc, offset + (i << 2), val); | |
331 | } | |
332 | ||
333 | static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, | |
334 | unsigned and, unsigned or) | |
335 | { | |
336 | edma_modify(ecc, offset + (i << 2), and, or); | |
337 | } | |
338 | ||
339 | static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, | |
340 | unsigned or) | |
341 | { | |
342 | edma_or(ecc, offset + (i << 2), or); | |
343 | } | |
344 | ||
345 | static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, | |
346 | unsigned or) | |
347 | { | |
348 | edma_or(ecc, offset + ((i * 2 + j) << 2), or); | |
349 | } | |
350 | ||
351 | static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, | |
352 | int j, unsigned val) | |
353 | { | |
354 | edma_write(ecc, offset + ((i * 2 + j) << 2), val); | |
355 | } | |
356 | ||
357 | static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) | |
358 | { | |
359 | return edma_read(ecc, EDMA_SHADOW0 + offset); | |
360 | } | |
361 | ||
362 | static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, | |
363 | int offset, int i) | |
364 | { | |
365 | return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); | |
366 | } | |
367 | ||
368 | static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, | |
369 | unsigned val) | |
370 | { | |
371 | edma_write(ecc, EDMA_SHADOW0 + offset, val); | |
372 | } | |
373 | ||
374 | static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, | |
375 | int i, unsigned val) | |
376 | { | |
377 | edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); | |
378 | } | |
379 | ||
d9c345d1 PU |
380 | static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, |
381 | int param_no) | |
2b6b3b74 PU |
382 | { |
383 | return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); | |
384 | } | |
385 | ||
d9c345d1 PU |
386 | static inline void edma_param_write(struct edma_cc *ecc, int offset, |
387 | int param_no, unsigned val) | |
2b6b3b74 PU |
388 | { |
389 | edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); | |
390 | } | |
391 | ||
d9c345d1 PU |
392 | static inline void edma_param_modify(struct edma_cc *ecc, int offset, |
393 | int param_no, unsigned and, unsigned or) | |
2b6b3b74 PU |
394 | { |
395 | edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); | |
396 | } | |
397 | ||
d9c345d1 PU |
398 | static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, |
399 | unsigned and) | |
2b6b3b74 PU |
400 | { |
401 | edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); | |
402 | } | |
403 | ||
d9c345d1 PU |
404 | static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, |
405 | unsigned or) | |
2b6b3b74 PU |
406 | { |
407 | edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); | |
408 | } | |
409 | ||
410 | static inline void set_bits(int offset, int len, unsigned long *p) | |
411 | { | |
412 | for (; len > 0; len--) | |
413 | set_bit(offset + (len - 1), p); | |
414 | } | |
415 | ||
416 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
417 | { | |
418 | for (; len > 0; len--) | |
419 | clear_bit(offset + (len - 1), p); | |
420 | } | |
421 | ||
2b6b3b74 PU |
422 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, |
423 | int priority) | |
424 | { | |
425 | int bit = queue_no * 4; | |
426 | ||
427 | edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); | |
428 | } | |
429 | ||
34cf3011 | 430 | static void edma_set_chmap(struct edma_chan *echan, int slot) |
2b6b3b74 | 431 | { |
34cf3011 PU |
432 | struct edma_cc *ecc = echan->ecc; |
433 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
434 | ||
e4e886c6 | 435 | if (ecc->chmap_exist) { |
e4e886c6 PU |
436 | slot = EDMA_CHAN_SLOT(slot); |
437 | edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); | |
438 | } | |
2b6b3b74 PU |
439 | } |
440 | ||
34cf3011 | 441 | static void edma_setup_interrupt(struct edma_chan *echan, bool enable) |
2b6b3b74 | 442 | { |
34cf3011 PU |
443 | struct edma_cc *ecc = echan->ecc; |
444 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
2b6b3b74 | 445 | |
79ad2e38 | 446 | if (enable) { |
34cf3011 PU |
447 | edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, |
448 | BIT(channel & 0x1f)); | |
449 | edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, | |
450 | BIT(channel & 0x1f)); | |
79ad2e38 | 451 | } else { |
34cf3011 PU |
452 | edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, |
453 | BIT(channel & 0x1f)); | |
2b6b3b74 PU |
454 | } |
455 | } | |
456 | ||
457 | /* | |
11c15733 | 458 | * paRAM slot management functions |
2b6b3b74 PU |
459 | */ |
460 | static void edma_write_slot(struct edma_cc *ecc, unsigned slot, | |
461 | const struct edmacc_param *param) | |
462 | { | |
463 | slot = EDMA_CHAN_SLOT(slot); | |
464 | if (slot >= ecc->num_slots) | |
465 | return; | |
466 | memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); | |
467 | } | |
468 | ||
2b6b3b74 PU |
469 | static void edma_read_slot(struct edma_cc *ecc, unsigned slot, |
470 | struct edmacc_param *param) | |
471 | { | |
472 | slot = EDMA_CHAN_SLOT(slot); | |
473 | if (slot >= ecc->num_slots) | |
474 | return; | |
475 | memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); | |
476 | } | |
477 | ||
478 | /** | |
479 | * edma_alloc_slot - allocate DMA parameter RAM | |
480 | * @ecc: pointer to edma_cc struct | |
481 | * @slot: specific slot to allocate; negative for "any unused slot" | |
482 | * | |
483 | * This allocates a parameter RAM slot, initializing it to hold a | |
484 | * dummy transfer. Slots allocated using this routine have not been | |
485 | * mapped to a hardware DMA channel, and will normally be used by | |
486 | * linking to them from a slot associated with a DMA channel. | |
487 | * | |
488 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
489 | * slots may be allocated on behalf of DSP firmware. | |
490 | * | |
491 | * Returns the number of the slot, else negative errno. | |
492 | */ | |
493 | static int edma_alloc_slot(struct edma_cc *ecc, int slot) | |
494 | { | |
d20313b2 | 495 | if (slot >= 0) { |
2b6b3b74 | 496 | slot = EDMA_CHAN_SLOT(slot); |
e4e886c6 PU |
497 | /* Requesting entry paRAM slot for a HW triggered channel. */ |
498 | if (ecc->chmap_exist && slot < ecc->num_channels) | |
499 | slot = EDMA_SLOT_ANY; | |
500 | } | |
501 | ||
2b6b3b74 | 502 | if (slot < 0) { |
e4e886c6 PU |
503 | if (ecc->chmap_exist) |
504 | slot = 0; | |
505 | else | |
506 | slot = ecc->num_channels; | |
2b6b3b74 | 507 | for (;;) { |
7a73b135 | 508 | slot = find_next_zero_bit(ecc->slot_inuse, |
2b6b3b74 PU |
509 | ecc->num_slots, |
510 | slot); | |
511 | if (slot == ecc->num_slots) | |
512 | return -ENOMEM; | |
7a73b135 | 513 | if (!test_and_set_bit(slot, ecc->slot_inuse)) |
2b6b3b74 PU |
514 | break; |
515 | } | |
e4e886c6 | 516 | } else if (slot >= ecc->num_slots) { |
2b6b3b74 | 517 | return -EINVAL; |
7a73b135 | 518 | } else if (test_and_set_bit(slot, ecc->slot_inuse)) { |
2b6b3b74 PU |
519 | return -EBUSY; |
520 | } | |
521 | ||
522 | edma_write_slot(ecc, slot, &dummy_paramset); | |
523 | ||
524 | return EDMA_CTLR_CHAN(ecc->id, slot); | |
525 | } | |
526 | ||
2b6b3b74 PU |
527 | static void edma_free_slot(struct edma_cc *ecc, unsigned slot) |
528 | { | |
529 | slot = EDMA_CHAN_SLOT(slot); | |
e4e886c6 | 530 | if (slot >= ecc->num_slots) |
2b6b3b74 PU |
531 | return; |
532 | ||
533 | edma_write_slot(ecc, slot, &dummy_paramset); | |
7a73b135 | 534 | clear_bit(slot, ecc->slot_inuse); |
2b6b3b74 PU |
535 | } |
536 | ||
537 | /** | |
538 | * edma_link - link one parameter RAM slot to another | |
539 | * @ecc: pointer to edma_cc struct | |
540 | * @from: parameter RAM slot originating the link | |
541 | * @to: parameter RAM slot which is the link target | |
542 | * | |
543 | * The originating slot should not be part of any active DMA transfer. | |
544 | */ | |
545 | static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) | |
546 | { | |
fc014095 PU |
547 | if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to))) |
548 | dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); | |
549 | ||
2b6b3b74 PU |
550 | from = EDMA_CHAN_SLOT(from); |
551 | to = EDMA_CHAN_SLOT(to); | |
552 | if (from >= ecc->num_slots || to >= ecc->num_slots) | |
553 | return; | |
554 | ||
d9c345d1 PU |
555 | edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, |
556 | PARM_OFFSET(to)); | |
2b6b3b74 PU |
557 | } |
558 | ||
559 | /** | |
560 | * edma_get_position - returns the current transfer point | |
561 | * @ecc: pointer to edma_cc struct | |
562 | * @slot: parameter RAM slot being examined | |
563 | * @dst: true selects the dest position, false the source | |
564 | * | |
565 | * Returns the position of the current active slot | |
566 | */ | |
567 | static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, | |
568 | bool dst) | |
569 | { | |
570 | u32 offs; | |
571 | ||
572 | slot = EDMA_CHAN_SLOT(slot); | |
573 | offs = PARM_OFFSET(slot); | |
574 | offs += dst ? PARM_DST : PARM_SRC; | |
575 | ||
576 | return edma_read(ecc, offs); | |
577 | } | |
578 | ||
34cf3011 | 579 | /* |
2b6b3b74 PU |
580 | * Channels with event associations will be triggered by their hardware |
581 | * events, and channels without such associations will be triggered by | |
582 | * software. (At this writing there is no interface for using software | |
583 | * triggers except with channels that don't support hardware triggers.) | |
2b6b3b74 | 584 | */ |
34cf3011 | 585 | static void edma_start(struct edma_chan *echan) |
2b6b3b74 | 586 | { |
34cf3011 PU |
587 | struct edma_cc *ecc = echan->ecc; |
588 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
589 | int j = (channel >> 5); | |
590 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 591 | |
1be5336b | 592 | if (!echan->hw_triggered) { |
2b6b3b74 | 593 | /* EDMA channels without event association */ |
34cf3011 PU |
594 | dev_dbg(ecc->dev, "ESR%d %08x\n", j, |
595 | edma_shadow0_read_array(ecc, SH_ESR, j)); | |
596 | edma_shadow0_write_array(ecc, SH_ESR, j, mask); | |
597 | } else { | |
2b6b3b74 | 598 | /* EDMA channel with event association */ |
3287fb4d PU |
599 | dev_dbg(ecc->dev, "ER%d %08x\n", j, |
600 | edma_shadow0_read_array(ecc, SH_ER, j)); | |
2b6b3b74 PU |
601 | /* Clear any pending event or error */ |
602 | edma_write_array(ecc, EDMA_ECR, j, mask); | |
603 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
604 | /* Clear any SER */ | |
605 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
606 | edma_shadow0_write_array(ecc, SH_EESR, j, mask); | |
3287fb4d PU |
607 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
608 | edma_shadow0_read_array(ecc, SH_EER, j)); | |
2b6b3b74 | 609 | } |
2b6b3b74 PU |
610 | } |
611 | ||
34cf3011 | 612 | static void edma_stop(struct edma_chan *echan) |
2b6b3b74 | 613 | { |
34cf3011 PU |
614 | struct edma_cc *ecc = echan->ecc; |
615 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
616 | int j = (channel >> 5); | |
617 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 618 | |
34cf3011 PU |
619 | edma_shadow0_write_array(ecc, SH_EECR, j, mask); |
620 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); | |
621 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
622 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
2b6b3b74 | 623 | |
34cf3011 PU |
624 | /* clear possibly pending completion interrupt */ |
625 | edma_shadow0_write_array(ecc, SH_ICR, j, mask); | |
2b6b3b74 | 626 | |
34cf3011 PU |
627 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
628 | edma_shadow0_read_array(ecc, SH_EER, j)); | |
2b6b3b74 | 629 | |
34cf3011 PU |
630 | /* REVISIT: consider guarding against inappropriate event |
631 | * chaining by overwriting with dummy_paramset. | |
632 | */ | |
2b6b3b74 PU |
633 | } |
634 | ||
11c15733 PU |
635 | /* |
636 | * Temporarily disable EDMA hardware events on the specified channel, | |
637 | * preventing them from triggering new transfers | |
2b6b3b74 | 638 | */ |
34cf3011 | 639 | static void edma_pause(struct edma_chan *echan) |
2b6b3b74 | 640 | { |
34cf3011 PU |
641 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
642 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 643 | |
34cf3011 | 644 | edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); |
2b6b3b74 PU |
645 | } |
646 | ||
11c15733 | 647 | /* Re-enable EDMA hardware events on the specified channel. */ |
34cf3011 | 648 | static void edma_resume(struct edma_chan *echan) |
2b6b3b74 | 649 | { |
34cf3011 PU |
650 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
651 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 652 | |
34cf3011 | 653 | edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); |
2b6b3b74 PU |
654 | } |
655 | ||
34cf3011 | 656 | static void edma_trigger_channel(struct edma_chan *echan) |
2b6b3b74 | 657 | { |
34cf3011 PU |
658 | struct edma_cc *ecc = echan->ecc; |
659 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
660 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 PU |
661 | |
662 | edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); | |
663 | ||
3287fb4d PU |
664 | dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), |
665 | edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); | |
2b6b3b74 PU |
666 | } |
667 | ||
34cf3011 | 668 | static void edma_clean_channel(struct edma_chan *echan) |
2b6b3b74 | 669 | { |
34cf3011 PU |
670 | struct edma_cc *ecc = echan->ecc; |
671 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
672 | int j = (channel >> 5); | |
673 | unsigned int mask = BIT(channel & 0x1f); | |
2b6b3b74 | 674 | |
34cf3011 PU |
675 | dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); |
676 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); | |
677 | /* Clear the corresponding EMR bits */ | |
678 | edma_write_array(ecc, EDMA_EMCR, j, mask); | |
679 | /* Clear any SER */ | |
680 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); | |
681 | edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); | |
2b6b3b74 PU |
682 | } |
683 | ||
f9425deb PU |
684 | /* Move channel to a specific event queue */ |
685 | static void edma_assign_channel_eventq(struct edma_chan *echan, | |
686 | enum dma_event_q eventq_no) | |
687 | { | |
688 | struct edma_cc *ecc = echan->ecc; | |
689 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
690 | int bit = (channel & 0x7) * 4; | |
691 | ||
692 | /* default to low priority queue */ | |
693 | if (eventq_no == EVENTQ_DEFAULT) | |
694 | eventq_no = ecc->default_queue; | |
695 | if (eventq_no >= ecc->num_tc) | |
696 | return; | |
697 | ||
698 | eventq_no &= 7; | |
699 | edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), | |
700 | eventq_no << bit); | |
701 | } | |
702 | ||
34cf3011 | 703 | static int edma_alloc_channel(struct edma_chan *echan, |
79ad2e38 | 704 | enum dma_event_q eventq_no) |
2b6b3b74 | 705 | { |
34cf3011 PU |
706 | struct edma_cc *ecc = echan->ecc; |
707 | int channel = EDMA_CHAN_SLOT(echan->ch_num); | |
2b6b3b74 | 708 | |
2b6b3b74 PU |
709 | /* ensure access through shadow region 0 */ |
710 | edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); | |
711 | ||
712 | /* ensure no events are pending */ | |
34cf3011 | 713 | edma_stop(echan); |
2b6b3b74 | 714 | |
34cf3011 | 715 | edma_setup_interrupt(echan, true); |
2b6b3b74 | 716 | |
f9425deb | 717 | edma_assign_channel_eventq(echan, eventq_no); |
2b6b3b74 | 718 | |
34cf3011 | 719 | return 0; |
2b6b3b74 PU |
720 | } |
721 | ||
34cf3011 | 722 | static void edma_free_channel(struct edma_chan *echan) |
2b6b3b74 | 723 | { |
34cf3011 PU |
724 | /* ensure no events are pending */ |
725 | edma_stop(echan); | |
2b6b3b74 | 726 | /* REVISIT should probably take out of shadow region 0 */ |
34cf3011 | 727 | edma_setup_interrupt(echan, false); |
2b6b3b74 PU |
728 | } |
729 | ||
c2dde5f8 MP |
730 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) |
731 | { | |
732 | return container_of(d, struct edma_cc, dma_slave); | |
733 | } | |
734 | ||
735 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
736 | { | |
737 | return container_of(c, struct edma_chan, vchan.chan); | |
738 | } | |
739 | ||
2b6b3b74 | 740 | static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) |
c2dde5f8 MP |
741 | { |
742 | return container_of(tx, struct edma_desc, vdesc.tx); | |
743 | } | |
744 | ||
745 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
746 | { | |
747 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
748 | } | |
749 | ||
750 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
751 | static void edma_execute(struct edma_chan *echan) | |
752 | { | |
2b6b3b74 | 753 | struct edma_cc *ecc = echan->ecc; |
53407062 | 754 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 755 | struct edma_desc *edesc; |
53407062 JF |
756 | struct device *dev = echan->vchan.chan.device->dev; |
757 | int i, j, left, nslots; | |
758 | ||
8fa7ff4f PU |
759 | if (!echan->edesc) { |
760 | /* Setup is needed for the first transfer */ | |
53407062 | 761 | vdesc = vchan_next_desc(&echan->vchan); |
8fa7ff4f | 762 | if (!vdesc) |
53407062 | 763 | return; |
53407062 JF |
764 | list_del(&vdesc->node); |
765 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
766 | } |
767 | ||
53407062 | 768 | edesc = echan->edesc; |
c2dde5f8 | 769 | |
53407062 JF |
770 | /* Find out how many left */ |
771 | left = edesc->pset_nr - edesc->processed; | |
772 | nslots = min(MAX_NR_SG, left); | |
740b41f7 | 773 | edesc->sg_len = 0; |
c2dde5f8 MP |
774 | |
775 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
776 | for (i = 0; i < nslots; i++) { |
777 | j = i + edesc->processed; | |
2b6b3b74 | 778 | edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); |
740b41f7 | 779 | edesc->sg_len += edesc->pset[j].len; |
907f74a0 PU |
780 | dev_vdbg(dev, |
781 | "\n pset[%d]:\n" | |
782 | " chnum\t%d\n" | |
783 | " slot\t%d\n" | |
784 | " opt\t%08x\n" | |
785 | " src\t%08x\n" | |
786 | " dst\t%08x\n" | |
787 | " abcnt\t%08x\n" | |
788 | " ccnt\t%08x\n" | |
789 | " bidx\t%08x\n" | |
790 | " cidx\t%08x\n" | |
791 | " lkrld\t%08x\n", | |
792 | j, echan->ch_num, echan->slot[i], | |
793 | edesc->pset[j].param.opt, | |
794 | edesc->pset[j].param.src, | |
795 | edesc->pset[j].param.dst, | |
796 | edesc->pset[j].param.a_b_cnt, | |
797 | edesc->pset[j].param.ccnt, | |
798 | edesc->pset[j].param.src_dst_bidx, | |
799 | edesc->pset[j].param.src_dst_cidx, | |
800 | edesc->pset[j].param.link_bcntrld); | |
c2dde5f8 | 801 | /* Link to the previous slot if not the last set */ |
53407062 | 802 | if (i != (nslots - 1)) |
2b6b3b74 | 803 | edma_link(ecc, echan->slot[i], echan->slot[i + 1]); |
c2dde5f8 MP |
804 | } |
805 | ||
53407062 JF |
806 | edesc->processed += nslots; |
807 | ||
b267b3bc JF |
808 | /* |
809 | * If this is either the last set in a set of SG-list transactions | |
810 | * then setup a link to the dummy slot, this results in all future | |
811 | * events being absorbed and that's OK because we're done | |
812 | */ | |
50a9c707 JF |
813 | if (edesc->processed == edesc->pset_nr) { |
814 | if (edesc->cyclic) | |
2b6b3b74 | 815 | edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); |
50a9c707 | 816 | else |
2b6b3b74 | 817 | edma_link(ecc, echan->slot[nslots - 1], |
50a9c707 JF |
818 | echan->ecc->dummy_slot); |
819 | } | |
b267b3bc | 820 | |
c5f47990 | 821 | if (echan->missed) { |
8fa7ff4f PU |
822 | /* |
823 | * This happens due to setup times between intermediate | |
824 | * transfers in long SG lists which have to be broken up into | |
825 | * transfers of MAX_NR_SG | |
826 | */ | |
9aac9096 | 827 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
34cf3011 PU |
828 | edma_clean_channel(echan); |
829 | edma_stop(echan); | |
830 | edma_start(echan); | |
831 | edma_trigger_channel(echan); | |
c5f47990 | 832 | echan->missed = 0; |
8fa7ff4f PU |
833 | } else if (edesc->processed <= MAX_NR_SG) { |
834 | dev_dbg(dev, "first transfer starting on channel %d\n", | |
835 | echan->ch_num); | |
34cf3011 | 836 | edma_start(echan); |
8fa7ff4f PU |
837 | } else { |
838 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
839 | echan->ch_num, edesc->processed); | |
34cf3011 | 840 | edma_resume(echan); |
c5f47990 | 841 | } |
c2dde5f8 MP |
842 | } |
843 | ||
aa7c09b6 | 844 | static int edma_terminate_all(struct dma_chan *chan) |
c2dde5f8 | 845 | { |
aa7c09b6 | 846 | struct edma_chan *echan = to_edma_chan(chan); |
c2dde5f8 MP |
847 | unsigned long flags; |
848 | LIST_HEAD(head); | |
849 | ||
850 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
851 | ||
852 | /* | |
853 | * Stop DMA activity: we assume the callback will not be called | |
854 | * after edma_dma() returns (even if it does, it will see | |
855 | * echan->edesc is NULL and exit.) | |
856 | */ | |
857 | if (echan->edesc) { | |
34cf3011 | 858 | edma_stop(echan); |
8fa7ff4f | 859 | /* Move the cyclic channel back to default queue */ |
1be5336b | 860 | if (!echan->tc && echan->edesc->cyclic) |
34cf3011 | 861 | edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); |
5ca9e7ce PK |
862 | /* |
863 | * free the running request descriptor | |
864 | * since it is not in any of the vdesc lists | |
865 | */ | |
866 | edma_desc_free(&echan->edesc->vdesc); | |
c2dde5f8 | 867 | echan->edesc = NULL; |
c2dde5f8 MP |
868 | } |
869 | ||
870 | vchan_get_all_descriptors(&echan->vchan, &head); | |
871 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
872 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
b84730ff PU |
877 | static void edma_synchronize(struct dma_chan *chan) |
878 | { | |
879 | struct edma_chan *echan = to_edma_chan(chan); | |
880 | ||
881 | vchan_synchronize(&echan->vchan); | |
882 | } | |
883 | ||
aa7c09b6 | 884 | static int edma_slave_config(struct dma_chan *chan, |
661f7cb5 | 885 | struct dma_slave_config *cfg) |
c2dde5f8 | 886 | { |
aa7c09b6 MR |
887 | struct edma_chan *echan = to_edma_chan(chan); |
888 | ||
661f7cb5 MP |
889 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
890 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
891 | return -EINVAL; |
892 | ||
661f7cb5 | 893 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
894 | |
895 | return 0; | |
896 | } | |
897 | ||
aa7c09b6 | 898 | static int edma_dma_pause(struct dma_chan *chan) |
72c7b67a | 899 | { |
aa7c09b6 MR |
900 | struct edma_chan *echan = to_edma_chan(chan); |
901 | ||
02ec6041 | 902 | if (!echan->edesc) |
72c7b67a PU |
903 | return -EINVAL; |
904 | ||
34cf3011 | 905 | edma_pause(echan); |
72c7b67a PU |
906 | return 0; |
907 | } | |
908 | ||
aa7c09b6 | 909 | static int edma_dma_resume(struct dma_chan *chan) |
72c7b67a | 910 | { |
aa7c09b6 MR |
911 | struct edma_chan *echan = to_edma_chan(chan); |
912 | ||
34cf3011 | 913 | edma_resume(echan); |
72c7b67a PU |
914 | return 0; |
915 | } | |
916 | ||
fd009035 JF |
917 | /* |
918 | * A PaRAM set configuration abstraction used by other modes | |
919 | * @chan: Channel who's PaRAM set we're configuring | |
920 | * @pset: PaRAM set to initialize and setup. | |
921 | * @src_addr: Source address of the DMA | |
922 | * @dst_addr: Destination address of the DMA | |
923 | * @burst: In units of dev_width, how much to send | |
924 | * @dev_width: How much is the dev_width | |
925 | * @dma_length: Total length of the DMA transfer | |
926 | * @direction: Direction of the transfer | |
927 | */ | |
b5088ad9 | 928 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
2b6b3b74 | 929 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
df6694f8 | 930 | unsigned int acnt, unsigned int dma_length, |
2b6b3b74 | 931 | enum dma_transfer_direction direction) |
fd009035 JF |
932 | { |
933 | struct edma_chan *echan = to_edma_chan(chan); | |
934 | struct device *dev = chan->device->dev; | |
b5088ad9 | 935 | struct edmacc_param *param = &epset->param; |
df6694f8 | 936 | int bcnt, ccnt, cidx; |
fd009035 JF |
937 | int src_bidx, dst_bidx, src_cidx, dst_cidx; |
938 | int absync; | |
939 | ||
b2b617de PU |
940 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ |
941 | if (!burst) | |
942 | burst = 1; | |
fd009035 JF |
943 | /* |
944 | * If the maxburst is equal to the fifo width, use | |
945 | * A-synced transfers. This allows for large contiguous | |
946 | * buffer transfers using only one PaRAM set. | |
947 | */ | |
948 | if (burst == 1) { | |
949 | /* | |
950 | * For the A-sync case, bcnt and ccnt are the remainder | |
951 | * and quotient respectively of the division of: | |
952 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
953 | * that in case bcnt over flows, we have ccnt to use. | |
954 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
955 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
956 | * In this case, the best way adopted is- bccnt for the | |
957 | * first frame will be the remainder below. Then for | |
958 | * every successive frame, bcnt will be SZ_64K-1. This | |
959 | * is assured as bcntrld = 0xffff in end of function. | |
960 | */ | |
961 | absync = false; | |
962 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
963 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
964 | /* | |
965 | * If bcnt is non-zero, we have a remainder and hence an | |
966 | * extra frame to transfer, so increment ccnt. | |
967 | */ | |
968 | if (bcnt) | |
969 | ccnt++; | |
970 | else | |
971 | bcnt = SZ_64K - 1; | |
972 | cidx = acnt; | |
973 | } else { | |
974 | /* | |
975 | * If maxburst is greater than the fifo address_width, | |
976 | * use AB-synced transfers where A count is the fifo | |
977 | * address_width and B count is the maxburst. In this | |
978 | * case, we are limited to transfers of C count frames | |
979 | * of (address_width * maxburst) where C count is limited | |
980 | * to SZ_64K-1. This places an upper bound on the length | |
981 | * of an SG segment that can be handled. | |
982 | */ | |
983 | absync = true; | |
984 | bcnt = burst; | |
985 | ccnt = dma_length / (acnt * bcnt); | |
986 | if (ccnt > (SZ_64K - 1)) { | |
987 | dev_err(dev, "Exceeded max SG segment size\n"); | |
988 | return -EINVAL; | |
989 | } | |
990 | cidx = acnt * bcnt; | |
991 | } | |
992 | ||
c2da2340 TG |
993 | epset->len = dma_length; |
994 | ||
fd009035 JF |
995 | if (direction == DMA_MEM_TO_DEV) { |
996 | src_bidx = acnt; | |
997 | src_cidx = cidx; | |
998 | dst_bidx = 0; | |
999 | dst_cidx = 0; | |
c2da2340 | 1000 | epset->addr = src_addr; |
fd009035 JF |
1001 | } else if (direction == DMA_DEV_TO_MEM) { |
1002 | src_bidx = 0; | |
1003 | src_cidx = 0; | |
1004 | dst_bidx = acnt; | |
1005 | dst_cidx = cidx; | |
c2da2340 | 1006 | epset->addr = dst_addr; |
8cc3e30b JF |
1007 | } else if (direction == DMA_MEM_TO_MEM) { |
1008 | src_bidx = acnt; | |
1009 | src_cidx = cidx; | |
1010 | dst_bidx = acnt; | |
1011 | dst_cidx = cidx; | |
fd009035 JF |
1012 | } else { |
1013 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
1014 | return -EINVAL; | |
1015 | } | |
1016 | ||
b5088ad9 | 1017 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
fd009035 JF |
1018 | /* Configure A or AB synchronized transfers */ |
1019 | if (absync) | |
b5088ad9 | 1020 | param->opt |= SYNCDIM; |
fd009035 | 1021 | |
b5088ad9 TG |
1022 | param->src = src_addr; |
1023 | param->dst = dst_addr; | |
fd009035 | 1024 | |
b5088ad9 TG |
1025 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
1026 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
fd009035 | 1027 | |
b5088ad9 TG |
1028 | param->a_b_cnt = bcnt << 16 | acnt; |
1029 | param->ccnt = ccnt; | |
fd009035 JF |
1030 | /* |
1031 | * Only time when (bcntrld) auto reload is required is for | |
1032 | * A-sync case, and in this case, a requirement of reload value | |
1033 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
1034 | * and then later will be populated by edma_execute. | |
1035 | */ | |
b5088ad9 | 1036 | param->link_bcntrld = 0xffffffff; |
fd009035 JF |
1037 | return absync; |
1038 | } | |
1039 | ||
c2dde5f8 MP |
1040 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
1041 | struct dma_chan *chan, struct scatterlist *sgl, | |
1042 | unsigned int sg_len, enum dma_transfer_direction direction, | |
1043 | unsigned long tx_flags, void *context) | |
1044 | { | |
1045 | struct edma_chan *echan = to_edma_chan(chan); | |
1046 | struct device *dev = chan->device->dev; | |
1047 | struct edma_desc *edesc; | |
fd009035 | 1048 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
1049 | enum dma_slave_buswidth dev_width; |
1050 | u32 burst; | |
c2dde5f8 | 1051 | struct scatterlist *sg; |
fd009035 | 1052 | int i, nslots, ret; |
c2dde5f8 MP |
1053 | |
1054 | if (unlikely(!echan || !sgl || !sg_len)) | |
1055 | return NULL; | |
1056 | ||
661f7cb5 | 1057 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 1058 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
1059 | dev_width = echan->cfg.src_addr_width; |
1060 | burst = echan->cfg.src_maxburst; | |
1061 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 1062 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
1063 | dev_width = echan->cfg.dst_addr_width; |
1064 | burst = echan->cfg.dst_maxburst; | |
1065 | } else { | |
e6fad592 | 1066 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
661f7cb5 MP |
1067 | return NULL; |
1068 | } | |
1069 | ||
1070 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 1071 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
1072 | return NULL; |
1073 | } | |
1074 | ||
2b6b3b74 PU |
1075 | edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]), |
1076 | GFP_ATOMIC); | |
aef94fea | 1077 | if (!edesc) |
c2dde5f8 | 1078 | return NULL; |
c2dde5f8 MP |
1079 | |
1080 | edesc->pset_nr = sg_len; | |
b6205c39 | 1081 | edesc->residue = 0; |
c2da2340 | 1082 | edesc->direction = direction; |
740b41f7 | 1083 | edesc->echan = echan; |
c2dde5f8 | 1084 | |
6fbe24da JF |
1085 | /* Allocate a PaRAM slot, if needed */ |
1086 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
1087 | ||
1088 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
1089 | if (echan->slot[i] < 0) { |
1090 | echan->slot[i] = | |
2b6b3b74 | 1091 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
c2dde5f8 | 1092 | if (echan->slot[i] < 0) { |
4b6271a6 | 1093 | kfree(edesc); |
c594c891 PU |
1094 | dev_err(dev, "%s: Failed to allocate slot\n", |
1095 | __func__); | |
c2dde5f8 MP |
1096 | return NULL; |
1097 | } | |
1098 | } | |
6fbe24da JF |
1099 | } |
1100 | ||
1101 | /* Configure PaRAM sets for each SG */ | |
1102 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
1103 | /* Get address for each SG */ |
1104 | if (direction == DMA_DEV_TO_MEM) | |
1105 | dst_addr = sg_dma_address(sg); | |
1106 | else | |
1107 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 1108 | |
fd009035 JF |
1109 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
1110 | dst_addr, burst, dev_width, | |
1111 | sg_dma_len(sg), direction); | |
b967aecf VK |
1112 | if (ret < 0) { |
1113 | kfree(edesc); | |
fd009035 | 1114 | return NULL; |
c2dde5f8 MP |
1115 | } |
1116 | ||
fd009035 | 1117 | edesc->absync = ret; |
b6205c39 | 1118 | edesc->residue += sg_dma_len(sg); |
6fbe24da | 1119 | |
c2dde5f8 | 1120 | if (i == sg_len - 1) |
2e4ed087 | 1121 | /* Enable completion interrupt */ |
b5088ad9 | 1122 | edesc->pset[i].param.opt |= TCINTEN; |
2e4ed087 PU |
1123 | else if (!((i+1) % MAX_NR_SG)) |
1124 | /* | |
1125 | * Enable early completion interrupt for the | |
1126 | * intermediateset. In this case the driver will be | |
1127 | * notified when the paRAM set is submitted to TC. This | |
1128 | * will allow more time to set up the next set of slots. | |
1129 | */ | |
1130 | edesc->pset[i].param.opt |= (TCINTEN | TCCMODE); | |
c2dde5f8 | 1131 | } |
740b41f7 | 1132 | edesc->residue_stat = edesc->residue; |
c2dde5f8 | 1133 | |
c2dde5f8 MP |
1134 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
1135 | } | |
c2dde5f8 | 1136 | |
b7a4fd53 | 1137 | static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
8cc3e30b JF |
1138 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
1139 | size_t len, unsigned long tx_flags) | |
1140 | { | |
df6694f8 | 1141 | int ret, nslots; |
8cc3e30b JF |
1142 | struct edma_desc *edesc; |
1143 | struct device *dev = chan->device->dev; | |
1144 | struct edma_chan *echan = to_edma_chan(chan); | |
df6694f8 | 1145 | unsigned int width, pset_len; |
8cc3e30b JF |
1146 | |
1147 | if (unlikely(!echan || !len)) | |
1148 | return NULL; | |
1149 | ||
df6694f8 PU |
1150 | if (len < SZ_64K) { |
1151 | /* | |
1152 | * Transfer size less than 64K can be handled with one paRAM | |
1153 | * slot and with one burst. | |
1154 | * ACNT = length | |
1155 | */ | |
1156 | width = len; | |
1157 | pset_len = len; | |
1158 | nslots = 1; | |
1159 | } else { | |
1160 | /* | |
1161 | * Transfer size bigger than 64K will be handled with maximum of | |
1162 | * two paRAM slots. | |
1163 | * slot1: (full_length / 32767) times 32767 bytes bursts. | |
1164 | * ACNT = 32767, length1: (full_length / 32767) * 32767 | |
1165 | * slot2: the remaining amount of data after slot1. | |
1166 | * ACNT = full_length - length1, length2 = ACNT | |
1167 | * | |
1168 | * When the full_length is multibple of 32767 one slot can be | |
1169 | * used to complete the transfer. | |
1170 | */ | |
1171 | width = SZ_32K - 1; | |
1172 | pset_len = rounddown(len, width); | |
1173 | /* One slot is enough for lengths multiple of (SZ_32K -1) */ | |
1174 | if (unlikely(pset_len == len)) | |
1175 | nslots = 1; | |
1176 | else | |
1177 | nslots = 2; | |
1178 | } | |
1179 | ||
1180 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), | |
1181 | GFP_ATOMIC); | |
aef94fea | 1182 | if (!edesc) |
8cc3e30b | 1183 | return NULL; |
8cc3e30b | 1184 | |
df6694f8 PU |
1185 | edesc->pset_nr = nslots; |
1186 | edesc->residue = edesc->residue_stat = len; | |
1187 | edesc->direction = DMA_MEM_TO_MEM; | |
1188 | edesc->echan = echan; | |
21a31846 | 1189 | |
8cc3e30b | 1190 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, |
df6694f8 PU |
1191 | width, pset_len, DMA_MEM_TO_MEM); |
1192 | if (ret < 0) { | |
1193 | kfree(edesc); | |
8cc3e30b | 1194 | return NULL; |
df6694f8 | 1195 | } |
8cc3e30b JF |
1196 | |
1197 | edesc->absync = ret; | |
1198 | ||
b0cce4ca | 1199 | edesc->pset[0].param.opt |= ITCCHEN; |
df6694f8 PU |
1200 | if (nslots == 1) { |
1201 | /* Enable transfer complete interrupt */ | |
1202 | edesc->pset[0].param.opt |= TCINTEN; | |
1203 | } else { | |
1204 | /* Enable transfer complete chaining for the first slot */ | |
1205 | edesc->pset[0].param.opt |= TCCHEN; | |
1206 | ||
1207 | if (echan->slot[1] < 0) { | |
1208 | echan->slot[1] = edma_alloc_slot(echan->ecc, | |
1209 | EDMA_SLOT_ANY); | |
1210 | if (echan->slot[1] < 0) { | |
1211 | kfree(edesc); | |
1212 | dev_err(dev, "%s: Failed to allocate slot\n", | |
1213 | __func__); | |
1214 | return NULL; | |
1215 | } | |
1216 | } | |
1217 | dest += pset_len; | |
1218 | src += pset_len; | |
1219 | pset_len = width = len % (SZ_32K - 1); | |
1220 | ||
1221 | ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, | |
1222 | width, pset_len, DMA_MEM_TO_MEM); | |
1223 | if (ret < 0) { | |
1224 | kfree(edesc); | |
1225 | return NULL; | |
1226 | } | |
1227 | ||
1228 | edesc->pset[1].param.opt |= ITCCHEN; | |
1229 | edesc->pset[1].param.opt |= TCINTEN; | |
1230 | } | |
8cc3e30b JF |
1231 | |
1232 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
1233 | } | |
1234 | ||
50a9c707 JF |
1235 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
1236 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
1237 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 1238 | unsigned long tx_flags) |
50a9c707 JF |
1239 | { |
1240 | struct edma_chan *echan = to_edma_chan(chan); | |
1241 | struct device *dev = chan->device->dev; | |
1242 | struct edma_desc *edesc; | |
1243 | dma_addr_t src_addr, dst_addr; | |
1244 | enum dma_slave_buswidth dev_width; | |
a482f4e0 | 1245 | bool use_intermediate = false; |
50a9c707 JF |
1246 | u32 burst; |
1247 | int i, ret, nslots; | |
1248 | ||
1249 | if (unlikely(!echan || !buf_len || !period_len)) | |
1250 | return NULL; | |
1251 | ||
1252 | if (direction == DMA_DEV_TO_MEM) { | |
1253 | src_addr = echan->cfg.src_addr; | |
1254 | dst_addr = buf_addr; | |
1255 | dev_width = echan->cfg.src_addr_width; | |
1256 | burst = echan->cfg.src_maxburst; | |
1257 | } else if (direction == DMA_MEM_TO_DEV) { | |
1258 | src_addr = buf_addr; | |
1259 | dst_addr = echan->cfg.dst_addr; | |
1260 | dev_width = echan->cfg.dst_addr_width; | |
1261 | burst = echan->cfg.dst_maxburst; | |
1262 | } else { | |
e6fad592 | 1263 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
50a9c707 JF |
1264 | return NULL; |
1265 | } | |
1266 | ||
1267 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 1268 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
1269 | return NULL; |
1270 | } | |
1271 | ||
1272 | if (unlikely(buf_len % period_len)) { | |
1273 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
1274 | return NULL; | |
1275 | } | |
1276 | ||
1277 | nslots = (buf_len / period_len) + 1; | |
1278 | ||
1279 | /* | |
1280 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
1281 | * by cases where the number of periods is more than the maximum | |
1282 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
1283 | * such as Slave SGs, such delays are tolerable and synchronized, | |
1284 | * but the synchronization is difficult to achieve with Cyclic and | |
1285 | * cannot be guaranteed, so we error out early. | |
1286 | */ | |
a482f4e0 JO |
1287 | if (nslots > MAX_NR_SG) { |
1288 | /* | |
1289 | * If the burst and period sizes are the same, we can put | |
1290 | * the full buffer into a single period and activate | |
1291 | * intermediate interrupts. This will produce interrupts | |
1292 | * after each burst, which is also after each desired period. | |
1293 | */ | |
1294 | if (burst == period_len) { | |
1295 | period_len = buf_len; | |
1296 | nslots = 2; | |
1297 | use_intermediate = true; | |
1298 | } else { | |
1299 | return NULL; | |
1300 | } | |
1301 | } | |
50a9c707 | 1302 | |
2b6b3b74 PU |
1303 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), |
1304 | GFP_ATOMIC); | |
aef94fea | 1305 | if (!edesc) |
50a9c707 | 1306 | return NULL; |
50a9c707 JF |
1307 | |
1308 | edesc->cyclic = 1; | |
1309 | edesc->pset_nr = nslots; | |
740b41f7 | 1310 | edesc->residue = edesc->residue_stat = buf_len; |
c2da2340 | 1311 | edesc->direction = direction; |
740b41f7 | 1312 | edesc->echan = echan; |
50a9c707 | 1313 | |
83bb3126 PU |
1314 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
1315 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
1316 | |
1317 | for (i = 0; i < nslots; i++) { | |
1318 | /* Allocate a PaRAM slot, if needed */ | |
1319 | if (echan->slot[i] < 0) { | |
1320 | echan->slot[i] = | |
2b6b3b74 | 1321 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
50a9c707 | 1322 | if (echan->slot[i] < 0) { |
e3ddc979 | 1323 | kfree(edesc); |
c594c891 PU |
1324 | dev_err(dev, "%s: Failed to allocate slot\n", |
1325 | __func__); | |
50a9c707 JF |
1326 | return NULL; |
1327 | } | |
1328 | } | |
1329 | ||
1330 | if (i == nslots - 1) { | |
1331 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
1332 | sizeof(edesc->pset[0])); | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
1337 | dst_addr, burst, dev_width, period_len, | |
1338 | direction); | |
e3ddc979 CE |
1339 | if (ret < 0) { |
1340 | kfree(edesc); | |
50a9c707 | 1341 | return NULL; |
e3ddc979 | 1342 | } |
c2dde5f8 | 1343 | |
50a9c707 JF |
1344 | if (direction == DMA_DEV_TO_MEM) |
1345 | dst_addr += period_len; | |
1346 | else | |
1347 | src_addr += period_len; | |
c2dde5f8 | 1348 | |
83bb3126 PU |
1349 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
1350 | dev_vdbg(dev, | |
50a9c707 JF |
1351 | "\n pset[%d]:\n" |
1352 | " chnum\t%d\n" | |
1353 | " slot\t%d\n" | |
1354 | " opt\t%08x\n" | |
1355 | " src\t%08x\n" | |
1356 | " dst\t%08x\n" | |
1357 | " abcnt\t%08x\n" | |
1358 | " ccnt\t%08x\n" | |
1359 | " bidx\t%08x\n" | |
1360 | " cidx\t%08x\n" | |
1361 | " lkrld\t%08x\n", | |
1362 | i, echan->ch_num, echan->slot[i], | |
b5088ad9 TG |
1363 | edesc->pset[i].param.opt, |
1364 | edesc->pset[i].param.src, | |
1365 | edesc->pset[i].param.dst, | |
1366 | edesc->pset[i].param.a_b_cnt, | |
1367 | edesc->pset[i].param.ccnt, | |
1368 | edesc->pset[i].param.src_dst_bidx, | |
1369 | edesc->pset[i].param.src_dst_cidx, | |
1370 | edesc->pset[i].param.link_bcntrld); | |
50a9c707 JF |
1371 | |
1372 | edesc->absync = ret; | |
1373 | ||
1374 | /* | |
a1f146f3 | 1375 | * Enable period interrupt only if it is requested |
50a9c707 | 1376 | */ |
a482f4e0 | 1377 | if (tx_flags & DMA_PREP_INTERRUPT) { |
a1f146f3 | 1378 | edesc->pset[i].param.opt |= TCINTEN; |
a482f4e0 JO |
1379 | |
1380 | /* Also enable intermediate interrupts if necessary */ | |
1381 | if (use_intermediate) | |
1382 | edesc->pset[i].param.opt |= ITCINTEN; | |
1383 | } | |
c2dde5f8 MP |
1384 | } |
1385 | ||
8e8805d5 | 1386 | /* Place the cyclic channel to highest priority queue */ |
1be5336b PU |
1387 | if (!echan->tc) |
1388 | edma_assign_channel_eventq(echan, EVENTQ_0); | |
8e8805d5 | 1389 | |
c2dde5f8 MP |
1390 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
1391 | } | |
1392 | ||
79ad2e38 | 1393 | static void edma_completion_handler(struct edma_chan *echan) |
c2dde5f8 | 1394 | { |
c2dde5f8 | 1395 | struct device *dev = echan->vchan.chan.device->dev; |
e4d8817c | 1396 | struct edma_desc *edesc; |
50a9c707 | 1397 | |
8fa7ff4f | 1398 | spin_lock(&echan->vchan.lock); |
e4d8817c PU |
1399 | edesc = echan->edesc; |
1400 | if (edesc) { | |
1401 | if (edesc->cyclic) { | |
1402 | vchan_cyclic_callback(&edesc->vdesc); | |
1403 | spin_unlock(&echan->vchan.lock); | |
1404 | return; | |
1405 | } else if (edesc->processed == edesc->pset_nr) { | |
1406 | edesc->residue = 0; | |
1407 | edma_stop(echan); | |
1408 | vchan_cookie_complete(&edesc->vdesc); | |
1409 | echan->edesc = NULL; | |
1410 | ||
1411 | dev_dbg(dev, "Transfer completed on channel %d\n", | |
1412 | echan->ch_num); | |
1413 | } else { | |
1414 | dev_dbg(dev, "Sub transfer completed on channel %d\n", | |
1415 | echan->ch_num); | |
1416 | ||
1417 | edma_pause(echan); | |
1418 | ||
1419 | /* Update statistics for tx_status */ | |
1420 | edesc->residue -= edesc->sg_len; | |
1421 | edesc->residue_stat = edesc->residue; | |
1422 | edesc->processed_stat = edesc->processed; | |
1423 | } | |
1424 | edma_execute(echan); | |
79ad2e38 | 1425 | } |
79ad2e38 PU |
1426 | |
1427 | spin_unlock(&echan->vchan.lock); | |
1428 | } | |
1429 | ||
1430 | /* eDMA interrupt handler */ | |
1431 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
1432 | { | |
1433 | struct edma_cc *ecc = data; | |
1434 | int ctlr; | |
1435 | u32 sh_ier; | |
1436 | u32 sh_ipr; | |
1437 | u32 bank; | |
1438 | ||
1439 | ctlr = ecc->id; | |
1440 | if (ctlr < 0) | |
1441 | return IRQ_NONE; | |
1442 | ||
1443 | dev_vdbg(ecc->dev, "dma_irq_handler\n"); | |
1444 | ||
1445 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); | |
1446 | if (!sh_ipr) { | |
1447 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); | |
1448 | if (!sh_ipr) | |
1449 | return IRQ_NONE; | |
1450 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); | |
1451 | bank = 1; | |
1452 | } else { | |
1453 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); | |
1454 | bank = 0; | |
1455 | } | |
1456 | ||
1457 | do { | |
1458 | u32 slot; | |
1459 | u32 channel; | |
1460 | ||
1461 | slot = __ffs(sh_ipr); | |
1462 | sh_ipr &= ~(BIT(slot)); | |
1463 | ||
1464 | if (sh_ier & BIT(slot)) { | |
1465 | channel = (bank << 5) | slot; | |
1466 | /* Clear the corresponding IPR bits */ | |
1467 | edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); | |
1468 | edma_completion_handler(&ecc->slave_chans[channel]); | |
c2dde5f8 | 1469 | } |
79ad2e38 PU |
1470 | } while (sh_ipr); |
1471 | ||
1472 | edma_shadow0_write(ecc, SH_IEVAL, 1); | |
1473 | return IRQ_HANDLED; | |
1474 | } | |
1475 | ||
1476 | static void edma_error_handler(struct edma_chan *echan) | |
1477 | { | |
1478 | struct edma_cc *ecc = echan->ecc; | |
1479 | struct device *dev = echan->vchan.chan.device->dev; | |
1480 | struct edmacc_param p; | |
1481 | ||
1482 | if (!echan->edesc) | |
1483 | return; | |
1484 | ||
1485 | spin_lock(&echan->vchan.lock); | |
c5f47990 | 1486 | |
79ad2e38 PU |
1487 | edma_read_slot(ecc, echan->slot[0], &p); |
1488 | /* | |
1489 | * Issue later based on missed flag which will be sure | |
1490 | * to happen as: | |
1491 | * (1) we finished transmitting an intermediate slot and | |
1492 | * edma_execute is coming up. | |
1493 | * (2) or we finished current transfer and issue will | |
1494 | * call edma_execute. | |
1495 | * | |
1496 | * Important note: issuing can be dangerous here and | |
1497 | * lead to some nasty recursion when we are in a NULL | |
1498 | * slot. So we avoid doing so and set the missed flag. | |
1499 | */ | |
1500 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
1501 | dev_dbg(dev, "Error on null slot, setting miss\n"); | |
1502 | echan->missed = 1; | |
1503 | } else { | |
c5f47990 | 1504 | /* |
79ad2e38 PU |
1505 | * The slot is already programmed but the event got |
1506 | * missed, so its safe to issue it here. | |
c5f47990 | 1507 | */ |
79ad2e38 | 1508 | dev_dbg(dev, "Missed event, TRIGGERING\n"); |
34cf3011 PU |
1509 | edma_clean_channel(echan); |
1510 | edma_stop(echan); | |
1511 | edma_start(echan); | |
1512 | edma_trigger_channel(echan); | |
79ad2e38 PU |
1513 | } |
1514 | spin_unlock(&echan->vchan.lock); | |
1515 | } | |
1516 | ||
7c3b8b3d PU |
1517 | static inline bool edma_error_pending(struct edma_cc *ecc) |
1518 | { | |
1519 | if (edma_read_array(ecc, EDMA_EMR, 0) || | |
1520 | edma_read_array(ecc, EDMA_EMR, 1) || | |
1521 | edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) | |
1522 | return true; | |
1523 | ||
1524 | return false; | |
1525 | } | |
1526 | ||
79ad2e38 PU |
1527 | /* eDMA error interrupt handler */ |
1528 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
1529 | { | |
1530 | struct edma_cc *ecc = data; | |
e4402a12 | 1531 | int i, j; |
79ad2e38 PU |
1532 | int ctlr; |
1533 | unsigned int cnt = 0; | |
e4402a12 | 1534 | unsigned int val; |
79ad2e38 PU |
1535 | |
1536 | ctlr = ecc->id; | |
1537 | if (ctlr < 0) | |
1538 | return IRQ_NONE; | |
1539 | ||
1540 | dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); | |
1541 | ||
3b2bc8a7 PU |
1542 | if (!edma_error_pending(ecc)) { |
1543 | /* | |
1544 | * The registers indicate no pending error event but the irq | |
1545 | * handler has been called. | |
1546 | * Ask eDMA to re-evaluate the error registers. | |
1547 | */ | |
1548 | dev_err(ecc->dev, "%s: Error interrupt without error event!\n", | |
1549 | __func__); | |
1550 | edma_write(ecc, EDMA_EEVAL, 1); | |
79ad2e38 | 1551 | return IRQ_NONE; |
3b2bc8a7 | 1552 | } |
79ad2e38 PU |
1553 | |
1554 | while (1) { | |
e4402a12 PU |
1555 | /* Event missed register(s) */ |
1556 | for (j = 0; j < 2; j++) { | |
1557 | unsigned long emr; | |
1558 | ||
1559 | val = edma_read_array(ecc, EDMA_EMR, j); | |
1560 | if (!val) | |
1561 | continue; | |
1562 | ||
1563 | dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); | |
1564 | emr = val; | |
1565 | for (i = find_next_bit(&emr, 32, 0); i < 32; | |
1566 | i = find_next_bit(&emr, 32, i + 1)) { | |
79ad2e38 PU |
1567 | int k = (j << 5) + i; |
1568 | ||
e4402a12 PU |
1569 | /* Clear the corresponding EMR bits */ |
1570 | edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); | |
1571 | /* Clear any SER */ | |
1572 | edma_shadow0_write_array(ecc, SH_SECR, j, | |
79ad2e38 | 1573 | BIT(i)); |
e4402a12 | 1574 | edma_error_handler(&ecc->slave_chans[k]); |
79ad2e38 | 1575 | } |
c5f47990 | 1576 | } |
e4402a12 PU |
1577 | |
1578 | val = edma_read(ecc, EDMA_QEMR); | |
1579 | if (val) { | |
1580 | dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); | |
1581 | /* Not reported, just clear the interrupt reason. */ | |
1582 | edma_write(ecc, EDMA_QEMCR, val); | |
1583 | edma_shadow0_write(ecc, SH_QSECR, val); | |
1584 | } | |
1585 | ||
1586 | val = edma_read(ecc, EDMA_CCERR); | |
1587 | if (val) { | |
1588 | dev_warn(ecc->dev, "CCERR 0x%08x\n", val); | |
1589 | /* Not reported, just clear the interrupt reason. */ | |
1590 | edma_write(ecc, EDMA_CCERRCLR, val); | |
1591 | } | |
1592 | ||
7c3b8b3d | 1593 | if (!edma_error_pending(ecc)) |
79ad2e38 PU |
1594 | break; |
1595 | cnt++; | |
1596 | if (cnt > 10) | |
1597 | break; | |
c2dde5f8 | 1598 | } |
79ad2e38 PU |
1599 | edma_write(ecc, EDMA_EEVAL, 1); |
1600 | return IRQ_HANDLED; | |
c2dde5f8 MP |
1601 | } |
1602 | ||
1603 | /* Alloc channel resources */ | |
1604 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
1605 | { | |
1606 | struct edma_chan *echan = to_edma_chan(chan); | |
1be5336b PU |
1607 | struct edma_cc *ecc = echan->ecc; |
1608 | struct device *dev = ecc->dev; | |
1609 | enum dma_event_q eventq_no = EVENTQ_DEFAULT; | |
c2dde5f8 | 1610 | int ret; |
c2dde5f8 | 1611 | |
1be5336b PU |
1612 | if (echan->tc) { |
1613 | eventq_no = echan->tc->id; | |
1614 | } else if (ecc->tc_list) { | |
1615 | /* memcpy channel */ | |
1616 | echan->tc = &ecc->tc_list[ecc->info->default_queue]; | |
1617 | eventq_no = echan->tc->id; | |
1618 | } | |
1619 | ||
1620 | ret = edma_alloc_channel(echan, eventq_no); | |
34cf3011 PU |
1621 | if (ret) |
1622 | return ret; | |
c2dde5f8 | 1623 | |
1be5336b | 1624 | echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); |
e4e886c6 PU |
1625 | if (echan->slot[0] < 0) { |
1626 | dev_err(dev, "Entry slot allocation failed for channel %u\n", | |
1627 | EDMA_CHAN_SLOT(echan->ch_num)); | |
34cf3011 | 1628 | goto err_slot; |
e4e886c6 PU |
1629 | } |
1630 | ||
1631 | /* Set up channel -> slot mapping for the entry slot */ | |
34cf3011 PU |
1632 | edma_set_chmap(echan, echan->slot[0]); |
1633 | echan->alloced = true; | |
c2dde5f8 | 1634 | |
1be5336b PU |
1635 | dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", |
1636 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, | |
1637 | echan->hw_triggered ? "HW" : "SW"); | |
1638 | ||
c2dde5f8 MP |
1639 | return 0; |
1640 | ||
34cf3011 PU |
1641 | err_slot: |
1642 | edma_free_channel(echan); | |
c2dde5f8 MP |
1643 | return ret; |
1644 | } | |
1645 | ||
1646 | /* Free channel resources */ | |
1647 | static void edma_free_chan_resources(struct dma_chan *chan) | |
1648 | { | |
1649 | struct edma_chan *echan = to_edma_chan(chan); | |
1be5336b | 1650 | struct device *dev = echan->ecc->dev; |
c2dde5f8 MP |
1651 | int i; |
1652 | ||
1653 | /* Terminate transfers */ | |
34cf3011 | 1654 | edma_stop(echan); |
c2dde5f8 MP |
1655 | |
1656 | vchan_free_chan_resources(&echan->vchan); | |
1657 | ||
1658 | /* Free EDMA PaRAM slots */ | |
e4e886c6 | 1659 | for (i = 0; i < EDMA_MAX_SLOTS; i++) { |
c2dde5f8 | 1660 | if (echan->slot[i] >= 0) { |
2b6b3b74 | 1661 | edma_free_slot(echan->ecc, echan->slot[i]); |
c2dde5f8 MP |
1662 | echan->slot[i] = -1; |
1663 | } | |
1664 | } | |
1665 | ||
e4e886c6 | 1666 | /* Set entry slot to the dummy slot */ |
34cf3011 | 1667 | edma_set_chmap(echan, echan->ecc->dummy_slot); |
e4e886c6 | 1668 | |
c2dde5f8 MP |
1669 | /* Free EDMA channel */ |
1670 | if (echan->alloced) { | |
34cf3011 | 1671 | edma_free_channel(echan); |
c2dde5f8 MP |
1672 | echan->alloced = false; |
1673 | } | |
1674 | ||
1be5336b PU |
1675 | echan->tc = NULL; |
1676 | echan->hw_triggered = false; | |
1677 | ||
1678 | dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", | |
1679 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); | |
c2dde5f8 MP |
1680 | } |
1681 | ||
1682 | /* Send pending descriptor to hardware */ | |
1683 | static void edma_issue_pending(struct dma_chan *chan) | |
1684 | { | |
1685 | struct edma_chan *echan = to_edma_chan(chan); | |
1686 | unsigned long flags; | |
1687 | ||
1688 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
1689 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
1690 | edma_execute(echan); | |
1691 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
1692 | } | |
1693 | ||
4ac31d18 JO |
1694 | /* |
1695 | * This limit exists to avoid a possible infinite loop when waiting for proof | |
1696 | * that a particular transfer is completed. This limit can be hit if there | |
1697 | * are large bursts to/from slow devices or the CPU is never able to catch | |
1698 | * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART | |
1699 | * RX-FIFO, as many as 55 loops have been seen. | |
1700 | */ | |
1701 | #define EDMA_MAX_TR_WAIT_LOOPS 1000 | |
1702 | ||
740b41f7 TG |
1703 | static u32 edma_residue(struct edma_desc *edesc) |
1704 | { | |
1705 | bool dst = edesc->direction == DMA_DEV_TO_MEM; | |
4ac31d18 JO |
1706 | int loop_count = EDMA_MAX_TR_WAIT_LOOPS; |
1707 | struct edma_chan *echan = edesc->echan; | |
740b41f7 TG |
1708 | struct edma_pset *pset = edesc->pset; |
1709 | dma_addr_t done, pos; | |
1710 | int i; | |
1711 | ||
1712 | /* | |
1713 | * We always read the dst/src position from the first RamPar | |
1714 | * pset. That's the one which is active now. | |
1715 | */ | |
4ac31d18 JO |
1716 | pos = edma_get_position(echan->ecc, echan->slot[0], dst); |
1717 | ||
1718 | /* | |
1719 | * "pos" may represent a transfer request that is still being | |
1720 | * processed by the EDMACC or EDMATC. We will busy wait until | |
1721 | * any one of the situations occurs: | |
1722 | * 1. the DMA hardware is idle | |
1723 | * 2. a new transfer request is setup | |
1724 | * 3. we hit the loop limit | |
1725 | */ | |
1726 | while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) { | |
1727 | /* check if a new transfer request is setup */ | |
1728 | if (edma_get_position(echan->ecc, | |
1729 | echan->slot[0], dst) != pos) { | |
1730 | break; | |
1731 | } | |
1732 | ||
1733 | if (!--loop_count) { | |
1734 | dev_dbg_ratelimited(echan->vchan.chan.device->dev, | |
1735 | "%s: timeout waiting for PaRAM update\n", | |
1736 | __func__); | |
1737 | break; | |
1738 | } | |
1739 | ||
1740 | cpu_relax(); | |
1741 | } | |
740b41f7 TG |
1742 | |
1743 | /* | |
1744 | * Cyclic is simple. Just subtract pset[0].addr from pos. | |
1745 | * | |
1746 | * We never update edesc->residue in the cyclic case, so we | |
1747 | * can tell the remaining room to the end of the circular | |
1748 | * buffer. | |
1749 | */ | |
1750 | if (edesc->cyclic) { | |
1751 | done = pos - pset->addr; | |
1752 | edesc->residue_stat = edesc->residue - done; | |
1753 | return edesc->residue_stat; | |
1754 | } | |
1755 | ||
1756 | /* | |
1757 | * For SG operation we catch up with the last processed | |
1758 | * status. | |
1759 | */ | |
1760 | pset += edesc->processed_stat; | |
1761 | ||
1762 | for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { | |
1763 | /* | |
1764 | * If we are inside this pset address range, we know | |
1765 | * this is the active one. Get the current delta and | |
1766 | * stop walking the psets. | |
1767 | */ | |
1768 | if (pos >= pset->addr && pos < pset->addr + pset->len) | |
1769 | return edesc->residue_stat - (pos - pset->addr); | |
1770 | ||
1771 | /* Otherwise mark it done and update residue_stat. */ | |
1772 | edesc->processed_stat++; | |
1773 | edesc->residue_stat -= pset->len; | |
1774 | } | |
1775 | return edesc->residue_stat; | |
1776 | } | |
1777 | ||
c2dde5f8 MP |
1778 | /* Check request completion status */ |
1779 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
1780 | dma_cookie_t cookie, | |
1781 | struct dma_tx_state *txstate) | |
1782 | { | |
1783 | struct edma_chan *echan = to_edma_chan(chan); | |
1784 | struct virt_dma_desc *vdesc; | |
1785 | enum dma_status ret; | |
1786 | unsigned long flags; | |
1787 | ||
1788 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 1789 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
1790 | return ret; |
1791 | ||
1792 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
de135939 | 1793 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
740b41f7 | 1794 | txstate->residue = edma_residue(echan->edesc); |
de135939 TG |
1795 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
1796 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; | |
c2dde5f8 MP |
1797 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
1798 | ||
1799 | return ret; | |
1800 | } | |
1801 | ||
ecb7dece | 1802 | static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels) |
1be5336b | 1803 | { |
1be5336b PU |
1804 | if (!memcpy_channels) |
1805 | return false; | |
ecb7dece PU |
1806 | while (*memcpy_channels != -1) { |
1807 | if (*memcpy_channels == ch_num) | |
1be5336b | 1808 | return true; |
ecb7dece | 1809 | memcpy_channels++; |
1be5336b PU |
1810 | } |
1811 | return false; | |
1812 | } | |
1813 | ||
02f77ef1 PU |
1814 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
1815 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
1816 | BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ | |
1817 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
1818 | ||
1be5336b | 1819 | static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) |
c2dde5f8 | 1820 | { |
1be5336b PU |
1821 | struct dma_device *s_ddev = &ecc->dma_slave; |
1822 | struct dma_device *m_ddev = NULL; | |
ecb7dece | 1823 | s32 *memcpy_channels = ecc->info->memcpy_channels; |
c2dde5f8 MP |
1824 | int i, j; |
1825 | ||
1be5336b PU |
1826 | dma_cap_zero(s_ddev->cap_mask); |
1827 | dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); | |
1828 | dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); | |
1829 | if (ecc->legacy_mode && !memcpy_channels) { | |
1830 | dev_warn(ecc->dev, | |
1831 | "Legacy memcpy is enabled, things might not work\n"); | |
02f77ef1 | 1832 | |
1be5336b PU |
1833 | dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); |
1834 | s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; | |
1835 | s_ddev->directions = BIT(DMA_MEM_TO_MEM); | |
1836 | } | |
02f77ef1 | 1837 | |
1be5336b PU |
1838 | s_ddev->device_prep_slave_sg = edma_prep_slave_sg; |
1839 | s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; | |
1840 | s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; | |
1841 | s_ddev->device_free_chan_resources = edma_free_chan_resources; | |
1842 | s_ddev->device_issue_pending = edma_issue_pending; | |
1843 | s_ddev->device_tx_status = edma_tx_status; | |
1844 | s_ddev->device_config = edma_slave_config; | |
1845 | s_ddev->device_pause = edma_dma_pause; | |
1846 | s_ddev->device_resume = edma_dma_resume; | |
1847 | s_ddev->device_terminate_all = edma_terminate_all; | |
b84730ff | 1848 | s_ddev->device_synchronize = edma_synchronize; |
1be5336b PU |
1849 | |
1850 | s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1851 | s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1852 | s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); | |
1853 | s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1854 | ||
1855 | s_ddev->dev = ecc->dev; | |
1856 | INIT_LIST_HEAD(&s_ddev->channels); | |
1857 | ||
1858 | if (memcpy_channels) { | |
1859 | m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); | |
1860 | ecc->dma_memcpy = m_ddev; | |
1861 | ||
1862 | dma_cap_zero(m_ddev->cap_mask); | |
1863 | dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); | |
1864 | ||
1865 | m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; | |
1866 | m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; | |
1867 | m_ddev->device_free_chan_resources = edma_free_chan_resources; | |
1868 | m_ddev->device_issue_pending = edma_issue_pending; | |
1869 | m_ddev->device_tx_status = edma_tx_status; | |
1870 | m_ddev->device_config = edma_slave_config; | |
1871 | m_ddev->device_pause = edma_dma_pause; | |
1872 | m_ddev->device_resume = edma_dma_resume; | |
1873 | m_ddev->device_terminate_all = edma_terminate_all; | |
b84730ff | 1874 | m_ddev->device_synchronize = edma_synchronize; |
1be5336b PU |
1875 | |
1876 | m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1877 | m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; | |
1878 | m_ddev->directions = BIT(DMA_MEM_TO_MEM); | |
1879 | m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1880 | ||
1881 | m_ddev->dev = ecc->dev; | |
1882 | INIT_LIST_HEAD(&m_ddev->channels); | |
1883 | } else if (!ecc->legacy_mode) { | |
1884 | dev_info(ecc->dev, "memcpy is disabled\n"); | |
1885 | } | |
02f77ef1 | 1886 | |
cb782059 | 1887 | for (i = 0; i < ecc->num_channels; i++) { |
02f77ef1 | 1888 | struct edma_chan *echan = &ecc->slave_chans[i]; |
2b6b3b74 | 1889 | echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); |
c2dde5f8 MP |
1890 | echan->ecc = ecc; |
1891 | echan->vchan.desc_free = edma_desc_free; | |
1892 | ||
1be5336b PU |
1893 | if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels)) |
1894 | vchan_init(&echan->vchan, m_ddev); | |
1895 | else | |
1896 | vchan_init(&echan->vchan, s_ddev); | |
c2dde5f8 MP |
1897 | |
1898 | INIT_LIST_HEAD(&echan->node); | |
1899 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
1900 | echan->slot[j] = -1; | |
1901 | } | |
1902 | } | |
1903 | ||
2b6b3b74 PU |
1904 | static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, |
1905 | struct edma_cc *ecc) | |
1906 | { | |
1907 | int i; | |
1908 | u32 value, cccfg; | |
1909 | s8 (*queue_priority_map)[2]; | |
1910 | ||
1911 | /* Decode the eDMA3 configuration from CCCFG register */ | |
1912 | cccfg = edma_read(ecc, EDMA_CCCFG); | |
1913 | ||
1914 | value = GET_NUM_REGN(cccfg); | |
1915 | ecc->num_region = BIT(value); | |
1916 | ||
1917 | value = GET_NUM_DMACH(cccfg); | |
1918 | ecc->num_channels = BIT(value + 1); | |
1919 | ||
633e42b8 PU |
1920 | value = GET_NUM_QDMACH(cccfg); |
1921 | ecc->num_qchannels = value * 2; | |
1922 | ||
2b6b3b74 PU |
1923 | value = GET_NUM_PAENTRY(cccfg); |
1924 | ecc->num_slots = BIT(value + 4); | |
1925 | ||
1926 | value = GET_NUM_EVQUE(cccfg); | |
1927 | ecc->num_tc = value + 1; | |
1928 | ||
4ab54f69 PU |
1929 | ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; |
1930 | ||
2b6b3b74 PU |
1931 | dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); |
1932 | dev_dbg(dev, "num_region: %u\n", ecc->num_region); | |
1933 | dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); | |
633e42b8 | 1934 | dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); |
2b6b3b74 PU |
1935 | dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); |
1936 | dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); | |
4ab54f69 | 1937 | dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); |
2b6b3b74 PU |
1938 | |
1939 | /* Nothing need to be done if queue priority is provided */ | |
1940 | if (pdata->queue_priority_mapping) | |
1941 | return 0; | |
1942 | ||
1943 | /* | |
1944 | * Configure TC/queue priority as follows: | |
1945 | * Q0 - priority 0 | |
1946 | * Q1 - priority 1 | |
1947 | * Q2 - priority 2 | |
1948 | * ... | |
1949 | * The meaning of priority numbers: 0 highest priority, 7 lowest | |
1950 | * priority. So Q0 is the highest priority queue and the last queue has | |
1951 | * the lowest priority. | |
1952 | */ | |
547c6e27 | 1953 | queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), |
2b6b3b74 PU |
1954 | GFP_KERNEL); |
1955 | if (!queue_priority_map) | |
1956 | return -ENOMEM; | |
1957 | ||
1958 | for (i = 0; i < ecc->num_tc; i++) { | |
1959 | queue_priority_map[i][0] = i; | |
1960 | queue_priority_map[i][1] = i; | |
1961 | } | |
1962 | queue_priority_map[i][0] = -1; | |
1963 | queue_priority_map[i][1] = -1; | |
1964 | ||
1965 | pdata->queue_priority_mapping = queue_priority_map; | |
1966 | /* Default queue has the lowest priority */ | |
1967 | pdata->default_queue = i - 1; | |
1968 | ||
1969 | return 0; | |
1970 | } | |
1971 | ||
1972 | #if IS_ENABLED(CONFIG_OF) | |
1973 | static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, | |
1974 | size_t sz) | |
1975 | { | |
1976 | const char pname[] = "ti,edma-xbar-event-map"; | |
1977 | struct resource res; | |
1978 | void __iomem *xbar; | |
1979 | s16 (*xbar_chans)[2]; | |
1980 | size_t nelm = sz / sizeof(s16); | |
1981 | u32 shift, offset, mux; | |
1982 | int ret, i; | |
1983 | ||
547c6e27 | 1984 | xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); |
2b6b3b74 PU |
1985 | if (!xbar_chans) |
1986 | return -ENOMEM; | |
1987 | ||
1988 | ret = of_address_to_resource(dev->of_node, 1, &res); | |
1989 | if (ret) | |
1990 | return -ENOMEM; | |
1991 | ||
1992 | xbar = devm_ioremap(dev, res.start, resource_size(&res)); | |
1993 | if (!xbar) | |
1994 | return -ENOMEM; | |
1995 | ||
1996 | ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, | |
1997 | nelm); | |
1998 | if (ret) | |
1999 | return -EIO; | |
2000 | ||
2001 | /* Invalidate last entry for the other user of this mess */ | |
2002 | nelm >>= 1; | |
2003 | xbar_chans[nelm][0] = -1; | |
2004 | xbar_chans[nelm][1] = -1; | |
2005 | ||
2006 | for (i = 0; i < nelm; i++) { | |
2007 | shift = (xbar_chans[i][1] & 0x03) << 3; | |
2008 | offset = xbar_chans[i][1] & 0xfffffffc; | |
2009 | mux = readl(xbar + offset); | |
2010 | mux &= ~(0xff << shift); | |
2011 | mux |= xbar_chans[i][0] << shift; | |
2012 | writel(mux, (xbar + offset)); | |
2013 | } | |
2014 | ||
2015 | pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; | |
2016 | return 0; | |
2017 | } | |
2018 | ||
1be5336b PU |
2019 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
2020 | bool legacy_mode) | |
2b6b3b74 PU |
2021 | { |
2022 | struct edma_soc_info *info; | |
966a87b5 PU |
2023 | struct property *prop; |
2024 | size_t sz; | |
2b6b3b74 PU |
2025 | int ret; |
2026 | ||
2027 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | |
2028 | if (!info) | |
2029 | return ERR_PTR(-ENOMEM); | |
2030 | ||
1be5336b PU |
2031 | if (legacy_mode) { |
2032 | prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", | |
2033 | &sz); | |
2034 | if (prop) { | |
2035 | ret = edma_xbar_event_map(dev, info, sz); | |
2036 | if (ret) | |
2037 | return ERR_PTR(ret); | |
2038 | } | |
2039 | return info; | |
2040 | } | |
2041 | ||
2042 | /* Get the list of channels allocated to be used for memcpy */ | |
2043 | prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); | |
2044 | if (prop) { | |
2045 | const char pname[] = "ti,edma-memcpy-channels"; | |
ecb7dece PU |
2046 | size_t nelm = sz / sizeof(s32); |
2047 | s32 *memcpy_ch; | |
1be5336b | 2048 | |
ecb7dece | 2049 | memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32), |
1be5336b PU |
2050 | GFP_KERNEL); |
2051 | if (!memcpy_ch) | |
2052 | return ERR_PTR(-ENOMEM); | |
2053 | ||
ecb7dece PU |
2054 | ret = of_property_read_u32_array(dev->of_node, pname, |
2055 | (u32 *)memcpy_ch, nelm); | |
1be5336b PU |
2056 | if (ret) |
2057 | return ERR_PTR(ret); | |
2058 | ||
2059 | memcpy_ch[nelm] = -1; | |
2060 | info->memcpy_channels = memcpy_ch; | |
2061 | } | |
2062 | ||
2063 | prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", | |
2064 | &sz); | |
966a87b5 | 2065 | if (prop) { |
1be5336b | 2066 | const char pname[] = "ti,edma-reserved-slot-ranges"; |
ae0add74 | 2067 | u32 (*tmp)[2]; |
1be5336b | 2068 | s16 (*rsv_slots)[2]; |
ae0add74 | 2069 | size_t nelm = sz / sizeof(*tmp); |
1be5336b | 2070 | struct edma_rsv_info *rsv_info; |
ae0add74 | 2071 | int i; |
1be5336b PU |
2072 | |
2073 | if (!nelm) | |
2074 | return info; | |
2075 | ||
ae0add74 PU |
2076 | tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL); |
2077 | if (!tmp) | |
2078 | return ERR_PTR(-ENOMEM); | |
2079 | ||
1be5336b | 2080 | rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); |
ae0add74 PU |
2081 | if (!rsv_info) { |
2082 | kfree(tmp); | |
1be5336b | 2083 | return ERR_PTR(-ENOMEM); |
ae0add74 | 2084 | } |
1be5336b PU |
2085 | |
2086 | rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), | |
2087 | GFP_KERNEL); | |
ae0add74 PU |
2088 | if (!rsv_slots) { |
2089 | kfree(tmp); | |
1be5336b | 2090 | return ERR_PTR(-ENOMEM); |
ae0add74 | 2091 | } |
1be5336b | 2092 | |
ae0add74 PU |
2093 | ret = of_property_read_u32_array(dev->of_node, pname, |
2094 | (u32 *)tmp, nelm * 2); | |
2095 | if (ret) { | |
2096 | kfree(tmp); | |
966a87b5 | 2097 | return ERR_PTR(ret); |
ae0add74 | 2098 | } |
1be5336b | 2099 | |
ae0add74 PU |
2100 | for (i = 0; i < nelm; i++) { |
2101 | rsv_slots[i][0] = tmp[i][0]; | |
2102 | rsv_slots[i][1] = tmp[i][1]; | |
2103 | } | |
1be5336b PU |
2104 | rsv_slots[nelm][0] = -1; |
2105 | rsv_slots[nelm][1] = -1; | |
ae0add74 | 2106 | |
1be5336b PU |
2107 | info->rsv = rsv_info; |
2108 | info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; | |
ae0add74 PU |
2109 | |
2110 | kfree(tmp); | |
966a87b5 | 2111 | } |
2b6b3b74 PU |
2112 | |
2113 | return info; | |
2114 | } | |
1be5336b PU |
2115 | |
2116 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, | |
2117 | struct of_dma *ofdma) | |
2118 | { | |
2119 | struct edma_cc *ecc = ofdma->of_dma_data; | |
2120 | struct dma_chan *chan = NULL; | |
2121 | struct edma_chan *echan; | |
2122 | int i; | |
2123 | ||
2124 | if (!ecc || dma_spec->args_count < 1) | |
2125 | return NULL; | |
2126 | ||
2127 | for (i = 0; i < ecc->num_channels; i++) { | |
2128 | echan = &ecc->slave_chans[i]; | |
2129 | if (echan->ch_num == dma_spec->args[0]) { | |
2130 | chan = &echan->vchan.chan; | |
2131 | break; | |
2132 | } | |
2133 | } | |
2134 | ||
2135 | if (!chan) | |
2136 | return NULL; | |
2137 | ||
2138 | if (echan->ecc->legacy_mode && dma_spec->args_count == 1) | |
2139 | goto out; | |
2140 | ||
2141 | if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && | |
2142 | dma_spec->args[1] < echan->ecc->num_tc) { | |
2143 | echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; | |
2144 | goto out; | |
2145 | } | |
2146 | ||
2147 | return NULL; | |
2148 | out: | |
2149 | /* The channel is going to be used as HW synchronized */ | |
2150 | echan->hw_triggered = true; | |
2151 | return dma_get_slave_channel(chan); | |
2152 | } | |
2b6b3b74 | 2153 | #else |
1be5336b PU |
2154 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
2155 | bool legacy_mode) | |
2b6b3b74 PU |
2156 | { |
2157 | return ERR_PTR(-EINVAL); | |
2158 | } | |
1be5336b PU |
2159 | |
2160 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, | |
2161 | struct of_dma *ofdma) | |
2162 | { | |
2163 | return NULL; | |
2164 | } | |
2b6b3b74 PU |
2165 | #endif |
2166 | ||
463a1f8b | 2167 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 | 2168 | { |
2b6b3b74 PU |
2169 | struct edma_soc_info *info = pdev->dev.platform_data; |
2170 | s8 (*queue_priority_mapping)[2]; | |
2171 | int i, off, ln; | |
2b6b3b74 PU |
2172 | const s16 (*rsv_slots)[2]; |
2173 | const s16 (*xbar_chans)[2]; | |
2174 | int irq; | |
2175 | char *irq_name; | |
2176 | struct resource *mem; | |
2177 | struct device_node *node = pdev->dev.of_node; | |
2178 | struct device *dev = &pdev->dev; | |
2179 | struct edma_cc *ecc; | |
1be5336b | 2180 | bool legacy_mode = true; |
c2dde5f8 MP |
2181 | int ret; |
2182 | ||
2b6b3b74 | 2183 | if (node) { |
1be5336b PU |
2184 | const struct of_device_id *match; |
2185 | ||
2186 | match = of_match_node(edma_of_ids, node); | |
2187 | if (match && (u32)match->data == EDMA_BINDING_TPCC) | |
2188 | legacy_mode = false; | |
2189 | ||
2190 | info = edma_setup_info_from_dt(dev, legacy_mode); | |
2b6b3b74 PU |
2191 | if (IS_ERR(info)) { |
2192 | dev_err(dev, "failed to get DT data\n"); | |
2193 | return PTR_ERR(info); | |
2194 | } | |
2195 | } | |
2196 | ||
2197 | if (!info) | |
2198 | return -ENODEV; | |
2199 | ||
2200 | pm_runtime_enable(dev); | |
2201 | ret = pm_runtime_get_sync(dev); | |
2202 | if (ret < 0) { | |
2203 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
2204 | return ret; | |
2205 | } | |
2206 | ||
907f74a0 | 2207 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
94cb0e79 RK |
2208 | if (ret) |
2209 | return ret; | |
2210 | ||
907f74a0 | 2211 | ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); |
aef94fea | 2212 | if (!ecc) |
c2dde5f8 | 2213 | return -ENOMEM; |
c2dde5f8 | 2214 | |
2b6b3b74 PU |
2215 | ecc->dev = dev; |
2216 | ecc->id = pdev->id; | |
1be5336b | 2217 | ecc->legacy_mode = legacy_mode; |
2b6b3b74 PU |
2218 | /* When booting with DT the pdev->id is -1 */ |
2219 | if (ecc->id < 0) | |
2220 | ecc->id = 0; | |
2221 | ||
2222 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); | |
2223 | if (!mem) { | |
2224 | dev_dbg(dev, "mem resource not found, using index 0\n"); | |
2225 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2226 | if (!mem) { | |
2227 | dev_err(dev, "no mem resource?\n"); | |
2228 | return -ENODEV; | |
2229 | } | |
2230 | } | |
2231 | ecc->base = devm_ioremap_resource(dev, mem); | |
2232 | if (IS_ERR(ecc->base)) | |
2233 | return PTR_ERR(ecc->base); | |
2234 | ||
2235 | platform_set_drvdata(pdev, ecc); | |
2236 | ||
2237 | /* Get eDMA3 configuration from IP */ | |
2238 | ret = edma_setup_from_hw(dev, info, ecc); | |
2239 | if (ret) | |
2240 | return ret; | |
2241 | ||
cb782059 PU |
2242 | /* Allocate memory based on the information we got from the IP */ |
2243 | ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, | |
2244 | sizeof(*ecc->slave_chans), GFP_KERNEL); | |
2245 | if (!ecc->slave_chans) | |
2246 | return -ENOMEM; | |
2247 | ||
7a73b135 | 2248 | ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), |
cb782059 | 2249 | sizeof(unsigned long), GFP_KERNEL); |
7a73b135 | 2250 | if (!ecc->slot_inuse) |
cb782059 PU |
2251 | return -ENOMEM; |
2252 | ||
2b6b3b74 PU |
2253 | ecc->default_queue = info->default_queue; |
2254 | ||
2255 | for (i = 0; i < ecc->num_slots; i++) | |
2256 | edma_write_slot(ecc, i, &dummy_paramset); | |
2257 | ||
2b6b3b74 | 2258 | if (info->rsv) { |
2b6b3b74 PU |
2259 | /* Set the reserved slots in inuse list */ |
2260 | rsv_slots = info->rsv->rsv_slots; | |
2261 | if (rsv_slots) { | |
2262 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
2263 | off = rsv_slots[i][0]; | |
2264 | ln = rsv_slots[i][1]; | |
7a73b135 | 2265 | set_bits(off, ln, ecc->slot_inuse); |
2b6b3b74 PU |
2266 | } |
2267 | } | |
2268 | } | |
2269 | ||
2270 | /* Clear the xbar mapped channels in unused list */ | |
2271 | xbar_chans = info->xbar_chans; | |
2272 | if (xbar_chans) { | |
2273 | for (i = 0; xbar_chans[i][1] != -1; i++) { | |
2274 | off = xbar_chans[i][1]; | |
2b6b3b74 PU |
2275 | } |
2276 | } | |
2277 | ||
2278 | irq = platform_get_irq_byname(pdev, "edma3_ccint"); | |
2279 | if (irq < 0 && node) | |
2280 | irq = irq_of_parse_and_map(node, 0); | |
2281 | ||
2282 | if (irq >= 0) { | |
2283 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", | |
2284 | dev_name(dev)); | |
2285 | ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, | |
2286 | ecc); | |
2287 | if (ret) { | |
2288 | dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); | |
2289 | return ret; | |
2290 | } | |
638001e0 | 2291 | ecc->ccint = irq; |
2b6b3b74 PU |
2292 | } |
2293 | ||
2294 | irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); | |
2295 | if (irq < 0 && node) | |
2296 | irq = irq_of_parse_and_map(node, 2); | |
2297 | ||
2298 | if (irq >= 0) { | |
2299 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", | |
2300 | dev_name(dev)); | |
2301 | ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, | |
2302 | ecc); | |
2303 | if (ret) { | |
2304 | dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); | |
2305 | return ret; | |
2306 | } | |
638001e0 | 2307 | ecc->ccerrint = irq; |
2b6b3b74 PU |
2308 | } |
2309 | ||
e4e886c6 PU |
2310 | ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); |
2311 | if (ecc->dummy_slot < 0) { | |
2312 | dev_err(dev, "Can't allocate PaRAM dummy slot\n"); | |
2313 | return ecc->dummy_slot; | |
2314 | } | |
2315 | ||
2b6b3b74 PU |
2316 | queue_priority_mapping = info->queue_priority_mapping; |
2317 | ||
1be5336b PU |
2318 | if (!ecc->legacy_mode) { |
2319 | int lowest_priority = 0; | |
2320 | struct of_phandle_args tc_args; | |
2321 | ||
2322 | ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, | |
2323 | sizeof(*ecc->tc_list), GFP_KERNEL); | |
2324 | if (!ecc->tc_list) | |
2325 | return -ENOMEM; | |
2326 | ||
2327 | for (i = 0;; i++) { | |
2328 | ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs", | |
2329 | 1, i, &tc_args); | |
2330 | if (ret || i == ecc->num_tc) | |
2331 | break; | |
2332 | ||
2333 | ecc->tc_list[i].node = tc_args.np; | |
2334 | ecc->tc_list[i].id = i; | |
2335 | queue_priority_mapping[i][1] = tc_args.args[0]; | |
2336 | if (queue_priority_mapping[i][1] > lowest_priority) { | |
2337 | lowest_priority = queue_priority_mapping[i][1]; | |
2338 | info->default_queue = i; | |
2339 | } | |
2340 | } | |
2341 | } | |
2342 | ||
2b6b3b74 PU |
2343 | /* Event queue priority mapping */ |
2344 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
2345 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], | |
2346 | queue_priority_mapping[i][1]); | |
ca304fa9 | 2347 | |
2b6b3b74 PU |
2348 | for (i = 0; i < ecc->num_region; i++) { |
2349 | edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); | |
2350 | edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); | |
2351 | edma_write_array(ecc, EDMA_QRAE, i, 0x0); | |
2352 | } | |
2353 | ecc->info = info; | |
2354 | ||
02f77ef1 | 2355 | /* Init the dma device and channels */ |
1be5336b | 2356 | edma_dma_init(ecc, legacy_mode); |
c2dde5f8 | 2357 | |
34cf3011 PU |
2358 | for (i = 0; i < ecc->num_channels; i++) { |
2359 | /* Assign all channels to the default queue */ | |
f9425deb PU |
2360 | edma_assign_channel_eventq(&ecc->slave_chans[i], |
2361 | info->default_queue); | |
34cf3011 PU |
2362 | /* Set entry slot to the dummy slot */ |
2363 | edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); | |
2364 | } | |
2365 | ||
23e6723c PU |
2366 | ecc->dma_slave.filter.map = info->slave_map; |
2367 | ecc->dma_slave.filter.mapcnt = info->slavecnt; | |
2368 | ecc->dma_slave.filter.fn = edma_filter_fn; | |
2369 | ||
c2dde5f8 | 2370 | ret = dma_async_device_register(&ecc->dma_slave); |
1be5336b PU |
2371 | if (ret) { |
2372 | dev_err(dev, "slave ddev registration failed (%d)\n", ret); | |
c2dde5f8 | 2373 | goto err_reg1; |
1be5336b PU |
2374 | } |
2375 | ||
2376 | if (ecc->dma_memcpy) { | |
2377 | ret = dma_async_device_register(ecc->dma_memcpy); | |
2378 | if (ret) { | |
2379 | dev_err(dev, "memcpy ddev registration failed (%d)\n", | |
2380 | ret); | |
2381 | dma_async_device_unregister(&ecc->dma_slave); | |
2382 | goto err_reg1; | |
2383 | } | |
2384 | } | |
c2dde5f8 | 2385 | |
2b6b3b74 | 2386 | if (node) |
1be5336b | 2387 | of_dma_controller_register(node, of_edma_xlate, ecc); |
dc9b6055 | 2388 | |
907f74a0 | 2389 | dev_info(dev, "TI EDMA DMA engine driver\n"); |
c2dde5f8 MP |
2390 | |
2391 | return 0; | |
2392 | ||
2393 | err_reg1: | |
2b6b3b74 | 2394 | edma_free_slot(ecc, ecc->dummy_slot); |
c2dde5f8 MP |
2395 | return ret; |
2396 | } | |
2397 | ||
f4e0628b VK |
2398 | static void edma_cleanupp_vchan(struct dma_device *dmadev) |
2399 | { | |
2400 | struct edma_chan *echan, *_echan; | |
2401 | ||
2402 | list_for_each_entry_safe(echan, _echan, | |
2403 | &dmadev->channels, vchan.chan.device_node) { | |
2404 | list_del(&echan->vchan.chan.device_node); | |
2405 | tasklet_kill(&echan->vchan.task); | |
2406 | } | |
2407 | } | |
2408 | ||
4bf27b8b | 2409 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
2410 | { |
2411 | struct device *dev = &pdev->dev; | |
2412 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
2413 | ||
638001e0 VK |
2414 | devm_free_irq(dev, ecc->ccint, ecc); |
2415 | devm_free_irq(dev, ecc->ccerrint, ecc); | |
2416 | ||
f4e0628b VK |
2417 | edma_cleanupp_vchan(&ecc->dma_slave); |
2418 | ||
907f74a0 PU |
2419 | if (dev->of_node) |
2420 | of_dma_controller_free(dev->of_node); | |
c2dde5f8 | 2421 | dma_async_device_unregister(&ecc->dma_slave); |
1be5336b PU |
2422 | if (ecc->dma_memcpy) |
2423 | dma_async_device_unregister(ecc->dma_memcpy); | |
2b6b3b74 | 2424 | edma_free_slot(ecc, ecc->dummy_slot); |
c2dde5f8 MP |
2425 | |
2426 | return 0; | |
2427 | } | |
2428 | ||
2b6b3b74 | 2429 | #ifdef CONFIG_PM_SLEEP |
1be5336b PU |
2430 | static int edma_pm_suspend(struct device *dev) |
2431 | { | |
2432 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
2433 | struct edma_chan *echan = ecc->slave_chans; | |
2434 | int i; | |
2435 | ||
2436 | for (i = 0; i < ecc->num_channels; i++) { | |
23f49fd2 | 2437 | if (echan[i].alloced) |
1be5336b | 2438 | edma_setup_interrupt(&echan[i], false); |
1be5336b PU |
2439 | } |
2440 | ||
2441 | return 0; | |
2442 | } | |
2443 | ||
2b6b3b74 PU |
2444 | static int edma_pm_resume(struct device *dev) |
2445 | { | |
2446 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
e4e886c6 | 2447 | struct edma_chan *echan = ecc->slave_chans; |
2b6b3b74 PU |
2448 | int i; |
2449 | s8 (*queue_priority_mapping)[2]; | |
2450 | ||
2451 | queue_priority_mapping = ecc->info->queue_priority_mapping; | |
2452 | ||
2453 | /* Event queue priority mapping */ | |
2454 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
2455 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], | |
2456 | queue_priority_mapping[i][1]); | |
2457 | ||
2b6b3b74 | 2458 | for (i = 0; i < ecc->num_channels; i++) { |
e4e886c6 | 2459 | if (echan[i].alloced) { |
2b6b3b74 PU |
2460 | /* ensure access through shadow region 0 */ |
2461 | edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, | |
2462 | BIT(i & 0x1f)); | |
2463 | ||
34cf3011 | 2464 | edma_setup_interrupt(&echan[i], true); |
e4e886c6 PU |
2465 | |
2466 | /* Set up channel -> slot mapping for the entry slot */ | |
34cf3011 | 2467 | edma_set_chmap(&echan[i], echan[i].slot[0]); |
2b6b3b74 PU |
2468 | } |
2469 | } | |
2470 | ||
2471 | return 0; | |
2472 | } | |
2473 | #endif | |
2474 | ||
2475 | static const struct dev_pm_ops edma_pm_ops = { | |
1be5336b | 2476 | SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume) |
2b6b3b74 PU |
2477 | }; |
2478 | ||
c2dde5f8 MP |
2479 | static struct platform_driver edma_driver = { |
2480 | .probe = edma_probe, | |
a7d6e3ec | 2481 | .remove = edma_remove, |
c2dde5f8 | 2482 | .driver = { |
2b6b3b74 PU |
2483 | .name = "edma", |
2484 | .pm = &edma_pm_ops, | |
2485 | .of_match_table = edma_of_ids, | |
c2dde5f8 MP |
2486 | }, |
2487 | }; | |
2488 | ||
4fa2d09c PU |
2489 | static int edma_tptc_probe(struct platform_device *pdev) |
2490 | { | |
23f49fd2 PU |
2491 | pm_runtime_enable(&pdev->dev); |
2492 | return pm_runtime_get_sync(&pdev->dev); | |
4fa2d09c PU |
2493 | } |
2494 | ||
34635b1a | 2495 | static struct platform_driver edma_tptc_driver = { |
4fa2d09c | 2496 | .probe = edma_tptc_probe, |
34635b1a PU |
2497 | .driver = { |
2498 | .name = "edma3-tptc", | |
2499 | .of_match_table = edma_tptc_of_ids, | |
2500 | }, | |
2501 | }; | |
2502 | ||
c2dde5f8 MP |
2503 | bool edma_filter_fn(struct dma_chan *chan, void *param) |
2504 | { | |
1be5336b PU |
2505 | bool match = false; |
2506 | ||
c2dde5f8 MP |
2507 | if (chan->device->dev->driver == &edma_driver.driver) { |
2508 | struct edma_chan *echan = to_edma_chan(chan); | |
2509 | unsigned ch_req = *(unsigned *)param; | |
1be5336b PU |
2510 | if (ch_req == echan->ch_num) { |
2511 | /* The channel is going to be used as HW synchronized */ | |
2512 | echan->hw_triggered = true; | |
2513 | match = true; | |
2514 | } | |
c2dde5f8 | 2515 | } |
1be5336b | 2516 | return match; |
c2dde5f8 MP |
2517 | } |
2518 | EXPORT_SYMBOL(edma_filter_fn); | |
2519 | ||
c2dde5f8 MP |
2520 | static int edma_init(void) |
2521 | { | |
34635b1a PU |
2522 | int ret; |
2523 | ||
2524 | ret = platform_driver_register(&edma_tptc_driver); | |
2525 | if (ret) | |
2526 | return ret; | |
2527 | ||
5305e4d6 | 2528 | return platform_driver_register(&edma_driver); |
c2dde5f8 MP |
2529 | } |
2530 | subsys_initcall(edma_init); | |
2531 | ||
2532 | static void __exit edma_exit(void) | |
2533 | { | |
c2dde5f8 | 2534 | platform_driver_unregister(&edma_driver); |
34635b1a | 2535 | platform_driver_unregister(&edma_tptc_driver); |
c2dde5f8 MP |
2536 | } |
2537 | module_exit(edma_exit); | |
2538 | ||
d71505b6 | 2539 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
2540 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
2541 | MODULE_LICENSE("GPL v2"); |