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Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
3ad7a42d | 27 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
28 | |
29 | #include "dmaengine.h" | |
30 | #include "virt-dma.h" | |
31 | ||
32 | /* | |
33 | * This will go away when the private EDMA API is folded | |
34 | * into this driver and the platform device(s) are | |
35 | * instantiated in the arch code. We can only get away | |
36 | * with this simplification because DA8XX may not be built | |
37 | * in the same kernel image with other DaVinci parts. This | |
38 | * avoids having to sprinkle dmaengine driver platform devices | |
39 | * and data throughout all the existing board files. | |
40 | */ | |
41 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
42 | #define EDMA_CTLRS 2 | |
43 | #define EDMA_CHANS 32 | |
44 | #else | |
45 | #define EDMA_CTLRS 1 | |
46 | #define EDMA_CHANS 64 | |
47 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
48 | ||
2abd5f1b JF |
49 | /* |
50 | * Max of 20 segments per channel to conserve PaRAM slots | |
51 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
52 | * that are required for ASoC, otherwise DMA prep calls will | |
53 | * fail. Today davinci-pcm is the only user of this driver and | |
54 | * requires atleast 17 slots, so we setup the default to 20. | |
55 | */ | |
56 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
57 | #define EDMA_MAX_SLOTS MAX_NR_SG |
58 | #define EDMA_DESCRIPTORS 16 | |
59 | ||
b5088ad9 TG |
60 | struct edma_pset { |
61 | struct edmacc_param param; | |
62 | }; | |
63 | ||
c2dde5f8 MP |
64 | struct edma_desc { |
65 | struct virt_dma_desc vdesc; | |
66 | struct list_head node; | |
50a9c707 | 67 | int cyclic; |
c2dde5f8 MP |
68 | int absync; |
69 | int pset_nr; | |
53407062 | 70 | int processed; |
b6205c39 | 71 | u32 residue; |
b5088ad9 | 72 | struct edma_pset pset[0]; |
c2dde5f8 MP |
73 | }; |
74 | ||
75 | struct edma_cc; | |
76 | ||
77 | struct edma_chan { | |
78 | struct virt_dma_chan vchan; | |
79 | struct list_head node; | |
80 | struct edma_desc *edesc; | |
81 | struct edma_cc *ecc; | |
82 | int ch_num; | |
83 | bool alloced; | |
84 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 85 | int missed; |
661f7cb5 | 86 | struct dma_slave_config cfg; |
c2dde5f8 MP |
87 | }; |
88 | ||
89 | struct edma_cc { | |
90 | int ctlr; | |
91 | struct dma_device dma_slave; | |
92 | struct edma_chan slave_chans[EDMA_CHANS]; | |
93 | int num_slave_chans; | |
94 | int dummy_slot; | |
95 | }; | |
96 | ||
97 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
98 | { | |
99 | return container_of(d, struct edma_cc, dma_slave); | |
100 | } | |
101 | ||
102 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
103 | { | |
104 | return container_of(c, struct edma_chan, vchan.chan); | |
105 | } | |
106 | ||
107 | static inline struct edma_desc | |
108 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
109 | { | |
110 | return container_of(tx, struct edma_desc, vdesc.tx); | |
111 | } | |
112 | ||
113 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
114 | { | |
115 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
116 | } | |
117 | ||
118 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
119 | static void edma_execute(struct edma_chan *echan) | |
120 | { | |
53407062 | 121 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 122 | struct edma_desc *edesc; |
53407062 JF |
123 | struct device *dev = echan->vchan.chan.device->dev; |
124 | int i, j, left, nslots; | |
125 | ||
126 | /* If either we processed all psets or we're still not started */ | |
127 | if (!echan->edesc || | |
128 | echan->edesc->pset_nr == echan->edesc->processed) { | |
129 | /* Get next vdesc */ | |
130 | vdesc = vchan_next_desc(&echan->vchan); | |
131 | if (!vdesc) { | |
132 | echan->edesc = NULL; | |
133 | return; | |
134 | } | |
135 | list_del(&vdesc->node); | |
136 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
137 | } |
138 | ||
53407062 | 139 | edesc = echan->edesc; |
c2dde5f8 | 140 | |
53407062 JF |
141 | /* Find out how many left */ |
142 | left = edesc->pset_nr - edesc->processed; | |
143 | nslots = min(MAX_NR_SG, left); | |
c2dde5f8 MP |
144 | |
145 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
146 | for (i = 0; i < nslots; i++) { |
147 | j = i + edesc->processed; | |
b5088ad9 | 148 | edma_write_slot(echan->slot[i], &edesc->pset[j].param); |
83bb3126 | 149 | dev_vdbg(echan->vchan.chan.device->dev, |
c2dde5f8 MP |
150 | "\n pset[%d]:\n" |
151 | " chnum\t%d\n" | |
152 | " slot\t%d\n" | |
153 | " opt\t%08x\n" | |
154 | " src\t%08x\n" | |
155 | " dst\t%08x\n" | |
156 | " abcnt\t%08x\n" | |
157 | " ccnt\t%08x\n" | |
158 | " bidx\t%08x\n" | |
159 | " cidx\t%08x\n" | |
160 | " lkrld\t%08x\n", | |
53407062 | 161 | j, echan->ch_num, echan->slot[i], |
b5088ad9 TG |
162 | edesc->pset[j].param.opt, |
163 | edesc->pset[j].param.src, | |
164 | edesc->pset[j].param.dst, | |
165 | edesc->pset[j].param.a_b_cnt, | |
166 | edesc->pset[j].param.ccnt, | |
167 | edesc->pset[j].param.src_dst_bidx, | |
168 | edesc->pset[j].param.src_dst_cidx, | |
169 | edesc->pset[j].param.link_bcntrld); | |
c2dde5f8 | 170 | /* Link to the previous slot if not the last set */ |
53407062 | 171 | if (i != (nslots - 1)) |
c2dde5f8 | 172 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
173 | } |
174 | ||
53407062 JF |
175 | edesc->processed += nslots; |
176 | ||
b267b3bc JF |
177 | /* |
178 | * If this is either the last set in a set of SG-list transactions | |
179 | * then setup a link to the dummy slot, this results in all future | |
180 | * events being absorbed and that's OK because we're done | |
181 | */ | |
50a9c707 JF |
182 | if (edesc->processed == edesc->pset_nr) { |
183 | if (edesc->cyclic) | |
184 | edma_link(echan->slot[nslots-1], echan->slot[1]); | |
185 | else | |
186 | edma_link(echan->slot[nslots-1], | |
187 | echan->ecc->dummy_slot); | |
188 | } | |
b267b3bc | 189 | |
53407062 | 190 | if (edesc->processed <= MAX_NR_SG) { |
9aac9096 PU |
191 | dev_dbg(dev, "first transfer starting on channel %d\n", |
192 | echan->ch_num); | |
53407062 | 193 | edma_start(echan->ch_num); |
5fc68a6c SN |
194 | } else { |
195 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
196 | echan->ch_num, edesc->processed); | |
197 | edma_resume(echan->ch_num); | |
53407062 | 198 | } |
c5f47990 JF |
199 | |
200 | /* | |
201 | * This happens due to setup times between intermediate transfers | |
202 | * in long SG lists which have to be broken up into transfers of | |
203 | * MAX_NR_SG | |
204 | */ | |
205 | if (echan->missed) { | |
9aac9096 | 206 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
c5f47990 JF |
207 | edma_clean_channel(echan->ch_num); |
208 | edma_stop(echan->ch_num); | |
209 | edma_start(echan->ch_num); | |
210 | edma_trigger_channel(echan->ch_num); | |
211 | echan->missed = 0; | |
212 | } | |
c2dde5f8 MP |
213 | } |
214 | ||
215 | static int edma_terminate_all(struct edma_chan *echan) | |
216 | { | |
217 | unsigned long flags; | |
218 | LIST_HEAD(head); | |
219 | ||
220 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
221 | ||
222 | /* | |
223 | * Stop DMA activity: we assume the callback will not be called | |
224 | * after edma_dma() returns (even if it does, it will see | |
225 | * echan->edesc is NULL and exit.) | |
226 | */ | |
227 | if (echan->edesc) { | |
228 | echan->edesc = NULL; | |
229 | edma_stop(echan->ch_num); | |
230 | } | |
231 | ||
232 | vchan_get_all_descriptors(&echan->vchan, &head); | |
233 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
234 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
c2dde5f8 | 239 | static int edma_slave_config(struct edma_chan *echan, |
661f7cb5 | 240 | struct dma_slave_config *cfg) |
c2dde5f8 | 241 | { |
661f7cb5 MP |
242 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
243 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
244 | return -EINVAL; |
245 | ||
661f7cb5 | 246 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
247 | |
248 | return 0; | |
249 | } | |
250 | ||
72c7b67a PU |
251 | static int edma_dma_pause(struct edma_chan *echan) |
252 | { | |
253 | /* Pause/Resume only allowed with cyclic mode */ | |
254 | if (!echan->edesc->cyclic) | |
255 | return -EINVAL; | |
256 | ||
257 | edma_pause(echan->ch_num); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static int edma_dma_resume(struct edma_chan *echan) | |
262 | { | |
263 | /* Pause/Resume only allowed with cyclic mode */ | |
264 | if (!echan->edesc->cyclic) | |
265 | return -EINVAL; | |
266 | ||
267 | edma_resume(echan->ch_num); | |
268 | return 0; | |
269 | } | |
270 | ||
c2dde5f8 MP |
271 | static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
272 | unsigned long arg) | |
273 | { | |
274 | int ret = 0; | |
275 | struct dma_slave_config *config; | |
276 | struct edma_chan *echan = to_edma_chan(chan); | |
277 | ||
278 | switch (cmd) { | |
279 | case DMA_TERMINATE_ALL: | |
280 | edma_terminate_all(echan); | |
281 | break; | |
282 | case DMA_SLAVE_CONFIG: | |
283 | config = (struct dma_slave_config *)arg; | |
284 | ret = edma_slave_config(echan, config); | |
285 | break; | |
72c7b67a PU |
286 | case DMA_PAUSE: |
287 | ret = edma_dma_pause(echan); | |
288 | break; | |
289 | ||
290 | case DMA_RESUME: | |
291 | ret = edma_dma_resume(echan); | |
292 | break; | |
293 | ||
c2dde5f8 MP |
294 | default: |
295 | ret = -ENOSYS; | |
296 | } | |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
fd009035 JF |
301 | /* |
302 | * A PaRAM set configuration abstraction used by other modes | |
303 | * @chan: Channel who's PaRAM set we're configuring | |
304 | * @pset: PaRAM set to initialize and setup. | |
305 | * @src_addr: Source address of the DMA | |
306 | * @dst_addr: Destination address of the DMA | |
307 | * @burst: In units of dev_width, how much to send | |
308 | * @dev_width: How much is the dev_width | |
309 | * @dma_length: Total length of the DMA transfer | |
310 | * @direction: Direction of the transfer | |
311 | */ | |
b5088ad9 | 312 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
fd009035 JF |
313 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
314 | enum dma_slave_buswidth dev_width, unsigned int dma_length, | |
315 | enum dma_transfer_direction direction) | |
316 | { | |
317 | struct edma_chan *echan = to_edma_chan(chan); | |
318 | struct device *dev = chan->device->dev; | |
b5088ad9 | 319 | struct edmacc_param *param = &epset->param; |
fd009035 JF |
320 | int acnt, bcnt, ccnt, cidx; |
321 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
322 | int absync; | |
323 | ||
324 | acnt = dev_width; | |
b2b617de PU |
325 | |
326 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ | |
327 | if (!burst) | |
328 | burst = 1; | |
fd009035 JF |
329 | /* |
330 | * If the maxburst is equal to the fifo width, use | |
331 | * A-synced transfers. This allows for large contiguous | |
332 | * buffer transfers using only one PaRAM set. | |
333 | */ | |
334 | if (burst == 1) { | |
335 | /* | |
336 | * For the A-sync case, bcnt and ccnt are the remainder | |
337 | * and quotient respectively of the division of: | |
338 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
339 | * that in case bcnt over flows, we have ccnt to use. | |
340 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
341 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
342 | * In this case, the best way adopted is- bccnt for the | |
343 | * first frame will be the remainder below. Then for | |
344 | * every successive frame, bcnt will be SZ_64K-1. This | |
345 | * is assured as bcntrld = 0xffff in end of function. | |
346 | */ | |
347 | absync = false; | |
348 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
349 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
350 | /* | |
351 | * If bcnt is non-zero, we have a remainder and hence an | |
352 | * extra frame to transfer, so increment ccnt. | |
353 | */ | |
354 | if (bcnt) | |
355 | ccnt++; | |
356 | else | |
357 | bcnt = SZ_64K - 1; | |
358 | cidx = acnt; | |
359 | } else { | |
360 | /* | |
361 | * If maxburst is greater than the fifo address_width, | |
362 | * use AB-synced transfers where A count is the fifo | |
363 | * address_width and B count is the maxburst. In this | |
364 | * case, we are limited to transfers of C count frames | |
365 | * of (address_width * maxburst) where C count is limited | |
366 | * to SZ_64K-1. This places an upper bound on the length | |
367 | * of an SG segment that can be handled. | |
368 | */ | |
369 | absync = true; | |
370 | bcnt = burst; | |
371 | ccnt = dma_length / (acnt * bcnt); | |
372 | if (ccnt > (SZ_64K - 1)) { | |
373 | dev_err(dev, "Exceeded max SG segment size\n"); | |
374 | return -EINVAL; | |
375 | } | |
376 | cidx = acnt * bcnt; | |
377 | } | |
378 | ||
379 | if (direction == DMA_MEM_TO_DEV) { | |
380 | src_bidx = acnt; | |
381 | src_cidx = cidx; | |
382 | dst_bidx = 0; | |
383 | dst_cidx = 0; | |
384 | } else if (direction == DMA_DEV_TO_MEM) { | |
385 | src_bidx = 0; | |
386 | src_cidx = 0; | |
387 | dst_bidx = acnt; | |
388 | dst_cidx = cidx; | |
8cc3e30b JF |
389 | } else if (direction == DMA_MEM_TO_MEM) { |
390 | src_bidx = acnt; | |
391 | src_cidx = cidx; | |
392 | dst_bidx = acnt; | |
393 | dst_cidx = cidx; | |
fd009035 JF |
394 | } else { |
395 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
396 | return -EINVAL; | |
397 | } | |
398 | ||
b5088ad9 | 399 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
fd009035 JF |
400 | /* Configure A or AB synchronized transfers */ |
401 | if (absync) | |
b5088ad9 | 402 | param->opt |= SYNCDIM; |
fd009035 | 403 | |
b5088ad9 TG |
404 | param->src = src_addr; |
405 | param->dst = dst_addr; | |
fd009035 | 406 | |
b5088ad9 TG |
407 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
408 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
fd009035 | 409 | |
b5088ad9 TG |
410 | param->a_b_cnt = bcnt << 16 | acnt; |
411 | param->ccnt = ccnt; | |
fd009035 JF |
412 | /* |
413 | * Only time when (bcntrld) auto reload is required is for | |
414 | * A-sync case, and in this case, a requirement of reload value | |
415 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
416 | * and then later will be populated by edma_execute. | |
417 | */ | |
b5088ad9 | 418 | param->link_bcntrld = 0xffffffff; |
fd009035 JF |
419 | return absync; |
420 | } | |
421 | ||
c2dde5f8 MP |
422 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
423 | struct dma_chan *chan, struct scatterlist *sgl, | |
424 | unsigned int sg_len, enum dma_transfer_direction direction, | |
425 | unsigned long tx_flags, void *context) | |
426 | { | |
427 | struct edma_chan *echan = to_edma_chan(chan); | |
428 | struct device *dev = chan->device->dev; | |
429 | struct edma_desc *edesc; | |
fd009035 | 430 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
431 | enum dma_slave_buswidth dev_width; |
432 | u32 burst; | |
c2dde5f8 | 433 | struct scatterlist *sg; |
fd009035 | 434 | int i, nslots, ret; |
c2dde5f8 MP |
435 | |
436 | if (unlikely(!echan || !sgl || !sg_len)) | |
437 | return NULL; | |
438 | ||
661f7cb5 | 439 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 440 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
441 | dev_width = echan->cfg.src_addr_width; |
442 | burst = echan->cfg.src_maxburst; | |
443 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 444 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
445 | dev_width = echan->cfg.dst_addr_width; |
446 | burst = echan->cfg.dst_maxburst; | |
447 | } else { | |
e6fad592 | 448 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
661f7cb5 MP |
449 | return NULL; |
450 | } | |
451 | ||
452 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 453 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
454 | return NULL; |
455 | } | |
456 | ||
c2dde5f8 MP |
457 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
458 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
459 | if (!edesc) { | |
c594c891 | 460 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
c2dde5f8 MP |
461 | return NULL; |
462 | } | |
463 | ||
464 | edesc->pset_nr = sg_len; | |
b6205c39 | 465 | edesc->residue = 0; |
c2dde5f8 | 466 | |
6fbe24da JF |
467 | /* Allocate a PaRAM slot, if needed */ |
468 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
469 | ||
470 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
471 | if (echan->slot[i] < 0) { |
472 | echan->slot[i] = | |
473 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
474 | EDMA_SLOT_ANY); | |
475 | if (echan->slot[i] < 0) { | |
4b6271a6 | 476 | kfree(edesc); |
c594c891 PU |
477 | dev_err(dev, "%s: Failed to allocate slot\n", |
478 | __func__); | |
c2dde5f8 MP |
479 | return NULL; |
480 | } | |
481 | } | |
6fbe24da JF |
482 | } |
483 | ||
484 | /* Configure PaRAM sets for each SG */ | |
485 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
486 | /* Get address for each SG */ |
487 | if (direction == DMA_DEV_TO_MEM) | |
488 | dst_addr = sg_dma_address(sg); | |
489 | else | |
490 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 491 | |
fd009035 JF |
492 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
493 | dst_addr, burst, dev_width, | |
494 | sg_dma_len(sg), direction); | |
b967aecf VK |
495 | if (ret < 0) { |
496 | kfree(edesc); | |
fd009035 | 497 | return NULL; |
c2dde5f8 MP |
498 | } |
499 | ||
fd009035 | 500 | edesc->absync = ret; |
b6205c39 | 501 | edesc->residue += sg_dma_len(sg); |
6fbe24da JF |
502 | |
503 | /* If this is the last in a current SG set of transactions, | |
504 | enable interrupts so that next set is processed */ | |
505 | if (!((i+1) % MAX_NR_SG)) | |
b5088ad9 | 506 | edesc->pset[i].param.opt |= TCINTEN; |
6fbe24da | 507 | |
c2dde5f8 MP |
508 | /* If this is the last set, enable completion interrupt flag */ |
509 | if (i == sg_len - 1) | |
b5088ad9 | 510 | edesc->pset[i].param.opt |= TCINTEN; |
c2dde5f8 | 511 | } |
c2dde5f8 | 512 | |
c2dde5f8 MP |
513 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
514 | } | |
c2dde5f8 | 515 | |
8cc3e30b JF |
516 | struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
517 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
518 | size_t len, unsigned long tx_flags) | |
519 | { | |
520 | int ret; | |
521 | struct edma_desc *edesc; | |
522 | struct device *dev = chan->device->dev; | |
523 | struct edma_chan *echan = to_edma_chan(chan); | |
524 | ||
525 | if (unlikely(!echan || !len)) | |
526 | return NULL; | |
527 | ||
528 | edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC); | |
529 | if (!edesc) { | |
530 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
531 | return NULL; | |
532 | } | |
533 | ||
534 | edesc->pset_nr = 1; | |
535 | ||
536 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, | |
537 | DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM); | |
538 | if (ret < 0) | |
539 | return NULL; | |
540 | ||
541 | edesc->absync = ret; | |
542 | ||
543 | /* | |
544 | * Enable intermediate transfer chaining to re-trigger channel | |
545 | * on completion of every TR, and enable transfer-completion | |
546 | * interrupt on completion of the whole transfer. | |
547 | */ | |
548 | edesc->pset[0].opt |= ITCCHEN; | |
549 | edesc->pset[0].opt |= TCINTEN; | |
550 | ||
551 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
552 | } | |
553 | ||
50a9c707 JF |
554 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
555 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
556 | size_t period_len, enum dma_transfer_direction direction, | |
557 | unsigned long tx_flags, void *context) | |
558 | { | |
559 | struct edma_chan *echan = to_edma_chan(chan); | |
560 | struct device *dev = chan->device->dev; | |
561 | struct edma_desc *edesc; | |
562 | dma_addr_t src_addr, dst_addr; | |
563 | enum dma_slave_buswidth dev_width; | |
564 | u32 burst; | |
565 | int i, ret, nslots; | |
566 | ||
567 | if (unlikely(!echan || !buf_len || !period_len)) | |
568 | return NULL; | |
569 | ||
570 | if (direction == DMA_DEV_TO_MEM) { | |
571 | src_addr = echan->cfg.src_addr; | |
572 | dst_addr = buf_addr; | |
573 | dev_width = echan->cfg.src_addr_width; | |
574 | burst = echan->cfg.src_maxburst; | |
575 | } else if (direction == DMA_MEM_TO_DEV) { | |
576 | src_addr = buf_addr; | |
577 | dst_addr = echan->cfg.dst_addr; | |
578 | dev_width = echan->cfg.dst_addr_width; | |
579 | burst = echan->cfg.dst_maxburst; | |
580 | } else { | |
e6fad592 | 581 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
50a9c707 JF |
582 | return NULL; |
583 | } | |
584 | ||
585 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 586 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
587 | return NULL; |
588 | } | |
589 | ||
590 | if (unlikely(buf_len % period_len)) { | |
591 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
592 | return NULL; | |
593 | } | |
594 | ||
595 | nslots = (buf_len / period_len) + 1; | |
596 | ||
597 | /* | |
598 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
599 | * by cases where the number of periods is more than the maximum | |
600 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
601 | * such as Slave SGs, such delays are tolerable and synchronized, | |
602 | * but the synchronization is difficult to achieve with Cyclic and | |
603 | * cannot be guaranteed, so we error out early. | |
604 | */ | |
605 | if (nslots > MAX_NR_SG) | |
606 | return NULL; | |
607 | ||
608 | edesc = kzalloc(sizeof(*edesc) + nslots * | |
609 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
610 | if (!edesc) { | |
c594c891 | 611 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
50a9c707 JF |
612 | return NULL; |
613 | } | |
614 | ||
615 | edesc->cyclic = 1; | |
616 | edesc->pset_nr = nslots; | |
b6205c39 | 617 | edesc->residue = buf_len; |
50a9c707 | 618 | |
83bb3126 PU |
619 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
620 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
621 | |
622 | for (i = 0; i < nslots; i++) { | |
623 | /* Allocate a PaRAM slot, if needed */ | |
624 | if (echan->slot[i] < 0) { | |
625 | echan->slot[i] = | |
626 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
627 | EDMA_SLOT_ANY); | |
628 | if (echan->slot[i] < 0) { | |
e3ddc979 | 629 | kfree(edesc); |
c594c891 PU |
630 | dev_err(dev, "%s: Failed to allocate slot\n", |
631 | __func__); | |
50a9c707 JF |
632 | return NULL; |
633 | } | |
634 | } | |
635 | ||
636 | if (i == nslots - 1) { | |
637 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
638 | sizeof(edesc->pset[0])); | |
639 | break; | |
640 | } | |
641 | ||
642 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
643 | dst_addr, burst, dev_width, period_len, | |
644 | direction); | |
e3ddc979 CE |
645 | if (ret < 0) { |
646 | kfree(edesc); | |
50a9c707 | 647 | return NULL; |
e3ddc979 | 648 | } |
c2dde5f8 | 649 | |
50a9c707 JF |
650 | if (direction == DMA_DEV_TO_MEM) |
651 | dst_addr += period_len; | |
652 | else | |
653 | src_addr += period_len; | |
c2dde5f8 | 654 | |
83bb3126 PU |
655 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
656 | dev_vdbg(dev, | |
50a9c707 JF |
657 | "\n pset[%d]:\n" |
658 | " chnum\t%d\n" | |
659 | " slot\t%d\n" | |
660 | " opt\t%08x\n" | |
661 | " src\t%08x\n" | |
662 | " dst\t%08x\n" | |
663 | " abcnt\t%08x\n" | |
664 | " ccnt\t%08x\n" | |
665 | " bidx\t%08x\n" | |
666 | " cidx\t%08x\n" | |
667 | " lkrld\t%08x\n", | |
668 | i, echan->ch_num, echan->slot[i], | |
b5088ad9 TG |
669 | edesc->pset[i].param.opt, |
670 | edesc->pset[i].param.src, | |
671 | edesc->pset[i].param.dst, | |
672 | edesc->pset[i].param.a_b_cnt, | |
673 | edesc->pset[i].param.ccnt, | |
674 | edesc->pset[i].param.src_dst_bidx, | |
675 | edesc->pset[i].param.src_dst_cidx, | |
676 | edesc->pset[i].param.link_bcntrld); | |
50a9c707 JF |
677 | |
678 | edesc->absync = ret; | |
679 | ||
680 | /* | |
681 | * Enable interrupts for every period because callback | |
682 | * has to be called for every period. | |
683 | */ | |
b5088ad9 | 684 | edesc->pset[i].param.opt |= TCINTEN; |
c2dde5f8 MP |
685 | } |
686 | ||
687 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
688 | } | |
689 | ||
690 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
691 | { | |
692 | struct edma_chan *echan = data; | |
693 | struct device *dev = echan->vchan.chan.device->dev; | |
694 | struct edma_desc *edesc; | |
c5f47990 | 695 | struct edmacc_param p; |
c2dde5f8 | 696 | |
50a9c707 JF |
697 | edesc = echan->edesc; |
698 | ||
699 | /* Pause the channel for non-cyclic */ | |
700 | if (!edesc || (edesc && !edesc->cyclic)) | |
701 | edma_pause(echan->ch_num); | |
c2dde5f8 MP |
702 | |
703 | switch (ch_status) { | |
db60d8da | 704 | case EDMA_DMA_COMPLETE: |
406efb1a | 705 | spin_lock(&echan->vchan.lock); |
c2dde5f8 | 706 | |
c2dde5f8 | 707 | if (edesc) { |
50a9c707 JF |
708 | if (edesc->cyclic) { |
709 | vchan_cyclic_callback(&edesc->vdesc); | |
710 | } else if (edesc->processed == edesc->pset_nr) { | |
53407062 | 711 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); |
b6205c39 | 712 | edesc->residue = 0; |
53407062 JF |
713 | edma_stop(echan->ch_num); |
714 | vchan_cookie_complete(&edesc->vdesc); | |
50a9c707 | 715 | edma_execute(echan); |
53407062 JF |
716 | } else { |
717 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
50a9c707 | 718 | edma_execute(echan); |
53407062 | 719 | } |
c2dde5f8 MP |
720 | } |
721 | ||
406efb1a | 722 | spin_unlock(&echan->vchan.lock); |
c2dde5f8 MP |
723 | |
724 | break; | |
db60d8da | 725 | case EDMA_DMA_CC_ERROR: |
406efb1a | 726 | spin_lock(&echan->vchan.lock); |
c5f47990 JF |
727 | |
728 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); | |
729 | ||
730 | /* | |
731 | * Issue later based on missed flag which will be sure | |
732 | * to happen as: | |
733 | * (1) we finished transmitting an intermediate slot and | |
734 | * edma_execute is coming up. | |
735 | * (2) or we finished current transfer and issue will | |
736 | * call edma_execute. | |
737 | * | |
738 | * Important note: issuing can be dangerous here and | |
739 | * lead to some nasty recursion when we are in a NULL | |
740 | * slot. So we avoid doing so and set the missed flag. | |
741 | */ | |
742 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
743 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
744 | echan->missed = 1; | |
745 | } else { | |
746 | /* | |
747 | * The slot is already programmed but the event got | |
748 | * missed, so its safe to issue it here. | |
749 | */ | |
750 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
751 | edma_clean_channel(echan->ch_num); | |
752 | edma_stop(echan->ch_num); | |
753 | edma_start(echan->ch_num); | |
754 | edma_trigger_channel(echan->ch_num); | |
755 | } | |
756 | ||
406efb1a | 757 | spin_unlock(&echan->vchan.lock); |
c5f47990 | 758 | |
c2dde5f8 MP |
759 | break; |
760 | default: | |
761 | break; | |
762 | } | |
763 | } | |
764 | ||
765 | /* Alloc channel resources */ | |
766 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
767 | { | |
768 | struct edma_chan *echan = to_edma_chan(chan); | |
769 | struct device *dev = chan->device->dev; | |
770 | int ret; | |
771 | int a_ch_num; | |
772 | LIST_HEAD(descs); | |
773 | ||
774 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
775 | chan, EVENTQ_DEFAULT); | |
776 | ||
777 | if (a_ch_num < 0) { | |
778 | ret = -ENODEV; | |
779 | goto err_no_chan; | |
780 | } | |
781 | ||
782 | if (a_ch_num != echan->ch_num) { | |
783 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
784 | EDMA_CTLR(echan->ch_num), | |
785 | EDMA_CHAN_SLOT(echan->ch_num)); | |
786 | ret = -ENODEV; | |
787 | goto err_wrong_chan; | |
788 | } | |
789 | ||
790 | echan->alloced = true; | |
791 | echan->slot[0] = echan->ch_num; | |
792 | ||
9aac9096 | 793 | dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, |
0e772c67 | 794 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); |
c2dde5f8 MP |
795 | |
796 | return 0; | |
797 | ||
798 | err_wrong_chan: | |
799 | edma_free_channel(a_ch_num); | |
800 | err_no_chan: | |
801 | return ret; | |
802 | } | |
803 | ||
804 | /* Free channel resources */ | |
805 | static void edma_free_chan_resources(struct dma_chan *chan) | |
806 | { | |
807 | struct edma_chan *echan = to_edma_chan(chan); | |
808 | struct device *dev = chan->device->dev; | |
809 | int i; | |
810 | ||
811 | /* Terminate transfers */ | |
812 | edma_stop(echan->ch_num); | |
813 | ||
814 | vchan_free_chan_resources(&echan->vchan); | |
815 | ||
816 | /* Free EDMA PaRAM slots */ | |
817 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
818 | if (echan->slot[i] >= 0) { | |
819 | edma_free_slot(echan->slot[i]); | |
820 | echan->slot[i] = -1; | |
821 | } | |
822 | } | |
823 | ||
824 | /* Free EDMA channel */ | |
825 | if (echan->alloced) { | |
826 | edma_free_channel(echan->ch_num); | |
827 | echan->alloced = false; | |
828 | } | |
829 | ||
0e772c67 | 830 | dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); |
c2dde5f8 MP |
831 | } |
832 | ||
833 | /* Send pending descriptor to hardware */ | |
834 | static void edma_issue_pending(struct dma_chan *chan) | |
835 | { | |
836 | struct edma_chan *echan = to_edma_chan(chan); | |
837 | unsigned long flags; | |
838 | ||
839 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
840 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
841 | edma_execute(echan); | |
842 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
843 | } | |
844 | ||
c2dde5f8 MP |
845 | /* Check request completion status */ |
846 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
847 | dma_cookie_t cookie, | |
848 | struct dma_tx_state *txstate) | |
849 | { | |
850 | struct edma_chan *echan = to_edma_chan(chan); | |
851 | struct virt_dma_desc *vdesc; | |
852 | enum dma_status ret; | |
853 | unsigned long flags; | |
854 | ||
855 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 856 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
857 | return ret; |
858 | ||
859 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
de135939 | 860 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
b6205c39 | 861 | txstate->residue = echan->edesc->residue; |
de135939 TG |
862 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
863 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; | |
c2dde5f8 MP |
864 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
865 | ||
866 | return ret; | |
867 | } | |
868 | ||
869 | static void __init edma_chan_init(struct edma_cc *ecc, | |
870 | struct dma_device *dma, | |
871 | struct edma_chan *echans) | |
872 | { | |
873 | int i, j; | |
874 | ||
875 | for (i = 0; i < EDMA_CHANS; i++) { | |
876 | struct edma_chan *echan = &echans[i]; | |
877 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
878 | echan->ecc = ecc; | |
879 | echan->vchan.desc_free = edma_desc_free; | |
880 | ||
881 | vchan_init(&echan->vchan, dma); | |
882 | ||
883 | INIT_LIST_HEAD(&echan->node); | |
884 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
885 | echan->slot[j] = -1; | |
886 | } | |
887 | } | |
888 | ||
2c88ee6b PU |
889 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
890 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
891 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
892 | ||
893 | static int edma_dma_device_slave_caps(struct dma_chan *dchan, | |
894 | struct dma_slave_caps *caps) | |
895 | { | |
896 | caps->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
897 | caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS; | |
898 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
899 | caps->cmd_pause = true; | |
900 | caps->cmd_terminate = true; | |
901 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
c2dde5f8 MP |
906 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, |
907 | struct device *dev) | |
908 | { | |
909 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
50a9c707 | 910 | dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; |
8cc3e30b | 911 | dma->device_prep_dma_memcpy = edma_prep_dma_memcpy; |
c2dde5f8 MP |
912 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; |
913 | dma->device_free_chan_resources = edma_free_chan_resources; | |
914 | dma->device_issue_pending = edma_issue_pending; | |
915 | dma->device_tx_status = edma_tx_status; | |
916 | dma->device_control = edma_control; | |
2c88ee6b | 917 | dma->device_slave_caps = edma_dma_device_slave_caps; |
c2dde5f8 MP |
918 | dma->dev = dev; |
919 | ||
8cc3e30b JF |
920 | /* |
921 | * code using dma memcpy must make sure alignment of | |
922 | * length is at dma->copy_align boundary. | |
923 | */ | |
924 | dma->copy_align = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
925 | ||
c2dde5f8 MP |
926 | INIT_LIST_HEAD(&dma->channels); |
927 | } | |
928 | ||
463a1f8b | 929 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
930 | { |
931 | struct edma_cc *ecc; | |
932 | int ret; | |
933 | ||
94cb0e79 RK |
934 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
935 | if (ret) | |
936 | return ret; | |
937 | ||
c2dde5f8 MP |
938 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); |
939 | if (!ecc) { | |
940 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
941 | return -ENOMEM; | |
942 | } | |
943 | ||
944 | ecc->ctlr = pdev->id; | |
945 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
946 | if (ecc->dummy_slot < 0) { | |
947 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
948 | return -EIO; | |
949 | } | |
950 | ||
951 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
952 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
232b223d | 953 | dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); |
8cc3e30b | 954 | dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); |
c2dde5f8 MP |
955 | |
956 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
957 | ||
958 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
959 | ||
960 | ret = dma_async_device_register(&ecc->dma_slave); | |
961 | if (ret) | |
962 | goto err_reg1; | |
963 | ||
964 | platform_set_drvdata(pdev, ecc); | |
965 | ||
966 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
967 | ||
968 | return 0; | |
969 | ||
970 | err_reg1: | |
971 | edma_free_slot(ecc->dummy_slot); | |
972 | return ret; | |
973 | } | |
974 | ||
4bf27b8b | 975 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
976 | { |
977 | struct device *dev = &pdev->dev; | |
978 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
979 | ||
980 | dma_async_device_unregister(&ecc->dma_slave); | |
981 | edma_free_slot(ecc->dummy_slot); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static struct platform_driver edma_driver = { | |
987 | .probe = edma_probe, | |
a7d6e3ec | 988 | .remove = edma_remove, |
c2dde5f8 MP |
989 | .driver = { |
990 | .name = "edma-dma-engine", | |
991 | .owner = THIS_MODULE, | |
992 | }, | |
993 | }; | |
994 | ||
995 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
996 | { | |
997 | if (chan->device->dev->driver == &edma_driver.driver) { | |
998 | struct edma_chan *echan = to_edma_chan(chan); | |
999 | unsigned ch_req = *(unsigned *)param; | |
1000 | return ch_req == echan->ch_num; | |
1001 | } | |
1002 | return false; | |
1003 | } | |
1004 | EXPORT_SYMBOL(edma_filter_fn); | |
1005 | ||
1006 | static struct platform_device *pdev0, *pdev1; | |
1007 | ||
1008 | static const struct platform_device_info edma_dev_info0 = { | |
1009 | .name = "edma-dma-engine", | |
1010 | .id = 0, | |
94cb0e79 | 1011 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
1012 | }; |
1013 | ||
1014 | static const struct platform_device_info edma_dev_info1 = { | |
1015 | .name = "edma-dma-engine", | |
1016 | .id = 1, | |
94cb0e79 | 1017 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
1018 | }; |
1019 | ||
1020 | static int edma_init(void) | |
1021 | { | |
1022 | int ret = platform_driver_register(&edma_driver); | |
1023 | ||
1024 | if (ret == 0) { | |
1025 | pdev0 = platform_device_register_full(&edma_dev_info0); | |
1026 | if (IS_ERR(pdev0)) { | |
1027 | platform_driver_unregister(&edma_driver); | |
1028 | ret = PTR_ERR(pdev0); | |
1029 | goto out; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | if (EDMA_CTLRS == 2) { | |
1034 | pdev1 = platform_device_register_full(&edma_dev_info1); | |
1035 | if (IS_ERR(pdev1)) { | |
1036 | platform_driver_unregister(&edma_driver); | |
1037 | platform_device_unregister(pdev0); | |
1038 | ret = PTR_ERR(pdev1); | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | out: | |
1043 | return ret; | |
1044 | } | |
1045 | subsys_initcall(edma_init); | |
1046 | ||
1047 | static void __exit edma_exit(void) | |
1048 | { | |
1049 | platform_device_unregister(pdev0); | |
1050 | if (pdev1) | |
1051 | platform_device_unregister(pdev1); | |
1052 | platform_driver_unregister(&edma_driver); | |
1053 | } | |
1054 | module_exit(edma_exit); | |
1055 | ||
d71505b6 | 1056 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
1057 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
1058 | MODULE_LICENSE("GPL v2"); |