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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
b7a4fd53 | 18 | #include <linux/edma.h> |
c2dde5f8 MP |
19 | #include <linux/err.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
ed64610f | 27 | #include <linux/of.h> |
c2dde5f8 | 28 | |
3ad7a42d | 29 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
30 | |
31 | #include "dmaengine.h" | |
32 | #include "virt-dma.h" | |
33 | ||
34 | /* | |
35 | * This will go away when the private EDMA API is folded | |
36 | * into this driver and the platform device(s) are | |
37 | * instantiated in the arch code. We can only get away | |
38 | * with this simplification because DA8XX may not be built | |
39 | * in the same kernel image with other DaVinci parts. This | |
40 | * avoids having to sprinkle dmaengine driver platform devices | |
41 | * and data throughout all the existing board files. | |
42 | */ | |
43 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
44 | #define EDMA_CTLRS 2 | |
45 | #define EDMA_CHANS 32 | |
46 | #else | |
47 | #define EDMA_CTLRS 1 | |
48 | #define EDMA_CHANS 64 | |
49 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
50 | ||
2abd5f1b JF |
51 | /* |
52 | * Max of 20 segments per channel to conserve PaRAM slots | |
53 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
54 | * that are required for ASoC, otherwise DMA prep calls will | |
55 | * fail. Today davinci-pcm is the only user of this driver and | |
56 | * requires atleast 17 slots, so we setup the default to 20. | |
57 | */ | |
58 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
59 | #define EDMA_MAX_SLOTS MAX_NR_SG |
60 | #define EDMA_DESCRIPTORS 16 | |
61 | ||
b5088ad9 | 62 | struct edma_pset { |
c2da2340 TG |
63 | u32 len; |
64 | dma_addr_t addr; | |
b5088ad9 TG |
65 | struct edmacc_param param; |
66 | }; | |
67 | ||
c2dde5f8 MP |
68 | struct edma_desc { |
69 | struct virt_dma_desc vdesc; | |
70 | struct list_head node; | |
c2da2340 | 71 | enum dma_transfer_direction direction; |
50a9c707 | 72 | int cyclic; |
c2dde5f8 MP |
73 | int absync; |
74 | int pset_nr; | |
04361d88 | 75 | struct edma_chan *echan; |
53407062 | 76 | int processed; |
04361d88 JF |
77 | |
78 | /* | |
79 | * The following 4 elements are used for residue accounting. | |
80 | * | |
81 | * - processed_stat: the number of SG elements we have traversed | |
82 | * so far to cover accounting. This is updated directly to processed | |
83 | * during edma_callback and is always <= processed, because processed | |
84 | * refers to the number of pending transfer (programmed to EDMA | |
85 | * controller), where as processed_stat tracks number of transfers | |
86 | * accounted for so far. | |
87 | * | |
88 | * - residue: The amount of bytes we have left to transfer for this desc | |
89 | * | |
90 | * - residue_stat: The residue in bytes of data we have covered | |
91 | * so far for accounting. This is updated directly to residue | |
92 | * during callbacks to keep it current. | |
93 | * | |
94 | * - sg_len: Tracks the length of the current intermediate transfer, | |
95 | * this is required to update the residue during intermediate transfer | |
96 | * completion callback. | |
97 | */ | |
740b41f7 | 98 | int processed_stat; |
740b41f7 | 99 | u32 sg_len; |
04361d88 | 100 | u32 residue; |
740b41f7 | 101 | u32 residue_stat; |
04361d88 | 102 | |
b5088ad9 | 103 | struct edma_pset pset[0]; |
c2dde5f8 MP |
104 | }; |
105 | ||
106 | struct edma_cc; | |
107 | ||
108 | struct edma_chan { | |
109 | struct virt_dma_chan vchan; | |
110 | struct list_head node; | |
111 | struct edma_desc *edesc; | |
112 | struct edma_cc *ecc; | |
113 | int ch_num; | |
114 | bool alloced; | |
115 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 116 | int missed; |
661f7cb5 | 117 | struct dma_slave_config cfg; |
c2dde5f8 MP |
118 | }; |
119 | ||
120 | struct edma_cc { | |
121 | int ctlr; | |
122 | struct dma_device dma_slave; | |
123 | struct edma_chan slave_chans[EDMA_CHANS]; | |
124 | int num_slave_chans; | |
125 | int dummy_slot; | |
126 | }; | |
127 | ||
128 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
129 | { | |
130 | return container_of(d, struct edma_cc, dma_slave); | |
131 | } | |
132 | ||
133 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
134 | { | |
135 | return container_of(c, struct edma_chan, vchan.chan); | |
136 | } | |
137 | ||
138 | static inline struct edma_desc | |
139 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
140 | { | |
141 | return container_of(tx, struct edma_desc, vdesc.tx); | |
142 | } | |
143 | ||
144 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
145 | { | |
146 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
147 | } | |
148 | ||
149 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
150 | static void edma_execute(struct edma_chan *echan) | |
151 | { | |
53407062 | 152 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 153 | struct edma_desc *edesc; |
53407062 JF |
154 | struct device *dev = echan->vchan.chan.device->dev; |
155 | int i, j, left, nslots; | |
156 | ||
8fa7ff4f PU |
157 | if (!echan->edesc) { |
158 | /* Setup is needed for the first transfer */ | |
53407062 | 159 | vdesc = vchan_next_desc(&echan->vchan); |
8fa7ff4f | 160 | if (!vdesc) |
53407062 | 161 | return; |
53407062 JF |
162 | list_del(&vdesc->node); |
163 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
164 | } |
165 | ||
53407062 | 166 | edesc = echan->edesc; |
c2dde5f8 | 167 | |
53407062 JF |
168 | /* Find out how many left */ |
169 | left = edesc->pset_nr - edesc->processed; | |
170 | nslots = min(MAX_NR_SG, left); | |
740b41f7 | 171 | edesc->sg_len = 0; |
c2dde5f8 MP |
172 | |
173 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
174 | for (i = 0; i < nslots; i++) { |
175 | j = i + edesc->processed; | |
b5088ad9 | 176 | edma_write_slot(echan->slot[i], &edesc->pset[j].param); |
740b41f7 | 177 | edesc->sg_len += edesc->pset[j].len; |
83bb3126 | 178 | dev_vdbg(echan->vchan.chan.device->dev, |
c2dde5f8 MP |
179 | "\n pset[%d]:\n" |
180 | " chnum\t%d\n" | |
181 | " slot\t%d\n" | |
182 | " opt\t%08x\n" | |
183 | " src\t%08x\n" | |
184 | " dst\t%08x\n" | |
185 | " abcnt\t%08x\n" | |
186 | " ccnt\t%08x\n" | |
187 | " bidx\t%08x\n" | |
188 | " cidx\t%08x\n" | |
189 | " lkrld\t%08x\n", | |
53407062 | 190 | j, echan->ch_num, echan->slot[i], |
b5088ad9 TG |
191 | edesc->pset[j].param.opt, |
192 | edesc->pset[j].param.src, | |
193 | edesc->pset[j].param.dst, | |
194 | edesc->pset[j].param.a_b_cnt, | |
195 | edesc->pset[j].param.ccnt, | |
196 | edesc->pset[j].param.src_dst_bidx, | |
197 | edesc->pset[j].param.src_dst_cidx, | |
198 | edesc->pset[j].param.link_bcntrld); | |
c2dde5f8 | 199 | /* Link to the previous slot if not the last set */ |
53407062 | 200 | if (i != (nslots - 1)) |
c2dde5f8 | 201 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
202 | } |
203 | ||
53407062 JF |
204 | edesc->processed += nslots; |
205 | ||
b267b3bc JF |
206 | /* |
207 | * If this is either the last set in a set of SG-list transactions | |
208 | * then setup a link to the dummy slot, this results in all future | |
209 | * events being absorbed and that's OK because we're done | |
210 | */ | |
50a9c707 JF |
211 | if (edesc->processed == edesc->pset_nr) { |
212 | if (edesc->cyclic) | |
213 | edma_link(echan->slot[nslots-1], echan->slot[1]); | |
214 | else | |
215 | edma_link(echan->slot[nslots-1], | |
216 | echan->ecc->dummy_slot); | |
217 | } | |
b267b3bc | 218 | |
c5f47990 | 219 | if (echan->missed) { |
8fa7ff4f PU |
220 | /* |
221 | * This happens due to setup times between intermediate | |
222 | * transfers in long SG lists which have to be broken up into | |
223 | * transfers of MAX_NR_SG | |
224 | */ | |
9aac9096 | 225 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
c5f47990 JF |
226 | edma_clean_channel(echan->ch_num); |
227 | edma_stop(echan->ch_num); | |
228 | edma_start(echan->ch_num); | |
229 | edma_trigger_channel(echan->ch_num); | |
230 | echan->missed = 0; | |
8fa7ff4f PU |
231 | } else if (edesc->processed <= MAX_NR_SG) { |
232 | dev_dbg(dev, "first transfer starting on channel %d\n", | |
233 | echan->ch_num); | |
234 | edma_start(echan->ch_num); | |
235 | } else { | |
236 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
237 | echan->ch_num, edesc->processed); | |
238 | edma_resume(echan->ch_num); | |
c5f47990 | 239 | } |
c2dde5f8 MP |
240 | } |
241 | ||
aa7c09b6 | 242 | static int edma_terminate_all(struct dma_chan *chan) |
c2dde5f8 | 243 | { |
aa7c09b6 | 244 | struct edma_chan *echan = to_edma_chan(chan); |
c2dde5f8 MP |
245 | unsigned long flags; |
246 | LIST_HEAD(head); | |
247 | ||
248 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
249 | ||
250 | /* | |
251 | * Stop DMA activity: we assume the callback will not be called | |
252 | * after edma_dma() returns (even if it does, it will see | |
253 | * echan->edesc is NULL and exit.) | |
254 | */ | |
255 | if (echan->edesc) { | |
8fa7ff4f PU |
256 | edma_stop(echan->ch_num); |
257 | /* Move the cyclic channel back to default queue */ | |
258 | if (echan->edesc->cyclic) | |
259 | edma_assign_channel_eventq(echan->ch_num, | |
260 | EVENTQ_DEFAULT); | |
5ca9e7ce PK |
261 | /* |
262 | * free the running request descriptor | |
263 | * since it is not in any of the vdesc lists | |
264 | */ | |
265 | edma_desc_free(&echan->edesc->vdesc); | |
c2dde5f8 | 266 | echan->edesc = NULL; |
c2dde5f8 MP |
267 | } |
268 | ||
269 | vchan_get_all_descriptors(&echan->vchan, &head); | |
270 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
271 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
aa7c09b6 | 276 | static int edma_slave_config(struct dma_chan *chan, |
661f7cb5 | 277 | struct dma_slave_config *cfg) |
c2dde5f8 | 278 | { |
aa7c09b6 MR |
279 | struct edma_chan *echan = to_edma_chan(chan); |
280 | ||
661f7cb5 MP |
281 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
282 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
283 | return -EINVAL; |
284 | ||
661f7cb5 | 285 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
aa7c09b6 | 290 | static int edma_dma_pause(struct dma_chan *chan) |
72c7b67a | 291 | { |
aa7c09b6 MR |
292 | struct edma_chan *echan = to_edma_chan(chan); |
293 | ||
02ec6041 | 294 | if (!echan->edesc) |
72c7b67a PU |
295 | return -EINVAL; |
296 | ||
297 | edma_pause(echan->ch_num); | |
298 | return 0; | |
299 | } | |
300 | ||
aa7c09b6 | 301 | static int edma_dma_resume(struct dma_chan *chan) |
72c7b67a | 302 | { |
aa7c09b6 MR |
303 | struct edma_chan *echan = to_edma_chan(chan); |
304 | ||
72c7b67a PU |
305 | edma_resume(echan->ch_num); |
306 | return 0; | |
307 | } | |
308 | ||
fd009035 JF |
309 | /* |
310 | * A PaRAM set configuration abstraction used by other modes | |
311 | * @chan: Channel who's PaRAM set we're configuring | |
312 | * @pset: PaRAM set to initialize and setup. | |
313 | * @src_addr: Source address of the DMA | |
314 | * @dst_addr: Destination address of the DMA | |
315 | * @burst: In units of dev_width, how much to send | |
316 | * @dev_width: How much is the dev_width | |
317 | * @dma_length: Total length of the DMA transfer | |
318 | * @direction: Direction of the transfer | |
319 | */ | |
b5088ad9 | 320 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
fd009035 JF |
321 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
322 | enum dma_slave_buswidth dev_width, unsigned int dma_length, | |
323 | enum dma_transfer_direction direction) | |
324 | { | |
325 | struct edma_chan *echan = to_edma_chan(chan); | |
326 | struct device *dev = chan->device->dev; | |
b5088ad9 | 327 | struct edmacc_param *param = &epset->param; |
fd009035 JF |
328 | int acnt, bcnt, ccnt, cidx; |
329 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
330 | int absync; | |
331 | ||
332 | acnt = dev_width; | |
b2b617de PU |
333 | |
334 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ | |
335 | if (!burst) | |
336 | burst = 1; | |
fd009035 JF |
337 | /* |
338 | * If the maxburst is equal to the fifo width, use | |
339 | * A-synced transfers. This allows for large contiguous | |
340 | * buffer transfers using only one PaRAM set. | |
341 | */ | |
342 | if (burst == 1) { | |
343 | /* | |
344 | * For the A-sync case, bcnt and ccnt are the remainder | |
345 | * and quotient respectively of the division of: | |
346 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
347 | * that in case bcnt over flows, we have ccnt to use. | |
348 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
349 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
350 | * In this case, the best way adopted is- bccnt for the | |
351 | * first frame will be the remainder below. Then for | |
352 | * every successive frame, bcnt will be SZ_64K-1. This | |
353 | * is assured as bcntrld = 0xffff in end of function. | |
354 | */ | |
355 | absync = false; | |
356 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
357 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
358 | /* | |
359 | * If bcnt is non-zero, we have a remainder and hence an | |
360 | * extra frame to transfer, so increment ccnt. | |
361 | */ | |
362 | if (bcnt) | |
363 | ccnt++; | |
364 | else | |
365 | bcnt = SZ_64K - 1; | |
366 | cidx = acnt; | |
367 | } else { | |
368 | /* | |
369 | * If maxburst is greater than the fifo address_width, | |
370 | * use AB-synced transfers where A count is the fifo | |
371 | * address_width and B count is the maxburst. In this | |
372 | * case, we are limited to transfers of C count frames | |
373 | * of (address_width * maxburst) where C count is limited | |
374 | * to SZ_64K-1. This places an upper bound on the length | |
375 | * of an SG segment that can be handled. | |
376 | */ | |
377 | absync = true; | |
378 | bcnt = burst; | |
379 | ccnt = dma_length / (acnt * bcnt); | |
380 | if (ccnt > (SZ_64K - 1)) { | |
381 | dev_err(dev, "Exceeded max SG segment size\n"); | |
382 | return -EINVAL; | |
383 | } | |
384 | cidx = acnt * bcnt; | |
385 | } | |
386 | ||
c2da2340 TG |
387 | epset->len = dma_length; |
388 | ||
fd009035 JF |
389 | if (direction == DMA_MEM_TO_DEV) { |
390 | src_bidx = acnt; | |
391 | src_cidx = cidx; | |
392 | dst_bidx = 0; | |
393 | dst_cidx = 0; | |
c2da2340 | 394 | epset->addr = src_addr; |
fd009035 JF |
395 | } else if (direction == DMA_DEV_TO_MEM) { |
396 | src_bidx = 0; | |
397 | src_cidx = 0; | |
398 | dst_bidx = acnt; | |
399 | dst_cidx = cidx; | |
c2da2340 | 400 | epset->addr = dst_addr; |
8cc3e30b JF |
401 | } else if (direction == DMA_MEM_TO_MEM) { |
402 | src_bidx = acnt; | |
403 | src_cidx = cidx; | |
404 | dst_bidx = acnt; | |
405 | dst_cidx = cidx; | |
fd009035 JF |
406 | } else { |
407 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
408 | return -EINVAL; | |
409 | } | |
410 | ||
b5088ad9 | 411 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
fd009035 JF |
412 | /* Configure A or AB synchronized transfers */ |
413 | if (absync) | |
b5088ad9 | 414 | param->opt |= SYNCDIM; |
fd009035 | 415 | |
b5088ad9 TG |
416 | param->src = src_addr; |
417 | param->dst = dst_addr; | |
fd009035 | 418 | |
b5088ad9 TG |
419 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
420 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
fd009035 | 421 | |
b5088ad9 TG |
422 | param->a_b_cnt = bcnt << 16 | acnt; |
423 | param->ccnt = ccnt; | |
fd009035 JF |
424 | /* |
425 | * Only time when (bcntrld) auto reload is required is for | |
426 | * A-sync case, and in this case, a requirement of reload value | |
427 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
428 | * and then later will be populated by edma_execute. | |
429 | */ | |
b5088ad9 | 430 | param->link_bcntrld = 0xffffffff; |
fd009035 JF |
431 | return absync; |
432 | } | |
433 | ||
c2dde5f8 MP |
434 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
435 | struct dma_chan *chan, struct scatterlist *sgl, | |
436 | unsigned int sg_len, enum dma_transfer_direction direction, | |
437 | unsigned long tx_flags, void *context) | |
438 | { | |
439 | struct edma_chan *echan = to_edma_chan(chan); | |
440 | struct device *dev = chan->device->dev; | |
441 | struct edma_desc *edesc; | |
fd009035 | 442 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
443 | enum dma_slave_buswidth dev_width; |
444 | u32 burst; | |
c2dde5f8 | 445 | struct scatterlist *sg; |
fd009035 | 446 | int i, nslots, ret; |
c2dde5f8 MP |
447 | |
448 | if (unlikely(!echan || !sgl || !sg_len)) | |
449 | return NULL; | |
450 | ||
661f7cb5 | 451 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 452 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
453 | dev_width = echan->cfg.src_addr_width; |
454 | burst = echan->cfg.src_maxburst; | |
455 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 456 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
457 | dev_width = echan->cfg.dst_addr_width; |
458 | burst = echan->cfg.dst_maxburst; | |
459 | } else { | |
e6fad592 | 460 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
661f7cb5 MP |
461 | return NULL; |
462 | } | |
463 | ||
464 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 465 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
466 | return NULL; |
467 | } | |
468 | ||
c2dde5f8 MP |
469 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
470 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
471 | if (!edesc) { | |
c594c891 | 472 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
c2dde5f8 MP |
473 | return NULL; |
474 | } | |
475 | ||
476 | edesc->pset_nr = sg_len; | |
b6205c39 | 477 | edesc->residue = 0; |
c2da2340 | 478 | edesc->direction = direction; |
740b41f7 | 479 | edesc->echan = echan; |
c2dde5f8 | 480 | |
6fbe24da JF |
481 | /* Allocate a PaRAM slot, if needed */ |
482 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
483 | ||
484 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
485 | if (echan->slot[i] < 0) { |
486 | echan->slot[i] = | |
487 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
488 | EDMA_SLOT_ANY); | |
489 | if (echan->slot[i] < 0) { | |
4b6271a6 | 490 | kfree(edesc); |
c594c891 PU |
491 | dev_err(dev, "%s: Failed to allocate slot\n", |
492 | __func__); | |
c2dde5f8 MP |
493 | return NULL; |
494 | } | |
495 | } | |
6fbe24da JF |
496 | } |
497 | ||
498 | /* Configure PaRAM sets for each SG */ | |
499 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
500 | /* Get address for each SG */ |
501 | if (direction == DMA_DEV_TO_MEM) | |
502 | dst_addr = sg_dma_address(sg); | |
503 | else | |
504 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 505 | |
fd009035 JF |
506 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
507 | dst_addr, burst, dev_width, | |
508 | sg_dma_len(sg), direction); | |
b967aecf VK |
509 | if (ret < 0) { |
510 | kfree(edesc); | |
fd009035 | 511 | return NULL; |
c2dde5f8 MP |
512 | } |
513 | ||
fd009035 | 514 | edesc->absync = ret; |
b6205c39 | 515 | edesc->residue += sg_dma_len(sg); |
6fbe24da JF |
516 | |
517 | /* If this is the last in a current SG set of transactions, | |
518 | enable interrupts so that next set is processed */ | |
519 | if (!((i+1) % MAX_NR_SG)) | |
b5088ad9 | 520 | edesc->pset[i].param.opt |= TCINTEN; |
6fbe24da | 521 | |
c2dde5f8 MP |
522 | /* If this is the last set, enable completion interrupt flag */ |
523 | if (i == sg_len - 1) | |
b5088ad9 | 524 | edesc->pset[i].param.opt |= TCINTEN; |
c2dde5f8 | 525 | } |
740b41f7 | 526 | edesc->residue_stat = edesc->residue; |
c2dde5f8 | 527 | |
c2dde5f8 MP |
528 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
529 | } | |
c2dde5f8 | 530 | |
b7a4fd53 | 531 | static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
8cc3e30b JF |
532 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
533 | size_t len, unsigned long tx_flags) | |
534 | { | |
535 | int ret; | |
536 | struct edma_desc *edesc; | |
537 | struct device *dev = chan->device->dev; | |
538 | struct edma_chan *echan = to_edma_chan(chan); | |
539 | ||
540 | if (unlikely(!echan || !len)) | |
541 | return NULL; | |
542 | ||
543 | edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC); | |
544 | if (!edesc) { | |
545 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
546 | return NULL; | |
547 | } | |
548 | ||
549 | edesc->pset_nr = 1; | |
550 | ||
551 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, | |
552 | DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM); | |
553 | if (ret < 0) | |
554 | return NULL; | |
555 | ||
556 | edesc->absync = ret; | |
557 | ||
558 | /* | |
559 | * Enable intermediate transfer chaining to re-trigger channel | |
560 | * on completion of every TR, and enable transfer-completion | |
561 | * interrupt on completion of the whole transfer. | |
562 | */ | |
b0cce4ca JF |
563 | edesc->pset[0].param.opt |= ITCCHEN; |
564 | edesc->pset[0].param.opt |= TCINTEN; | |
8cc3e30b JF |
565 | |
566 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
567 | } | |
568 | ||
50a9c707 JF |
569 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
570 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
571 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 572 | unsigned long tx_flags) |
50a9c707 JF |
573 | { |
574 | struct edma_chan *echan = to_edma_chan(chan); | |
575 | struct device *dev = chan->device->dev; | |
576 | struct edma_desc *edesc; | |
577 | dma_addr_t src_addr, dst_addr; | |
578 | enum dma_slave_buswidth dev_width; | |
579 | u32 burst; | |
580 | int i, ret, nslots; | |
581 | ||
582 | if (unlikely(!echan || !buf_len || !period_len)) | |
583 | return NULL; | |
584 | ||
585 | if (direction == DMA_DEV_TO_MEM) { | |
586 | src_addr = echan->cfg.src_addr; | |
587 | dst_addr = buf_addr; | |
588 | dev_width = echan->cfg.src_addr_width; | |
589 | burst = echan->cfg.src_maxburst; | |
590 | } else if (direction == DMA_MEM_TO_DEV) { | |
591 | src_addr = buf_addr; | |
592 | dst_addr = echan->cfg.dst_addr; | |
593 | dev_width = echan->cfg.dst_addr_width; | |
594 | burst = echan->cfg.dst_maxburst; | |
595 | } else { | |
e6fad592 | 596 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
50a9c707 JF |
597 | return NULL; |
598 | } | |
599 | ||
600 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 601 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
602 | return NULL; |
603 | } | |
604 | ||
605 | if (unlikely(buf_len % period_len)) { | |
606 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
607 | return NULL; | |
608 | } | |
609 | ||
610 | nslots = (buf_len / period_len) + 1; | |
611 | ||
612 | /* | |
613 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
614 | * by cases where the number of periods is more than the maximum | |
615 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
616 | * such as Slave SGs, such delays are tolerable and synchronized, | |
617 | * but the synchronization is difficult to achieve with Cyclic and | |
618 | * cannot be guaranteed, so we error out early. | |
619 | */ | |
620 | if (nslots > MAX_NR_SG) | |
621 | return NULL; | |
622 | ||
623 | edesc = kzalloc(sizeof(*edesc) + nslots * | |
624 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
625 | if (!edesc) { | |
c594c891 | 626 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
50a9c707 JF |
627 | return NULL; |
628 | } | |
629 | ||
630 | edesc->cyclic = 1; | |
631 | edesc->pset_nr = nslots; | |
740b41f7 | 632 | edesc->residue = edesc->residue_stat = buf_len; |
c2da2340 | 633 | edesc->direction = direction; |
740b41f7 | 634 | edesc->echan = echan; |
50a9c707 | 635 | |
83bb3126 PU |
636 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
637 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
638 | |
639 | for (i = 0; i < nslots; i++) { | |
640 | /* Allocate a PaRAM slot, if needed */ | |
641 | if (echan->slot[i] < 0) { | |
642 | echan->slot[i] = | |
643 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
644 | EDMA_SLOT_ANY); | |
645 | if (echan->slot[i] < 0) { | |
e3ddc979 | 646 | kfree(edesc); |
c594c891 PU |
647 | dev_err(dev, "%s: Failed to allocate slot\n", |
648 | __func__); | |
50a9c707 JF |
649 | return NULL; |
650 | } | |
651 | } | |
652 | ||
653 | if (i == nslots - 1) { | |
654 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
655 | sizeof(edesc->pset[0])); | |
656 | break; | |
657 | } | |
658 | ||
659 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
660 | dst_addr, burst, dev_width, period_len, | |
661 | direction); | |
e3ddc979 CE |
662 | if (ret < 0) { |
663 | kfree(edesc); | |
50a9c707 | 664 | return NULL; |
e3ddc979 | 665 | } |
c2dde5f8 | 666 | |
50a9c707 JF |
667 | if (direction == DMA_DEV_TO_MEM) |
668 | dst_addr += period_len; | |
669 | else | |
670 | src_addr += period_len; | |
c2dde5f8 | 671 | |
83bb3126 PU |
672 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
673 | dev_vdbg(dev, | |
50a9c707 JF |
674 | "\n pset[%d]:\n" |
675 | " chnum\t%d\n" | |
676 | " slot\t%d\n" | |
677 | " opt\t%08x\n" | |
678 | " src\t%08x\n" | |
679 | " dst\t%08x\n" | |
680 | " abcnt\t%08x\n" | |
681 | " ccnt\t%08x\n" | |
682 | " bidx\t%08x\n" | |
683 | " cidx\t%08x\n" | |
684 | " lkrld\t%08x\n", | |
685 | i, echan->ch_num, echan->slot[i], | |
b5088ad9 TG |
686 | edesc->pset[i].param.opt, |
687 | edesc->pset[i].param.src, | |
688 | edesc->pset[i].param.dst, | |
689 | edesc->pset[i].param.a_b_cnt, | |
690 | edesc->pset[i].param.ccnt, | |
691 | edesc->pset[i].param.src_dst_bidx, | |
692 | edesc->pset[i].param.src_dst_cidx, | |
693 | edesc->pset[i].param.link_bcntrld); | |
50a9c707 JF |
694 | |
695 | edesc->absync = ret; | |
696 | ||
697 | /* | |
a1f146f3 | 698 | * Enable period interrupt only if it is requested |
50a9c707 | 699 | */ |
a1f146f3 PU |
700 | if (tx_flags & DMA_PREP_INTERRUPT) |
701 | edesc->pset[i].param.opt |= TCINTEN; | |
c2dde5f8 MP |
702 | } |
703 | ||
8e8805d5 PU |
704 | /* Place the cyclic channel to highest priority queue */ |
705 | edma_assign_channel_eventq(echan->ch_num, EVENTQ_0); | |
706 | ||
c2dde5f8 MP |
707 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
708 | } | |
709 | ||
710 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
711 | { | |
712 | struct edma_chan *echan = data; | |
713 | struct device *dev = echan->vchan.chan.device->dev; | |
714 | struct edma_desc *edesc; | |
c5f47990 | 715 | struct edmacc_param p; |
c2dde5f8 | 716 | |
50a9c707 JF |
717 | edesc = echan->edesc; |
718 | ||
8fa7ff4f | 719 | spin_lock(&echan->vchan.lock); |
c2dde5f8 | 720 | switch (ch_status) { |
db60d8da | 721 | case EDMA_DMA_COMPLETE: |
c2dde5f8 | 722 | if (edesc) { |
50a9c707 JF |
723 | if (edesc->cyclic) { |
724 | vchan_cyclic_callback(&edesc->vdesc); | |
8fa7ff4f | 725 | goto out; |
50a9c707 | 726 | } else if (edesc->processed == edesc->pset_nr) { |
53407062 | 727 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); |
b6205c39 | 728 | edesc->residue = 0; |
53407062 JF |
729 | edma_stop(echan->ch_num); |
730 | vchan_cookie_complete(&edesc->vdesc); | |
8fa7ff4f | 731 | echan->edesc = NULL; |
53407062 JF |
732 | } else { |
733 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
740b41f7 | 734 | |
8fa7ff4f PU |
735 | edma_pause(echan->ch_num); |
736 | ||
740b41f7 TG |
737 | /* Update statistics for tx_status */ |
738 | edesc->residue -= edesc->sg_len; | |
739 | edesc->residue_stat = edesc->residue; | |
740 | edesc->processed_stat = edesc->processed; | |
53407062 | 741 | } |
8fa7ff4f | 742 | edma_execute(echan); |
c2dde5f8 | 743 | } |
c2dde5f8 | 744 | break; |
db60d8da | 745 | case EDMA_DMA_CC_ERROR: |
c5f47990 JF |
746 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); |
747 | ||
748 | /* | |
749 | * Issue later based on missed flag which will be sure | |
750 | * to happen as: | |
751 | * (1) we finished transmitting an intermediate slot and | |
752 | * edma_execute is coming up. | |
753 | * (2) or we finished current transfer and issue will | |
754 | * call edma_execute. | |
755 | * | |
756 | * Important note: issuing can be dangerous here and | |
757 | * lead to some nasty recursion when we are in a NULL | |
758 | * slot. So we avoid doing so and set the missed flag. | |
759 | */ | |
760 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
761 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
762 | echan->missed = 1; | |
763 | } else { | |
764 | /* | |
765 | * The slot is already programmed but the event got | |
766 | * missed, so its safe to issue it here. | |
767 | */ | |
768 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
769 | edma_clean_channel(echan->ch_num); | |
770 | edma_stop(echan->ch_num); | |
771 | edma_start(echan->ch_num); | |
772 | edma_trigger_channel(echan->ch_num); | |
773 | } | |
c2dde5f8 MP |
774 | break; |
775 | default: | |
776 | break; | |
777 | } | |
8fa7ff4f PU |
778 | out: |
779 | spin_unlock(&echan->vchan.lock); | |
c2dde5f8 MP |
780 | } |
781 | ||
782 | /* Alloc channel resources */ | |
783 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
784 | { | |
785 | struct edma_chan *echan = to_edma_chan(chan); | |
786 | struct device *dev = chan->device->dev; | |
787 | int ret; | |
788 | int a_ch_num; | |
789 | LIST_HEAD(descs); | |
790 | ||
791 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
ab7add30 | 792 | echan, EVENTQ_DEFAULT); |
c2dde5f8 MP |
793 | |
794 | if (a_ch_num < 0) { | |
795 | ret = -ENODEV; | |
796 | goto err_no_chan; | |
797 | } | |
798 | ||
799 | if (a_ch_num != echan->ch_num) { | |
800 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
801 | EDMA_CTLR(echan->ch_num), | |
802 | EDMA_CHAN_SLOT(echan->ch_num)); | |
803 | ret = -ENODEV; | |
804 | goto err_wrong_chan; | |
805 | } | |
806 | ||
807 | echan->alloced = true; | |
808 | echan->slot[0] = echan->ch_num; | |
809 | ||
9aac9096 | 810 | dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, |
0e772c67 | 811 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); |
c2dde5f8 MP |
812 | |
813 | return 0; | |
814 | ||
815 | err_wrong_chan: | |
816 | edma_free_channel(a_ch_num); | |
817 | err_no_chan: | |
818 | return ret; | |
819 | } | |
820 | ||
821 | /* Free channel resources */ | |
822 | static void edma_free_chan_resources(struct dma_chan *chan) | |
823 | { | |
824 | struct edma_chan *echan = to_edma_chan(chan); | |
825 | struct device *dev = chan->device->dev; | |
826 | int i; | |
827 | ||
828 | /* Terminate transfers */ | |
829 | edma_stop(echan->ch_num); | |
830 | ||
831 | vchan_free_chan_resources(&echan->vchan); | |
832 | ||
833 | /* Free EDMA PaRAM slots */ | |
834 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
835 | if (echan->slot[i] >= 0) { | |
836 | edma_free_slot(echan->slot[i]); | |
837 | echan->slot[i] = -1; | |
838 | } | |
839 | } | |
840 | ||
841 | /* Free EDMA channel */ | |
842 | if (echan->alloced) { | |
843 | edma_free_channel(echan->ch_num); | |
844 | echan->alloced = false; | |
845 | } | |
846 | ||
0e772c67 | 847 | dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); |
c2dde5f8 MP |
848 | } |
849 | ||
850 | /* Send pending descriptor to hardware */ | |
851 | static void edma_issue_pending(struct dma_chan *chan) | |
852 | { | |
853 | struct edma_chan *echan = to_edma_chan(chan); | |
854 | unsigned long flags; | |
855 | ||
856 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
857 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
858 | edma_execute(echan); | |
859 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
860 | } | |
861 | ||
740b41f7 TG |
862 | static u32 edma_residue(struct edma_desc *edesc) |
863 | { | |
864 | bool dst = edesc->direction == DMA_DEV_TO_MEM; | |
865 | struct edma_pset *pset = edesc->pset; | |
866 | dma_addr_t done, pos; | |
867 | int i; | |
868 | ||
869 | /* | |
870 | * We always read the dst/src position from the first RamPar | |
871 | * pset. That's the one which is active now. | |
872 | */ | |
873 | pos = edma_get_position(edesc->echan->slot[0], dst); | |
874 | ||
875 | /* | |
876 | * Cyclic is simple. Just subtract pset[0].addr from pos. | |
877 | * | |
878 | * We never update edesc->residue in the cyclic case, so we | |
879 | * can tell the remaining room to the end of the circular | |
880 | * buffer. | |
881 | */ | |
882 | if (edesc->cyclic) { | |
883 | done = pos - pset->addr; | |
884 | edesc->residue_stat = edesc->residue - done; | |
885 | return edesc->residue_stat; | |
886 | } | |
887 | ||
888 | /* | |
889 | * For SG operation we catch up with the last processed | |
890 | * status. | |
891 | */ | |
892 | pset += edesc->processed_stat; | |
893 | ||
894 | for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { | |
895 | /* | |
896 | * If we are inside this pset address range, we know | |
897 | * this is the active one. Get the current delta and | |
898 | * stop walking the psets. | |
899 | */ | |
900 | if (pos >= pset->addr && pos < pset->addr + pset->len) | |
901 | return edesc->residue_stat - (pos - pset->addr); | |
902 | ||
903 | /* Otherwise mark it done and update residue_stat. */ | |
904 | edesc->processed_stat++; | |
905 | edesc->residue_stat -= pset->len; | |
906 | } | |
907 | return edesc->residue_stat; | |
908 | } | |
909 | ||
c2dde5f8 MP |
910 | /* Check request completion status */ |
911 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
912 | dma_cookie_t cookie, | |
913 | struct dma_tx_state *txstate) | |
914 | { | |
915 | struct edma_chan *echan = to_edma_chan(chan); | |
916 | struct virt_dma_desc *vdesc; | |
917 | enum dma_status ret; | |
918 | unsigned long flags; | |
919 | ||
920 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 921 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
922 | return ret; |
923 | ||
924 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
de135939 | 925 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
740b41f7 | 926 | txstate->residue = edma_residue(echan->edesc); |
de135939 TG |
927 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
928 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; | |
c2dde5f8 MP |
929 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
934 | static void __init edma_chan_init(struct edma_cc *ecc, | |
935 | struct dma_device *dma, | |
936 | struct edma_chan *echans) | |
937 | { | |
938 | int i, j; | |
939 | ||
940 | for (i = 0; i < EDMA_CHANS; i++) { | |
941 | struct edma_chan *echan = &echans[i]; | |
942 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
943 | echan->ecc = ecc; | |
944 | echan->vchan.desc_free = edma_desc_free; | |
945 | ||
946 | vchan_init(&echan->vchan, dma); | |
947 | ||
948 | INIT_LIST_HEAD(&echan->node); | |
949 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
950 | echan->slot[j] = -1; | |
951 | } | |
952 | } | |
953 | ||
2c88ee6b PU |
954 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
955 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
e4a899d9 | 956 | BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ |
2c88ee6b PU |
957 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) |
958 | ||
c2dde5f8 MP |
959 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, |
960 | struct device *dev) | |
961 | { | |
962 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
50a9c707 | 963 | dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; |
8cc3e30b | 964 | dma->device_prep_dma_memcpy = edma_prep_dma_memcpy; |
c2dde5f8 MP |
965 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; |
966 | dma->device_free_chan_resources = edma_free_chan_resources; | |
967 | dma->device_issue_pending = edma_issue_pending; | |
968 | dma->device_tx_status = edma_tx_status; | |
aa7c09b6 MR |
969 | dma->device_config = edma_slave_config; |
970 | dma->device_pause = edma_dma_pause; | |
971 | dma->device_resume = edma_dma_resume; | |
972 | dma->device_terminate_all = edma_terminate_all; | |
9f59cd05 MR |
973 | |
974 | dma->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
975 | dma->dst_addr_widths = EDMA_DMA_BUSWIDTHS; | |
976 | dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
977 | dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
978 | ||
c2dde5f8 MP |
979 | dma->dev = dev; |
980 | ||
8cc3e30b JF |
981 | /* |
982 | * code using dma memcpy must make sure alignment of | |
983 | * length is at dma->copy_align boundary. | |
984 | */ | |
77a68e56 | 985 | dma->copy_align = DMAENGINE_ALIGN_4_BYTES; |
8cc3e30b | 986 | |
c2dde5f8 MP |
987 | INIT_LIST_HEAD(&dma->channels); |
988 | } | |
989 | ||
463a1f8b | 990 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
991 | { |
992 | struct edma_cc *ecc; | |
993 | int ret; | |
994 | ||
94cb0e79 RK |
995 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
996 | if (ret) | |
997 | return ret; | |
998 | ||
c2dde5f8 MP |
999 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); |
1000 | if (!ecc) { | |
1001 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
1002 | return -ENOMEM; | |
1003 | } | |
1004 | ||
1005 | ecc->ctlr = pdev->id; | |
1006 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
1007 | if (ecc->dummy_slot < 0) { | |
1008 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
04d537d9 | 1009 | return ecc->dummy_slot; |
c2dde5f8 MP |
1010 | } |
1011 | ||
1012 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
1013 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
232b223d | 1014 | dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); |
8cc3e30b | 1015 | dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); |
c2dde5f8 MP |
1016 | |
1017 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
1018 | ||
1019 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
1020 | ||
1021 | ret = dma_async_device_register(&ecc->dma_slave); | |
1022 | if (ret) | |
1023 | goto err_reg1; | |
1024 | ||
1025 | platform_set_drvdata(pdev, ecc); | |
1026 | ||
1027 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
1028 | ||
1029 | return 0; | |
1030 | ||
1031 | err_reg1: | |
1032 | edma_free_slot(ecc->dummy_slot); | |
1033 | return ret; | |
1034 | } | |
1035 | ||
4bf27b8b | 1036 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
1037 | { |
1038 | struct device *dev = &pdev->dev; | |
1039 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
1040 | ||
1041 | dma_async_device_unregister(&ecc->dma_slave); | |
1042 | edma_free_slot(ecc->dummy_slot); | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | static struct platform_driver edma_driver = { | |
1048 | .probe = edma_probe, | |
a7d6e3ec | 1049 | .remove = edma_remove, |
c2dde5f8 MP |
1050 | .driver = { |
1051 | .name = "edma-dma-engine", | |
c2dde5f8 MP |
1052 | }, |
1053 | }; | |
1054 | ||
1055 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
1056 | { | |
1057 | if (chan->device->dev->driver == &edma_driver.driver) { | |
1058 | struct edma_chan *echan = to_edma_chan(chan); | |
1059 | unsigned ch_req = *(unsigned *)param; | |
1060 | return ch_req == echan->ch_num; | |
1061 | } | |
1062 | return false; | |
1063 | } | |
1064 | EXPORT_SYMBOL(edma_filter_fn); | |
1065 | ||
c2dde5f8 MP |
1066 | static int edma_init(void) |
1067 | { | |
5305e4d6 | 1068 | return platform_driver_register(&edma_driver); |
c2dde5f8 MP |
1069 | } |
1070 | subsys_initcall(edma_init); | |
1071 | ||
1072 | static void __exit edma_exit(void) | |
1073 | { | |
c2dde5f8 MP |
1074 | platform_driver_unregister(&edma_driver); |
1075 | } | |
1076 | module_exit(edma_exit); | |
1077 | ||
d71505b6 | 1078 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
1079 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
1080 | MODULE_LICENSE("GPL v2"); |