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[mirror_ubuntu-bionic-kernel.git] / drivers / dma / fsldma.c
CommitLineData
173acc7c
ZW
1/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
e2c8e425 4 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
173acc7c
ZW
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
c2e07b3a 13 * The support for MPC8349 DMA controller is also added.
173acc7c 14 *
a7aea373
IS
15 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
173acc7c
ZW
20 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
5a0e3ad6 30#include <linux/slab.h>
173acc7c
ZW
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
5af50730
RH
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
173acc7c 38#include <linux/of_platform.h>
0a5642be 39#include <linux/fsldma.h>
d2ebfb33 40#include "dmaengine.h"
173acc7c
ZW
41#include "fsldma.h"
42
b158471e
IS
43#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
c1433041 47
b158471e 48static const char msg_ld_oom[] = "No free memory for link descriptor";
173acc7c 49
e8bd84df
IS
50/*
51 * Register Helpers
52 */
173acc7c 53
a1c03319 54static void set_sr(struct fsldma_chan *chan, u32 val)
173acc7c 55{
a1c03319 56 DMA_OUT(chan, &chan->regs->sr, val, 32);
173acc7c
ZW
57}
58
a1c03319 59static u32 get_sr(struct fsldma_chan *chan)
173acc7c 60{
a1c03319 61 return DMA_IN(chan, &chan->regs->sr, 32);
173acc7c
ZW
62}
63
ccdce9a0
HZ
64static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
e8bd84df
IS
74static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
75{
76 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
77}
78
79static dma_addr_t get_cdar(struct fsldma_chan *chan)
80{
81 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
82}
83
ccdce9a0
HZ
84static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
e8bd84df
IS
89static u32 get_bcr(struct fsldma_chan *chan)
90{
91 return DMA_IN(chan, &chan->regs->bcr, 32);
92}
93
94/*
95 * Descriptor Helpers
96 */
97
a1c03319 98static void set_desc_cnt(struct fsldma_chan *chan,
173acc7c
ZW
99 struct fsl_dma_ld_hw *hw, u32 count)
100{
a1c03319 101 hw->count = CPU_TO_DMA(chan, count, 32);
173acc7c
ZW
102}
103
a1c03319 104static void set_desc_src(struct fsldma_chan *chan,
31f4306c 105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
173acc7c
ZW
106{
107 u64 snoop_bits;
108
a1c03319 109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
173acc7c 110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
a1c03319 111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
173acc7c
ZW
112}
113
a1c03319 114static void set_desc_dst(struct fsldma_chan *chan,
31f4306c 115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
173acc7c
ZW
116{
117 u64 snoop_bits;
118
a1c03319 119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
173acc7c 120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
a1c03319 121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
173acc7c
ZW
122}
123
a1c03319 124static void set_desc_next(struct fsldma_chan *chan,
31f4306c 125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
173acc7c
ZW
126{
127 u64 snoop_bits;
128
a1c03319 129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
173acc7c 130 ? FSL_DMA_SNEN : 0;
a1c03319 131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
173acc7c
ZW
132}
133
31f4306c 134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
173acc7c 135{
e8bd84df 136 u64 snoop_bits;
173acc7c 137
e8bd84df
IS
138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
139 ? FSL_DMA_SNEN : 0;
173acc7c 140
e8bd84df
IS
141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
143 | snoop_bits, 64);
173acc7c
ZW
144}
145
e8bd84df
IS
146/*
147 * DMA Engine Hardware Control Helpers
148 */
149
150static void dma_init(struct fsldma_chan *chan)
f79abb62 151{
e8bd84df 152 /* Reset the channel */
ccdce9a0 153 set_mr(chan, 0);
e8bd84df
IS
154
155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
e8bd84df
IS
159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
ccdce9a0
HZ
162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
e8bd84df
IS
164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
ccdce9a0 170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
e8bd84df
IS
171 break;
172 }
f79abb62
ZW
173}
174
a1c03319 175static int dma_is_idle(struct fsldma_chan *chan)
173acc7c 176{
a1c03319 177 u32 sr = get_sr(chan);
173acc7c
ZW
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
f04cd407
IS
181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
a1c03319 188static void dma_start(struct fsldma_chan *chan)
173acc7c 189{
272ca655
IS
190 u32 mode;
191
ccdce9a0 192 mode = get_mr(chan);
272ca655 193
f04cd407 194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
ccdce9a0 195 set_bcr(chan, 0);
f04cd407
IS
196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
43a1a3ed 199 }
173acc7c 200
f04cd407 201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
272ca655 202 mode |= FSL_DMA_MR_EMS_EN;
f04cd407
IS
203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
272ca655 205 mode |= FSL_DMA_MR_CS;
f04cd407 206 }
173acc7c 207
ccdce9a0 208 set_mr(chan, mode);
173acc7c
ZW
209}
210
a1c03319 211static void dma_halt(struct fsldma_chan *chan)
173acc7c 212{
272ca655 213 u32 mode;
900325a6
DW
214 int i;
215
a00ae34a 216 /* read the mode register */
ccdce9a0 217 mode = get_mr(chan);
272ca655 218
a00ae34a
IS
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
ccdce9a0 226 set_mr(chan, mode);
a00ae34a
IS
227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
ccdce9a0 233 set_mr(chan, mode);
173acc7c 234
a00ae34a 235 /* wait for the DMA controller to become idle */
900325a6 236 for (i = 0; i < 100; i++) {
a1c03319 237 if (dma_is_idle(chan))
9c3a50b7
IS
238 return;
239
173acc7c 240 udelay(10);
900325a6 241 }
272ca655 242
9c3a50b7 243 if (!dma_is_idle(chan))
b158471e 244 chan_err(chan, "DMA halt timeout!\n");
173acc7c
ZW
245}
246
173acc7c
ZW
247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
a1c03319 249 * @chan : Freescale DMA channel
173acc7c
ZW
250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
a1c03319 258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
173acc7c 259{
272ca655
IS
260 u32 mode;
261
ccdce9a0 262 mode = get_mr(chan);
272ca655 263
173acc7c
ZW
264 switch (size) {
265 case 0:
272ca655 266 mode &= ~FSL_DMA_MR_SAHE;
173acc7c
ZW
267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
272ca655 272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
173acc7c
ZW
273 break;
274 }
272ca655 275
ccdce9a0 276 set_mr(chan, mode);
173acc7c
ZW
277}
278
279/**
738f5f7e 280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
a1c03319 281 * @chan : Freescale DMA channel
173acc7c
ZW
282 * @size : Address loop size, 0 for disable loop
283 *
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
289 */
a1c03319 290static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
173acc7c 291{
272ca655
IS
292 u32 mode;
293
ccdce9a0 294 mode = get_mr(chan);
272ca655 295
173acc7c
ZW
296 switch (size) {
297 case 0:
272ca655 298 mode &= ~FSL_DMA_MR_DAHE;
173acc7c
ZW
299 break;
300 case 1:
301 case 2:
302 case 4:
303 case 8:
272ca655 304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
173acc7c
ZW
305 break;
306 }
272ca655 307
ccdce9a0 308 set_mr(chan, mode);
173acc7c
ZW
309}
310
311/**
e6c7ecb6 312 * fsl_chan_set_request_count - Set DMA Request Count for external control
a1c03319 313 * @chan : Freescale DMA channel
e6c7ecb6
IS
314 * @size : Number of bytes to transfer in a single request
315 *
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
319 * operation.
173acc7c 320 *
e6c7ecb6 321 * A size of 0 disables external pause control. The maximum size is 1024.
173acc7c 322 */
a1c03319 323static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
173acc7c 324{
272ca655
IS
325 u32 mode;
326
e6c7ecb6 327 BUG_ON(size > 1024);
272ca655 328
ccdce9a0 329 mode = get_mr(chan);
272ca655
IS
330 mode |= (__ilog2(size) << 24) & 0x0f000000;
331
ccdce9a0 332 set_mr(chan, mode);
e6c7ecb6 333}
173acc7c 334
e6c7ecb6
IS
335/**
336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
a1c03319 337 * @chan : Freescale DMA channel
e6c7ecb6
IS
338 * @enable : 0 is disabled, 1 is enabled.
339 *
340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
343 */
a1c03319 344static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
e6c7ecb6
IS
345{
346 if (enable)
a1c03319 347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
e6c7ecb6 348 else
a1c03319 349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
173acc7c
ZW
350}
351
352/**
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
a1c03319 354 * @chan : Freescale DMA channel
173acc7c
ZW
355 * @enable : 0 is disabled, 1 is enabled.
356 *
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
361 */
a1c03319 362static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
173acc7c
ZW
363{
364 if (enable)
a1c03319 365 chan->feature |= FSL_DMA_CHAN_START_EXT;
173acc7c 366 else
a1c03319 367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
173acc7c
ZW
368}
369
0a5642be
VK
370int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371{
372 struct fsldma_chan *chan;
373
374 if (!dchan)
375 return -EINVAL;
376
377 chan = to_fsl_chan(dchan);
378
379 fsl_chan_toggle_ext_start(chan, enable);
380 return 0;
381}
382EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383
31f4306c 384static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
9c3a50b7
IS
385{
386 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387
388 if (list_empty(&chan->ld_pending))
389 goto out_splice;
390
391 /*
392 * Add the hardware descriptor to the chain of hardware descriptors
393 * that already exists in memory.
394 *
395 * This will un-set the EOL bit of the existing transaction, and the
396 * last link in this transaction will become the EOL descriptor.
397 */
398 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399
400 /*
401 * Add the software descriptor and all children to the list
402 * of pending transactions
403 */
404out_splice:
405 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406}
407
173acc7c
ZW
408static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409{
a1c03319 410 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
eda34234
DW
411 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412 struct fsl_desc_sw *child;
bbc76560 413 dma_cookie_t cookie = -EINVAL;
173acc7c 414
2baff570 415 spin_lock_bh(&chan->desc_lock);
173acc7c 416
14c6a333
HZ
417#ifdef CONFIG_PM
418 if (unlikely(chan->pm_state != RUNNING)) {
419 chan_dbg(chan, "cannot submit due to suspend\n");
420 spin_unlock_bh(&chan->desc_lock);
421 return -1;
422 }
423#endif
424
9c3a50b7
IS
425 /*
426 * assign cookies to all of the software descriptors
427 * that make up this transaction
428 */
eda34234 429 list_for_each_entry(child, &desc->tx_list, node) {
884485e1 430 cookie = dma_cookie_assign(&child->async_tx);
bcfb7465
IS
431 }
432
9c3a50b7 433 /* put this transaction onto the tail of the pending queue */
a1c03319 434 append_ld_queue(chan, desc);
173acc7c 435
2baff570 436 spin_unlock_bh(&chan->desc_lock);
173acc7c
ZW
437
438 return cookie;
439}
440
86d19a54
HZ
441/**
442 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443 * @chan : Freescale DMA channel
444 * @desc: descriptor to be freed
445 */
446static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447 struct fsl_desc_sw *desc)
448{
449 list_del(&desc->node);
450 chan_dbg(chan, "LD %p free\n", desc);
451 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452}
453
173acc7c
ZW
454/**
455 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
a1c03319 456 * @chan : Freescale DMA channel
173acc7c
ZW
457 *
458 * Return - The descriptor allocated. NULL for failed.
459 */
31f4306c 460static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
173acc7c 461{
9c3a50b7 462 struct fsl_desc_sw *desc;
173acc7c 463 dma_addr_t pdesc;
9c3a50b7 464
43764557 465 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
9c3a50b7 466 if (!desc) {
b158471e 467 chan_dbg(chan, "out of memory for link descriptor\n");
9c3a50b7 468 return NULL;
173acc7c
ZW
469 }
470
9c3a50b7
IS
471 INIT_LIST_HEAD(&desc->tx_list);
472 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
473 desc->async_tx.tx_submit = fsl_dma_tx_submit;
474 desc->async_tx.phys = pdesc;
475
0ab09c36 476 chan_dbg(chan, "LD %p allocated\n", desc);
0ab09c36 477
9c3a50b7 478 return desc;
173acc7c
ZW
479}
480
43452fad
HZ
481/**
482 * fsldma_clean_completed_descriptor - free all descriptors which
483 * has been completed and acked
484 * @chan: Freescale DMA channel
485 *
486 * This function is used on all completed and acked descriptors.
487 * All descriptors should only be freed in this function.
488 */
489static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
490{
491 struct fsl_desc_sw *desc, *_desc;
492
493 /* Run the callback for each descriptor, in order */
494 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
495 if (async_tx_test_ack(&desc->async_tx))
496 fsl_dma_free_descriptor(chan, desc);
497}
498
499/**
500 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
501 * @chan: Freescale DMA channel
502 * @desc: descriptor to cleanup and free
503 * @cookie: Freescale DMA transaction identifier
504 *
505 * This function is used on a descriptor which has been executed by the DMA
506 * controller. It will run any callbacks, submit any dependencies.
507 */
508static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
509 struct fsl_desc_sw *desc, dma_cookie_t cookie)
510{
511 struct dma_async_tx_descriptor *txd = &desc->async_tx;
512 dma_cookie_t ret = cookie;
513
514 BUG_ON(txd->cookie < 0);
515
516 if (txd->cookie > 0) {
517 ret = txd->cookie;
518
519 /* Run the link descriptor callback function */
520 if (txd->callback) {
521 chan_dbg(chan, "LD %p callback\n", desc);
522 txd->callback(txd->callback_param);
523 }
a9af316c
XS
524
525 dma_descriptor_unmap(txd);
43452fad
HZ
526 }
527
528 /* Run any dependencies */
529 dma_run_dependencies(txd);
530
531 return ret;
532}
533
534/**
535 * fsldma_clean_running_descriptor - move the completed descriptor from
536 * ld_running to ld_completed
537 * @chan: Freescale DMA channel
538 * @desc: the descriptor which is completed
539 *
540 * Free the descriptor directly if acked by async_tx api, or move it to
541 * queue ld_completed.
542 */
543static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
544 struct fsl_desc_sw *desc)
545{
546 /* Remove from the list of transactions */
547 list_del(&desc->node);
548
549 /*
550 * the client is allowed to attach dependent operations
551 * until 'ack' is set
552 */
553 if (!async_tx_test_ack(&desc->async_tx)) {
554 /*
555 * Move this descriptor to the list of descriptors which is
556 * completed, but still awaiting the 'ack' bit to be set.
557 */
558 list_add_tail(&desc->node, &chan->ld_completed);
559 return;
560 }
561
562 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
563}
564
2a5ecb79
HZ
565/**
566 * fsl_chan_xfer_ld_queue - transfer any pending transactions
567 * @chan : Freescale DMA channel
568 *
569 * HARDWARE STATE: idle
570 * LOCKING: must hold chan->desc_lock
571 */
572static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
573{
574 struct fsl_desc_sw *desc;
575
576 /*
577 * If the list of pending descriptors is empty, then we
578 * don't need to do any work at all
579 */
580 if (list_empty(&chan->ld_pending)) {
581 chan_dbg(chan, "no pending LDs\n");
582 return;
583 }
584
585 /*
586 * The DMA controller is not idle, which means that the interrupt
587 * handler will start any queued transactions when it runs after
588 * this transaction finishes
589 */
590 if (!chan->idle) {
591 chan_dbg(chan, "DMA controller still busy\n");
592 return;
593 }
594
595 /*
596 * If there are some link descriptors which have not been
597 * transferred, we need to start the controller
598 */
599
600 /*
601 * Move all elements from the queue of pending transactions
602 * onto the list of running transactions
603 */
604 chan_dbg(chan, "idle, starting controller\n");
605 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
606 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
607
608 /*
609 * The 85xx DMA controller doesn't clear the channel start bit
610 * automatically at the end of a transfer. Therefore we must clear
611 * it in software before starting the transfer.
612 */
613 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
614 u32 mode;
615
616 mode = get_mr(chan);
617 mode &= ~FSL_DMA_MR_CS;
618 set_mr(chan, mode);
619 }
620
621 /*
622 * Program the descriptor's address into the DMA controller,
623 * then start the DMA transaction
624 */
625 set_cdar(chan, desc->async_tx.phys);
626 get_cdar(chan);
627
628 dma_start(chan);
629 chan->idle = false;
630}
631
632/**
43452fad
HZ
633 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
634 * and move them to ld_completed to free until flag 'ack' is set
2a5ecb79 635 * @chan: Freescale DMA channel
2a5ecb79 636 *
43452fad
HZ
637 * This function is used on descriptors which have been executed by the DMA
638 * controller. It will run any callbacks, submit any dependencies, then
639 * free these descriptors if flag 'ack' is set.
2a5ecb79 640 */
43452fad 641static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
2a5ecb79 642{
43452fad
HZ
643 struct fsl_desc_sw *desc, *_desc;
644 dma_cookie_t cookie = 0;
645 dma_addr_t curr_phys = get_cdar(chan);
646 int seen_current = 0;
2a5ecb79 647
43452fad
HZ
648 fsldma_clean_completed_descriptor(chan);
649
650 /* Run the callback for each descriptor, in order */
651 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
652 /*
653 * do not advance past the current descriptor loaded into the
654 * hardware channel, subsequent descriptors are either in
655 * process or have not been submitted
656 */
657 if (seen_current)
658 break;
659
660 /*
661 * stop the search if we reach the current descriptor and the
662 * channel is busy
663 */
664 if (desc->async_tx.phys == curr_phys) {
665 seen_current = 1;
666 if (!dma_is_idle(chan))
667 break;
668 }
669
670 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
671
672 fsldma_clean_running_descriptor(chan, desc);
2a5ecb79
HZ
673 }
674
43452fad
HZ
675 /*
676 * Start any pending transactions automatically
677 *
678 * In the ideal case, we keep the DMA controller busy while we go
679 * ahead and free the descriptors below.
680 */
681 fsl_chan_xfer_ld_queue(chan);
2a5ecb79 682
43452fad
HZ
683 if (cookie > 0)
684 chan->common.completed_cookie = cookie;
2a5ecb79
HZ
685}
686
173acc7c
ZW
687/**
688 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
a1c03319 689 * @chan : Freescale DMA channel
173acc7c
ZW
690 *
691 * This function will create a dma pool for descriptor allocation.
692 *
693 * Return - The number of descriptors allocated.
694 */
a1c03319 695static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
173acc7c 696{
a1c03319 697 struct fsldma_chan *chan = to_fsl_chan(dchan);
77cd62e8
TT
698
699 /* Has this channel already been allocated? */
a1c03319 700 if (chan->desc_pool)
77cd62e8 701 return 1;
173acc7c 702
9c3a50b7
IS
703 /*
704 * We need the descriptor to be aligned to 32bytes
173acc7c
ZW
705 * for meeting FSL DMA specification requirement.
706 */
b158471e 707 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
9c3a50b7
IS
708 sizeof(struct fsl_desc_sw),
709 __alignof__(struct fsl_desc_sw), 0);
a1c03319 710 if (!chan->desc_pool) {
b158471e 711 chan_err(chan, "unable to allocate descriptor pool\n");
9c3a50b7 712 return -ENOMEM;
173acc7c
ZW
713 }
714
9c3a50b7 715 /* there is at least one descriptor free to be allocated */
173acc7c
ZW
716 return 1;
717}
718
9c3a50b7
IS
719/**
720 * fsldma_free_desc_list - Free all descriptors in a queue
721 * @chan: Freescae DMA channel
722 * @list: the list to free
723 *
724 * LOCKING: must hold chan->desc_lock
725 */
726static void fsldma_free_desc_list(struct fsldma_chan *chan,
727 struct list_head *list)
728{
729 struct fsl_desc_sw *desc, *_desc;
730
86d19a54
HZ
731 list_for_each_entry_safe(desc, _desc, list, node)
732 fsl_dma_free_descriptor(chan, desc);
9c3a50b7
IS
733}
734
735static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
736 struct list_head *list)
737{
738 struct fsl_desc_sw *desc, *_desc;
739
86d19a54
HZ
740 list_for_each_entry_safe_reverse(desc, _desc, list, node)
741 fsl_dma_free_descriptor(chan, desc);
9c3a50b7
IS
742}
743
173acc7c
ZW
744/**
745 * fsl_dma_free_chan_resources - Free all resources of the channel.
a1c03319 746 * @chan : Freescale DMA channel
173acc7c 747 */
a1c03319 748static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
173acc7c 749{
a1c03319 750 struct fsldma_chan *chan = to_fsl_chan(dchan);
173acc7c 751
b158471e 752 chan_dbg(chan, "free all channel resources\n");
2baff570 753 spin_lock_bh(&chan->desc_lock);
43452fad 754 fsldma_cleanup_descriptors(chan);
9c3a50b7
IS
755 fsldma_free_desc_list(chan, &chan->ld_pending);
756 fsldma_free_desc_list(chan, &chan->ld_running);
43452fad 757 fsldma_free_desc_list(chan, &chan->ld_completed);
2baff570 758 spin_unlock_bh(&chan->desc_lock);
77cd62e8 759
9c3a50b7 760 dma_pool_destroy(chan->desc_pool);
a1c03319 761 chan->desc_pool = NULL;
173acc7c
ZW
762}
763
31f4306c
IS
764static struct dma_async_tx_descriptor *
765fsl_dma_prep_memcpy(struct dma_chan *dchan,
766 dma_addr_t dma_dst, dma_addr_t dma_src,
173acc7c
ZW
767 size_t len, unsigned long flags)
768{
a1c03319 769 struct fsldma_chan *chan;
173acc7c
ZW
770 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
771 size_t copy;
173acc7c 772
a1c03319 773 if (!dchan)
173acc7c
ZW
774 return NULL;
775
776 if (!len)
777 return NULL;
778
a1c03319 779 chan = to_fsl_chan(dchan);
173acc7c
ZW
780
781 do {
782
783 /* Allocate the link descriptor from DMA pool */
a1c03319 784 new = fsl_dma_alloc_descriptor(chan);
173acc7c 785 if (!new) {
b158471e 786 chan_err(chan, "%s\n", msg_ld_oom);
2e077f8e 787 goto fail;
173acc7c 788 }
173acc7c 789
56822843 790 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
173acc7c 791
a1c03319
IS
792 set_desc_cnt(chan, &new->hw, copy);
793 set_desc_src(chan, &new->hw, dma_src);
794 set_desc_dst(chan, &new->hw, dma_dst);
173acc7c
ZW
795
796 if (!first)
797 first = new;
798 else
a1c03319 799 set_desc_next(chan, &prev->hw, new->async_tx.phys);
173acc7c
ZW
800
801 new->async_tx.cookie = 0;
636bdeaa 802 async_tx_ack(&new->async_tx);
173acc7c
ZW
803
804 prev = new;
805 len -= copy;
806 dma_src += copy;
738f5f7e 807 dma_dst += copy;
173acc7c
ZW
808
809 /* Insert the link descriptor to the LD ring */
eda34234 810 list_add_tail(&new->node, &first->tx_list);
173acc7c
ZW
811 } while (len);
812
636bdeaa 813 new->async_tx.flags = flags; /* client is in control of this ack */
173acc7c
ZW
814 new->async_tx.cookie = -EBUSY;
815
31f4306c 816 /* Set End-of-link to the last link descriptor of new list */
a1c03319 817 set_ld_eol(chan, new);
173acc7c 818
2e077f8e
IS
819 return &first->async_tx;
820
821fail:
822 if (!first)
823 return NULL;
824
9c3a50b7 825 fsldma_free_desc_list_reverse(chan, &first->tx_list);
2e077f8e 826 return NULL;
173acc7c
ZW
827}
828
c1433041
IS
829static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
830 struct scatterlist *dst_sg, unsigned int dst_nents,
831 struct scatterlist *src_sg, unsigned int src_nents,
832 unsigned long flags)
833{
834 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
835 struct fsldma_chan *chan = to_fsl_chan(dchan);
836 size_t dst_avail, src_avail;
837 dma_addr_t dst, src;
838 size_t len;
839
840 /* basic sanity checks */
841 if (dst_nents == 0 || src_nents == 0)
842 return NULL;
843
844 if (dst_sg == NULL || src_sg == NULL)
845 return NULL;
846
847 /*
848 * TODO: should we check that both scatterlists have the same
849 * TODO: number of bytes in total? Is that really an error?
850 */
851
852 /* get prepared for the loop */
853 dst_avail = sg_dma_len(dst_sg);
854 src_avail = sg_dma_len(src_sg);
855
856 /* run until we are out of scatterlist entries */
857 while (true) {
858
859 /* create the largest transaction possible */
860 len = min_t(size_t, src_avail, dst_avail);
861 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
862 if (len == 0)
863 goto fetch;
864
865 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
866 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
867
868 /* allocate and populate the descriptor */
869 new = fsl_dma_alloc_descriptor(chan);
870 if (!new) {
b158471e 871 chan_err(chan, "%s\n", msg_ld_oom);
c1433041
IS
872 goto fail;
873 }
c1433041
IS
874
875 set_desc_cnt(chan, &new->hw, len);
876 set_desc_src(chan, &new->hw, src);
877 set_desc_dst(chan, &new->hw, dst);
878
879 if (!first)
880 first = new;
881 else
882 set_desc_next(chan, &prev->hw, new->async_tx.phys);
883
884 new->async_tx.cookie = 0;
885 async_tx_ack(&new->async_tx);
886 prev = new;
887
888 /* Insert the link descriptor to the LD ring */
889 list_add_tail(&new->node, &first->tx_list);
890
891 /* update metadata */
892 dst_avail -= len;
893 src_avail -= len;
894
895fetch:
896 /* fetch the next dst scatterlist entry */
897 if (dst_avail == 0) {
898
899 /* no more entries: we're done */
900 if (dst_nents == 0)
901 break;
902
903 /* fetch the next entry: if there are no more: done */
904 dst_sg = sg_next(dst_sg);
905 if (dst_sg == NULL)
906 break;
907
908 dst_nents--;
909 dst_avail = sg_dma_len(dst_sg);
910 }
911
912 /* fetch the next src scatterlist entry */
913 if (src_avail == 0) {
914
915 /* no more entries: we're done */
916 if (src_nents == 0)
917 break;
918
919 /* fetch the next entry: if there are no more: done */
920 src_sg = sg_next(src_sg);
921 if (src_sg == NULL)
922 break;
923
924 src_nents--;
925 src_avail = sg_dma_len(src_sg);
926 }
927 }
928
929 new->async_tx.flags = flags; /* client is in control of this ack */
930 new->async_tx.cookie = -EBUSY;
931
932 /* Set End-of-link to the last link descriptor of new list */
933 set_ld_eol(chan, new);
934
935 return &first->async_tx;
936
937fail:
938 if (!first)
939 return NULL;
940
941 fsldma_free_desc_list_reverse(chan, &first->tx_list);
942 return NULL;
943}
944
b7f7552b 945static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
bbea0b6e 946{
a1c03319 947 struct fsldma_chan *chan;
c3635c78 948
a1c03319 949 if (!dchan)
c3635c78 950 return -EINVAL;
bbea0b6e 951
a1c03319 952 chan = to_fsl_chan(dchan);
bbea0b6e 953
b7f7552b 954 spin_lock_bh(&chan->desc_lock);
bbea0b6e 955
b7f7552b
MR
956 /* Halt the DMA engine */
957 dma_halt(chan);
bbea0b6e 958
b7f7552b
MR
959 /* Remove and free all of the descriptors in the LD queue */
960 fsldma_free_desc_list(chan, &chan->ld_pending);
961 fsldma_free_desc_list(chan, &chan->ld_running);
962 fsldma_free_desc_list(chan, &chan->ld_completed);
963 chan->idle = true;
968f19ae 964
b7f7552b
MR
965 spin_unlock_bh(&chan->desc_lock);
966 return 0;
967}
968f19ae 968
b7f7552b
MR
969static int fsl_dma_device_config(struct dma_chan *dchan,
970 struct dma_slave_config *config)
971{
972 struct fsldma_chan *chan;
973 int size;
968f19ae 974
b7f7552b
MR
975 if (!dchan)
976 return -EINVAL;
968f19ae 977
b7f7552b 978 chan = to_fsl_chan(dchan);
968f19ae 979
b7f7552b
MR
980 /* make sure the channel supports setting burst size */
981 if (!chan->set_request_count)
968f19ae 982 return -ENXIO;
c3635c78 983
b7f7552b
MR
984 /* we set the controller burst size depending on direction */
985 if (config->direction == DMA_MEM_TO_DEV)
986 size = config->dst_addr_width * config->dst_maxburst;
987 else
988 size = config->src_addr_width * config->src_maxburst;
989
990 chan->set_request_count(chan, size);
c3635c78 991 return 0;
bbea0b6e
IS
992}
993
b7f7552b 994
173acc7c
ZW
995/**
996 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
a1c03319 997 * @chan : Freescale DMA channel
173acc7c 998 */
a1c03319 999static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
173acc7c 1000{
a1c03319 1001 struct fsldma_chan *chan = to_fsl_chan(dchan);
dc8d4091 1002
2baff570 1003 spin_lock_bh(&chan->desc_lock);
a1c03319 1004 fsl_chan_xfer_ld_queue(chan);
2baff570 1005 spin_unlock_bh(&chan->desc_lock);
173acc7c
ZW
1006}
1007
173acc7c 1008/**
07934481 1009 * fsl_tx_status - Determine the DMA status
a1c03319 1010 * @chan : Freescale DMA channel
173acc7c 1011 */
07934481 1012static enum dma_status fsl_tx_status(struct dma_chan *dchan,
173acc7c 1013 dma_cookie_t cookie,
07934481 1014 struct dma_tx_state *txstate)
173acc7c 1015{
43452fad
HZ
1016 struct fsldma_chan *chan = to_fsl_chan(dchan);
1017 enum dma_status ret;
1018
1019 ret = dma_cookie_status(dchan, cookie, txstate);
1020 if (ret == DMA_COMPLETE)
1021 return ret;
1022
1023 spin_lock_bh(&chan->desc_lock);
1024 fsldma_cleanup_descriptors(chan);
1025 spin_unlock_bh(&chan->desc_lock);
1026
9b0b0bdc 1027 return dma_cookie_status(dchan, cookie, txstate);
173acc7c
ZW
1028}
1029
d3f620b2
IS
1030/*----------------------------------------------------------------------------*/
1031/* Interrupt Handling */
1032/*----------------------------------------------------------------------------*/
1033
e7a29151 1034static irqreturn_t fsldma_chan_irq(int irq, void *data)
173acc7c 1035{
a1c03319 1036 struct fsldma_chan *chan = data;
a1c03319 1037 u32 stat;
173acc7c 1038
9c3a50b7 1039 /* save and clear the status register */
a1c03319 1040 stat = get_sr(chan);
9c3a50b7 1041 set_sr(chan, stat);
b158471e 1042 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
173acc7c 1043
f04cd407 1044 /* check that this was really our device */
173acc7c
ZW
1045 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1046 if (!stat)
1047 return IRQ_NONE;
1048
1049 if (stat & FSL_DMA_SR_TE)
b158471e 1050 chan_err(chan, "Transfer Error!\n");
173acc7c 1051
9c3a50b7
IS
1052 /*
1053 * Programming Error
f79abb62 1054 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
d73111c6 1055 * trigger a PE interrupt.
f79abb62
ZW
1056 */
1057 if (stat & FSL_DMA_SR_PE) {
b158471e 1058 chan_dbg(chan, "irq: Programming Error INT\n");
f79abb62 1059 stat &= ~FSL_DMA_SR_PE;
f04cd407
IS
1060 if (get_bcr(chan) != 0)
1061 chan_err(chan, "Programming Error!\n");
1c62979e
ZW
1062 }
1063
9c3a50b7
IS
1064 /*
1065 * For MPC8349, EOCDI event need to update cookie
1c62979e
ZW
1066 * and start the next transfer if it exist.
1067 */
1068 if (stat & FSL_DMA_SR_EOCDI) {
b158471e 1069 chan_dbg(chan, "irq: End-of-Chain link INT\n");
1c62979e 1070 stat &= ~FSL_DMA_SR_EOCDI;
173acc7c
ZW
1071 }
1072
9c3a50b7
IS
1073 /*
1074 * If it current transfer is the end-of-transfer,
173acc7c
ZW
1075 * we should clear the Channel Start bit for
1076 * prepare next transfer.
1077 */
1c62979e 1078 if (stat & FSL_DMA_SR_EOLNI) {
b158471e 1079 chan_dbg(chan, "irq: End-of-link INT\n");
173acc7c 1080 stat &= ~FSL_DMA_SR_EOLNI;
173acc7c
ZW
1081 }
1082
f04cd407
IS
1083 /* check that the DMA controller is really idle */
1084 if (!dma_is_idle(chan))
1085 chan_err(chan, "irq: controller not idle!\n");
1086
1087 /* check that we handled all of the bits */
173acc7c 1088 if (stat)
f04cd407 1089 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
173acc7c 1090
f04cd407
IS
1091 /*
1092 * Schedule the tasklet to handle all cleanup of the current
1093 * transaction. It will start a new transaction if there is
1094 * one pending.
1095 */
a1c03319 1096 tasklet_schedule(&chan->tasklet);
f04cd407 1097 chan_dbg(chan, "irq: Exit\n");
173acc7c
ZW
1098 return IRQ_HANDLED;
1099}
1100
d3f620b2
IS
1101static void dma_do_tasklet(unsigned long data)
1102{
a1c03319 1103 struct fsldma_chan *chan = (struct fsldma_chan *)data;
f04cd407
IS
1104
1105 chan_dbg(chan, "tasklet entry\n");
1106
2baff570 1107 spin_lock_bh(&chan->desc_lock);
dc8d4091 1108
dc8d4091 1109 /* the hardware is now idle and ready for more */
f04cd407 1110 chan->idle = true;
f04cd407 1111
43452fad
HZ
1112 /* Run all cleanup for descriptors which have been completed */
1113 fsldma_cleanup_descriptors(chan);
dc8d4091 1114
43452fad 1115 spin_unlock_bh(&chan->desc_lock);
dc8d4091 1116
f04cd407 1117 chan_dbg(chan, "tasklet exit\n");
d3f620b2
IS
1118}
1119
1120static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
173acc7c 1121{
a4f56d4b 1122 struct fsldma_device *fdev = data;
d3f620b2
IS
1123 struct fsldma_chan *chan;
1124 unsigned int handled = 0;
1125 u32 gsr, mask;
1126 int i;
173acc7c 1127
e7a29151 1128 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
d3f620b2
IS
1129 : in_le32(fdev->regs);
1130 mask = 0xff000000;
1131 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
173acc7c 1132
d3f620b2
IS
1133 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1134 chan = fdev->chan[i];
1135 if (!chan)
1136 continue;
1137
1138 if (gsr & mask) {
1139 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1140 fsldma_chan_irq(irq, chan);
1141 handled++;
1142 }
1143
1144 gsr &= ~mask;
1145 mask >>= 8;
1146 }
1147
1148 return IRQ_RETVAL(handled);
173acc7c
ZW
1149}
1150
d3f620b2 1151static void fsldma_free_irqs(struct fsldma_device *fdev)
173acc7c 1152{
d3f620b2
IS
1153 struct fsldma_chan *chan;
1154 int i;
1155
1156 if (fdev->irq != NO_IRQ) {
1157 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1158 free_irq(fdev->irq, fdev);
1159 return;
1160 }
1161
1162 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1163 chan = fdev->chan[i];
1164 if (chan && chan->irq != NO_IRQ) {
b158471e 1165 chan_dbg(chan, "free per-channel IRQ\n");
d3f620b2
IS
1166 free_irq(chan->irq, chan);
1167 }
1168 }
1169}
1170
1171static int fsldma_request_irqs(struct fsldma_device *fdev)
1172{
1173 struct fsldma_chan *chan;
1174 int ret;
1175 int i;
1176
1177 /* if we have a per-controller IRQ, use that */
1178 if (fdev->irq != NO_IRQ) {
1179 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1180 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1181 "fsldma-controller", fdev);
1182 return ret;
1183 }
1184
1185 /* no per-controller IRQ, use the per-channel IRQs */
1186 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1187 chan = fdev->chan[i];
1188 if (!chan)
1189 continue;
1190
1191 if (chan->irq == NO_IRQ) {
b158471e 1192 chan_err(chan, "interrupts property missing in device tree\n");
d3f620b2
IS
1193 ret = -ENODEV;
1194 goto out_unwind;
1195 }
1196
b158471e 1197 chan_dbg(chan, "request per-channel IRQ\n");
d3f620b2
IS
1198 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1199 "fsldma-chan", chan);
1200 if (ret) {
b158471e 1201 chan_err(chan, "unable to request per-channel IRQ\n");
d3f620b2
IS
1202 goto out_unwind;
1203 }
1204 }
1205
1206 return 0;
1207
1208out_unwind:
1209 for (/* none */; i >= 0; i--) {
1210 chan = fdev->chan[i];
1211 if (!chan)
1212 continue;
1213
1214 if (chan->irq == NO_IRQ)
1215 continue;
1216
1217 free_irq(chan->irq, chan);
1218 }
1219
1220 return ret;
173acc7c
ZW
1221}
1222
a4f56d4b
IS
1223/*----------------------------------------------------------------------------*/
1224/* OpenFirmware Subsystem */
1225/*----------------------------------------------------------------------------*/
1226
463a1f8b 1227static int fsl_dma_chan_probe(struct fsldma_device *fdev,
77cd62e8 1228 struct device_node *node, u32 feature, const char *compatible)
173acc7c 1229{
a1c03319 1230 struct fsldma_chan *chan;
4ce0e953 1231 struct resource res;
173acc7c
ZW
1232 int err;
1233
173acc7c 1234 /* alloc channel */
a1c03319
IS
1235 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1236 if (!chan) {
e7a29151
IS
1237 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1238 err = -ENOMEM;
1239 goto out_return;
1240 }
1241
1242 /* ioremap registers for use */
a1c03319
IS
1243 chan->regs = of_iomap(node, 0);
1244 if (!chan->regs) {
e7a29151
IS
1245 dev_err(fdev->dev, "unable to ioremap registers\n");
1246 err = -ENOMEM;
a1c03319 1247 goto out_free_chan;
173acc7c
ZW
1248 }
1249
4ce0e953 1250 err = of_address_to_resource(node, 0, &res);
173acc7c 1251 if (err) {
e7a29151
IS
1252 dev_err(fdev->dev, "unable to find 'reg' property\n");
1253 goto out_iounmap_regs;
173acc7c
ZW
1254 }
1255
a1c03319 1256 chan->feature = feature;
173acc7c 1257 if (!fdev->feature)
a1c03319 1258 fdev->feature = chan->feature;
173acc7c 1259
e7a29151
IS
1260 /*
1261 * If the DMA device's feature is different than the feature
1262 * of its channels, report the bug
173acc7c 1263 */
a1c03319 1264 WARN_ON(fdev->feature != chan->feature);
e7a29151 1265
a1c03319 1266 chan->dev = fdev->dev;
8de7a7d9
HZ
1267 chan->id = (res.start & 0xfff) < 0x300 ?
1268 ((res.start - 0x100) & 0xfff) >> 7 :
1269 ((res.start - 0x200) & 0xfff) >> 7;
a1c03319 1270 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
e7a29151 1271 dev_err(fdev->dev, "too many channels for device\n");
173acc7c 1272 err = -EINVAL;
e7a29151 1273 goto out_iounmap_regs;
173acc7c 1274 }
173acc7c 1275
a1c03319
IS
1276 fdev->chan[chan->id] = chan;
1277 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
b158471e 1278 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
e7a29151
IS
1279
1280 /* Initialize the channel */
a1c03319 1281 dma_init(chan);
173acc7c
ZW
1282
1283 /* Clear cdar registers */
a1c03319 1284 set_cdar(chan, 0);
173acc7c 1285
a1c03319 1286 switch (chan->feature & FSL_DMA_IP_MASK) {
173acc7c 1287 case FSL_DMA_IP_85XX:
a1c03319 1288 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
173acc7c 1289 case FSL_DMA_IP_83XX:
a1c03319
IS
1290 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1291 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1292 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1293 chan->set_request_count = fsl_chan_set_request_count;
173acc7c
ZW
1294 }
1295
a1c03319 1296 spin_lock_init(&chan->desc_lock);
9c3a50b7
IS
1297 INIT_LIST_HEAD(&chan->ld_pending);
1298 INIT_LIST_HEAD(&chan->ld_running);
43452fad 1299 INIT_LIST_HEAD(&chan->ld_completed);
f04cd407 1300 chan->idle = true;
14c6a333
HZ
1301#ifdef CONFIG_PM
1302 chan->pm_state = RUNNING;
1303#endif
173acc7c 1304
a1c03319 1305 chan->common.device = &fdev->common;
8ac69546 1306 dma_cookie_init(&chan->common);
173acc7c 1307
d3f620b2 1308 /* find the IRQ line, if it exists in the device tree */
a1c03319 1309 chan->irq = irq_of_parse_and_map(node, 0);
d3f620b2 1310
173acc7c 1311 /* Add the channel to DMA device channel list */
a1c03319 1312 list_add_tail(&chan->common.device_node, &fdev->common.channels);
173acc7c 1313
a1c03319
IS
1314 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1315 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
173acc7c
ZW
1316
1317 return 0;
51ee87f2 1318
e7a29151 1319out_iounmap_regs:
a1c03319
IS
1320 iounmap(chan->regs);
1321out_free_chan:
1322 kfree(chan);
e7a29151 1323out_return:
173acc7c
ZW
1324 return err;
1325}
1326
a1c03319 1327static void fsl_dma_chan_remove(struct fsldma_chan *chan)
173acc7c 1328{
a1c03319
IS
1329 irq_dispose_mapping(chan->irq);
1330 list_del(&chan->common.device_node);
1331 iounmap(chan->regs);
1332 kfree(chan);
173acc7c
ZW
1333}
1334
463a1f8b 1335static int fsldma_of_probe(struct platform_device *op)
173acc7c 1336{
a4f56d4b 1337 struct fsldma_device *fdev;
77cd62e8 1338 struct device_node *child;
e7a29151 1339 int err;
173acc7c 1340
a4f56d4b 1341 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
173acc7c 1342 if (!fdev) {
e7a29151
IS
1343 dev_err(&op->dev, "No enough memory for 'priv'\n");
1344 err = -ENOMEM;
1345 goto out_return;
173acc7c 1346 }
e7a29151
IS
1347
1348 fdev->dev = &op->dev;
173acc7c
ZW
1349 INIT_LIST_HEAD(&fdev->common.channels);
1350
e7a29151 1351 /* ioremap the registers for use */
61c7a080 1352 fdev->regs = of_iomap(op->dev.of_node, 0);
e7a29151
IS
1353 if (!fdev->regs) {
1354 dev_err(&op->dev, "unable to ioremap registers\n");
1355 err = -ENOMEM;
1356 goto out_free_fdev;
173acc7c
ZW
1357 }
1358
d3f620b2 1359 /* map the channel IRQ if it exists, but don't hookup the handler yet */
61c7a080 1360 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
d3f620b2 1361
173acc7c 1362 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
c1433041 1363 dma_cap_set(DMA_SG, fdev->common.cap_mask);
bbea0b6e 1364 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
173acc7c
ZW
1365 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1366 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1367 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
c1433041 1368 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
07934481 1369 fdev->common.device_tx_status = fsl_tx_status;
173acc7c 1370 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
b7f7552b
MR
1371 fdev->common.device_config = fsl_dma_device_config;
1372 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
e7a29151 1373 fdev->common.dev = &op->dev;
173acc7c 1374
75dc1775
KH
1375 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1376 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1377 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1378 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1379
e2c8e425
LY
1380 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1381
dd3daca1 1382 platform_set_drvdata(op, fdev);
77cd62e8 1383
e7a29151
IS
1384 /*
1385 * We cannot use of_platform_bus_probe() because there is no
1386 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
77cd62e8
TT
1387 * channel object.
1388 */
61c7a080 1389 for_each_child_of_node(op->dev.of_node, child) {
e7a29151 1390 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
77cd62e8
TT
1391 fsl_dma_chan_probe(fdev, child,
1392 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1393 "fsl,eloplus-dma-channel");
e7a29151
IS
1394 }
1395
1396 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
77cd62e8
TT
1397 fsl_dma_chan_probe(fdev, child,
1398 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1399 "fsl,elo-dma-channel");
e7a29151 1400 }
77cd62e8 1401 }
173acc7c 1402
d3f620b2
IS
1403 /*
1404 * Hookup the IRQ handler(s)
1405 *
1406 * If we have a per-controller interrupt, we prefer that to the
1407 * per-channel interrupts to reduce the number of shared interrupt
1408 * handlers on the same IRQ line
1409 */
1410 err = fsldma_request_irqs(fdev);
1411 if (err) {
1412 dev_err(fdev->dev, "unable to request IRQs\n");
1413 goto out_free_fdev;
1414 }
1415
173acc7c
ZW
1416 dma_async_device_register(&fdev->common);
1417 return 0;
1418
e7a29151 1419out_free_fdev:
d3f620b2 1420 irq_dispose_mapping(fdev->irq);
173acc7c 1421 kfree(fdev);
e7a29151 1422out_return:
173acc7c
ZW
1423 return err;
1424}
1425
2dc11581 1426static int fsldma_of_remove(struct platform_device *op)
77cd62e8 1427{
a4f56d4b 1428 struct fsldma_device *fdev;
77cd62e8
TT
1429 unsigned int i;
1430
dd3daca1 1431 fdev = platform_get_drvdata(op);
77cd62e8
TT
1432 dma_async_device_unregister(&fdev->common);
1433
d3f620b2
IS
1434 fsldma_free_irqs(fdev);
1435
e7a29151 1436 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
77cd62e8
TT
1437 if (fdev->chan[i])
1438 fsl_dma_chan_remove(fdev->chan[i]);
e7a29151 1439 }
77cd62e8 1440
e7a29151 1441 iounmap(fdev->regs);
77cd62e8 1442 kfree(fdev);
77cd62e8
TT
1443
1444 return 0;
1445}
1446
14c6a333
HZ
1447#ifdef CONFIG_PM
1448static int fsldma_suspend_late(struct device *dev)
1449{
1450 struct platform_device *pdev = to_platform_device(dev);
1451 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1452 struct fsldma_chan *chan;
1453 int i;
1454
1455 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1456 chan = fdev->chan[i];
1457 if (!chan)
1458 continue;
1459
1460 spin_lock_bh(&chan->desc_lock);
1461 if (unlikely(!chan->idle))
1462 goto out;
1463 chan->regs_save.mr = get_mr(chan);
1464 chan->pm_state = SUSPENDED;
1465 spin_unlock_bh(&chan->desc_lock);
1466 }
1467 return 0;
1468
1469out:
1470 for (; i >= 0; i--) {
1471 chan = fdev->chan[i];
1472 if (!chan)
1473 continue;
1474 chan->pm_state = RUNNING;
1475 spin_unlock_bh(&chan->desc_lock);
1476 }
1477 return -EBUSY;
1478}
1479
1480static int fsldma_resume_early(struct device *dev)
1481{
1482 struct platform_device *pdev = to_platform_device(dev);
1483 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1484 struct fsldma_chan *chan;
1485 u32 mode;
1486 int i;
1487
1488 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1489 chan = fdev->chan[i];
1490 if (!chan)
1491 continue;
1492
1493 spin_lock_bh(&chan->desc_lock);
1494 mode = chan->regs_save.mr
1495 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1496 set_mr(chan, mode);
1497 chan->pm_state = RUNNING;
1498 spin_unlock_bh(&chan->desc_lock);
1499 }
1500
1501 return 0;
1502}
1503
1504static const struct dev_pm_ops fsldma_pm_ops = {
1505 .suspend_late = fsldma_suspend_late,
1506 .resume_early = fsldma_resume_early,
1507};
1508#endif
1509
4b1cf1fa 1510static const struct of_device_id fsldma_of_ids[] = {
8de7a7d9 1511 { .compatible = "fsl,elo3-dma", },
049c9d45
KG
1512 { .compatible = "fsl,eloplus-dma", },
1513 { .compatible = "fsl,elo-dma", },
173acc7c
ZW
1514 {}
1515};
7522c240 1516MODULE_DEVICE_TABLE(of, fsldma_of_ids);
173acc7c 1517
8faa7cf8 1518static struct platform_driver fsldma_of_driver = {
4018294b
GL
1519 .driver = {
1520 .name = "fsl-elo-dma",
4018294b 1521 .of_match_table = fsldma_of_ids,
14c6a333
HZ
1522#ifdef CONFIG_PM
1523 .pm = &fsldma_pm_ops,
1524#endif
4018294b
GL
1525 },
1526 .probe = fsldma_of_probe,
1527 .remove = fsldma_of_remove,
173acc7c
ZW
1528};
1529
a4f56d4b
IS
1530/*----------------------------------------------------------------------------*/
1531/* Module Init / Exit */
1532/*----------------------------------------------------------------------------*/
1533
1534static __init int fsldma_init(void)
173acc7c 1535{
8de7a7d9 1536 pr_info("Freescale Elo series DMA driver\n");
00006124 1537 return platform_driver_register(&fsldma_of_driver);
77cd62e8
TT
1538}
1539
a4f56d4b 1540static void __exit fsldma_exit(void)
77cd62e8 1541{
00006124 1542 platform_driver_unregister(&fsldma_of_driver);
173acc7c
ZW
1543}
1544
a4f56d4b
IS
1545subsys_initcall(fsldma_init);
1546module_exit(fsldma_exit);
77cd62e8 1547
8de7a7d9 1548MODULE_DESCRIPTION("Freescale Elo series DMA driver");
77cd62e8 1549MODULE_LICENSE("GPL");