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Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
38 | #include "fsldma.h" | |
39 | ||
b158471e IS |
40 | #define chan_dbg(chan, fmt, arg...) \ |
41 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
42 | #define chan_err(chan, fmt, arg...) \ | |
43 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
44 | ||
45 | static const char msg_ld_oom[] = "No free memory for link descriptor"; | |
c1433041 | 46 | |
e8bd84df IS |
47 | /* |
48 | * Register Helpers | |
49 | */ | |
173acc7c | 50 | |
a1c03319 | 51 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 52 | { |
a1c03319 | 53 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
54 | } |
55 | ||
a1c03319 | 56 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 57 | { |
a1c03319 | 58 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
59 | } |
60 | ||
e8bd84df IS |
61 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
62 | { | |
63 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
64 | } | |
65 | ||
66 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
67 | { | |
68 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
69 | } | |
70 | ||
71 | static dma_addr_t get_ndar(struct fsldma_chan *chan) | |
72 | { | |
73 | return DMA_IN(chan, &chan->regs->ndar, 64); | |
74 | } | |
75 | ||
76 | static u32 get_bcr(struct fsldma_chan *chan) | |
77 | { | |
78 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
79 | } | |
80 | ||
81 | /* | |
82 | * Descriptor Helpers | |
83 | */ | |
84 | ||
a1c03319 | 85 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
86 | struct fsl_dma_ld_hw *hw, u32 count) |
87 | { | |
a1c03319 | 88 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
89 | } |
90 | ||
a1c03319 | 91 | static void set_desc_src(struct fsldma_chan *chan, |
173acc7c ZW |
92 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
93 | { | |
94 | u64 snoop_bits; | |
95 | ||
a1c03319 | 96 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 97 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 98 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
99 | } |
100 | ||
a1c03319 | 101 | static void set_desc_dst(struct fsldma_chan *chan, |
738f5f7e | 102 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
103 | { |
104 | u64 snoop_bits; | |
105 | ||
a1c03319 | 106 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 107 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 108 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
109 | } |
110 | ||
a1c03319 | 111 | static void set_desc_next(struct fsldma_chan *chan, |
173acc7c ZW |
112 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
113 | { | |
114 | u64 snoop_bits; | |
115 | ||
a1c03319 | 116 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 117 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 118 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
119 | } |
120 | ||
e8bd84df IS |
121 | static void set_ld_eol(struct fsldma_chan *chan, |
122 | struct fsl_desc_sw *desc) | |
173acc7c | 123 | { |
e8bd84df | 124 | u64 snoop_bits; |
173acc7c | 125 | |
e8bd84df IS |
126 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
127 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 128 | |
e8bd84df IS |
129 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
130 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
131 | | snoop_bits, 64); | |
173acc7c ZW |
132 | } |
133 | ||
e8bd84df IS |
134 | /* |
135 | * DMA Engine Hardware Control Helpers | |
136 | */ | |
137 | ||
138 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 139 | { |
e8bd84df IS |
140 | /* Reset the channel */ |
141 | DMA_OUT(chan, &chan->regs->mr, 0, 32); | |
142 | ||
143 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
144 | case FSL_DMA_IP_85XX: | |
145 | /* Set the channel to below modes: | |
146 | * EIE - Error interrupt enable | |
147 | * EOSIE - End of segments interrupt enable (basic mode) | |
148 | * EOLNIE - End of links interrupt enable | |
149 | * BWC - Bandwidth sharing among channels | |
150 | */ | |
151 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC | |
152 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE | |
153 | | FSL_DMA_MR_EOSIE, 32); | |
154 | break; | |
155 | case FSL_DMA_IP_83XX: | |
156 | /* Set the channel to below modes: | |
157 | * EOTIE - End-of-transfer interrupt enable | |
158 | * PRC_RM - PCI read multiple | |
159 | */ | |
160 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | |
161 | | FSL_DMA_MR_PRC_RM, 32); | |
162 | break; | |
163 | } | |
f79abb62 ZW |
164 | } |
165 | ||
a1c03319 | 166 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 167 | { |
a1c03319 | 168 | u32 sr = get_sr(chan); |
173acc7c ZW |
169 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
170 | } | |
171 | ||
a1c03319 | 172 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 173 | { |
272ca655 IS |
174 | u32 mode; |
175 | ||
a1c03319 | 176 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 177 | |
a1c03319 IS |
178 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
179 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
180 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
272ca655 IS |
181 | mode |= FSL_DMA_MR_EMP_EN; |
182 | } else { | |
183 | mode &= ~FSL_DMA_MR_EMP_EN; | |
184 | } | |
43a1a3ed | 185 | } |
173acc7c | 186 | |
a1c03319 | 187 | if (chan->feature & FSL_DMA_CHAN_START_EXT) |
272ca655 | 188 | mode |= FSL_DMA_MR_EMS_EN; |
173acc7c | 189 | else |
272ca655 | 190 | mode |= FSL_DMA_MR_CS; |
173acc7c | 191 | |
a1c03319 | 192 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
193 | } |
194 | ||
a1c03319 | 195 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 196 | { |
272ca655 | 197 | u32 mode; |
900325a6 DW |
198 | int i; |
199 | ||
a1c03319 | 200 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 201 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 202 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
203 | |
204 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 205 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 206 | |
900325a6 | 207 | for (i = 0; i < 100; i++) { |
a1c03319 | 208 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
209 | return; |
210 | ||
173acc7c | 211 | udelay(10); |
900325a6 | 212 | } |
272ca655 | 213 | |
9c3a50b7 | 214 | if (!dma_is_idle(chan)) |
b158471e | 215 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
216 | } |
217 | ||
173acc7c ZW |
218 | /** |
219 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 220 | * @chan : Freescale DMA channel |
173acc7c ZW |
221 | * @size : Address loop size, 0 for disable loop |
222 | * | |
223 | * The set source address hold transfer size. The source | |
224 | * address hold or loop transfer size is when the DMA transfer | |
225 | * data from source address (SA), if the loop size is 4, the DMA will | |
226 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
227 | * SA + 1 ... and so on. | |
228 | */ | |
a1c03319 | 229 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 230 | { |
272ca655 IS |
231 | u32 mode; |
232 | ||
a1c03319 | 233 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 234 | |
173acc7c ZW |
235 | switch (size) { |
236 | case 0: | |
272ca655 | 237 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
238 | break; |
239 | case 1: | |
240 | case 2: | |
241 | case 4: | |
242 | case 8: | |
272ca655 | 243 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
244 | break; |
245 | } | |
272ca655 | 246 | |
a1c03319 | 247 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
248 | } |
249 | ||
250 | /** | |
738f5f7e | 251 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 252 | * @chan : Freescale DMA channel |
173acc7c ZW |
253 | * @size : Address loop size, 0 for disable loop |
254 | * | |
255 | * The set destination address hold transfer size. The destination | |
256 | * address hold or loop transfer size is when the DMA transfer | |
257 | * data to destination address (TA), if the loop size is 4, the DMA will | |
258 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
259 | * TA + 1 ... and so on. | |
260 | */ | |
a1c03319 | 261 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 262 | { |
272ca655 IS |
263 | u32 mode; |
264 | ||
a1c03319 | 265 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 266 | |
173acc7c ZW |
267 | switch (size) { |
268 | case 0: | |
272ca655 | 269 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
270 | break; |
271 | case 1: | |
272 | case 2: | |
273 | case 4: | |
274 | case 8: | |
272ca655 | 275 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
276 | break; |
277 | } | |
272ca655 | 278 | |
a1c03319 | 279 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
280 | } |
281 | ||
282 | /** | |
e6c7ecb6 | 283 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 284 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
285 | * @size : Number of bytes to transfer in a single request |
286 | * | |
287 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
288 | * The DMA request count is how many bytes are allowed to transfer before | |
289 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
290 | * operation. | |
173acc7c | 291 | * |
e6c7ecb6 | 292 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 293 | */ |
a1c03319 | 294 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 295 | { |
272ca655 IS |
296 | u32 mode; |
297 | ||
e6c7ecb6 | 298 | BUG_ON(size > 1024); |
272ca655 | 299 | |
a1c03319 | 300 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
301 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
302 | ||
a1c03319 | 303 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 304 | } |
173acc7c | 305 | |
e6c7ecb6 IS |
306 | /** |
307 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 308 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
309 | * @enable : 0 is disabled, 1 is enabled. |
310 | * | |
311 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
312 | * The DMA Request Count feature should be used in addition to this feature | |
313 | * to set the number of bytes to transfer before pausing the channel. | |
314 | */ | |
a1c03319 | 315 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
316 | { |
317 | if (enable) | |
a1c03319 | 318 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 319 | else |
a1c03319 | 320 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
321 | } |
322 | ||
323 | /** | |
324 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 325 | * @chan : Freescale DMA channel |
173acc7c ZW |
326 | * @enable : 0 is disabled, 1 is enabled. |
327 | * | |
328 | * If enable the external start, the channel can be started by an | |
329 | * external DMA start pin. So the dma_start() does not start the | |
330 | * transfer immediately. The DMA channel will wait for the | |
331 | * control pin asserted. | |
332 | */ | |
a1c03319 | 333 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
334 | { |
335 | if (enable) | |
a1c03319 | 336 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 337 | else |
a1c03319 | 338 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
339 | } |
340 | ||
9c3a50b7 IS |
341 | static void append_ld_queue(struct fsldma_chan *chan, |
342 | struct fsl_desc_sw *desc) | |
343 | { | |
344 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
345 | ||
346 | if (list_empty(&chan->ld_pending)) | |
347 | goto out_splice; | |
348 | ||
349 | /* | |
350 | * Add the hardware descriptor to the chain of hardware descriptors | |
351 | * that already exists in memory. | |
352 | * | |
353 | * This will un-set the EOL bit of the existing transaction, and the | |
354 | * last link in this transaction will become the EOL descriptor. | |
355 | */ | |
356 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
357 | ||
358 | /* | |
359 | * Add the software descriptor and all children to the list | |
360 | * of pending transactions | |
361 | */ | |
362 | out_splice: | |
363 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
364 | } | |
365 | ||
173acc7c ZW |
366 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
367 | { | |
a1c03319 | 368 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
369 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
370 | struct fsl_desc_sw *child; | |
173acc7c ZW |
371 | unsigned long flags; |
372 | dma_cookie_t cookie; | |
373 | ||
a1c03319 | 374 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 375 | |
9c3a50b7 IS |
376 | /* |
377 | * assign cookies to all of the software descriptors | |
378 | * that make up this transaction | |
379 | */ | |
a1c03319 | 380 | cookie = chan->common.cookie; |
eda34234 | 381 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 IS |
382 | cookie++; |
383 | if (cookie < 0) | |
384 | cookie = 1; | |
385 | ||
6ca3a7a9 | 386 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
387 | } |
388 | ||
a1c03319 | 389 | chan->common.cookie = cookie; |
9c3a50b7 IS |
390 | |
391 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 392 | append_ld_queue(chan, desc); |
173acc7c | 393 | |
a1c03319 | 394 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
395 | |
396 | return cookie; | |
397 | } | |
398 | ||
399 | /** | |
400 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 401 | * @chan : Freescale DMA channel |
173acc7c ZW |
402 | * |
403 | * Return - The descriptor allocated. NULL for failed. | |
404 | */ | |
405 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
a1c03319 | 406 | struct fsldma_chan *chan) |
173acc7c | 407 | { |
9c3a50b7 | 408 | struct fsl_desc_sw *desc; |
173acc7c | 409 | dma_addr_t pdesc; |
9c3a50b7 IS |
410 | |
411 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
412 | if (!desc) { | |
b158471e | 413 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 414 | return NULL; |
173acc7c ZW |
415 | } |
416 | ||
9c3a50b7 IS |
417 | memset(desc, 0, sizeof(*desc)); |
418 | INIT_LIST_HEAD(&desc->tx_list); | |
419 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
420 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
421 | desc->async_tx.phys = pdesc; | |
422 | ||
0ab09c36 IS |
423 | #ifdef FSL_DMA_LD_DEBUG |
424 | chan_dbg(chan, "LD %p allocated\n", desc); | |
425 | #endif | |
426 | ||
9c3a50b7 | 427 | return desc; |
173acc7c ZW |
428 | } |
429 | ||
430 | ||
431 | /** | |
432 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 433 | * @chan : Freescale DMA channel |
173acc7c ZW |
434 | * |
435 | * This function will create a dma pool for descriptor allocation. | |
436 | * | |
437 | * Return - The number of descriptors allocated. | |
438 | */ | |
a1c03319 | 439 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 440 | { |
a1c03319 | 441 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
442 | |
443 | /* Has this channel already been allocated? */ | |
a1c03319 | 444 | if (chan->desc_pool) |
77cd62e8 | 445 | return 1; |
173acc7c | 446 | |
9c3a50b7 IS |
447 | /* |
448 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
449 | * for meeting FSL DMA specification requirement. |
450 | */ | |
b158471e | 451 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
452 | sizeof(struct fsl_desc_sw), |
453 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 454 | if (!chan->desc_pool) { |
b158471e | 455 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 456 | return -ENOMEM; |
173acc7c ZW |
457 | } |
458 | ||
9c3a50b7 | 459 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
460 | return 1; |
461 | } | |
462 | ||
9c3a50b7 IS |
463 | /** |
464 | * fsldma_free_desc_list - Free all descriptors in a queue | |
465 | * @chan: Freescae DMA channel | |
466 | * @list: the list to free | |
467 | * | |
468 | * LOCKING: must hold chan->desc_lock | |
469 | */ | |
470 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
471 | struct list_head *list) | |
472 | { | |
473 | struct fsl_desc_sw *desc, *_desc; | |
474 | ||
475 | list_for_each_entry_safe(desc, _desc, list, node) { | |
476 | list_del(&desc->node); | |
0ab09c36 IS |
477 | #ifdef FSL_DMA_LD_DEBUG |
478 | chan_dbg(chan, "LD %p free\n", desc); | |
479 | #endif | |
9c3a50b7 IS |
480 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
481 | } | |
482 | } | |
483 | ||
484 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
485 | struct list_head *list) | |
486 | { | |
487 | struct fsl_desc_sw *desc, *_desc; | |
488 | ||
489 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
490 | list_del(&desc->node); | |
0ab09c36 IS |
491 | #ifdef FSL_DMA_LD_DEBUG |
492 | chan_dbg(chan, "LD %p free\n", desc); | |
493 | #endif | |
9c3a50b7 IS |
494 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
495 | } | |
496 | } | |
497 | ||
173acc7c ZW |
498 | /** |
499 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 500 | * @chan : Freescale DMA channel |
173acc7c | 501 | */ |
a1c03319 | 502 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 503 | { |
a1c03319 | 504 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
505 | unsigned long flags; |
506 | ||
b158471e | 507 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 508 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
509 | fsldma_free_desc_list(chan, &chan->ld_pending); |
510 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 511 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 512 | |
9c3a50b7 | 513 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 514 | chan->desc_pool = NULL; |
173acc7c ZW |
515 | } |
516 | ||
2187c269 | 517 | static struct dma_async_tx_descriptor * |
a1c03319 | 518 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 519 | { |
a1c03319 | 520 | struct fsldma_chan *chan; |
2187c269 ZW |
521 | struct fsl_desc_sw *new; |
522 | ||
a1c03319 | 523 | if (!dchan) |
2187c269 ZW |
524 | return NULL; |
525 | ||
a1c03319 | 526 | chan = to_fsl_chan(dchan); |
2187c269 | 527 | |
a1c03319 | 528 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 529 | if (!new) { |
b158471e | 530 | chan_err(chan, "%s\n", msg_ld_oom); |
2187c269 ZW |
531 | return NULL; |
532 | } | |
533 | ||
534 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 535 | new->async_tx.flags = flags; |
2187c269 | 536 | |
f79abb62 | 537 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 538 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 539 | |
2187c269 | 540 | /* Set End-of-link to the last link descriptor of new list*/ |
a1c03319 | 541 | set_ld_eol(chan, new); |
2187c269 ZW |
542 | |
543 | return &new->async_tx; | |
544 | } | |
545 | ||
173acc7c | 546 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
a1c03319 | 547 | struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, |
173acc7c ZW |
548 | size_t len, unsigned long flags) |
549 | { | |
a1c03319 | 550 | struct fsldma_chan *chan; |
173acc7c ZW |
551 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
552 | size_t copy; | |
173acc7c | 553 | |
a1c03319 | 554 | if (!dchan) |
173acc7c ZW |
555 | return NULL; |
556 | ||
557 | if (!len) | |
558 | return NULL; | |
559 | ||
a1c03319 | 560 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
561 | |
562 | do { | |
563 | ||
564 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 565 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 566 | if (!new) { |
b158471e | 567 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 568 | goto fail; |
173acc7c | 569 | } |
173acc7c | 570 | |
56822843 | 571 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 572 | |
a1c03319 IS |
573 | set_desc_cnt(chan, &new->hw, copy); |
574 | set_desc_src(chan, &new->hw, dma_src); | |
575 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
576 | |
577 | if (!first) | |
578 | first = new; | |
579 | else | |
a1c03319 | 580 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
581 | |
582 | new->async_tx.cookie = 0; | |
636bdeaa | 583 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
584 | |
585 | prev = new; | |
586 | len -= copy; | |
587 | dma_src += copy; | |
738f5f7e | 588 | dma_dst += copy; |
173acc7c ZW |
589 | |
590 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 591 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
592 | } while (len); |
593 | ||
636bdeaa | 594 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
595 | new->async_tx.cookie = -EBUSY; |
596 | ||
597 | /* Set End-of-link to the last link descriptor of new list*/ | |
a1c03319 | 598 | set_ld_eol(chan, new); |
173acc7c | 599 | |
2e077f8e IS |
600 | return &first->async_tx; |
601 | ||
602 | fail: | |
603 | if (!first) | |
604 | return NULL; | |
605 | ||
9c3a50b7 | 606 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 607 | return NULL; |
173acc7c ZW |
608 | } |
609 | ||
c1433041 IS |
610 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
611 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
612 | struct scatterlist *src_sg, unsigned int src_nents, | |
613 | unsigned long flags) | |
614 | { | |
615 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
616 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
617 | size_t dst_avail, src_avail; | |
618 | dma_addr_t dst, src; | |
619 | size_t len; | |
620 | ||
621 | /* basic sanity checks */ | |
622 | if (dst_nents == 0 || src_nents == 0) | |
623 | return NULL; | |
624 | ||
625 | if (dst_sg == NULL || src_sg == NULL) | |
626 | return NULL; | |
627 | ||
628 | /* | |
629 | * TODO: should we check that both scatterlists have the same | |
630 | * TODO: number of bytes in total? Is that really an error? | |
631 | */ | |
632 | ||
633 | /* get prepared for the loop */ | |
634 | dst_avail = sg_dma_len(dst_sg); | |
635 | src_avail = sg_dma_len(src_sg); | |
636 | ||
637 | /* run until we are out of scatterlist entries */ | |
638 | while (true) { | |
639 | ||
640 | /* create the largest transaction possible */ | |
641 | len = min_t(size_t, src_avail, dst_avail); | |
642 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
643 | if (len == 0) | |
644 | goto fetch; | |
645 | ||
646 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
647 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
648 | ||
649 | /* allocate and populate the descriptor */ | |
650 | new = fsl_dma_alloc_descriptor(chan); | |
651 | if (!new) { | |
b158471e | 652 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
653 | goto fail; |
654 | } | |
c1433041 IS |
655 | |
656 | set_desc_cnt(chan, &new->hw, len); | |
657 | set_desc_src(chan, &new->hw, src); | |
658 | set_desc_dst(chan, &new->hw, dst); | |
659 | ||
660 | if (!first) | |
661 | first = new; | |
662 | else | |
663 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
664 | ||
665 | new->async_tx.cookie = 0; | |
666 | async_tx_ack(&new->async_tx); | |
667 | prev = new; | |
668 | ||
669 | /* Insert the link descriptor to the LD ring */ | |
670 | list_add_tail(&new->node, &first->tx_list); | |
671 | ||
672 | /* update metadata */ | |
673 | dst_avail -= len; | |
674 | src_avail -= len; | |
675 | ||
676 | fetch: | |
677 | /* fetch the next dst scatterlist entry */ | |
678 | if (dst_avail == 0) { | |
679 | ||
680 | /* no more entries: we're done */ | |
681 | if (dst_nents == 0) | |
682 | break; | |
683 | ||
684 | /* fetch the next entry: if there are no more: done */ | |
685 | dst_sg = sg_next(dst_sg); | |
686 | if (dst_sg == NULL) | |
687 | break; | |
688 | ||
689 | dst_nents--; | |
690 | dst_avail = sg_dma_len(dst_sg); | |
691 | } | |
692 | ||
693 | /* fetch the next src scatterlist entry */ | |
694 | if (src_avail == 0) { | |
695 | ||
696 | /* no more entries: we're done */ | |
697 | if (src_nents == 0) | |
698 | break; | |
699 | ||
700 | /* fetch the next entry: if there are no more: done */ | |
701 | src_sg = sg_next(src_sg); | |
702 | if (src_sg == NULL) | |
703 | break; | |
704 | ||
705 | src_nents--; | |
706 | src_avail = sg_dma_len(src_sg); | |
707 | } | |
708 | } | |
709 | ||
710 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
711 | new->async_tx.cookie = -EBUSY; | |
712 | ||
713 | /* Set End-of-link to the last link descriptor of new list */ | |
714 | set_ld_eol(chan, new); | |
715 | ||
716 | return &first->async_tx; | |
717 | ||
718 | fail: | |
719 | if (!first) | |
720 | return NULL; | |
721 | ||
722 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
723 | return NULL; | |
724 | } | |
725 | ||
bbea0b6e IS |
726 | /** |
727 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
728 | * @chan: DMA channel | |
729 | * @sgl: scatterlist to transfer to/from | |
730 | * @sg_len: number of entries in @scatterlist | |
731 | * @direction: DMA direction | |
732 | * @flags: DMAEngine flags | |
733 | * | |
734 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
735 | * DMA_SLAVE API, this gets the device-specific information from the | |
736 | * chan->private variable. | |
737 | */ | |
738 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 739 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
740 | enum dma_data_direction direction, unsigned long flags) |
741 | { | |
bbea0b6e | 742 | /* |
968f19ae | 743 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 744 | * |
968f19ae IS |
745 | * However, we need to provide the function pointer to allow the |
746 | * device_control() method to work. | |
bbea0b6e | 747 | */ |
bbea0b6e IS |
748 | return NULL; |
749 | } | |
750 | ||
c3635c78 | 751 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 752 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 753 | { |
968f19ae | 754 | struct dma_slave_config *config; |
a1c03319 | 755 | struct fsldma_chan *chan; |
bbea0b6e | 756 | unsigned long flags; |
968f19ae | 757 | int size; |
c3635c78 | 758 | |
a1c03319 | 759 | if (!dchan) |
c3635c78 | 760 | return -EINVAL; |
bbea0b6e | 761 | |
a1c03319 | 762 | chan = to_fsl_chan(dchan); |
bbea0b6e | 763 | |
968f19ae IS |
764 | switch (cmd) { |
765 | case DMA_TERMINATE_ALL: | |
766 | /* Halt the DMA engine */ | |
767 | dma_halt(chan); | |
bbea0b6e | 768 | |
968f19ae | 769 | spin_lock_irqsave(&chan->desc_lock, flags); |
bbea0b6e | 770 | |
968f19ae IS |
771 | /* Remove and free all of the descriptors in the LD queue */ |
772 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
773 | fsldma_free_desc_list(chan, &chan->ld_running); | |
bbea0b6e | 774 | |
968f19ae IS |
775 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
776 | return 0; | |
777 | ||
778 | case DMA_SLAVE_CONFIG: | |
779 | config = (struct dma_slave_config *)arg; | |
780 | ||
781 | /* make sure the channel supports setting burst size */ | |
782 | if (!chan->set_request_count) | |
783 | return -ENXIO; | |
784 | ||
785 | /* we set the controller burst size depending on direction */ | |
786 | if (config->direction == DMA_TO_DEVICE) | |
787 | size = config->dst_addr_width * config->dst_maxburst; | |
788 | else | |
789 | size = config->src_addr_width * config->src_maxburst; | |
790 | ||
791 | chan->set_request_count(chan, size); | |
792 | return 0; | |
793 | ||
794 | case FSLDMA_EXTERNAL_START: | |
795 | ||
796 | /* make sure the channel supports external start */ | |
797 | if (!chan->toggle_ext_start) | |
798 | return -ENXIO; | |
799 | ||
800 | chan->toggle_ext_start(chan, arg); | |
801 | return 0; | |
802 | ||
803 | default: | |
804 | return -ENXIO; | |
805 | } | |
c3635c78 LW |
806 | |
807 | return 0; | |
bbea0b6e IS |
808 | } |
809 | ||
173acc7c ZW |
810 | /** |
811 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
a1c03319 | 812 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
813 | * |
814 | * CONTEXT: hardirq | |
173acc7c | 815 | */ |
a1c03319 | 816 | static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) |
173acc7c | 817 | { |
9c3a50b7 IS |
818 | struct fsl_desc_sw *desc; |
819 | unsigned long flags; | |
820 | dma_cookie_t cookie; | |
173acc7c | 821 | |
9c3a50b7 | 822 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 823 | |
9c3a50b7 | 824 | if (list_empty(&chan->ld_running)) { |
b158471e | 825 | chan_dbg(chan, "no running descriptors\n"); |
9c3a50b7 | 826 | goto out_unlock; |
173acc7c | 827 | } |
9c3a50b7 IS |
828 | |
829 | /* Get the last descriptor, update the cookie to that */ | |
830 | desc = to_fsl_desc(chan->ld_running.prev); | |
831 | if (dma_is_idle(chan)) | |
832 | cookie = desc->async_tx.cookie; | |
76bd061f | 833 | else { |
9c3a50b7 | 834 | cookie = desc->async_tx.cookie - 1; |
76bd061f SM |
835 | if (unlikely(cookie < DMA_MIN_COOKIE)) |
836 | cookie = DMA_MAX_COOKIE; | |
837 | } | |
9c3a50b7 IS |
838 | |
839 | chan->completed_cookie = cookie; | |
840 | ||
841 | out_unlock: | |
842 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
843 | } | |
844 | ||
845 | /** | |
846 | * fsldma_desc_status - Check the status of a descriptor | |
847 | * @chan: Freescale DMA channel | |
848 | * @desc: DMA SW descriptor | |
849 | * | |
850 | * This function will return the status of the given descriptor | |
851 | */ | |
852 | static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, | |
853 | struct fsl_desc_sw *desc) | |
854 | { | |
855 | return dma_async_is_complete(desc->async_tx.cookie, | |
856 | chan->completed_cookie, | |
857 | chan->common.cookie); | |
173acc7c ZW |
858 | } |
859 | ||
860 | /** | |
861 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
a1c03319 | 862 | * @chan : Freescale DMA channel |
173acc7c ZW |
863 | * |
864 | * This function clean up the ld_queue of DMA channel. | |
173acc7c | 865 | */ |
a1c03319 | 866 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c ZW |
867 | { |
868 | struct fsl_desc_sw *desc, *_desc; | |
869 | unsigned long flags; | |
870 | ||
a1c03319 | 871 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 872 | |
b158471e | 873 | chan_dbg(chan, "chan completed_cookie = %d\n", chan->completed_cookie); |
9c3a50b7 | 874 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { |
173acc7c ZW |
875 | dma_async_tx_callback callback; |
876 | void *callback_param; | |
877 | ||
9c3a50b7 | 878 | if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) |
173acc7c ZW |
879 | break; |
880 | ||
9c3a50b7 | 881 | /* Remove from the list of running transactions */ |
173acc7c ZW |
882 | list_del(&desc->node); |
883 | ||
173acc7c | 884 | /* Run the link descriptor callback function */ |
9c3a50b7 IS |
885 | callback = desc->async_tx.callback; |
886 | callback_param = desc->async_tx.callback_param; | |
173acc7c | 887 | if (callback) { |
a1c03319 | 888 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
0ab09c36 | 889 | #ifdef FSL_DMA_LD_DEBUG |
b158471e | 890 | chan_dbg(chan, "LD %p callback\n", desc); |
0ab09c36 | 891 | #endif |
173acc7c | 892 | callback(callback_param); |
a1c03319 | 893 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 894 | } |
9c3a50b7 IS |
895 | |
896 | /* Run any dependencies, then free the descriptor */ | |
897 | dma_run_dependencies(&desc->async_tx); | |
0ab09c36 IS |
898 | #ifdef FSL_DMA_LD_DEBUG |
899 | chan_dbg(chan, "LD %p free\n", desc); | |
900 | #endif | |
9c3a50b7 | 901 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
173acc7c | 902 | } |
9c3a50b7 | 903 | |
a1c03319 | 904 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
905 | } |
906 | ||
907 | /** | |
9c3a50b7 | 908 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 909 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
910 | * |
911 | * This will make sure that any pending transactions will be run. | |
912 | * If the DMA controller is idle, it will be started. Otherwise, | |
913 | * the DMA controller's interrupt handler will start any pending | |
914 | * transactions when it becomes idle. | |
173acc7c | 915 | */ |
a1c03319 | 916 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 917 | { |
9c3a50b7 | 918 | struct fsl_desc_sw *desc; |
173acc7c ZW |
919 | unsigned long flags; |
920 | ||
a1c03319 | 921 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 922 | |
9c3a50b7 IS |
923 | /* |
924 | * If the list of pending descriptors is empty, then we | |
925 | * don't need to do any work at all | |
926 | */ | |
927 | if (list_empty(&chan->ld_pending)) { | |
b158471e | 928 | chan_dbg(chan, "no pending LDs\n"); |
138ef018 | 929 | goto out_unlock; |
9c3a50b7 | 930 | } |
173acc7c | 931 | |
9c3a50b7 IS |
932 | /* |
933 | * The DMA controller is not idle, which means the interrupt | |
934 | * handler will start any queued transactions when it runs | |
935 | * at the end of the current transaction | |
936 | */ | |
937 | if (!dma_is_idle(chan)) { | |
b158471e | 938 | chan_dbg(chan, "DMA controller still busy\n"); |
9c3a50b7 IS |
939 | goto out_unlock; |
940 | } | |
941 | ||
942 | /* | |
943 | * TODO: | |
944 | * make sure the dma_halt() function really un-wedges the | |
945 | * controller as much as possible | |
946 | */ | |
a1c03319 | 947 | dma_halt(chan); |
173acc7c | 948 | |
9c3a50b7 IS |
949 | /* |
950 | * If there are some link descriptors which have not been | |
951 | * transferred, we need to start the controller | |
173acc7c | 952 | */ |
173acc7c | 953 | |
9c3a50b7 IS |
954 | /* |
955 | * Move all elements from the queue of pending transactions | |
956 | * onto the list of running transactions | |
957 | */ | |
958 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
959 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
960 | ||
961 | /* | |
962 | * Program the descriptor's address into the DMA controller, | |
963 | * then start the DMA transaction | |
964 | */ | |
965 | set_cdar(chan, desc->async_tx.phys); | |
966 | dma_start(chan); | |
138ef018 IS |
967 | |
968 | out_unlock: | |
a1c03319 | 969 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
970 | } |
971 | ||
972 | /** | |
973 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 974 | * @chan : Freescale DMA channel |
173acc7c | 975 | */ |
a1c03319 | 976 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 977 | { |
a1c03319 | 978 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
a1c03319 | 979 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
980 | } |
981 | ||
173acc7c | 982 | /** |
07934481 | 983 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 984 | * @chan : Freescale DMA channel |
173acc7c | 985 | */ |
07934481 | 986 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 987 | dma_cookie_t cookie, |
07934481 | 988 | struct dma_tx_state *txstate) |
173acc7c | 989 | { |
a1c03319 | 990 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
991 | dma_cookie_t last_used; |
992 | dma_cookie_t last_complete; | |
993 | ||
a1c03319 | 994 | fsl_chan_ld_cleanup(chan); |
173acc7c | 995 | |
a1c03319 IS |
996 | last_used = dchan->cookie; |
997 | last_complete = chan->completed_cookie; | |
173acc7c | 998 | |
bca34692 | 999 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
1000 | |
1001 | return dma_async_is_complete(cookie, last_complete, last_used); | |
1002 | } | |
1003 | ||
d3f620b2 IS |
1004 | /*----------------------------------------------------------------------------*/ |
1005 | /* Interrupt Handling */ | |
1006 | /*----------------------------------------------------------------------------*/ | |
1007 | ||
e7a29151 | 1008 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 1009 | { |
a1c03319 | 1010 | struct fsldma_chan *chan = data; |
1c62979e ZW |
1011 | int update_cookie = 0; |
1012 | int xfer_ld_q = 0; | |
a1c03319 | 1013 | u32 stat; |
173acc7c | 1014 | |
9c3a50b7 | 1015 | /* save and clear the status register */ |
a1c03319 | 1016 | stat = get_sr(chan); |
9c3a50b7 | 1017 | set_sr(chan, stat); |
b158471e | 1018 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c ZW |
1019 | |
1020 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
1021 | if (!stat) | |
1022 | return IRQ_NONE; | |
1023 | ||
1024 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 1025 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 1026 | |
9c3a50b7 IS |
1027 | /* |
1028 | * Programming Error | |
f79abb62 ZW |
1029 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1030 | * triger a PE interrupt. | |
1031 | */ | |
1032 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 1033 | chan_dbg(chan, "irq: Programming Error INT\n"); |
a1c03319 | 1034 | if (get_bcr(chan) == 0) { |
f79abb62 ZW |
1035 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. |
1036 | * Now, update the completed cookie, and continue the | |
1037 | * next uncompleted transfer. | |
1038 | */ | |
1c62979e ZW |
1039 | update_cookie = 1; |
1040 | xfer_ld_q = 1; | |
f79abb62 ZW |
1041 | } |
1042 | stat &= ~FSL_DMA_SR_PE; | |
1043 | } | |
1044 | ||
9c3a50b7 IS |
1045 | /* |
1046 | * If the link descriptor segment transfer finishes, | |
173acc7c ZW |
1047 | * we will recycle the used descriptor. |
1048 | */ | |
1049 | if (stat & FSL_DMA_SR_EOSI) { | |
b158471e IS |
1050 | chan_dbg(chan, "irq: End-of-segments INT\n"); |
1051 | chan_dbg(chan, "irq: clndar 0x%llx, nlndar 0x%llx\n", | |
a1c03319 IS |
1052 | (unsigned long long)get_cdar(chan), |
1053 | (unsigned long long)get_ndar(chan)); | |
173acc7c | 1054 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
1055 | update_cookie = 1; |
1056 | } | |
1057 | ||
9c3a50b7 IS |
1058 | /* |
1059 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1060 | * and start the next transfer if it exist. |
1061 | */ | |
1062 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 1063 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e ZW |
1064 | stat &= ~FSL_DMA_SR_EOCDI; |
1065 | update_cookie = 1; | |
1066 | xfer_ld_q = 1; | |
173acc7c ZW |
1067 | } |
1068 | ||
9c3a50b7 IS |
1069 | /* |
1070 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1071 | * we should clear the Channel Start bit for |
1072 | * prepare next transfer. | |
1073 | */ | |
1c62979e | 1074 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 1075 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 1076 | stat &= ~FSL_DMA_SR_EOLNI; |
1c62979e | 1077 | xfer_ld_q = 1; |
173acc7c ZW |
1078 | } |
1079 | ||
1c62979e | 1080 | if (update_cookie) |
a1c03319 | 1081 | fsl_dma_update_completed_cookie(chan); |
1c62979e | 1082 | if (xfer_ld_q) |
a1c03319 | 1083 | fsl_chan_xfer_ld_queue(chan); |
173acc7c | 1084 | if (stat) |
b158471e | 1085 | chan_dbg(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1086 | |
b158471e | 1087 | chan_dbg(chan, "irq: Exit\n"); |
a1c03319 | 1088 | tasklet_schedule(&chan->tasklet); |
173acc7c ZW |
1089 | return IRQ_HANDLED; |
1090 | } | |
1091 | ||
d3f620b2 IS |
1092 | static void dma_do_tasklet(unsigned long data) |
1093 | { | |
a1c03319 IS |
1094 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
1095 | fsl_chan_ld_cleanup(chan); | |
d3f620b2 IS |
1096 | } |
1097 | ||
1098 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1099 | { |
a4f56d4b | 1100 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1101 | struct fsldma_chan *chan; |
1102 | unsigned int handled = 0; | |
1103 | u32 gsr, mask; | |
1104 | int i; | |
173acc7c | 1105 | |
e7a29151 | 1106 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1107 | : in_le32(fdev->regs); |
1108 | mask = 0xff000000; | |
1109 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1110 | |
d3f620b2 IS |
1111 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1112 | chan = fdev->chan[i]; | |
1113 | if (!chan) | |
1114 | continue; | |
1115 | ||
1116 | if (gsr & mask) { | |
1117 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1118 | fsldma_chan_irq(irq, chan); | |
1119 | handled++; | |
1120 | } | |
1121 | ||
1122 | gsr &= ~mask; | |
1123 | mask >>= 8; | |
1124 | } | |
1125 | ||
1126 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1127 | } |
1128 | ||
d3f620b2 | 1129 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1130 | { |
d3f620b2 IS |
1131 | struct fsldma_chan *chan; |
1132 | int i; | |
1133 | ||
1134 | if (fdev->irq != NO_IRQ) { | |
1135 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1136 | free_irq(fdev->irq, fdev); | |
1137 | return; | |
1138 | } | |
1139 | ||
1140 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1141 | chan = fdev->chan[i]; | |
1142 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1143 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1144 | free_irq(chan->irq, chan); |
1145 | } | |
1146 | } | |
1147 | } | |
1148 | ||
1149 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1150 | { | |
1151 | struct fsldma_chan *chan; | |
1152 | int ret; | |
1153 | int i; | |
1154 | ||
1155 | /* if we have a per-controller IRQ, use that */ | |
1156 | if (fdev->irq != NO_IRQ) { | |
1157 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1158 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1159 | "fsldma-controller", fdev); | |
1160 | return ret; | |
1161 | } | |
1162 | ||
1163 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1164 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1165 | chan = fdev->chan[i]; | |
1166 | if (!chan) | |
1167 | continue; | |
1168 | ||
1169 | if (chan->irq == NO_IRQ) { | |
b158471e | 1170 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1171 | ret = -ENODEV; |
1172 | goto out_unwind; | |
1173 | } | |
1174 | ||
b158471e | 1175 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1176 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1177 | "fsldma-chan", chan); | |
1178 | if (ret) { | |
b158471e | 1179 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1180 | goto out_unwind; |
1181 | } | |
1182 | } | |
1183 | ||
1184 | return 0; | |
1185 | ||
1186 | out_unwind: | |
1187 | for (/* none */; i >= 0; i--) { | |
1188 | chan = fdev->chan[i]; | |
1189 | if (!chan) | |
1190 | continue; | |
1191 | ||
1192 | if (chan->irq == NO_IRQ) | |
1193 | continue; | |
1194 | ||
1195 | free_irq(chan->irq, chan); | |
1196 | } | |
1197 | ||
1198 | return ret; | |
173acc7c ZW |
1199 | } |
1200 | ||
a4f56d4b IS |
1201 | /*----------------------------------------------------------------------------*/ |
1202 | /* OpenFirmware Subsystem */ | |
1203 | /*----------------------------------------------------------------------------*/ | |
1204 | ||
1205 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1206 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1207 | { |
a1c03319 | 1208 | struct fsldma_chan *chan; |
4ce0e953 | 1209 | struct resource res; |
173acc7c ZW |
1210 | int err; |
1211 | ||
173acc7c | 1212 | /* alloc channel */ |
a1c03319 IS |
1213 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1214 | if (!chan) { | |
e7a29151 IS |
1215 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1216 | err = -ENOMEM; | |
1217 | goto out_return; | |
1218 | } | |
1219 | ||
1220 | /* ioremap registers for use */ | |
a1c03319 IS |
1221 | chan->regs = of_iomap(node, 0); |
1222 | if (!chan->regs) { | |
e7a29151 IS |
1223 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1224 | err = -ENOMEM; | |
a1c03319 | 1225 | goto out_free_chan; |
173acc7c ZW |
1226 | } |
1227 | ||
4ce0e953 | 1228 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1229 | if (err) { |
e7a29151 IS |
1230 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1231 | goto out_iounmap_regs; | |
173acc7c ZW |
1232 | } |
1233 | ||
a1c03319 | 1234 | chan->feature = feature; |
173acc7c | 1235 | if (!fdev->feature) |
a1c03319 | 1236 | fdev->feature = chan->feature; |
173acc7c | 1237 | |
e7a29151 IS |
1238 | /* |
1239 | * If the DMA device's feature is different than the feature | |
1240 | * of its channels, report the bug | |
173acc7c | 1241 | */ |
a1c03319 | 1242 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1243 | |
a1c03319 IS |
1244 | chan->dev = fdev->dev; |
1245 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1246 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1247 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1248 | err = -EINVAL; |
e7a29151 | 1249 | goto out_iounmap_regs; |
173acc7c | 1250 | } |
173acc7c | 1251 | |
a1c03319 IS |
1252 | fdev->chan[chan->id] = chan; |
1253 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1254 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1255 | |
1256 | /* Initialize the channel */ | |
a1c03319 | 1257 | dma_init(chan); |
173acc7c ZW |
1258 | |
1259 | /* Clear cdar registers */ | |
a1c03319 | 1260 | set_cdar(chan, 0); |
173acc7c | 1261 | |
a1c03319 | 1262 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1263 | case FSL_DMA_IP_85XX: |
a1c03319 | 1264 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1265 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1266 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1267 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1268 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1269 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1270 | } |
1271 | ||
a1c03319 | 1272 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1273 | INIT_LIST_HEAD(&chan->ld_pending); |
1274 | INIT_LIST_HEAD(&chan->ld_running); | |
173acc7c | 1275 | |
a1c03319 | 1276 | chan->common.device = &fdev->common; |
173acc7c | 1277 | |
d3f620b2 | 1278 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1279 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1280 | |
173acc7c | 1281 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1282 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1283 | fdev->common.chancnt++; |
1284 | ||
a1c03319 IS |
1285 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1286 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1287 | |
1288 | return 0; | |
51ee87f2 | 1289 | |
e7a29151 | 1290 | out_iounmap_regs: |
a1c03319 IS |
1291 | iounmap(chan->regs); |
1292 | out_free_chan: | |
1293 | kfree(chan); | |
e7a29151 | 1294 | out_return: |
173acc7c ZW |
1295 | return err; |
1296 | } | |
1297 | ||
a1c03319 | 1298 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1299 | { |
a1c03319 IS |
1300 | irq_dispose_mapping(chan->irq); |
1301 | list_del(&chan->common.device_node); | |
1302 | iounmap(chan->regs); | |
1303 | kfree(chan); | |
173acc7c ZW |
1304 | } |
1305 | ||
2dc11581 | 1306 | static int __devinit fsldma_of_probe(struct platform_device *op, |
173acc7c ZW |
1307 | const struct of_device_id *match) |
1308 | { | |
a4f56d4b | 1309 | struct fsldma_device *fdev; |
77cd62e8 | 1310 | struct device_node *child; |
e7a29151 | 1311 | int err; |
173acc7c | 1312 | |
a4f56d4b | 1313 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1314 | if (!fdev) { |
e7a29151 IS |
1315 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1316 | err = -ENOMEM; | |
1317 | goto out_return; | |
173acc7c | 1318 | } |
e7a29151 IS |
1319 | |
1320 | fdev->dev = &op->dev; | |
173acc7c ZW |
1321 | INIT_LIST_HEAD(&fdev->common.channels); |
1322 | ||
e7a29151 | 1323 | /* ioremap the registers for use */ |
61c7a080 | 1324 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1325 | if (!fdev->regs) { |
1326 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1327 | err = -ENOMEM; | |
1328 | goto out_free_fdev; | |
173acc7c ZW |
1329 | } |
1330 | ||
d3f620b2 | 1331 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1332 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1333 | |
173acc7c ZW |
1334 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1335 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1336 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1337 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1338 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1339 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1340 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1341 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1342 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1343 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1344 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1345 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1346 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1347 | fdev->common.dev = &op->dev; |
173acc7c | 1348 | |
e2c8e425 LY |
1349 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1350 | ||
e7a29151 | 1351 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1352 | |
e7a29151 IS |
1353 | /* |
1354 | * We cannot use of_platform_bus_probe() because there is no | |
1355 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1356 | * channel object. |
1357 | */ | |
61c7a080 | 1358 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1359 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1360 | fsl_dma_chan_probe(fdev, child, |
1361 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1362 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1363 | } |
1364 | ||
1365 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1366 | fsl_dma_chan_probe(fdev, child, |
1367 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1368 | "fsl,elo-dma-channel"); | |
e7a29151 | 1369 | } |
77cd62e8 | 1370 | } |
173acc7c | 1371 | |
d3f620b2 IS |
1372 | /* |
1373 | * Hookup the IRQ handler(s) | |
1374 | * | |
1375 | * If we have a per-controller interrupt, we prefer that to the | |
1376 | * per-channel interrupts to reduce the number of shared interrupt | |
1377 | * handlers on the same IRQ line | |
1378 | */ | |
1379 | err = fsldma_request_irqs(fdev); | |
1380 | if (err) { | |
1381 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1382 | goto out_free_fdev; | |
1383 | } | |
1384 | ||
173acc7c ZW |
1385 | dma_async_device_register(&fdev->common); |
1386 | return 0; | |
1387 | ||
e7a29151 | 1388 | out_free_fdev: |
d3f620b2 | 1389 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1390 | kfree(fdev); |
e7a29151 | 1391 | out_return: |
173acc7c ZW |
1392 | return err; |
1393 | } | |
1394 | ||
2dc11581 | 1395 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1396 | { |
a4f56d4b | 1397 | struct fsldma_device *fdev; |
77cd62e8 TT |
1398 | unsigned int i; |
1399 | ||
e7a29151 | 1400 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1401 | dma_async_device_unregister(&fdev->common); |
1402 | ||
d3f620b2 IS |
1403 | fsldma_free_irqs(fdev); |
1404 | ||
e7a29151 | 1405 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1406 | if (fdev->chan[i]) |
1407 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1408 | } |
77cd62e8 | 1409 | |
e7a29151 IS |
1410 | iounmap(fdev->regs); |
1411 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1412 | kfree(fdev); |
77cd62e8 TT |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
4b1cf1fa | 1417 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1418 | { .compatible = "fsl,eloplus-dma", }, |
1419 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1420 | {} |
1421 | }; | |
1422 | ||
a4f56d4b | 1423 | static struct of_platform_driver fsldma_of_driver = { |
4018294b GL |
1424 | .driver = { |
1425 | .name = "fsl-elo-dma", | |
1426 | .owner = THIS_MODULE, | |
1427 | .of_match_table = fsldma_of_ids, | |
1428 | }, | |
1429 | .probe = fsldma_of_probe, | |
1430 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1431 | }; |
1432 | ||
a4f56d4b IS |
1433 | /*----------------------------------------------------------------------------*/ |
1434 | /* Module Init / Exit */ | |
1435 | /*----------------------------------------------------------------------------*/ | |
1436 | ||
1437 | static __init int fsldma_init(void) | |
173acc7c | 1438 | { |
77cd62e8 TT |
1439 | int ret; |
1440 | ||
1441 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1442 | ||
a4f56d4b | 1443 | ret = of_register_platform_driver(&fsldma_of_driver); |
77cd62e8 TT |
1444 | if (ret) |
1445 | pr_err("fsldma: failed to register platform driver\n"); | |
1446 | ||
1447 | return ret; | |
1448 | } | |
1449 | ||
a4f56d4b | 1450 | static void __exit fsldma_exit(void) |
77cd62e8 | 1451 | { |
a4f56d4b | 1452 | of_unregister_platform_driver(&fsldma_of_driver); |
173acc7c ZW |
1453 | } |
1454 | ||
a4f56d4b IS |
1455 | subsys_initcall(fsldma_init); |
1456 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1457 | |
1458 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1459 | MODULE_LICENSE("GPL"); |