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Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
d2ebfb33 | 38 | #include "dmaengine.h" |
173acc7c ZW |
39 | #include "fsldma.h" |
40 | ||
b158471e IS |
41 | #define chan_dbg(chan, fmt, arg...) \ |
42 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
43 | #define chan_err(chan, fmt, arg...) \ | |
44 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 45 | |
b158471e | 46 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 47 | |
e8bd84df IS |
48 | /* |
49 | * Register Helpers | |
50 | */ | |
173acc7c | 51 | |
a1c03319 | 52 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 53 | { |
a1c03319 | 54 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
55 | } |
56 | ||
a1c03319 | 57 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 58 | { |
a1c03319 | 59 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
60 | } |
61 | ||
e8bd84df IS |
62 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
63 | { | |
64 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
65 | } | |
66 | ||
67 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
68 | { | |
69 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
70 | } | |
71 | ||
e8bd84df IS |
72 | static u32 get_bcr(struct fsldma_chan *chan) |
73 | { | |
74 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
75 | } | |
76 | ||
77 | /* | |
78 | * Descriptor Helpers | |
79 | */ | |
80 | ||
a1c03319 | 81 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
82 | struct fsl_dma_ld_hw *hw, u32 count) |
83 | { | |
a1c03319 | 84 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
85 | } |
86 | ||
9c4d1e7b IS |
87 | static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
88 | { | |
89 | return DMA_TO_CPU(chan, desc->hw.count, 32); | |
90 | } | |
91 | ||
a1c03319 | 92 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 93 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
94 | { |
95 | u64 snoop_bits; | |
96 | ||
a1c03319 | 97 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 98 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 99 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
100 | } |
101 | ||
9c4d1e7b IS |
102 | static dma_addr_t get_desc_src(struct fsldma_chan *chan, |
103 | struct fsl_desc_sw *desc) | |
104 | { | |
105 | u64 snoop_bits; | |
106 | ||
107 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
108 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; | |
109 | return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits; | |
110 | } | |
111 | ||
a1c03319 | 112 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 113 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
114 | { |
115 | u64 snoop_bits; | |
116 | ||
a1c03319 | 117 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 118 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 119 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
120 | } |
121 | ||
9c4d1e7b IS |
122 | static dma_addr_t get_desc_dst(struct fsldma_chan *chan, |
123 | struct fsl_desc_sw *desc) | |
124 | { | |
125 | u64 snoop_bits; | |
126 | ||
127 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
128 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; | |
129 | return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits; | |
130 | } | |
131 | ||
a1c03319 | 132 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 133 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
134 | { |
135 | u64 snoop_bits; | |
136 | ||
a1c03319 | 137 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 138 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 139 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
140 | } |
141 | ||
31f4306c | 142 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 143 | { |
e8bd84df | 144 | u64 snoop_bits; |
173acc7c | 145 | |
e8bd84df IS |
146 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
147 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 148 | |
e8bd84df IS |
149 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
150 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
151 | | snoop_bits, 64); | |
173acc7c ZW |
152 | } |
153 | ||
e8bd84df IS |
154 | /* |
155 | * DMA Engine Hardware Control Helpers | |
156 | */ | |
157 | ||
158 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 159 | { |
e8bd84df IS |
160 | /* Reset the channel */ |
161 | DMA_OUT(chan, &chan->regs->mr, 0, 32); | |
162 | ||
163 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
164 | case FSL_DMA_IP_85XX: | |
165 | /* Set the channel to below modes: | |
166 | * EIE - Error interrupt enable | |
e8bd84df IS |
167 | * EOLNIE - End of links interrupt enable |
168 | * BWC - Bandwidth sharing among channels | |
169 | */ | |
170 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC | |
f04cd407 | 171 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); |
e8bd84df IS |
172 | break; |
173 | case FSL_DMA_IP_83XX: | |
174 | /* Set the channel to below modes: | |
175 | * EOTIE - End-of-transfer interrupt enable | |
176 | * PRC_RM - PCI read multiple | |
177 | */ | |
178 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | |
179 | | FSL_DMA_MR_PRC_RM, 32); | |
180 | break; | |
181 | } | |
f79abb62 ZW |
182 | } |
183 | ||
a1c03319 | 184 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 185 | { |
a1c03319 | 186 | u32 sr = get_sr(chan); |
173acc7c ZW |
187 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
188 | } | |
189 | ||
f04cd407 IS |
190 | /* |
191 | * Start the DMA controller | |
192 | * | |
193 | * Preconditions: | |
194 | * - the CDAR register must point to the start descriptor | |
195 | * - the MRn[CS] bit must be cleared | |
196 | */ | |
a1c03319 | 197 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 198 | { |
272ca655 IS |
199 | u32 mode; |
200 | ||
a1c03319 | 201 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 202 | |
f04cd407 IS |
203 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
204 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
205 | mode |= FSL_DMA_MR_EMP_EN; | |
206 | } else { | |
207 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 208 | } |
173acc7c | 209 | |
f04cd407 | 210 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 211 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
212 | } else { |
213 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 214 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 215 | } |
173acc7c | 216 | |
a1c03319 | 217 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
218 | } |
219 | ||
a1c03319 | 220 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 221 | { |
272ca655 | 222 | u32 mode; |
900325a6 DW |
223 | int i; |
224 | ||
a00ae34a | 225 | /* read the mode register */ |
a1c03319 | 226 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 227 | |
a00ae34a IS |
228 | /* |
229 | * The 85xx controller supports channel abort, which will stop | |
230 | * the current transfer. On 83xx, this bit is the transfer error | |
231 | * mask bit, which should not be changed. | |
232 | */ | |
233 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
234 | mode |= FSL_DMA_MR_CA; | |
235 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
236 | ||
237 | mode &= ~FSL_DMA_MR_CA; | |
238 | } | |
239 | ||
240 | /* stop the DMA controller */ | |
241 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
a1c03319 | 242 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 243 | |
a00ae34a | 244 | /* wait for the DMA controller to become idle */ |
900325a6 | 245 | for (i = 0; i < 100; i++) { |
a1c03319 | 246 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
247 | return; |
248 | ||
173acc7c | 249 | udelay(10); |
900325a6 | 250 | } |
272ca655 | 251 | |
9c3a50b7 | 252 | if (!dma_is_idle(chan)) |
b158471e | 253 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
254 | } |
255 | ||
173acc7c ZW |
256 | /** |
257 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 258 | * @chan : Freescale DMA channel |
173acc7c ZW |
259 | * @size : Address loop size, 0 for disable loop |
260 | * | |
261 | * The set source address hold transfer size. The source | |
262 | * address hold or loop transfer size is when the DMA transfer | |
263 | * data from source address (SA), if the loop size is 4, the DMA will | |
264 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
265 | * SA + 1 ... and so on. | |
266 | */ | |
a1c03319 | 267 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 268 | { |
272ca655 IS |
269 | u32 mode; |
270 | ||
a1c03319 | 271 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 272 | |
173acc7c ZW |
273 | switch (size) { |
274 | case 0: | |
272ca655 | 275 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
276 | break; |
277 | case 1: | |
278 | case 2: | |
279 | case 4: | |
280 | case 8: | |
272ca655 | 281 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
282 | break; |
283 | } | |
272ca655 | 284 | |
a1c03319 | 285 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
286 | } |
287 | ||
288 | /** | |
738f5f7e | 289 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 290 | * @chan : Freescale DMA channel |
173acc7c ZW |
291 | * @size : Address loop size, 0 for disable loop |
292 | * | |
293 | * The set destination address hold transfer size. The destination | |
294 | * address hold or loop transfer size is when the DMA transfer | |
295 | * data to destination address (TA), if the loop size is 4, the DMA will | |
296 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
297 | * TA + 1 ... and so on. | |
298 | */ | |
a1c03319 | 299 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 300 | { |
272ca655 IS |
301 | u32 mode; |
302 | ||
a1c03319 | 303 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 304 | |
173acc7c ZW |
305 | switch (size) { |
306 | case 0: | |
272ca655 | 307 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
308 | break; |
309 | case 1: | |
310 | case 2: | |
311 | case 4: | |
312 | case 8: | |
272ca655 | 313 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
314 | break; |
315 | } | |
272ca655 | 316 | |
a1c03319 | 317 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
318 | } |
319 | ||
320 | /** | |
e6c7ecb6 | 321 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 322 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
323 | * @size : Number of bytes to transfer in a single request |
324 | * | |
325 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
326 | * The DMA request count is how many bytes are allowed to transfer before | |
327 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
328 | * operation. | |
173acc7c | 329 | * |
e6c7ecb6 | 330 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 331 | */ |
a1c03319 | 332 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 333 | { |
272ca655 IS |
334 | u32 mode; |
335 | ||
e6c7ecb6 | 336 | BUG_ON(size > 1024); |
272ca655 | 337 | |
a1c03319 | 338 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
339 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
340 | ||
a1c03319 | 341 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 342 | } |
173acc7c | 343 | |
e6c7ecb6 IS |
344 | /** |
345 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 346 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
347 | * @enable : 0 is disabled, 1 is enabled. |
348 | * | |
349 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
350 | * The DMA Request Count feature should be used in addition to this feature | |
351 | * to set the number of bytes to transfer before pausing the channel. | |
352 | */ | |
a1c03319 | 353 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
354 | { |
355 | if (enable) | |
a1c03319 | 356 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 357 | else |
a1c03319 | 358 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
359 | } |
360 | ||
361 | /** | |
362 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 363 | * @chan : Freescale DMA channel |
173acc7c ZW |
364 | * @enable : 0 is disabled, 1 is enabled. |
365 | * | |
366 | * If enable the external start, the channel can be started by an | |
367 | * external DMA start pin. So the dma_start() does not start the | |
368 | * transfer immediately. The DMA channel will wait for the | |
369 | * control pin asserted. | |
370 | */ | |
a1c03319 | 371 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
372 | { |
373 | if (enable) | |
a1c03319 | 374 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 375 | else |
a1c03319 | 376 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
377 | } |
378 | ||
31f4306c | 379 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
380 | { |
381 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
382 | ||
383 | if (list_empty(&chan->ld_pending)) | |
384 | goto out_splice; | |
385 | ||
386 | /* | |
387 | * Add the hardware descriptor to the chain of hardware descriptors | |
388 | * that already exists in memory. | |
389 | * | |
390 | * This will un-set the EOL bit of the existing transaction, and the | |
391 | * last link in this transaction will become the EOL descriptor. | |
392 | */ | |
393 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
394 | ||
395 | /* | |
396 | * Add the software descriptor and all children to the list | |
397 | * of pending transactions | |
398 | */ | |
399 | out_splice: | |
400 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
401 | } | |
402 | ||
173acc7c ZW |
403 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
404 | { | |
a1c03319 | 405 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
406 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
407 | struct fsl_desc_sw *child; | |
173acc7c ZW |
408 | unsigned long flags; |
409 | dma_cookie_t cookie; | |
410 | ||
a1c03319 | 411 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 412 | |
9c3a50b7 IS |
413 | /* |
414 | * assign cookies to all of the software descriptors | |
415 | * that make up this transaction | |
416 | */ | |
eda34234 | 417 | list_for_each_entry(child, &desc->tx_list, node) { |
884485e1 | 418 | cookie = dma_cookie_assign(&child->async_tx); |
bcfb7465 IS |
419 | } |
420 | ||
9c3a50b7 | 421 | /* put this transaction onto the tail of the pending queue */ |
a1c03319 | 422 | append_ld_queue(chan, desc); |
173acc7c | 423 | |
a1c03319 | 424 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
425 | |
426 | return cookie; | |
427 | } | |
428 | ||
429 | /** | |
430 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 431 | * @chan : Freescale DMA channel |
173acc7c ZW |
432 | * |
433 | * Return - The descriptor allocated. NULL for failed. | |
434 | */ | |
31f4306c | 435 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 436 | { |
9c3a50b7 | 437 | struct fsl_desc_sw *desc; |
173acc7c | 438 | dma_addr_t pdesc; |
9c3a50b7 IS |
439 | |
440 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
441 | if (!desc) { | |
b158471e | 442 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 443 | return NULL; |
173acc7c ZW |
444 | } |
445 | ||
9c3a50b7 IS |
446 | memset(desc, 0, sizeof(*desc)); |
447 | INIT_LIST_HEAD(&desc->tx_list); | |
448 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
449 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
450 | desc->async_tx.phys = pdesc; | |
451 | ||
0ab09c36 IS |
452 | #ifdef FSL_DMA_LD_DEBUG |
453 | chan_dbg(chan, "LD %p allocated\n", desc); | |
454 | #endif | |
455 | ||
9c3a50b7 | 456 | return desc; |
173acc7c ZW |
457 | } |
458 | ||
173acc7c ZW |
459 | /** |
460 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 461 | * @chan : Freescale DMA channel |
173acc7c ZW |
462 | * |
463 | * This function will create a dma pool for descriptor allocation. | |
464 | * | |
465 | * Return - The number of descriptors allocated. | |
466 | */ | |
a1c03319 | 467 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 468 | { |
a1c03319 | 469 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
470 | |
471 | /* Has this channel already been allocated? */ | |
a1c03319 | 472 | if (chan->desc_pool) |
77cd62e8 | 473 | return 1; |
173acc7c | 474 | |
9c3a50b7 IS |
475 | /* |
476 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
477 | * for meeting FSL DMA specification requirement. |
478 | */ | |
b158471e | 479 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
480 | sizeof(struct fsl_desc_sw), |
481 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 482 | if (!chan->desc_pool) { |
b158471e | 483 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 484 | return -ENOMEM; |
173acc7c ZW |
485 | } |
486 | ||
9c3a50b7 | 487 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
488 | return 1; |
489 | } | |
490 | ||
9c3a50b7 IS |
491 | /** |
492 | * fsldma_free_desc_list - Free all descriptors in a queue | |
493 | * @chan: Freescae DMA channel | |
494 | * @list: the list to free | |
495 | * | |
496 | * LOCKING: must hold chan->desc_lock | |
497 | */ | |
498 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
499 | struct list_head *list) | |
500 | { | |
501 | struct fsl_desc_sw *desc, *_desc; | |
502 | ||
503 | list_for_each_entry_safe(desc, _desc, list, node) { | |
504 | list_del(&desc->node); | |
0ab09c36 IS |
505 | #ifdef FSL_DMA_LD_DEBUG |
506 | chan_dbg(chan, "LD %p free\n", desc); | |
507 | #endif | |
9c3a50b7 IS |
508 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
509 | } | |
510 | } | |
511 | ||
512 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
513 | struct list_head *list) | |
514 | { | |
515 | struct fsl_desc_sw *desc, *_desc; | |
516 | ||
517 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
518 | list_del(&desc->node); | |
0ab09c36 IS |
519 | #ifdef FSL_DMA_LD_DEBUG |
520 | chan_dbg(chan, "LD %p free\n", desc); | |
521 | #endif | |
9c3a50b7 IS |
522 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
523 | } | |
524 | } | |
525 | ||
173acc7c ZW |
526 | /** |
527 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 528 | * @chan : Freescale DMA channel |
173acc7c | 529 | */ |
a1c03319 | 530 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 531 | { |
a1c03319 | 532 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
533 | unsigned long flags; |
534 | ||
b158471e | 535 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 536 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
537 | fsldma_free_desc_list(chan, &chan->ld_pending); |
538 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 539 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 540 | |
9c3a50b7 | 541 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 542 | chan->desc_pool = NULL; |
173acc7c ZW |
543 | } |
544 | ||
2187c269 | 545 | static struct dma_async_tx_descriptor * |
a1c03319 | 546 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 547 | { |
a1c03319 | 548 | struct fsldma_chan *chan; |
2187c269 ZW |
549 | struct fsl_desc_sw *new; |
550 | ||
a1c03319 | 551 | if (!dchan) |
2187c269 ZW |
552 | return NULL; |
553 | ||
a1c03319 | 554 | chan = to_fsl_chan(dchan); |
2187c269 | 555 | |
a1c03319 | 556 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 557 | if (!new) { |
b158471e | 558 | chan_err(chan, "%s\n", msg_ld_oom); |
2187c269 ZW |
559 | return NULL; |
560 | } | |
561 | ||
562 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 563 | new->async_tx.flags = flags; |
2187c269 | 564 | |
f79abb62 | 565 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 566 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 567 | |
31f4306c | 568 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 569 | set_ld_eol(chan, new); |
2187c269 ZW |
570 | |
571 | return &new->async_tx; | |
572 | } | |
573 | ||
31f4306c IS |
574 | static struct dma_async_tx_descriptor * |
575 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
576 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
577 | size_t len, unsigned long flags) |
578 | { | |
a1c03319 | 579 | struct fsldma_chan *chan; |
173acc7c ZW |
580 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
581 | size_t copy; | |
173acc7c | 582 | |
a1c03319 | 583 | if (!dchan) |
173acc7c ZW |
584 | return NULL; |
585 | ||
586 | if (!len) | |
587 | return NULL; | |
588 | ||
a1c03319 | 589 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
590 | |
591 | do { | |
592 | ||
593 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 594 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 595 | if (!new) { |
b158471e | 596 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 597 | goto fail; |
173acc7c | 598 | } |
173acc7c | 599 | |
56822843 | 600 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 601 | |
a1c03319 IS |
602 | set_desc_cnt(chan, &new->hw, copy); |
603 | set_desc_src(chan, &new->hw, dma_src); | |
604 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
605 | |
606 | if (!first) | |
607 | first = new; | |
608 | else | |
a1c03319 | 609 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
610 | |
611 | new->async_tx.cookie = 0; | |
636bdeaa | 612 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
613 | |
614 | prev = new; | |
615 | len -= copy; | |
616 | dma_src += copy; | |
738f5f7e | 617 | dma_dst += copy; |
173acc7c ZW |
618 | |
619 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 620 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
621 | } while (len); |
622 | ||
636bdeaa | 623 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
624 | new->async_tx.cookie = -EBUSY; |
625 | ||
31f4306c | 626 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 627 | set_ld_eol(chan, new); |
173acc7c | 628 | |
2e077f8e IS |
629 | return &first->async_tx; |
630 | ||
631 | fail: | |
632 | if (!first) | |
633 | return NULL; | |
634 | ||
9c3a50b7 | 635 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 636 | return NULL; |
173acc7c ZW |
637 | } |
638 | ||
c1433041 IS |
639 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
640 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
641 | struct scatterlist *src_sg, unsigned int src_nents, | |
642 | unsigned long flags) | |
643 | { | |
644 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
645 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
646 | size_t dst_avail, src_avail; | |
647 | dma_addr_t dst, src; | |
648 | size_t len; | |
649 | ||
650 | /* basic sanity checks */ | |
651 | if (dst_nents == 0 || src_nents == 0) | |
652 | return NULL; | |
653 | ||
654 | if (dst_sg == NULL || src_sg == NULL) | |
655 | return NULL; | |
656 | ||
657 | /* | |
658 | * TODO: should we check that both scatterlists have the same | |
659 | * TODO: number of bytes in total? Is that really an error? | |
660 | */ | |
661 | ||
662 | /* get prepared for the loop */ | |
663 | dst_avail = sg_dma_len(dst_sg); | |
664 | src_avail = sg_dma_len(src_sg); | |
665 | ||
666 | /* run until we are out of scatterlist entries */ | |
667 | while (true) { | |
668 | ||
669 | /* create the largest transaction possible */ | |
670 | len = min_t(size_t, src_avail, dst_avail); | |
671 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
672 | if (len == 0) | |
673 | goto fetch; | |
674 | ||
675 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
676 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
677 | ||
678 | /* allocate and populate the descriptor */ | |
679 | new = fsl_dma_alloc_descriptor(chan); | |
680 | if (!new) { | |
b158471e | 681 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
682 | goto fail; |
683 | } | |
c1433041 IS |
684 | |
685 | set_desc_cnt(chan, &new->hw, len); | |
686 | set_desc_src(chan, &new->hw, src); | |
687 | set_desc_dst(chan, &new->hw, dst); | |
688 | ||
689 | if (!first) | |
690 | first = new; | |
691 | else | |
692 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
693 | ||
694 | new->async_tx.cookie = 0; | |
695 | async_tx_ack(&new->async_tx); | |
696 | prev = new; | |
697 | ||
698 | /* Insert the link descriptor to the LD ring */ | |
699 | list_add_tail(&new->node, &first->tx_list); | |
700 | ||
701 | /* update metadata */ | |
702 | dst_avail -= len; | |
703 | src_avail -= len; | |
704 | ||
705 | fetch: | |
706 | /* fetch the next dst scatterlist entry */ | |
707 | if (dst_avail == 0) { | |
708 | ||
709 | /* no more entries: we're done */ | |
710 | if (dst_nents == 0) | |
711 | break; | |
712 | ||
713 | /* fetch the next entry: if there are no more: done */ | |
714 | dst_sg = sg_next(dst_sg); | |
715 | if (dst_sg == NULL) | |
716 | break; | |
717 | ||
718 | dst_nents--; | |
719 | dst_avail = sg_dma_len(dst_sg); | |
720 | } | |
721 | ||
722 | /* fetch the next src scatterlist entry */ | |
723 | if (src_avail == 0) { | |
724 | ||
725 | /* no more entries: we're done */ | |
726 | if (src_nents == 0) | |
727 | break; | |
728 | ||
729 | /* fetch the next entry: if there are no more: done */ | |
730 | src_sg = sg_next(src_sg); | |
731 | if (src_sg == NULL) | |
732 | break; | |
733 | ||
734 | src_nents--; | |
735 | src_avail = sg_dma_len(src_sg); | |
736 | } | |
737 | } | |
738 | ||
739 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
740 | new->async_tx.cookie = -EBUSY; | |
741 | ||
742 | /* Set End-of-link to the last link descriptor of new list */ | |
743 | set_ld_eol(chan, new); | |
744 | ||
745 | return &first->async_tx; | |
746 | ||
747 | fail: | |
748 | if (!first) | |
749 | return NULL; | |
750 | ||
751 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
752 | return NULL; | |
753 | } | |
754 | ||
bbea0b6e IS |
755 | /** |
756 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
757 | * @chan: DMA channel | |
758 | * @sgl: scatterlist to transfer to/from | |
759 | * @sg_len: number of entries in @scatterlist | |
760 | * @direction: DMA direction | |
761 | * @flags: DMAEngine flags | |
762 | * | |
763 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
764 | * DMA_SLAVE API, this gets the device-specific information from the | |
765 | * chan->private variable. | |
766 | */ | |
767 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 768 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
db8196df | 769 | enum dma_transfer_direction direction, unsigned long flags) |
bbea0b6e | 770 | { |
bbea0b6e | 771 | /* |
968f19ae | 772 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 773 | * |
968f19ae IS |
774 | * However, we need to provide the function pointer to allow the |
775 | * device_control() method to work. | |
bbea0b6e | 776 | */ |
bbea0b6e IS |
777 | return NULL; |
778 | } | |
779 | ||
c3635c78 | 780 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 781 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 782 | { |
968f19ae | 783 | struct dma_slave_config *config; |
a1c03319 | 784 | struct fsldma_chan *chan; |
bbea0b6e | 785 | unsigned long flags; |
968f19ae | 786 | int size; |
c3635c78 | 787 | |
a1c03319 | 788 | if (!dchan) |
c3635c78 | 789 | return -EINVAL; |
bbea0b6e | 790 | |
a1c03319 | 791 | chan = to_fsl_chan(dchan); |
bbea0b6e | 792 | |
968f19ae IS |
793 | switch (cmd) { |
794 | case DMA_TERMINATE_ALL: | |
f04cd407 IS |
795 | spin_lock_irqsave(&chan->desc_lock, flags); |
796 | ||
968f19ae IS |
797 | /* Halt the DMA engine */ |
798 | dma_halt(chan); | |
bbea0b6e | 799 | |
968f19ae IS |
800 | /* Remove and free all of the descriptors in the LD queue */ |
801 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
802 | fsldma_free_desc_list(chan, &chan->ld_running); | |
f04cd407 | 803 | chan->idle = true; |
bbea0b6e | 804 | |
968f19ae IS |
805 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
806 | return 0; | |
807 | ||
808 | case DMA_SLAVE_CONFIG: | |
809 | config = (struct dma_slave_config *)arg; | |
810 | ||
811 | /* make sure the channel supports setting burst size */ | |
812 | if (!chan->set_request_count) | |
813 | return -ENXIO; | |
814 | ||
815 | /* we set the controller burst size depending on direction */ | |
db8196df | 816 | if (config->direction == DMA_MEM_TO_DEV) |
968f19ae IS |
817 | size = config->dst_addr_width * config->dst_maxburst; |
818 | else | |
819 | size = config->src_addr_width * config->src_maxburst; | |
820 | ||
821 | chan->set_request_count(chan, size); | |
822 | return 0; | |
823 | ||
824 | case FSLDMA_EXTERNAL_START: | |
825 | ||
826 | /* make sure the channel supports external start */ | |
827 | if (!chan->toggle_ext_start) | |
828 | return -ENXIO; | |
829 | ||
830 | chan->toggle_ext_start(chan, arg); | |
831 | return 0; | |
832 | ||
833 | default: | |
834 | return -ENXIO; | |
835 | } | |
c3635c78 LW |
836 | |
837 | return 0; | |
bbea0b6e IS |
838 | } |
839 | ||
173acc7c | 840 | /** |
9c4d1e7b | 841 | * fsldma_cleanup_descriptor - cleanup and free a single link descriptor |
9c3a50b7 | 842 | * @chan: Freescale DMA channel |
9c4d1e7b | 843 | * @desc: descriptor to cleanup and free |
173acc7c | 844 | * |
9c4d1e7b IS |
845 | * This function is used on a descriptor which has been executed by the DMA |
846 | * controller. It will run any callbacks, submit any dependencies, and then | |
847 | * free the descriptor. | |
173acc7c | 848 | */ |
9c4d1e7b IS |
849 | static void fsldma_cleanup_descriptor(struct fsldma_chan *chan, |
850 | struct fsl_desc_sw *desc) | |
173acc7c | 851 | { |
9c4d1e7b IS |
852 | struct dma_async_tx_descriptor *txd = &desc->async_tx; |
853 | struct device *dev = chan->common.device->dev; | |
854 | dma_addr_t src = get_desc_src(chan, desc); | |
855 | dma_addr_t dst = get_desc_dst(chan, desc); | |
856 | u32 len = get_desc_cnt(chan, desc); | |
857 | ||
858 | /* Run the link descriptor callback function */ | |
859 | if (txd->callback) { | |
860 | #ifdef FSL_DMA_LD_DEBUG | |
861 | chan_dbg(chan, "LD %p callback\n", desc); | |
862 | #endif | |
863 | txd->callback(txd->callback_param); | |
864 | } | |
173acc7c | 865 | |
9c4d1e7b IS |
866 | /* Run any dependencies */ |
867 | dma_run_dependencies(txd); | |
173acc7c | 868 | |
9c4d1e7b IS |
869 | /* Unmap the dst buffer, if requested */ |
870 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
871 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
872 | dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE); | |
873 | else | |
874 | dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE); | |
875 | } | |
9c3a50b7 | 876 | |
9c4d1e7b IS |
877 | /* Unmap the src buffer, if requested */ |
878 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
879 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
880 | dma_unmap_single(dev, src, len, DMA_TO_DEVICE); | |
881 | else | |
882 | dma_unmap_page(dev, src, len, DMA_TO_DEVICE); | |
173acc7c | 883 | } |
9c3a50b7 | 884 | |
9c4d1e7b IS |
885 | #ifdef FSL_DMA_LD_DEBUG |
886 | chan_dbg(chan, "LD %p free\n", desc); | |
887 | #endif | |
888 | dma_pool_free(chan->desc_pool, desc, txd->phys); | |
173acc7c ZW |
889 | } |
890 | ||
891 | /** | |
9c3a50b7 | 892 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 893 | * @chan : Freescale DMA channel |
9c3a50b7 | 894 | * |
f04cd407 | 895 | * HARDWARE STATE: idle |
dc8d4091 | 896 | * LOCKING: must hold chan->desc_lock |
173acc7c | 897 | */ |
a1c03319 | 898 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 899 | { |
9c3a50b7 | 900 | struct fsl_desc_sw *desc; |
138ef018 | 901 | |
9c3a50b7 IS |
902 | /* |
903 | * If the list of pending descriptors is empty, then we | |
904 | * don't need to do any work at all | |
905 | */ | |
906 | if (list_empty(&chan->ld_pending)) { | |
b158471e | 907 | chan_dbg(chan, "no pending LDs\n"); |
dc8d4091 | 908 | return; |
9c3a50b7 | 909 | } |
173acc7c | 910 | |
9c3a50b7 | 911 | /* |
f04cd407 IS |
912 | * The DMA controller is not idle, which means that the interrupt |
913 | * handler will start any queued transactions when it runs after | |
914 | * this transaction finishes | |
9c3a50b7 | 915 | */ |
f04cd407 | 916 | if (!chan->idle) { |
b158471e | 917 | chan_dbg(chan, "DMA controller still busy\n"); |
dc8d4091 | 918 | return; |
9c3a50b7 IS |
919 | } |
920 | ||
9c3a50b7 IS |
921 | /* |
922 | * If there are some link descriptors which have not been | |
923 | * transferred, we need to start the controller | |
173acc7c | 924 | */ |
173acc7c | 925 | |
9c3a50b7 IS |
926 | /* |
927 | * Move all elements from the queue of pending transactions | |
928 | * onto the list of running transactions | |
929 | */ | |
f04cd407 | 930 | chan_dbg(chan, "idle, starting controller\n"); |
9c3a50b7 IS |
931 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); |
932 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
933 | ||
f04cd407 IS |
934 | /* |
935 | * The 85xx DMA controller doesn't clear the channel start bit | |
936 | * automatically at the end of a transfer. Therefore we must clear | |
937 | * it in software before starting the transfer. | |
938 | */ | |
939 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
940 | u32 mode; | |
941 | ||
942 | mode = DMA_IN(chan, &chan->regs->mr, 32); | |
943 | mode &= ~FSL_DMA_MR_CS; | |
944 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
945 | } | |
946 | ||
9c3a50b7 IS |
947 | /* |
948 | * Program the descriptor's address into the DMA controller, | |
949 | * then start the DMA transaction | |
950 | */ | |
951 | set_cdar(chan, desc->async_tx.phys); | |
f04cd407 | 952 | get_cdar(chan); |
138ef018 | 953 | |
9c3a50b7 | 954 | dma_start(chan); |
f04cd407 | 955 | chan->idle = false; |
173acc7c ZW |
956 | } |
957 | ||
958 | /** | |
959 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 960 | * @chan : Freescale DMA channel |
173acc7c | 961 | */ |
a1c03319 | 962 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 963 | { |
a1c03319 | 964 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 IS |
965 | unsigned long flags; |
966 | ||
967 | spin_lock_irqsave(&chan->desc_lock, flags); | |
a1c03319 | 968 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 | 969 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
970 | } |
971 | ||
173acc7c | 972 | /** |
07934481 | 973 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 974 | * @chan : Freescale DMA channel |
173acc7c | 975 | */ |
07934481 | 976 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 977 | dma_cookie_t cookie, |
07934481 | 978 | struct dma_tx_state *txstate) |
173acc7c | 979 | { |
a1c03319 | 980 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c | 981 | dma_cookie_t last_complete; |
f04cd407 IS |
982 | dma_cookie_t last_used; |
983 | unsigned long flags; | |
173acc7c | 984 | |
f04cd407 | 985 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 986 | |
4d4e58de | 987 | last_complete = dchan->completed_cookie; |
f04cd407 | 988 | last_used = dchan->cookie; |
173acc7c | 989 | |
f04cd407 | 990 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c | 991 | |
f04cd407 | 992 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
993 | return dma_async_is_complete(cookie, last_complete, last_used); |
994 | } | |
995 | ||
d3f620b2 IS |
996 | /*----------------------------------------------------------------------------*/ |
997 | /* Interrupt Handling */ | |
998 | /*----------------------------------------------------------------------------*/ | |
999 | ||
e7a29151 | 1000 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 1001 | { |
a1c03319 | 1002 | struct fsldma_chan *chan = data; |
a1c03319 | 1003 | u32 stat; |
173acc7c | 1004 | |
9c3a50b7 | 1005 | /* save and clear the status register */ |
a1c03319 | 1006 | stat = get_sr(chan); |
9c3a50b7 | 1007 | set_sr(chan, stat); |
b158471e | 1008 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 1009 | |
f04cd407 | 1010 | /* check that this was really our device */ |
173acc7c ZW |
1011 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
1012 | if (!stat) | |
1013 | return IRQ_NONE; | |
1014 | ||
1015 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 1016 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 1017 | |
9c3a50b7 IS |
1018 | /* |
1019 | * Programming Error | |
f79abb62 ZW |
1020 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1021 | * triger a PE interrupt. | |
1022 | */ | |
1023 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 1024 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 1025 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
1026 | if (get_bcr(chan) != 0) |
1027 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
1028 | } |
1029 | ||
9c3a50b7 IS |
1030 | /* |
1031 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1032 | * and start the next transfer if it exist. |
1033 | */ | |
1034 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 1035 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 1036 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
1037 | } |
1038 | ||
9c3a50b7 IS |
1039 | /* |
1040 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1041 | * we should clear the Channel Start bit for |
1042 | * prepare next transfer. | |
1043 | */ | |
1c62979e | 1044 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 1045 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 1046 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
1047 | } |
1048 | ||
f04cd407 IS |
1049 | /* check that the DMA controller is really idle */ |
1050 | if (!dma_is_idle(chan)) | |
1051 | chan_err(chan, "irq: controller not idle!\n"); | |
1052 | ||
1053 | /* check that we handled all of the bits */ | |
173acc7c | 1054 | if (stat) |
f04cd407 | 1055 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1056 | |
f04cd407 IS |
1057 | /* |
1058 | * Schedule the tasklet to handle all cleanup of the current | |
1059 | * transaction. It will start a new transaction if there is | |
1060 | * one pending. | |
1061 | */ | |
a1c03319 | 1062 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 1063 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
1064 | return IRQ_HANDLED; |
1065 | } | |
1066 | ||
d3f620b2 IS |
1067 | static void dma_do_tasklet(unsigned long data) |
1068 | { | |
a1c03319 | 1069 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
dc8d4091 IS |
1070 | struct fsl_desc_sw *desc, *_desc; |
1071 | LIST_HEAD(ld_cleanup); | |
f04cd407 IS |
1072 | unsigned long flags; |
1073 | ||
1074 | chan_dbg(chan, "tasklet entry\n"); | |
1075 | ||
f04cd407 | 1076 | spin_lock_irqsave(&chan->desc_lock, flags); |
dc8d4091 IS |
1077 | |
1078 | /* update the cookie if we have some descriptors to cleanup */ | |
1079 | if (!list_empty(&chan->ld_running)) { | |
1080 | dma_cookie_t cookie; | |
1081 | ||
1082 | desc = to_fsl_desc(chan->ld_running.prev); | |
1083 | cookie = desc->async_tx.cookie; | |
1084 | ||
4d4e58de | 1085 | chan->common.completed_cookie = cookie; |
dc8d4091 IS |
1086 | chan_dbg(chan, "completed_cookie=%d\n", cookie); |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * move the descriptors to a temporary list so we can drop the lock | |
1091 | * during the entire cleanup operation | |
1092 | */ | |
1093 | list_splice_tail_init(&chan->ld_running, &ld_cleanup); | |
1094 | ||
1095 | /* the hardware is now idle and ready for more */ | |
f04cd407 | 1096 | chan->idle = true; |
f04cd407 | 1097 | |
dc8d4091 IS |
1098 | /* |
1099 | * Start any pending transactions automatically | |
1100 | * | |
1101 | * In the ideal case, we keep the DMA controller busy while we go | |
1102 | * ahead and free the descriptors below. | |
1103 | */ | |
f04cd407 | 1104 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 IS |
1105 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
1106 | ||
1107 | /* Run the callback for each descriptor, in order */ | |
1108 | list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) { | |
1109 | ||
1110 | /* Remove from the list of transactions */ | |
1111 | list_del(&desc->node); | |
1112 | ||
1113 | /* Run all cleanup for this descriptor */ | |
1114 | fsldma_cleanup_descriptor(chan, desc); | |
1115 | } | |
1116 | ||
f04cd407 | 1117 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1118 | } |
1119 | ||
1120 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1121 | { |
a4f56d4b | 1122 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1123 | struct fsldma_chan *chan; |
1124 | unsigned int handled = 0; | |
1125 | u32 gsr, mask; | |
1126 | int i; | |
173acc7c | 1127 | |
e7a29151 | 1128 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1129 | : in_le32(fdev->regs); |
1130 | mask = 0xff000000; | |
1131 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1132 | |
d3f620b2 IS |
1133 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1134 | chan = fdev->chan[i]; | |
1135 | if (!chan) | |
1136 | continue; | |
1137 | ||
1138 | if (gsr & mask) { | |
1139 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1140 | fsldma_chan_irq(irq, chan); | |
1141 | handled++; | |
1142 | } | |
1143 | ||
1144 | gsr &= ~mask; | |
1145 | mask >>= 8; | |
1146 | } | |
1147 | ||
1148 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1149 | } |
1150 | ||
d3f620b2 | 1151 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1152 | { |
d3f620b2 IS |
1153 | struct fsldma_chan *chan; |
1154 | int i; | |
1155 | ||
1156 | if (fdev->irq != NO_IRQ) { | |
1157 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1158 | free_irq(fdev->irq, fdev); | |
1159 | return; | |
1160 | } | |
1161 | ||
1162 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1163 | chan = fdev->chan[i]; | |
1164 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1165 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1166 | free_irq(chan->irq, chan); |
1167 | } | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1172 | { | |
1173 | struct fsldma_chan *chan; | |
1174 | int ret; | |
1175 | int i; | |
1176 | ||
1177 | /* if we have a per-controller IRQ, use that */ | |
1178 | if (fdev->irq != NO_IRQ) { | |
1179 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1180 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1181 | "fsldma-controller", fdev); | |
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1186 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1187 | chan = fdev->chan[i]; | |
1188 | if (!chan) | |
1189 | continue; | |
1190 | ||
1191 | if (chan->irq == NO_IRQ) { | |
b158471e | 1192 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1193 | ret = -ENODEV; |
1194 | goto out_unwind; | |
1195 | } | |
1196 | ||
b158471e | 1197 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1198 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1199 | "fsldma-chan", chan); | |
1200 | if (ret) { | |
b158471e | 1201 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1202 | goto out_unwind; |
1203 | } | |
1204 | } | |
1205 | ||
1206 | return 0; | |
1207 | ||
1208 | out_unwind: | |
1209 | for (/* none */; i >= 0; i--) { | |
1210 | chan = fdev->chan[i]; | |
1211 | if (!chan) | |
1212 | continue; | |
1213 | ||
1214 | if (chan->irq == NO_IRQ) | |
1215 | continue; | |
1216 | ||
1217 | free_irq(chan->irq, chan); | |
1218 | } | |
1219 | ||
1220 | return ret; | |
173acc7c ZW |
1221 | } |
1222 | ||
a4f56d4b IS |
1223 | /*----------------------------------------------------------------------------*/ |
1224 | /* OpenFirmware Subsystem */ | |
1225 | /*----------------------------------------------------------------------------*/ | |
1226 | ||
1227 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1228 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1229 | { |
a1c03319 | 1230 | struct fsldma_chan *chan; |
4ce0e953 | 1231 | struct resource res; |
173acc7c ZW |
1232 | int err; |
1233 | ||
173acc7c | 1234 | /* alloc channel */ |
a1c03319 IS |
1235 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1236 | if (!chan) { | |
e7a29151 IS |
1237 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1238 | err = -ENOMEM; | |
1239 | goto out_return; | |
1240 | } | |
1241 | ||
1242 | /* ioremap registers for use */ | |
a1c03319 IS |
1243 | chan->regs = of_iomap(node, 0); |
1244 | if (!chan->regs) { | |
e7a29151 IS |
1245 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1246 | err = -ENOMEM; | |
a1c03319 | 1247 | goto out_free_chan; |
173acc7c ZW |
1248 | } |
1249 | ||
4ce0e953 | 1250 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1251 | if (err) { |
e7a29151 IS |
1252 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1253 | goto out_iounmap_regs; | |
173acc7c ZW |
1254 | } |
1255 | ||
a1c03319 | 1256 | chan->feature = feature; |
173acc7c | 1257 | if (!fdev->feature) |
a1c03319 | 1258 | fdev->feature = chan->feature; |
173acc7c | 1259 | |
e7a29151 IS |
1260 | /* |
1261 | * If the DMA device's feature is different than the feature | |
1262 | * of its channels, report the bug | |
173acc7c | 1263 | */ |
a1c03319 | 1264 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1265 | |
a1c03319 IS |
1266 | chan->dev = fdev->dev; |
1267 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1268 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1269 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1270 | err = -EINVAL; |
e7a29151 | 1271 | goto out_iounmap_regs; |
173acc7c | 1272 | } |
173acc7c | 1273 | |
a1c03319 IS |
1274 | fdev->chan[chan->id] = chan; |
1275 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1276 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1277 | |
1278 | /* Initialize the channel */ | |
a1c03319 | 1279 | dma_init(chan); |
173acc7c ZW |
1280 | |
1281 | /* Clear cdar registers */ | |
a1c03319 | 1282 | set_cdar(chan, 0); |
173acc7c | 1283 | |
a1c03319 | 1284 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1285 | case FSL_DMA_IP_85XX: |
a1c03319 | 1286 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1287 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1288 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1289 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1290 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1291 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1292 | } |
1293 | ||
a1c03319 | 1294 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1295 | INIT_LIST_HEAD(&chan->ld_pending); |
1296 | INIT_LIST_HEAD(&chan->ld_running); | |
f04cd407 | 1297 | chan->idle = true; |
173acc7c | 1298 | |
a1c03319 | 1299 | chan->common.device = &fdev->common; |
173acc7c | 1300 | |
d3f620b2 | 1301 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1302 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1303 | |
173acc7c | 1304 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1305 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1306 | fdev->common.chancnt++; |
1307 | ||
a1c03319 IS |
1308 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1309 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1310 | |
1311 | return 0; | |
51ee87f2 | 1312 | |
e7a29151 | 1313 | out_iounmap_regs: |
a1c03319 IS |
1314 | iounmap(chan->regs); |
1315 | out_free_chan: | |
1316 | kfree(chan); | |
e7a29151 | 1317 | out_return: |
173acc7c ZW |
1318 | return err; |
1319 | } | |
1320 | ||
a1c03319 | 1321 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1322 | { |
a1c03319 IS |
1323 | irq_dispose_mapping(chan->irq); |
1324 | list_del(&chan->common.device_node); | |
1325 | iounmap(chan->regs); | |
1326 | kfree(chan); | |
173acc7c ZW |
1327 | } |
1328 | ||
00006124 | 1329 | static int __devinit fsldma_of_probe(struct platform_device *op) |
173acc7c | 1330 | { |
a4f56d4b | 1331 | struct fsldma_device *fdev; |
77cd62e8 | 1332 | struct device_node *child; |
e7a29151 | 1333 | int err; |
173acc7c | 1334 | |
a4f56d4b | 1335 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1336 | if (!fdev) { |
e7a29151 IS |
1337 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1338 | err = -ENOMEM; | |
1339 | goto out_return; | |
173acc7c | 1340 | } |
e7a29151 IS |
1341 | |
1342 | fdev->dev = &op->dev; | |
173acc7c ZW |
1343 | INIT_LIST_HEAD(&fdev->common.channels); |
1344 | ||
e7a29151 | 1345 | /* ioremap the registers for use */ |
61c7a080 | 1346 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1347 | if (!fdev->regs) { |
1348 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1349 | err = -ENOMEM; | |
1350 | goto out_free_fdev; | |
173acc7c ZW |
1351 | } |
1352 | ||
d3f620b2 | 1353 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1354 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1355 | |
173acc7c ZW |
1356 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1357 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1358 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1359 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1360 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1361 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1362 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1363 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1364 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1365 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1366 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1367 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1368 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1369 | fdev->common.dev = &op->dev; |
173acc7c | 1370 | |
e2c8e425 LY |
1371 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1372 | ||
e7a29151 | 1373 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1374 | |
e7a29151 IS |
1375 | /* |
1376 | * We cannot use of_platform_bus_probe() because there is no | |
1377 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1378 | * channel object. |
1379 | */ | |
61c7a080 | 1380 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1381 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1382 | fsl_dma_chan_probe(fdev, child, |
1383 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1384 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1385 | } |
1386 | ||
1387 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1388 | fsl_dma_chan_probe(fdev, child, |
1389 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1390 | "fsl,elo-dma-channel"); | |
e7a29151 | 1391 | } |
77cd62e8 | 1392 | } |
173acc7c | 1393 | |
d3f620b2 IS |
1394 | /* |
1395 | * Hookup the IRQ handler(s) | |
1396 | * | |
1397 | * If we have a per-controller interrupt, we prefer that to the | |
1398 | * per-channel interrupts to reduce the number of shared interrupt | |
1399 | * handlers on the same IRQ line | |
1400 | */ | |
1401 | err = fsldma_request_irqs(fdev); | |
1402 | if (err) { | |
1403 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1404 | goto out_free_fdev; | |
1405 | } | |
1406 | ||
173acc7c ZW |
1407 | dma_async_device_register(&fdev->common); |
1408 | return 0; | |
1409 | ||
e7a29151 | 1410 | out_free_fdev: |
d3f620b2 | 1411 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1412 | kfree(fdev); |
e7a29151 | 1413 | out_return: |
173acc7c ZW |
1414 | return err; |
1415 | } | |
1416 | ||
2dc11581 | 1417 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1418 | { |
a4f56d4b | 1419 | struct fsldma_device *fdev; |
77cd62e8 TT |
1420 | unsigned int i; |
1421 | ||
e7a29151 | 1422 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1423 | dma_async_device_unregister(&fdev->common); |
1424 | ||
d3f620b2 IS |
1425 | fsldma_free_irqs(fdev); |
1426 | ||
e7a29151 | 1427 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1428 | if (fdev->chan[i]) |
1429 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1430 | } |
77cd62e8 | 1431 | |
e7a29151 IS |
1432 | iounmap(fdev->regs); |
1433 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1434 | kfree(fdev); |
77cd62e8 TT |
1435 | |
1436 | return 0; | |
1437 | } | |
1438 | ||
4b1cf1fa | 1439 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1440 | { .compatible = "fsl,eloplus-dma", }, |
1441 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1442 | {} |
1443 | }; | |
1444 | ||
8faa7cf8 | 1445 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1446 | .driver = { |
1447 | .name = "fsl-elo-dma", | |
1448 | .owner = THIS_MODULE, | |
1449 | .of_match_table = fsldma_of_ids, | |
1450 | }, | |
1451 | .probe = fsldma_of_probe, | |
1452 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1453 | }; |
1454 | ||
a4f56d4b IS |
1455 | /*----------------------------------------------------------------------------*/ |
1456 | /* Module Init / Exit */ | |
1457 | /*----------------------------------------------------------------------------*/ | |
1458 | ||
1459 | static __init int fsldma_init(void) | |
173acc7c | 1460 | { |
77cd62e8 | 1461 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); |
00006124 | 1462 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1463 | } |
1464 | ||
a4f56d4b | 1465 | static void __exit fsldma_exit(void) |
77cd62e8 | 1466 | { |
00006124 | 1467 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1468 | } |
1469 | ||
a4f56d4b IS |
1470 | subsys_initcall(fsldma_init); |
1471 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1472 | |
1473 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1474 | MODULE_LICENSE("GPL"); |