]>
Commit | Line | Data |
---|---|---|
173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
4 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
13 | * The support for MPC8349 DMA contorller is also added. | |
14 | * | |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/dmaengine.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/dmapool.h> | |
35 | #include <linux/of_platform.h> | |
36 | ||
bbea0b6e | 37 | #include <asm/fsldma.h> |
173acc7c ZW |
38 | #include "fsldma.h" |
39 | ||
a1c03319 | 40 | static void dma_init(struct fsldma_chan *chan) |
173acc7c ZW |
41 | { |
42 | /* Reset the channel */ | |
a1c03319 | 43 | DMA_OUT(chan, &chan->regs->mr, 0, 32); |
173acc7c | 44 | |
a1c03319 | 45 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c ZW |
46 | case FSL_DMA_IP_85XX: |
47 | /* Set the channel to below modes: | |
48 | * EIE - Error interrupt enable | |
49 | * EOSIE - End of segments interrupt enable (basic mode) | |
50 | * EOLNIE - End of links interrupt enable | |
51 | */ | |
a1c03319 | 52 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE |
173acc7c ZW |
53 | | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); |
54 | break; | |
55 | case FSL_DMA_IP_83XX: | |
56 | /* Set the channel to below modes: | |
57 | * EOTIE - End-of-transfer interrupt enable | |
a7aea373 | 58 | * PRC_RM - PCI read multiple |
173acc7c | 59 | */ |
a1c03319 | 60 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE |
a7aea373 | 61 | | FSL_DMA_MR_PRC_RM, 32); |
173acc7c ZW |
62 | break; |
63 | } | |
64 | ||
65 | } | |
66 | ||
a1c03319 | 67 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 68 | { |
a1c03319 | 69 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
70 | } |
71 | ||
a1c03319 | 72 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 73 | { |
a1c03319 | 74 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
75 | } |
76 | ||
a1c03319 | 77 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
78 | struct fsl_dma_ld_hw *hw, u32 count) |
79 | { | |
a1c03319 | 80 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
81 | } |
82 | ||
a1c03319 | 83 | static void set_desc_src(struct fsldma_chan *chan, |
173acc7c ZW |
84 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
85 | { | |
86 | u64 snoop_bits; | |
87 | ||
a1c03319 | 88 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 89 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 90 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
91 | } |
92 | ||
a1c03319 | 93 | static void set_desc_dst(struct fsldma_chan *chan, |
738f5f7e | 94 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
95 | { |
96 | u64 snoop_bits; | |
97 | ||
a1c03319 | 98 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 99 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 100 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
101 | } |
102 | ||
a1c03319 | 103 | static void set_desc_next(struct fsldma_chan *chan, |
173acc7c ZW |
104 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
105 | { | |
106 | u64 snoop_bits; | |
107 | ||
a1c03319 | 108 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 109 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 110 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
111 | } |
112 | ||
a1c03319 | 113 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
173acc7c | 114 | { |
a1c03319 | 115 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
173acc7c ZW |
116 | } |
117 | ||
a1c03319 | 118 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
173acc7c | 119 | { |
a1c03319 | 120 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
173acc7c ZW |
121 | } |
122 | ||
a1c03319 | 123 | static void set_ndar(struct fsldma_chan *chan, dma_addr_t addr) |
173acc7c | 124 | { |
a1c03319 | 125 | DMA_OUT(chan, &chan->regs->ndar, addr, 64); |
173acc7c ZW |
126 | } |
127 | ||
a1c03319 | 128 | static dma_addr_t get_ndar(struct fsldma_chan *chan) |
173acc7c | 129 | { |
a1c03319 | 130 | return DMA_IN(chan, &chan->regs->ndar, 64); |
173acc7c ZW |
131 | } |
132 | ||
a1c03319 | 133 | static u32 get_bcr(struct fsldma_chan *chan) |
f79abb62 | 134 | { |
a1c03319 | 135 | return DMA_IN(chan, &chan->regs->bcr, 32); |
f79abb62 ZW |
136 | } |
137 | ||
a1c03319 | 138 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 139 | { |
a1c03319 | 140 | u32 sr = get_sr(chan); |
173acc7c ZW |
141 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
142 | } | |
143 | ||
a1c03319 | 144 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 145 | { |
272ca655 IS |
146 | u32 mode; |
147 | ||
a1c03319 | 148 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 149 | |
a1c03319 IS |
150 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
151 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
152 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
272ca655 IS |
153 | mode |= FSL_DMA_MR_EMP_EN; |
154 | } else { | |
155 | mode &= ~FSL_DMA_MR_EMP_EN; | |
156 | } | |
43a1a3ed | 157 | } |
173acc7c | 158 | |
a1c03319 | 159 | if (chan->feature & FSL_DMA_CHAN_START_EXT) |
272ca655 | 160 | mode |= FSL_DMA_MR_EMS_EN; |
173acc7c | 161 | else |
272ca655 | 162 | mode |= FSL_DMA_MR_CS; |
173acc7c | 163 | |
a1c03319 | 164 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
165 | } |
166 | ||
a1c03319 | 167 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 168 | { |
272ca655 | 169 | u32 mode; |
900325a6 DW |
170 | int i; |
171 | ||
a1c03319 | 172 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 173 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 174 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
175 | |
176 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 177 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 178 | |
900325a6 | 179 | for (i = 0; i < 100; i++) { |
a1c03319 | 180 | if (dma_is_idle(chan)) |
900325a6 | 181 | break; |
173acc7c | 182 | udelay(10); |
900325a6 | 183 | } |
272ca655 | 184 | |
a1c03319 IS |
185 | if (i >= 100 && !dma_is_idle(chan)) |
186 | dev_err(chan->dev, "DMA halt timeout!\n"); | |
173acc7c ZW |
187 | } |
188 | ||
a1c03319 | 189 | static void set_ld_eol(struct fsldma_chan *chan, |
173acc7c ZW |
190 | struct fsl_desc_sw *desc) |
191 | { | |
776c8943 IS |
192 | u64 snoop_bits; |
193 | ||
a1c03319 | 194 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
776c8943 IS |
195 | ? FSL_DMA_SNEN : 0; |
196 | ||
a1c03319 IS |
197 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
198 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
776c8943 | 199 | | snoop_bits, 64); |
173acc7c ZW |
200 | } |
201 | ||
a1c03319 | 202 | static void append_ld_queue(struct fsldma_chan *chan, |
173acc7c ZW |
203 | struct fsl_desc_sw *new_desc) |
204 | { | |
a1c03319 | 205 | struct fsl_desc_sw *queue_tail = to_fsl_desc(chan->ld_queue.prev); |
173acc7c | 206 | |
a1c03319 | 207 | if (list_empty(&chan->ld_queue)) |
173acc7c ZW |
208 | return; |
209 | ||
210 | /* Link to the new descriptor physical address and | |
211 | * Enable End-of-segment interrupt for | |
212 | * the last link descriptor. | |
213 | * (the previous node's next link descriptor) | |
214 | * | |
215 | * For FSL_DMA_IP_83xx, the snoop enable bit need be set. | |
216 | */ | |
a1c03319 | 217 | queue_tail->hw.next_ln_addr = CPU_TO_DMA(chan, |
173acc7c | 218 | new_desc->async_tx.phys | FSL_DMA_EOSIE | |
a1c03319 | 219 | (((chan->feature & FSL_DMA_IP_MASK) |
173acc7c ZW |
220 | == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); |
221 | } | |
222 | ||
223 | /** | |
224 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 225 | * @chan : Freescale DMA channel |
173acc7c ZW |
226 | * @size : Address loop size, 0 for disable loop |
227 | * | |
228 | * The set source address hold transfer size. The source | |
229 | * address hold or loop transfer size is when the DMA transfer | |
230 | * data from source address (SA), if the loop size is 4, the DMA will | |
231 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
232 | * SA + 1 ... and so on. | |
233 | */ | |
a1c03319 | 234 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 235 | { |
272ca655 IS |
236 | u32 mode; |
237 | ||
a1c03319 | 238 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 239 | |
173acc7c ZW |
240 | switch (size) { |
241 | case 0: | |
272ca655 | 242 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
243 | break; |
244 | case 1: | |
245 | case 2: | |
246 | case 4: | |
247 | case 8: | |
272ca655 | 248 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
249 | break; |
250 | } | |
272ca655 | 251 | |
a1c03319 | 252 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
253 | } |
254 | ||
255 | /** | |
738f5f7e | 256 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 257 | * @chan : Freescale DMA channel |
173acc7c ZW |
258 | * @size : Address loop size, 0 for disable loop |
259 | * | |
260 | * The set destination address hold transfer size. The destination | |
261 | * address hold or loop transfer size is when the DMA transfer | |
262 | * data to destination address (TA), if the loop size is 4, the DMA will | |
263 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
264 | * TA + 1 ... and so on. | |
265 | */ | |
a1c03319 | 266 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 267 | { |
272ca655 IS |
268 | u32 mode; |
269 | ||
a1c03319 | 270 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 271 | |
173acc7c ZW |
272 | switch (size) { |
273 | case 0: | |
272ca655 | 274 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
275 | break; |
276 | case 1: | |
277 | case 2: | |
278 | case 4: | |
279 | case 8: | |
272ca655 | 280 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
281 | break; |
282 | } | |
272ca655 | 283 | |
a1c03319 | 284 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
285 | } |
286 | ||
287 | /** | |
e6c7ecb6 | 288 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 289 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
290 | * @size : Number of bytes to transfer in a single request |
291 | * | |
292 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
293 | * The DMA request count is how many bytes are allowed to transfer before | |
294 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
295 | * operation. | |
173acc7c | 296 | * |
e6c7ecb6 | 297 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 298 | */ |
a1c03319 | 299 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 300 | { |
272ca655 IS |
301 | u32 mode; |
302 | ||
e6c7ecb6 | 303 | BUG_ON(size > 1024); |
272ca655 | 304 | |
a1c03319 | 305 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
306 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
307 | ||
a1c03319 | 308 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 309 | } |
173acc7c | 310 | |
e6c7ecb6 IS |
311 | /** |
312 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 313 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
314 | * @enable : 0 is disabled, 1 is enabled. |
315 | * | |
316 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
317 | * The DMA Request Count feature should be used in addition to this feature | |
318 | * to set the number of bytes to transfer before pausing the channel. | |
319 | */ | |
a1c03319 | 320 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
321 | { |
322 | if (enable) | |
a1c03319 | 323 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 324 | else |
a1c03319 | 325 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
326 | } |
327 | ||
328 | /** | |
329 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 330 | * @chan : Freescale DMA channel |
173acc7c ZW |
331 | * @enable : 0 is disabled, 1 is enabled. |
332 | * | |
333 | * If enable the external start, the channel can be started by an | |
334 | * external DMA start pin. So the dma_start() does not start the | |
335 | * transfer immediately. The DMA channel will wait for the | |
336 | * control pin asserted. | |
337 | */ | |
a1c03319 | 338 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
339 | { |
340 | if (enable) | |
a1c03319 | 341 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 342 | else |
a1c03319 | 343 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
344 | } |
345 | ||
346 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
347 | { | |
a1c03319 | 348 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
349 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
350 | struct fsl_desc_sw *child; | |
173acc7c ZW |
351 | unsigned long flags; |
352 | dma_cookie_t cookie; | |
353 | ||
354 | /* cookie increment and adding to ld_queue must be atomic */ | |
a1c03319 | 355 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 356 | |
a1c03319 | 357 | cookie = chan->common.cookie; |
eda34234 | 358 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 IS |
359 | cookie++; |
360 | if (cookie < 0) | |
361 | cookie = 1; | |
362 | ||
363 | desc->async_tx.cookie = cookie; | |
364 | } | |
365 | ||
a1c03319 IS |
366 | chan->common.cookie = cookie; |
367 | append_ld_queue(chan, desc); | |
368 | list_splice_init(&desc->tx_list, chan->ld_queue.prev); | |
173acc7c | 369 | |
a1c03319 | 370 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
371 | |
372 | return cookie; | |
373 | } | |
374 | ||
375 | /** | |
376 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 377 | * @chan : Freescale DMA channel |
173acc7c ZW |
378 | * |
379 | * Return - The descriptor allocated. NULL for failed. | |
380 | */ | |
381 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
a1c03319 | 382 | struct fsldma_chan *chan) |
173acc7c ZW |
383 | { |
384 | dma_addr_t pdesc; | |
385 | struct fsl_desc_sw *desc_sw; | |
386 | ||
a1c03319 | 387 | desc_sw = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); |
173acc7c ZW |
388 | if (desc_sw) { |
389 | memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); | |
eda34234 | 390 | INIT_LIST_HEAD(&desc_sw->tx_list); |
173acc7c | 391 | dma_async_tx_descriptor_init(&desc_sw->async_tx, |
a1c03319 | 392 | &chan->common); |
173acc7c | 393 | desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; |
173acc7c ZW |
394 | desc_sw->async_tx.phys = pdesc; |
395 | } | |
396 | ||
397 | return desc_sw; | |
398 | } | |
399 | ||
400 | ||
401 | /** | |
402 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 403 | * @chan : Freescale DMA channel |
173acc7c ZW |
404 | * |
405 | * This function will create a dma pool for descriptor allocation. | |
406 | * | |
407 | * Return - The number of descriptors allocated. | |
408 | */ | |
a1c03319 | 409 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 410 | { |
a1c03319 | 411 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
412 | |
413 | /* Has this channel already been allocated? */ | |
a1c03319 | 414 | if (chan->desc_pool) |
77cd62e8 | 415 | return 1; |
173acc7c ZW |
416 | |
417 | /* We need the descriptor to be aligned to 32bytes | |
418 | * for meeting FSL DMA specification requirement. | |
419 | */ | |
a1c03319 IS |
420 | chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", |
421 | chan->dev, sizeof(struct fsl_desc_sw), | |
173acc7c | 422 | 32, 0); |
a1c03319 IS |
423 | if (!chan->desc_pool) { |
424 | dev_err(chan->dev, "No memory for channel %d " | |
425 | "descriptor dma pool.\n", chan->id); | |
173acc7c ZW |
426 | return 0; |
427 | } | |
428 | ||
429 | return 1; | |
430 | } | |
431 | ||
432 | /** | |
433 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 434 | * @chan : Freescale DMA channel |
173acc7c | 435 | */ |
a1c03319 | 436 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 437 | { |
a1c03319 | 438 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
439 | struct fsl_desc_sw *desc, *_desc; |
440 | unsigned long flags; | |
441 | ||
a1c03319 IS |
442 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
443 | spin_lock_irqsave(&chan->desc_lock, flags); | |
444 | list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { | |
173acc7c | 445 | #ifdef FSL_DMA_LD_DEBUG |
a1c03319 | 446 | dev_dbg(chan->dev, |
173acc7c ZW |
447 | "LD %p will be released.\n", desc); |
448 | #endif | |
449 | list_del(&desc->node); | |
450 | /* free link descriptor */ | |
a1c03319 | 451 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
173acc7c | 452 | } |
a1c03319 IS |
453 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
454 | dma_pool_destroy(chan->desc_pool); | |
77cd62e8 | 455 | |
a1c03319 | 456 | chan->desc_pool = NULL; |
173acc7c ZW |
457 | } |
458 | ||
2187c269 | 459 | static struct dma_async_tx_descriptor * |
a1c03319 | 460 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 461 | { |
a1c03319 | 462 | struct fsldma_chan *chan; |
2187c269 ZW |
463 | struct fsl_desc_sw *new; |
464 | ||
a1c03319 | 465 | if (!dchan) |
2187c269 ZW |
466 | return NULL; |
467 | ||
a1c03319 | 468 | chan = to_fsl_chan(dchan); |
2187c269 | 469 | |
a1c03319 | 470 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 471 | if (!new) { |
a1c03319 | 472 | dev_err(chan->dev, "No free memory for link descriptor\n"); |
2187c269 ZW |
473 | return NULL; |
474 | } | |
475 | ||
476 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 477 | new->async_tx.flags = flags; |
2187c269 | 478 | |
f79abb62 | 479 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 480 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 481 | |
2187c269 | 482 | /* Set End-of-link to the last link descriptor of new list*/ |
a1c03319 | 483 | set_ld_eol(chan, new); |
2187c269 ZW |
484 | |
485 | return &new->async_tx; | |
486 | } | |
487 | ||
173acc7c | 488 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
a1c03319 | 489 | struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, |
173acc7c ZW |
490 | size_t len, unsigned long flags) |
491 | { | |
a1c03319 | 492 | struct fsldma_chan *chan; |
173acc7c | 493 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
2e077f8e | 494 | struct list_head *list; |
173acc7c | 495 | size_t copy; |
173acc7c | 496 | |
a1c03319 | 497 | if (!dchan) |
173acc7c ZW |
498 | return NULL; |
499 | ||
500 | if (!len) | |
501 | return NULL; | |
502 | ||
a1c03319 | 503 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
504 | |
505 | do { | |
506 | ||
507 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 508 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 509 | if (!new) { |
a1c03319 | 510 | dev_err(chan->dev, |
173acc7c | 511 | "No free memory for link descriptor\n"); |
2e077f8e | 512 | goto fail; |
173acc7c ZW |
513 | } |
514 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 515 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
173acc7c ZW |
516 | #endif |
517 | ||
56822843 | 518 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 519 | |
a1c03319 IS |
520 | set_desc_cnt(chan, &new->hw, copy); |
521 | set_desc_src(chan, &new->hw, dma_src); | |
522 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
523 | |
524 | if (!first) | |
525 | first = new; | |
526 | else | |
a1c03319 | 527 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
528 | |
529 | new->async_tx.cookie = 0; | |
636bdeaa | 530 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
531 | |
532 | prev = new; | |
533 | len -= copy; | |
534 | dma_src += copy; | |
738f5f7e | 535 | dma_dst += copy; |
173acc7c ZW |
536 | |
537 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 538 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
539 | } while (len); |
540 | ||
636bdeaa | 541 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
542 | new->async_tx.cookie = -EBUSY; |
543 | ||
544 | /* Set End-of-link to the last link descriptor of new list*/ | |
a1c03319 | 545 | set_ld_eol(chan, new); |
173acc7c | 546 | |
2e077f8e IS |
547 | return &first->async_tx; |
548 | ||
549 | fail: | |
550 | if (!first) | |
551 | return NULL; | |
552 | ||
eda34234 | 553 | list = &first->tx_list; |
2e077f8e IS |
554 | list_for_each_entry_safe_reverse(new, prev, list, node) { |
555 | list_del(&new->node); | |
a1c03319 | 556 | dma_pool_free(chan->desc_pool, new, new->async_tx.phys); |
2e077f8e IS |
557 | } |
558 | ||
559 | return NULL; | |
173acc7c ZW |
560 | } |
561 | ||
bbea0b6e IS |
562 | /** |
563 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
564 | * @chan: DMA channel | |
565 | * @sgl: scatterlist to transfer to/from | |
566 | * @sg_len: number of entries in @scatterlist | |
567 | * @direction: DMA direction | |
568 | * @flags: DMAEngine flags | |
569 | * | |
570 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
571 | * DMA_SLAVE API, this gets the device-specific information from the | |
572 | * chan->private variable. | |
573 | */ | |
574 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 575 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
576 | enum dma_data_direction direction, unsigned long flags) |
577 | { | |
a1c03319 | 578 | struct fsldma_chan *chan; |
bbea0b6e IS |
579 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; |
580 | struct fsl_dma_slave *slave; | |
581 | struct list_head *tx_list; | |
582 | size_t copy; | |
583 | ||
584 | int i; | |
585 | struct scatterlist *sg; | |
586 | size_t sg_used; | |
587 | size_t hw_used; | |
588 | struct fsl_dma_hw_addr *hw; | |
589 | dma_addr_t dma_dst, dma_src; | |
590 | ||
a1c03319 | 591 | if (!dchan) |
bbea0b6e IS |
592 | return NULL; |
593 | ||
a1c03319 | 594 | if (!dchan->private) |
bbea0b6e IS |
595 | return NULL; |
596 | ||
a1c03319 IS |
597 | chan = to_fsl_chan(dchan); |
598 | slave = dchan->private; | |
bbea0b6e IS |
599 | |
600 | if (list_empty(&slave->addresses)) | |
601 | return NULL; | |
602 | ||
603 | hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); | |
604 | hw_used = 0; | |
605 | ||
606 | /* | |
607 | * Build the hardware transaction to copy from the scatterlist to | |
608 | * the hardware, or from the hardware to the scatterlist | |
609 | * | |
610 | * If you are copying from the hardware to the scatterlist and it | |
611 | * takes two hardware entries to fill an entire page, then both | |
612 | * hardware entries will be coalesced into the same page | |
613 | * | |
614 | * If you are copying from the scatterlist to the hardware and a | |
615 | * single page can fill two hardware entries, then the data will | |
616 | * be read out of the page into the first hardware entry, and so on | |
617 | */ | |
618 | for_each_sg(sgl, sg, sg_len, i) { | |
619 | sg_used = 0; | |
620 | ||
621 | /* Loop until the entire scatterlist entry is used */ | |
622 | while (sg_used < sg_dma_len(sg)) { | |
623 | ||
624 | /* | |
625 | * If we've used up the current hardware address/length | |
626 | * pair, we need to load a new one | |
627 | * | |
628 | * This is done in a while loop so that descriptors with | |
629 | * length == 0 will be skipped | |
630 | */ | |
631 | while (hw_used >= hw->length) { | |
632 | ||
633 | /* | |
634 | * If the current hardware entry is the last | |
635 | * entry in the list, we're finished | |
636 | */ | |
637 | if (list_is_last(&hw->entry, &slave->addresses)) | |
638 | goto finished; | |
639 | ||
640 | /* Get the next hardware address/length pair */ | |
641 | hw = list_entry(hw->entry.next, | |
642 | struct fsl_dma_hw_addr, entry); | |
643 | hw_used = 0; | |
644 | } | |
645 | ||
646 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 647 | new = fsl_dma_alloc_descriptor(chan); |
bbea0b6e | 648 | if (!new) { |
a1c03319 | 649 | dev_err(chan->dev, "No free memory for " |
bbea0b6e IS |
650 | "link descriptor\n"); |
651 | goto fail; | |
652 | } | |
653 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 654 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
bbea0b6e IS |
655 | #endif |
656 | ||
657 | /* | |
658 | * Calculate the maximum number of bytes to transfer, | |
659 | * making sure it is less than the DMA controller limit | |
660 | */ | |
661 | copy = min_t(size_t, sg_dma_len(sg) - sg_used, | |
662 | hw->length - hw_used); | |
663 | copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); | |
664 | ||
665 | /* | |
666 | * DMA_FROM_DEVICE | |
667 | * from the hardware to the scatterlist | |
668 | * | |
669 | * DMA_TO_DEVICE | |
670 | * from the scatterlist to the hardware | |
671 | */ | |
672 | if (direction == DMA_FROM_DEVICE) { | |
673 | dma_src = hw->address + hw_used; | |
674 | dma_dst = sg_dma_address(sg) + sg_used; | |
675 | } else { | |
676 | dma_src = sg_dma_address(sg) + sg_used; | |
677 | dma_dst = hw->address + hw_used; | |
678 | } | |
679 | ||
680 | /* Fill in the descriptor */ | |
a1c03319 IS |
681 | set_desc_cnt(chan, &new->hw, copy); |
682 | set_desc_src(chan, &new->hw, dma_src); | |
683 | set_desc_dst(chan, &new->hw, dma_dst); | |
bbea0b6e IS |
684 | |
685 | /* | |
686 | * If this is not the first descriptor, chain the | |
687 | * current descriptor after the previous descriptor | |
688 | */ | |
689 | if (!first) { | |
690 | first = new; | |
691 | } else { | |
a1c03319 | 692 | set_desc_next(chan, &prev->hw, |
bbea0b6e IS |
693 | new->async_tx.phys); |
694 | } | |
695 | ||
696 | new->async_tx.cookie = 0; | |
697 | async_tx_ack(&new->async_tx); | |
698 | ||
699 | prev = new; | |
700 | sg_used += copy; | |
701 | hw_used += copy; | |
702 | ||
703 | /* Insert the link descriptor into the LD ring */ | |
704 | list_add_tail(&new->node, &first->tx_list); | |
705 | } | |
706 | } | |
707 | ||
708 | finished: | |
709 | ||
710 | /* All of the hardware address/length pairs had length == 0 */ | |
711 | if (!first || !new) | |
712 | return NULL; | |
713 | ||
714 | new->async_tx.flags = flags; | |
715 | new->async_tx.cookie = -EBUSY; | |
716 | ||
717 | /* Set End-of-link to the last link descriptor of new list */ | |
a1c03319 | 718 | set_ld_eol(chan, new); |
bbea0b6e IS |
719 | |
720 | /* Enable extra controller features */ | |
a1c03319 IS |
721 | if (chan->set_src_loop_size) |
722 | chan->set_src_loop_size(chan, slave->src_loop_size); | |
bbea0b6e | 723 | |
a1c03319 IS |
724 | if (chan->set_dst_loop_size) |
725 | chan->set_dst_loop_size(chan, slave->dst_loop_size); | |
bbea0b6e | 726 | |
a1c03319 IS |
727 | if (chan->toggle_ext_start) |
728 | chan->toggle_ext_start(chan, slave->external_start); | |
bbea0b6e | 729 | |
a1c03319 IS |
730 | if (chan->toggle_ext_pause) |
731 | chan->toggle_ext_pause(chan, slave->external_pause); | |
bbea0b6e | 732 | |
a1c03319 IS |
733 | if (chan->set_request_count) |
734 | chan->set_request_count(chan, slave->request_count); | |
bbea0b6e IS |
735 | |
736 | return &first->async_tx; | |
737 | ||
738 | fail: | |
739 | /* If first was not set, then we failed to allocate the very first | |
740 | * descriptor, and we're done */ | |
741 | if (!first) | |
742 | return NULL; | |
743 | ||
744 | /* | |
745 | * First is set, so all of the descriptors we allocated have been added | |
746 | * to first->tx_list, INCLUDING "first" itself. Therefore we | |
747 | * must traverse the list backwards freeing each descriptor in turn | |
748 | * | |
749 | * We're re-using variables for the loop, oh well | |
750 | */ | |
751 | tx_list = &first->tx_list; | |
752 | list_for_each_entry_safe_reverse(new, prev, tx_list, node) { | |
753 | list_del_init(&new->node); | |
a1c03319 | 754 | dma_pool_free(chan->desc_pool, new, new->async_tx.phys); |
bbea0b6e IS |
755 | } |
756 | ||
757 | return NULL; | |
758 | } | |
759 | ||
a1c03319 | 760 | static void fsl_dma_device_terminate_all(struct dma_chan *dchan) |
bbea0b6e | 761 | { |
a1c03319 | 762 | struct fsldma_chan *chan; |
bbea0b6e IS |
763 | struct fsl_desc_sw *desc, *tmp; |
764 | unsigned long flags; | |
765 | ||
a1c03319 | 766 | if (!dchan) |
bbea0b6e IS |
767 | return; |
768 | ||
a1c03319 | 769 | chan = to_fsl_chan(dchan); |
bbea0b6e IS |
770 | |
771 | /* Halt the DMA engine */ | |
a1c03319 | 772 | dma_halt(chan); |
bbea0b6e | 773 | |
a1c03319 | 774 | spin_lock_irqsave(&chan->desc_lock, flags); |
bbea0b6e IS |
775 | |
776 | /* Remove and free all of the descriptors in the LD queue */ | |
a1c03319 | 777 | list_for_each_entry_safe(desc, tmp, &chan->ld_queue, node) { |
bbea0b6e | 778 | list_del(&desc->node); |
a1c03319 | 779 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
bbea0b6e IS |
780 | } |
781 | ||
a1c03319 | 782 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
bbea0b6e IS |
783 | } |
784 | ||
173acc7c ZW |
785 | /** |
786 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
a1c03319 | 787 | * @chan : Freescale DMA channel |
173acc7c | 788 | */ |
a1c03319 | 789 | static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) |
173acc7c ZW |
790 | { |
791 | struct fsl_desc_sw *cur_desc, *desc; | |
792 | dma_addr_t ld_phy; | |
793 | ||
a1c03319 | 794 | ld_phy = get_cdar(chan) & FSL_DMA_NLDA_MASK; |
173acc7c ZW |
795 | |
796 | if (ld_phy) { | |
797 | cur_desc = NULL; | |
a1c03319 | 798 | list_for_each_entry(desc, &chan->ld_queue, node) |
173acc7c ZW |
799 | if (desc->async_tx.phys == ld_phy) { |
800 | cur_desc = desc; | |
801 | break; | |
802 | } | |
803 | ||
804 | if (cur_desc && cur_desc->async_tx.cookie) { | |
a1c03319 IS |
805 | if (dma_is_idle(chan)) |
806 | chan->completed_cookie = | |
173acc7c ZW |
807 | cur_desc->async_tx.cookie; |
808 | else | |
a1c03319 | 809 | chan->completed_cookie = |
173acc7c ZW |
810 | cur_desc->async_tx.cookie - 1; |
811 | } | |
812 | } | |
813 | } | |
814 | ||
815 | /** | |
816 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
a1c03319 | 817 | * @chan : Freescale DMA channel |
173acc7c ZW |
818 | * |
819 | * This function clean up the ld_queue of DMA channel. | |
820 | * If 'in_intr' is set, the function will move the link descriptor to | |
821 | * the recycle list. Otherwise, free it directly. | |
822 | */ | |
a1c03319 | 823 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c ZW |
824 | { |
825 | struct fsl_desc_sw *desc, *_desc; | |
826 | unsigned long flags; | |
827 | ||
a1c03319 | 828 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 829 | |
a1c03319 IS |
830 | dev_dbg(chan->dev, "chan completed_cookie = %d\n", |
831 | chan->completed_cookie); | |
832 | list_for_each_entry_safe(desc, _desc, &chan->ld_queue, node) { | |
173acc7c ZW |
833 | dma_async_tx_callback callback; |
834 | void *callback_param; | |
835 | ||
836 | if (dma_async_is_complete(desc->async_tx.cookie, | |
a1c03319 | 837 | chan->completed_cookie, chan->common.cookie) |
173acc7c ZW |
838 | == DMA_IN_PROGRESS) |
839 | break; | |
840 | ||
841 | callback = desc->async_tx.callback; | |
842 | callback_param = desc->async_tx.callback_param; | |
843 | ||
844 | /* Remove from ld_queue list */ | |
845 | list_del(&desc->node); | |
846 | ||
a1c03319 | 847 | dev_dbg(chan->dev, "link descriptor %p will be recycle.\n", |
173acc7c | 848 | desc); |
a1c03319 | 849 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
173acc7c ZW |
850 | |
851 | /* Run the link descriptor callback function */ | |
852 | if (callback) { | |
a1c03319 IS |
853 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
854 | dev_dbg(chan->dev, "link descriptor %p callback\n", | |
173acc7c ZW |
855 | desc); |
856 | callback(callback_param); | |
a1c03319 | 857 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c ZW |
858 | } |
859 | } | |
a1c03319 | 860 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
861 | } |
862 | ||
863 | /** | |
864 | * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. | |
a1c03319 | 865 | * @chan : Freescale DMA channel |
173acc7c | 866 | */ |
a1c03319 | 867 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c ZW |
868 | { |
869 | struct list_head *ld_node; | |
738f5f7e | 870 | dma_addr_t next_dst_addr; |
173acc7c ZW |
871 | unsigned long flags; |
872 | ||
a1c03319 | 873 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 874 | |
a1c03319 | 875 | if (!dma_is_idle(chan)) |
138ef018 | 876 | goto out_unlock; |
173acc7c | 877 | |
a1c03319 | 878 | dma_halt(chan); |
173acc7c ZW |
879 | |
880 | /* If there are some link descriptors | |
881 | * not transfered in queue. We need to start it. | |
882 | */ | |
173acc7c ZW |
883 | |
884 | /* Find the first un-transfer desciptor */ | |
a1c03319 IS |
885 | for (ld_node = chan->ld_queue.next; |
886 | (ld_node != &chan->ld_queue) | |
173acc7c ZW |
887 | && (dma_async_is_complete( |
888 | to_fsl_desc(ld_node)->async_tx.cookie, | |
a1c03319 IS |
889 | chan->completed_cookie, |
890 | chan->common.cookie) == DMA_SUCCESS); | |
173acc7c ZW |
891 | ld_node = ld_node->next); |
892 | ||
a1c03319 | 893 | if (ld_node != &chan->ld_queue) { |
173acc7c | 894 | /* Get the ld start address from ld_queue */ |
738f5f7e | 895 | next_dst_addr = to_fsl_desc(ld_node)->async_tx.phys; |
a1c03319 | 896 | dev_dbg(chan->dev, "xfer LDs staring from 0x%llx\n", |
738f5f7e | 897 | (unsigned long long)next_dst_addr); |
a1c03319 IS |
898 | set_cdar(chan, next_dst_addr); |
899 | dma_start(chan); | |
173acc7c | 900 | } else { |
a1c03319 IS |
901 | set_cdar(chan, 0); |
902 | set_ndar(chan, 0); | |
173acc7c | 903 | } |
138ef018 IS |
904 | |
905 | out_unlock: | |
a1c03319 | 906 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
907 | } |
908 | ||
909 | /** | |
910 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 911 | * @chan : Freescale DMA channel |
173acc7c | 912 | */ |
a1c03319 | 913 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 914 | { |
a1c03319 | 915 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
916 | |
917 | #ifdef FSL_DMA_LD_DEBUG | |
918 | struct fsl_desc_sw *ld; | |
919 | unsigned long flags; | |
920 | ||
a1c03319 IS |
921 | spin_lock_irqsave(&chan->desc_lock, flags); |
922 | if (list_empty(&chan->ld_queue)) { | |
923 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
173acc7c ZW |
924 | return; |
925 | } | |
926 | ||
a1c03319 IS |
927 | dev_dbg(chan->dev, "--memcpy issue--\n"); |
928 | list_for_each_entry(ld, &chan->ld_queue, node) { | |
173acc7c | 929 | int i; |
a1c03319 IS |
930 | dev_dbg(chan->dev, "Ch %d, LD %08x\n", |
931 | chan->id, ld->async_tx.phys); | |
173acc7c | 932 | for (i = 0; i < 8; i++) |
a1c03319 | 933 | dev_dbg(chan->dev, "LD offset %d: %08x\n", |
173acc7c ZW |
934 | i, *(((u32 *)&ld->hw) + i)); |
935 | } | |
a1c03319 IS |
936 | dev_dbg(chan->dev, "----------------\n"); |
937 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
173acc7c ZW |
938 | #endif |
939 | ||
a1c03319 | 940 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
941 | } |
942 | ||
173acc7c ZW |
943 | /** |
944 | * fsl_dma_is_complete - Determine the DMA status | |
a1c03319 | 945 | * @chan : Freescale DMA channel |
173acc7c | 946 | */ |
a1c03319 | 947 | static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan, |
173acc7c ZW |
948 | dma_cookie_t cookie, |
949 | dma_cookie_t *done, | |
950 | dma_cookie_t *used) | |
951 | { | |
a1c03319 | 952 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
953 | dma_cookie_t last_used; |
954 | dma_cookie_t last_complete; | |
955 | ||
a1c03319 | 956 | fsl_chan_ld_cleanup(chan); |
173acc7c | 957 | |
a1c03319 IS |
958 | last_used = dchan->cookie; |
959 | last_complete = chan->completed_cookie; | |
173acc7c ZW |
960 | |
961 | if (done) | |
962 | *done = last_complete; | |
963 | ||
964 | if (used) | |
965 | *used = last_used; | |
966 | ||
967 | return dma_async_is_complete(cookie, last_complete, last_used); | |
968 | } | |
969 | ||
d3f620b2 IS |
970 | /*----------------------------------------------------------------------------*/ |
971 | /* Interrupt Handling */ | |
972 | /*----------------------------------------------------------------------------*/ | |
973 | ||
e7a29151 | 974 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 975 | { |
a1c03319 | 976 | struct fsldma_chan *chan = data; |
1c62979e ZW |
977 | int update_cookie = 0; |
978 | int xfer_ld_q = 0; | |
a1c03319 | 979 | u32 stat; |
173acc7c | 980 | |
a1c03319 IS |
981 | stat = get_sr(chan); |
982 | dev_dbg(chan->dev, "event: channel %d, stat = 0x%x\n", | |
983 | chan->id, stat); | |
984 | set_sr(chan, stat); /* Clear the event register */ | |
173acc7c ZW |
985 | |
986 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
987 | if (!stat) | |
988 | return IRQ_NONE; | |
989 | ||
990 | if (stat & FSL_DMA_SR_TE) | |
a1c03319 | 991 | dev_err(chan->dev, "Transfer Error!\n"); |
173acc7c | 992 | |
f79abb62 ZW |
993 | /* Programming Error |
994 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will | |
995 | * triger a PE interrupt. | |
996 | */ | |
997 | if (stat & FSL_DMA_SR_PE) { | |
a1c03319 IS |
998 | dev_dbg(chan->dev, "event: Programming Error INT\n"); |
999 | if (get_bcr(chan) == 0) { | |
f79abb62 ZW |
1000 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. |
1001 | * Now, update the completed cookie, and continue the | |
1002 | * next uncompleted transfer. | |
1003 | */ | |
1c62979e ZW |
1004 | update_cookie = 1; |
1005 | xfer_ld_q = 1; | |
f79abb62 ZW |
1006 | } |
1007 | stat &= ~FSL_DMA_SR_PE; | |
1008 | } | |
1009 | ||
173acc7c ZW |
1010 | /* If the link descriptor segment transfer finishes, |
1011 | * we will recycle the used descriptor. | |
1012 | */ | |
1013 | if (stat & FSL_DMA_SR_EOSI) { | |
a1c03319 IS |
1014 | dev_dbg(chan->dev, "event: End-of-segments INT\n"); |
1015 | dev_dbg(chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", | |
1016 | (unsigned long long)get_cdar(chan), | |
1017 | (unsigned long long)get_ndar(chan)); | |
173acc7c | 1018 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
1019 | update_cookie = 1; |
1020 | } | |
1021 | ||
1022 | /* For MPC8349, EOCDI event need to update cookie | |
1023 | * and start the next transfer if it exist. | |
1024 | */ | |
1025 | if (stat & FSL_DMA_SR_EOCDI) { | |
a1c03319 | 1026 | dev_dbg(chan->dev, "event: End-of-Chain link INT\n"); |
1c62979e ZW |
1027 | stat &= ~FSL_DMA_SR_EOCDI; |
1028 | update_cookie = 1; | |
1029 | xfer_ld_q = 1; | |
173acc7c ZW |
1030 | } |
1031 | ||
1032 | /* If it current transfer is the end-of-transfer, | |
1033 | * we should clear the Channel Start bit for | |
1034 | * prepare next transfer. | |
1035 | */ | |
1c62979e | 1036 | if (stat & FSL_DMA_SR_EOLNI) { |
a1c03319 | 1037 | dev_dbg(chan->dev, "event: End-of-link INT\n"); |
173acc7c | 1038 | stat &= ~FSL_DMA_SR_EOLNI; |
1c62979e | 1039 | xfer_ld_q = 1; |
173acc7c ZW |
1040 | } |
1041 | ||
1c62979e | 1042 | if (update_cookie) |
a1c03319 | 1043 | fsl_dma_update_completed_cookie(chan); |
1c62979e | 1044 | if (xfer_ld_q) |
a1c03319 | 1045 | fsl_chan_xfer_ld_queue(chan); |
173acc7c | 1046 | if (stat) |
a1c03319 | 1047 | dev_dbg(chan->dev, "event: unhandled sr 0x%02x\n", |
173acc7c ZW |
1048 | stat); |
1049 | ||
a1c03319 IS |
1050 | dev_dbg(chan->dev, "event: Exit\n"); |
1051 | tasklet_schedule(&chan->tasklet); | |
173acc7c ZW |
1052 | return IRQ_HANDLED; |
1053 | } | |
1054 | ||
d3f620b2 IS |
1055 | static void dma_do_tasklet(unsigned long data) |
1056 | { | |
a1c03319 IS |
1057 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
1058 | fsl_chan_ld_cleanup(chan); | |
d3f620b2 IS |
1059 | } |
1060 | ||
1061 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1062 | { |
a4f56d4b | 1063 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1064 | struct fsldma_chan *chan; |
1065 | unsigned int handled = 0; | |
1066 | u32 gsr, mask; | |
1067 | int i; | |
173acc7c | 1068 | |
e7a29151 | 1069 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1070 | : in_le32(fdev->regs); |
1071 | mask = 0xff000000; | |
1072 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1073 | |
d3f620b2 IS |
1074 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1075 | chan = fdev->chan[i]; | |
1076 | if (!chan) | |
1077 | continue; | |
1078 | ||
1079 | if (gsr & mask) { | |
1080 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1081 | fsldma_chan_irq(irq, chan); | |
1082 | handled++; | |
1083 | } | |
1084 | ||
1085 | gsr &= ~mask; | |
1086 | mask >>= 8; | |
1087 | } | |
1088 | ||
1089 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1090 | } |
1091 | ||
d3f620b2 | 1092 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1093 | { |
d3f620b2 IS |
1094 | struct fsldma_chan *chan; |
1095 | int i; | |
1096 | ||
1097 | if (fdev->irq != NO_IRQ) { | |
1098 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1099 | free_irq(fdev->irq, fdev); | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1104 | chan = fdev->chan[i]; | |
1105 | if (chan && chan->irq != NO_IRQ) { | |
1106 | dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); | |
1107 | free_irq(chan->irq, chan); | |
1108 | } | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1113 | { | |
1114 | struct fsldma_chan *chan; | |
1115 | int ret; | |
1116 | int i; | |
1117 | ||
1118 | /* if we have a per-controller IRQ, use that */ | |
1119 | if (fdev->irq != NO_IRQ) { | |
1120 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1121 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1122 | "fsldma-controller", fdev); | |
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1127 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1128 | chan = fdev->chan[i]; | |
1129 | if (!chan) | |
1130 | continue; | |
1131 | ||
1132 | if (chan->irq == NO_IRQ) { | |
1133 | dev_err(fdev->dev, "no interrupts property defined for " | |
1134 | "DMA channel %d. Please fix your " | |
1135 | "device tree\n", chan->id); | |
1136 | ret = -ENODEV; | |
1137 | goto out_unwind; | |
1138 | } | |
1139 | ||
1140 | dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); | |
1141 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, | |
1142 | "fsldma-chan", chan); | |
1143 | if (ret) { | |
1144 | dev_err(fdev->dev, "unable to request IRQ for DMA " | |
1145 | "channel %d\n", chan->id); | |
1146 | goto out_unwind; | |
1147 | } | |
1148 | } | |
1149 | ||
1150 | return 0; | |
1151 | ||
1152 | out_unwind: | |
1153 | for (/* none */; i >= 0; i--) { | |
1154 | chan = fdev->chan[i]; | |
1155 | if (!chan) | |
1156 | continue; | |
1157 | ||
1158 | if (chan->irq == NO_IRQ) | |
1159 | continue; | |
1160 | ||
1161 | free_irq(chan->irq, chan); | |
1162 | } | |
1163 | ||
1164 | return ret; | |
173acc7c ZW |
1165 | } |
1166 | ||
a4f56d4b IS |
1167 | /*----------------------------------------------------------------------------*/ |
1168 | /* OpenFirmware Subsystem */ | |
1169 | /*----------------------------------------------------------------------------*/ | |
1170 | ||
1171 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1172 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1173 | { |
a1c03319 | 1174 | struct fsldma_chan *chan; |
4ce0e953 | 1175 | struct resource res; |
173acc7c ZW |
1176 | int err; |
1177 | ||
173acc7c | 1178 | /* alloc channel */ |
a1c03319 IS |
1179 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1180 | if (!chan) { | |
e7a29151 IS |
1181 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1182 | err = -ENOMEM; | |
1183 | goto out_return; | |
1184 | } | |
1185 | ||
1186 | /* ioremap registers for use */ | |
a1c03319 IS |
1187 | chan->regs = of_iomap(node, 0); |
1188 | if (!chan->regs) { | |
e7a29151 IS |
1189 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1190 | err = -ENOMEM; | |
a1c03319 | 1191 | goto out_free_chan; |
173acc7c ZW |
1192 | } |
1193 | ||
4ce0e953 | 1194 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1195 | if (err) { |
e7a29151 IS |
1196 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1197 | goto out_iounmap_regs; | |
173acc7c ZW |
1198 | } |
1199 | ||
a1c03319 | 1200 | chan->feature = feature; |
173acc7c | 1201 | if (!fdev->feature) |
a1c03319 | 1202 | fdev->feature = chan->feature; |
173acc7c | 1203 | |
e7a29151 IS |
1204 | /* |
1205 | * If the DMA device's feature is different than the feature | |
1206 | * of its channels, report the bug | |
173acc7c | 1207 | */ |
a1c03319 | 1208 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1209 | |
a1c03319 IS |
1210 | chan->dev = fdev->dev; |
1211 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1212 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1213 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1214 | err = -EINVAL; |
e7a29151 | 1215 | goto out_iounmap_regs; |
173acc7c | 1216 | } |
173acc7c | 1217 | |
a1c03319 IS |
1218 | fdev->chan[chan->id] = chan; |
1219 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
e7a29151 IS |
1220 | |
1221 | /* Initialize the channel */ | |
a1c03319 | 1222 | dma_init(chan); |
173acc7c ZW |
1223 | |
1224 | /* Clear cdar registers */ | |
a1c03319 | 1225 | set_cdar(chan, 0); |
173acc7c | 1226 | |
a1c03319 | 1227 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1228 | case FSL_DMA_IP_85XX: |
a1c03319 | 1229 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1230 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1231 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1232 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1233 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1234 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1235 | } |
1236 | ||
a1c03319 IS |
1237 | spin_lock_init(&chan->desc_lock); |
1238 | INIT_LIST_HEAD(&chan->ld_queue); | |
173acc7c | 1239 | |
a1c03319 | 1240 | chan->common.device = &fdev->common; |
173acc7c | 1241 | |
d3f620b2 | 1242 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1243 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1244 | |
173acc7c | 1245 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1246 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1247 | fdev->common.chancnt++; |
1248 | ||
a1c03319 IS |
1249 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1250 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1251 | |
1252 | return 0; | |
51ee87f2 | 1253 | |
e7a29151 | 1254 | out_iounmap_regs: |
a1c03319 IS |
1255 | iounmap(chan->regs); |
1256 | out_free_chan: | |
1257 | kfree(chan); | |
e7a29151 | 1258 | out_return: |
173acc7c ZW |
1259 | return err; |
1260 | } | |
1261 | ||
a1c03319 | 1262 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1263 | { |
a1c03319 IS |
1264 | irq_dispose_mapping(chan->irq); |
1265 | list_del(&chan->common.device_node); | |
1266 | iounmap(chan->regs); | |
1267 | kfree(chan); | |
173acc7c ZW |
1268 | } |
1269 | ||
e7a29151 | 1270 | static int __devinit fsldma_of_probe(struct of_device *op, |
173acc7c ZW |
1271 | const struct of_device_id *match) |
1272 | { | |
a4f56d4b | 1273 | struct fsldma_device *fdev; |
77cd62e8 | 1274 | struct device_node *child; |
e7a29151 | 1275 | int err; |
173acc7c | 1276 | |
a4f56d4b | 1277 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1278 | if (!fdev) { |
e7a29151 IS |
1279 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1280 | err = -ENOMEM; | |
1281 | goto out_return; | |
173acc7c | 1282 | } |
e7a29151 IS |
1283 | |
1284 | fdev->dev = &op->dev; | |
173acc7c ZW |
1285 | INIT_LIST_HEAD(&fdev->common.channels); |
1286 | ||
e7a29151 IS |
1287 | /* ioremap the registers for use */ |
1288 | fdev->regs = of_iomap(op->node, 0); | |
1289 | if (!fdev->regs) { | |
1290 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1291 | err = -ENOMEM; | |
1292 | goto out_free_fdev; | |
173acc7c ZW |
1293 | } |
1294 | ||
d3f620b2 IS |
1295 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
1296 | fdev->irq = irq_of_parse_and_map(op->node, 0); | |
1297 | ||
173acc7c ZW |
1298 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1299 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
bbea0b6e | 1300 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1301 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1302 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1303 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c ZW |
1304 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
1305 | fdev->common.device_is_tx_complete = fsl_dma_is_complete; | |
1306 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; | |
bbea0b6e IS |
1307 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
1308 | fdev->common.device_terminate_all = fsl_dma_device_terminate_all; | |
e7a29151 | 1309 | fdev->common.dev = &op->dev; |
173acc7c | 1310 | |
e7a29151 | 1311 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1312 | |
e7a29151 IS |
1313 | /* |
1314 | * We cannot use of_platform_bus_probe() because there is no | |
1315 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1316 | * channel object. |
1317 | */ | |
e7a29151 IS |
1318 | for_each_child_of_node(op->node, child) { |
1319 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { | |
77cd62e8 TT |
1320 | fsl_dma_chan_probe(fdev, child, |
1321 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1322 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1323 | } |
1324 | ||
1325 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1326 | fsl_dma_chan_probe(fdev, child, |
1327 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1328 | "fsl,elo-dma-channel"); | |
e7a29151 | 1329 | } |
77cd62e8 | 1330 | } |
173acc7c | 1331 | |
d3f620b2 IS |
1332 | /* |
1333 | * Hookup the IRQ handler(s) | |
1334 | * | |
1335 | * If we have a per-controller interrupt, we prefer that to the | |
1336 | * per-channel interrupts to reduce the number of shared interrupt | |
1337 | * handlers on the same IRQ line | |
1338 | */ | |
1339 | err = fsldma_request_irqs(fdev); | |
1340 | if (err) { | |
1341 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1342 | goto out_free_fdev; | |
1343 | } | |
1344 | ||
173acc7c ZW |
1345 | dma_async_device_register(&fdev->common); |
1346 | return 0; | |
1347 | ||
e7a29151 | 1348 | out_free_fdev: |
d3f620b2 | 1349 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1350 | kfree(fdev); |
e7a29151 | 1351 | out_return: |
173acc7c ZW |
1352 | return err; |
1353 | } | |
1354 | ||
e7a29151 | 1355 | static int fsldma_of_remove(struct of_device *op) |
77cd62e8 | 1356 | { |
a4f56d4b | 1357 | struct fsldma_device *fdev; |
77cd62e8 TT |
1358 | unsigned int i; |
1359 | ||
e7a29151 | 1360 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1361 | dma_async_device_unregister(&fdev->common); |
1362 | ||
d3f620b2 IS |
1363 | fsldma_free_irqs(fdev); |
1364 | ||
e7a29151 | 1365 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1366 | if (fdev->chan[i]) |
1367 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1368 | } |
77cd62e8 | 1369 | |
e7a29151 IS |
1370 | iounmap(fdev->regs); |
1371 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1372 | kfree(fdev); |
77cd62e8 TT |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
a4f56d4b | 1377 | static struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1378 | { .compatible = "fsl,eloplus-dma", }, |
1379 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1380 | {} |
1381 | }; | |
1382 | ||
a4f56d4b IS |
1383 | static struct of_platform_driver fsldma_of_driver = { |
1384 | .name = "fsl-elo-dma", | |
1385 | .match_table = fsldma_of_ids, | |
1386 | .probe = fsldma_of_probe, | |
1387 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1388 | }; |
1389 | ||
a4f56d4b IS |
1390 | /*----------------------------------------------------------------------------*/ |
1391 | /* Module Init / Exit */ | |
1392 | /*----------------------------------------------------------------------------*/ | |
1393 | ||
1394 | static __init int fsldma_init(void) | |
173acc7c | 1395 | { |
77cd62e8 TT |
1396 | int ret; |
1397 | ||
1398 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1399 | ||
a4f56d4b | 1400 | ret = of_register_platform_driver(&fsldma_of_driver); |
77cd62e8 TT |
1401 | if (ret) |
1402 | pr_err("fsldma: failed to register platform driver\n"); | |
1403 | ||
1404 | return ret; | |
1405 | } | |
1406 | ||
a4f56d4b | 1407 | static void __exit fsldma_exit(void) |
77cd62e8 | 1408 | { |
a4f56d4b | 1409 | of_unregister_platform_driver(&fsldma_of_driver); |
173acc7c ZW |
1410 | } |
1411 | ||
a4f56d4b IS |
1412 | subsys_initcall(fsldma_init); |
1413 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1414 | |
1415 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1416 | MODULE_LICENSE("GPL"); |