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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
4 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
13 | * The support for MPC8349 DMA contorller is also added. | |
14 | * | |
15 | * This is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dmaengine.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/dmapool.h> | |
30 | #include <linux/of_platform.h> | |
31 | ||
32 | #include "fsldma.h" | |
33 | ||
34 | static void dma_init(struct fsl_dma_chan *fsl_chan) | |
35 | { | |
36 | /* Reset the channel */ | |
37 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); | |
38 | ||
39 | switch (fsl_chan->feature & FSL_DMA_IP_MASK) { | |
40 | case FSL_DMA_IP_85XX: | |
41 | /* Set the channel to below modes: | |
42 | * EIE - Error interrupt enable | |
43 | * EOSIE - End of segments interrupt enable (basic mode) | |
44 | * EOLNIE - End of links interrupt enable | |
45 | */ | |
46 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE | |
47 | | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); | |
48 | break; | |
49 | case FSL_DMA_IP_83XX: | |
50 | /* Set the channel to below modes: | |
51 | * EOTIE - End-of-transfer interrupt enable | |
52 | */ | |
53 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE, | |
54 | 32); | |
55 | break; | |
56 | } | |
57 | ||
58 | } | |
59 | ||
56822843 | 60 | static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) |
173acc7c ZW |
61 | { |
62 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); | |
63 | } | |
64 | ||
56822843 | 65 | static u32 get_sr(struct fsl_dma_chan *fsl_chan) |
173acc7c ZW |
66 | { |
67 | return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); | |
68 | } | |
69 | ||
70 | static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, | |
71 | struct fsl_dma_ld_hw *hw, u32 count) | |
72 | { | |
73 | hw->count = CPU_TO_DMA(fsl_chan, count, 32); | |
74 | } | |
75 | ||
76 | static void set_desc_src(struct fsl_dma_chan *fsl_chan, | |
77 | struct fsl_dma_ld_hw *hw, dma_addr_t src) | |
78 | { | |
79 | u64 snoop_bits; | |
80 | ||
81 | snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
82 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; | |
83 | hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); | |
84 | } | |
85 | ||
86 | static void set_desc_dest(struct fsl_dma_chan *fsl_chan, | |
87 | struct fsl_dma_ld_hw *hw, dma_addr_t dest) | |
88 | { | |
89 | u64 snoop_bits; | |
90 | ||
91 | snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) | |
92 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; | |
93 | hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); | |
94 | } | |
95 | ||
96 | static void set_desc_next(struct fsl_dma_chan *fsl_chan, | |
97 | struct fsl_dma_ld_hw *hw, dma_addr_t next) | |
98 | { | |
99 | u64 snoop_bits; | |
100 | ||
101 | snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) | |
102 | ? FSL_DMA_SNEN : 0; | |
103 | hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); | |
104 | } | |
105 | ||
106 | static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) | |
107 | { | |
108 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); | |
109 | } | |
110 | ||
111 | static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) | |
112 | { | |
113 | return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; | |
114 | } | |
115 | ||
116 | static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) | |
117 | { | |
118 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); | |
119 | } | |
120 | ||
121 | static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) | |
122 | { | |
123 | return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); | |
124 | } | |
125 | ||
f79abb62 ZW |
126 | static u32 get_bcr(struct fsl_dma_chan *fsl_chan) |
127 | { | |
128 | return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); | |
129 | } | |
130 | ||
173acc7c ZW |
131 | static int dma_is_idle(struct fsl_dma_chan *fsl_chan) |
132 | { | |
133 | u32 sr = get_sr(fsl_chan); | |
134 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); | |
135 | } | |
136 | ||
137 | static void dma_start(struct fsl_dma_chan *fsl_chan) | |
138 | { | |
139 | u32 mr_set = 0;; | |
140 | ||
141 | if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
142 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); | |
143 | mr_set |= FSL_DMA_MR_EMP_EN; | |
144 | } else | |
145 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
146 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | |
147 | & ~FSL_DMA_MR_EMP_EN, 32); | |
148 | ||
149 | if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) | |
150 | mr_set |= FSL_DMA_MR_EMS_EN; | |
151 | else | |
152 | mr_set |= FSL_DMA_MR_CS; | |
153 | ||
154 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
155 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | |
156 | | mr_set, 32); | |
157 | } | |
158 | ||
159 | static void dma_halt(struct fsl_dma_chan *fsl_chan) | |
160 | { | |
900325a6 DW |
161 | int i; |
162 | ||
173acc7c ZW |
163 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, |
164 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, | |
165 | 32); | |
166 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
167 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS | |
168 | | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); | |
169 | ||
900325a6 DW |
170 | for (i = 0; i < 100; i++) { |
171 | if (dma_is_idle(fsl_chan)) | |
172 | break; | |
173acc7c | 173 | udelay(10); |
900325a6 | 174 | } |
173acc7c ZW |
175 | if (i >= 100 && !dma_is_idle(fsl_chan)) |
176 | dev_err(fsl_chan->dev, "DMA halt timeout!\n"); | |
177 | } | |
178 | ||
179 | static void set_ld_eol(struct fsl_dma_chan *fsl_chan, | |
180 | struct fsl_desc_sw *desc) | |
181 | { | |
182 | desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, | |
183 | DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL, | |
184 | 64); | |
185 | } | |
186 | ||
187 | static void append_ld_queue(struct fsl_dma_chan *fsl_chan, | |
188 | struct fsl_desc_sw *new_desc) | |
189 | { | |
190 | struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); | |
191 | ||
192 | if (list_empty(&fsl_chan->ld_queue)) | |
193 | return; | |
194 | ||
195 | /* Link to the new descriptor physical address and | |
196 | * Enable End-of-segment interrupt for | |
197 | * the last link descriptor. | |
198 | * (the previous node's next link descriptor) | |
199 | * | |
200 | * For FSL_DMA_IP_83xx, the snoop enable bit need be set. | |
201 | */ | |
202 | queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, | |
203 | new_desc->async_tx.phys | FSL_DMA_EOSIE | | |
204 | (((fsl_chan->feature & FSL_DMA_IP_MASK) | |
205 | == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); | |
206 | } | |
207 | ||
208 | /** | |
209 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
210 | * @fsl_chan : Freescale DMA channel | |
211 | * @size : Address loop size, 0 for disable loop | |
212 | * | |
213 | * The set source address hold transfer size. The source | |
214 | * address hold or loop transfer size is when the DMA transfer | |
215 | * data from source address (SA), if the loop size is 4, the DMA will | |
216 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
217 | * SA + 1 ... and so on. | |
218 | */ | |
219 | static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) | |
220 | { | |
221 | switch (size) { | |
222 | case 0: | |
223 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
224 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & | |
225 | (~FSL_DMA_MR_SAHE), 32); | |
226 | break; | |
227 | case 1: | |
228 | case 2: | |
229 | case 4: | |
230 | case 8: | |
231 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
232 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | | |
233 | FSL_DMA_MR_SAHE | (__ilog2(size) << 14), | |
234 | 32); | |
235 | break; | |
236 | } | |
237 | } | |
238 | ||
239 | /** | |
240 | * fsl_chan_set_dest_loop_size - Set destination address hold transfer size | |
241 | * @fsl_chan : Freescale DMA channel | |
242 | * @size : Address loop size, 0 for disable loop | |
243 | * | |
244 | * The set destination address hold transfer size. The destination | |
245 | * address hold or loop transfer size is when the DMA transfer | |
246 | * data to destination address (TA), if the loop size is 4, the DMA will | |
247 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
248 | * TA + 1 ... and so on. | |
249 | */ | |
250 | static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) | |
251 | { | |
252 | switch (size) { | |
253 | case 0: | |
254 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
255 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & | |
256 | (~FSL_DMA_MR_DAHE), 32); | |
257 | break; | |
258 | case 1: | |
259 | case 2: | |
260 | case 4: | |
261 | case 8: | |
262 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
263 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | | |
264 | FSL_DMA_MR_DAHE | (__ilog2(size) << 16), | |
265 | 32); | |
266 | break; | |
267 | } | |
268 | } | |
269 | ||
270 | /** | |
271 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
272 | * @fsl_chan : Freescale DMA channel | |
273 | * @size : Pause control size, 0 for disable external pause control. | |
274 | * The maximum is 1024. | |
275 | * | |
276 | * The Freescale DMA channel can be controlled by the external | |
277 | * signal DREQ#. The pause control size is how many bytes are allowed | |
278 | * to transfer before pausing the channel, after which a new assertion | |
279 | * of DREQ# resumes channel operation. | |
280 | */ | |
281 | static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) | |
282 | { | |
283 | if (size > 1024) | |
284 | return; | |
285 | ||
286 | if (size) { | |
287 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | |
288 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | |
289 | | ((__ilog2(size) << 24) & 0x0f000000), | |
290 | 32); | |
291 | fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; | |
292 | } else | |
293 | fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; | |
294 | } | |
295 | ||
296 | /** | |
297 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
298 | * @fsl_chan : Freescale DMA channel | |
299 | * @enable : 0 is disabled, 1 is enabled. | |
300 | * | |
301 | * If enable the external start, the channel can be started by an | |
302 | * external DMA start pin. So the dma_start() does not start the | |
303 | * transfer immediately. The DMA channel will wait for the | |
304 | * control pin asserted. | |
305 | */ | |
306 | static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) | |
307 | { | |
308 | if (enable) | |
309 | fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; | |
310 | else | |
311 | fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; | |
312 | } | |
313 | ||
314 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
315 | { | |
173acc7c | 316 | struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); |
bcfb7465 | 317 | struct fsl_desc_sw *desc; |
173acc7c ZW |
318 | unsigned long flags; |
319 | dma_cookie_t cookie; | |
320 | ||
321 | /* cookie increment and adding to ld_queue must be atomic */ | |
322 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); | |
323 | ||
324 | cookie = fsl_chan->common.cookie; | |
bcfb7465 IS |
325 | list_for_each_entry(desc, &tx->tx_list, node) { |
326 | cookie++; | |
327 | if (cookie < 0) | |
328 | cookie = 1; | |
329 | ||
330 | desc->async_tx.cookie = cookie; | |
331 | } | |
332 | ||
333 | fsl_chan->common.cookie = cookie; | |
334 | append_ld_queue(fsl_chan, tx_to_fsl_desc(tx)); | |
335 | list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev); | |
173acc7c ZW |
336 | |
337 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
338 | ||
339 | return cookie; | |
340 | } | |
341 | ||
342 | /** | |
343 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
344 | * @fsl_chan : Freescale DMA channel | |
345 | * | |
346 | * Return - The descriptor allocated. NULL for failed. | |
347 | */ | |
348 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
349 | struct fsl_dma_chan *fsl_chan) | |
350 | { | |
351 | dma_addr_t pdesc; | |
352 | struct fsl_desc_sw *desc_sw; | |
353 | ||
354 | desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); | |
355 | if (desc_sw) { | |
356 | memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); | |
357 | dma_async_tx_descriptor_init(&desc_sw->async_tx, | |
358 | &fsl_chan->common); | |
359 | desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; | |
173acc7c ZW |
360 | desc_sw->async_tx.phys = pdesc; |
361 | } | |
362 | ||
363 | return desc_sw; | |
364 | } | |
365 | ||
366 | ||
367 | /** | |
368 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
369 | * @fsl_chan : Freescale DMA channel | |
370 | * | |
371 | * This function will create a dma pool for descriptor allocation. | |
372 | * | |
373 | * Return - The number of descriptors allocated. | |
374 | */ | |
aa1e6f1a | 375 | static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) |
173acc7c ZW |
376 | { |
377 | struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); | |
77cd62e8 TT |
378 | |
379 | /* Has this channel already been allocated? */ | |
380 | if (fsl_chan->desc_pool) | |
381 | return 1; | |
173acc7c ZW |
382 | |
383 | /* We need the descriptor to be aligned to 32bytes | |
384 | * for meeting FSL DMA specification requirement. | |
385 | */ | |
386 | fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", | |
387 | fsl_chan->dev, sizeof(struct fsl_desc_sw), | |
388 | 32, 0); | |
389 | if (!fsl_chan->desc_pool) { | |
390 | dev_err(fsl_chan->dev, "No memory for channel %d " | |
391 | "descriptor dma pool.\n", fsl_chan->id); | |
392 | return 0; | |
393 | } | |
394 | ||
395 | return 1; | |
396 | } | |
397 | ||
398 | /** | |
399 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
400 | * @fsl_chan : Freescale DMA channel | |
401 | */ | |
402 | static void fsl_dma_free_chan_resources(struct dma_chan *chan) | |
403 | { | |
404 | struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); | |
405 | struct fsl_desc_sw *desc, *_desc; | |
406 | unsigned long flags; | |
407 | ||
408 | dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); | |
409 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); | |
410 | list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { | |
411 | #ifdef FSL_DMA_LD_DEBUG | |
412 | dev_dbg(fsl_chan->dev, | |
413 | "LD %p will be released.\n", desc); | |
414 | #endif | |
415 | list_del(&desc->node); | |
416 | /* free link descriptor */ | |
417 | dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); | |
418 | } | |
419 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
420 | dma_pool_destroy(fsl_chan->desc_pool); | |
77cd62e8 TT |
421 | |
422 | fsl_chan->desc_pool = NULL; | |
173acc7c ZW |
423 | } |
424 | ||
2187c269 | 425 | static struct dma_async_tx_descriptor * |
636bdeaa | 426 | fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) |
2187c269 ZW |
427 | { |
428 | struct fsl_dma_chan *fsl_chan; | |
429 | struct fsl_desc_sw *new; | |
430 | ||
431 | if (!chan) | |
432 | return NULL; | |
433 | ||
434 | fsl_chan = to_fsl_chan(chan); | |
435 | ||
436 | new = fsl_dma_alloc_descriptor(fsl_chan); | |
437 | if (!new) { | |
438 | dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); | |
439 | return NULL; | |
440 | } | |
441 | ||
442 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 443 | new->async_tx.flags = flags; |
2187c269 | 444 | |
f79abb62 ZW |
445 | /* Insert the link descriptor to the LD ring */ |
446 | list_add_tail(&new->node, &new->async_tx.tx_list); | |
447 | ||
2187c269 ZW |
448 | /* Set End-of-link to the last link descriptor of new list*/ |
449 | set_ld_eol(fsl_chan, new); | |
450 | ||
451 | return &new->async_tx; | |
452 | } | |
453 | ||
173acc7c ZW |
454 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
455 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
456 | size_t len, unsigned long flags) | |
457 | { | |
458 | struct fsl_dma_chan *fsl_chan; | |
459 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; | |
460 | size_t copy; | |
461 | LIST_HEAD(link_chain); | |
462 | ||
463 | if (!chan) | |
464 | return NULL; | |
465 | ||
466 | if (!len) | |
467 | return NULL; | |
468 | ||
469 | fsl_chan = to_fsl_chan(chan); | |
470 | ||
471 | do { | |
472 | ||
473 | /* Allocate the link descriptor from DMA pool */ | |
474 | new = fsl_dma_alloc_descriptor(fsl_chan); | |
475 | if (!new) { | |
476 | dev_err(fsl_chan->dev, | |
477 | "No free memory for link descriptor\n"); | |
478 | return NULL; | |
479 | } | |
480 | #ifdef FSL_DMA_LD_DEBUG | |
481 | dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); | |
482 | #endif | |
483 | ||
56822843 | 484 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c ZW |
485 | |
486 | set_desc_cnt(fsl_chan, &new->hw, copy); | |
487 | set_desc_src(fsl_chan, &new->hw, dma_src); | |
488 | set_desc_dest(fsl_chan, &new->hw, dma_dest); | |
489 | ||
490 | if (!first) | |
491 | first = new; | |
492 | else | |
493 | set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); | |
494 | ||
495 | new->async_tx.cookie = 0; | |
636bdeaa | 496 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
497 | |
498 | prev = new; | |
499 | len -= copy; | |
500 | dma_src += copy; | |
501 | dma_dest += copy; | |
502 | ||
503 | /* Insert the link descriptor to the LD ring */ | |
504 | list_add_tail(&new->node, &first->async_tx.tx_list); | |
505 | } while (len); | |
506 | ||
636bdeaa | 507 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
508 | new->async_tx.cookie = -EBUSY; |
509 | ||
510 | /* Set End-of-link to the last link descriptor of new list*/ | |
511 | set_ld_eol(fsl_chan, new); | |
512 | ||
513 | return first ? &first->async_tx : NULL; | |
514 | } | |
515 | ||
516 | /** | |
517 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
518 | * @fsl_chan : Freescale DMA channel | |
519 | */ | |
520 | static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) | |
521 | { | |
522 | struct fsl_desc_sw *cur_desc, *desc; | |
523 | dma_addr_t ld_phy; | |
524 | ||
525 | ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; | |
526 | ||
527 | if (ld_phy) { | |
528 | cur_desc = NULL; | |
529 | list_for_each_entry(desc, &fsl_chan->ld_queue, node) | |
530 | if (desc->async_tx.phys == ld_phy) { | |
531 | cur_desc = desc; | |
532 | break; | |
533 | } | |
534 | ||
535 | if (cur_desc && cur_desc->async_tx.cookie) { | |
536 | if (dma_is_idle(fsl_chan)) | |
537 | fsl_chan->completed_cookie = | |
538 | cur_desc->async_tx.cookie; | |
539 | else | |
540 | fsl_chan->completed_cookie = | |
541 | cur_desc->async_tx.cookie - 1; | |
542 | } | |
543 | } | |
544 | } | |
545 | ||
546 | /** | |
547 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
548 | * @fsl_chan : Freescale DMA channel | |
549 | * | |
550 | * This function clean up the ld_queue of DMA channel. | |
551 | * If 'in_intr' is set, the function will move the link descriptor to | |
552 | * the recycle list. Otherwise, free it directly. | |
553 | */ | |
554 | static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) | |
555 | { | |
556 | struct fsl_desc_sw *desc, *_desc; | |
557 | unsigned long flags; | |
558 | ||
559 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); | |
560 | ||
173acc7c ZW |
561 | dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", |
562 | fsl_chan->completed_cookie); | |
563 | list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { | |
564 | dma_async_tx_callback callback; | |
565 | void *callback_param; | |
566 | ||
567 | if (dma_async_is_complete(desc->async_tx.cookie, | |
568 | fsl_chan->completed_cookie, fsl_chan->common.cookie) | |
569 | == DMA_IN_PROGRESS) | |
570 | break; | |
571 | ||
572 | callback = desc->async_tx.callback; | |
573 | callback_param = desc->async_tx.callback_param; | |
574 | ||
575 | /* Remove from ld_queue list */ | |
576 | list_del(&desc->node); | |
577 | ||
578 | dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", | |
579 | desc); | |
580 | dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); | |
581 | ||
582 | /* Run the link descriptor callback function */ | |
583 | if (callback) { | |
584 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
585 | dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", | |
586 | desc); | |
587 | callback(callback_param); | |
588 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); | |
589 | } | |
590 | } | |
591 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
592 | } | |
593 | ||
594 | /** | |
595 | * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. | |
596 | * @fsl_chan : Freescale DMA channel | |
597 | */ | |
598 | static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) | |
599 | { | |
600 | struct list_head *ld_node; | |
601 | dma_addr_t next_dest_addr; | |
602 | unsigned long flags; | |
603 | ||
138ef018 IS |
604 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); |
605 | ||
173acc7c | 606 | if (!dma_is_idle(fsl_chan)) |
138ef018 | 607 | goto out_unlock; |
173acc7c ZW |
608 | |
609 | dma_halt(fsl_chan); | |
610 | ||
611 | /* If there are some link descriptors | |
612 | * not transfered in queue. We need to start it. | |
613 | */ | |
173acc7c ZW |
614 | |
615 | /* Find the first un-transfer desciptor */ | |
616 | for (ld_node = fsl_chan->ld_queue.next; | |
617 | (ld_node != &fsl_chan->ld_queue) | |
618 | && (dma_async_is_complete( | |
619 | to_fsl_desc(ld_node)->async_tx.cookie, | |
620 | fsl_chan->completed_cookie, | |
621 | fsl_chan->common.cookie) == DMA_SUCCESS); | |
622 | ld_node = ld_node->next); | |
623 | ||
173acc7c ZW |
624 | if (ld_node != &fsl_chan->ld_queue) { |
625 | /* Get the ld start address from ld_queue */ | |
626 | next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; | |
56822843 ZW |
627 | dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n", |
628 | (void *)next_dest_addr); | |
173acc7c ZW |
629 | set_cdar(fsl_chan, next_dest_addr); |
630 | dma_start(fsl_chan); | |
631 | } else { | |
632 | set_cdar(fsl_chan, 0); | |
633 | set_ndar(fsl_chan, 0); | |
634 | } | |
138ef018 IS |
635 | |
636 | out_unlock: | |
637 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
173acc7c ZW |
638 | } |
639 | ||
640 | /** | |
641 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
642 | * @fsl_chan : Freescale DMA channel | |
643 | */ | |
644 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) | |
645 | { | |
646 | struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); | |
647 | ||
648 | #ifdef FSL_DMA_LD_DEBUG | |
649 | struct fsl_desc_sw *ld; | |
650 | unsigned long flags; | |
651 | ||
652 | spin_lock_irqsave(&fsl_chan->desc_lock, flags); | |
653 | if (list_empty(&fsl_chan->ld_queue)) { | |
654 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
655 | return; | |
656 | } | |
657 | ||
658 | dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); | |
659 | list_for_each_entry(ld, &fsl_chan->ld_queue, node) { | |
660 | int i; | |
661 | dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", | |
662 | fsl_chan->id, ld->async_tx.phys); | |
663 | for (i = 0; i < 8; i++) | |
664 | dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", | |
665 | i, *(((u32 *)&ld->hw) + i)); | |
666 | } | |
667 | dev_dbg(fsl_chan->dev, "----------------\n"); | |
668 | spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); | |
669 | #endif | |
670 | ||
671 | fsl_chan_xfer_ld_queue(fsl_chan); | |
672 | } | |
673 | ||
173acc7c ZW |
674 | /** |
675 | * fsl_dma_is_complete - Determine the DMA status | |
676 | * @fsl_chan : Freescale DMA channel | |
677 | */ | |
678 | static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, | |
679 | dma_cookie_t cookie, | |
680 | dma_cookie_t *done, | |
681 | dma_cookie_t *used) | |
682 | { | |
683 | struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); | |
684 | dma_cookie_t last_used; | |
685 | dma_cookie_t last_complete; | |
686 | ||
687 | fsl_chan_ld_cleanup(fsl_chan); | |
688 | ||
689 | last_used = chan->cookie; | |
690 | last_complete = fsl_chan->completed_cookie; | |
691 | ||
692 | if (done) | |
693 | *done = last_complete; | |
694 | ||
695 | if (used) | |
696 | *used = last_used; | |
697 | ||
698 | return dma_async_is_complete(cookie, last_complete, last_used); | |
699 | } | |
700 | ||
701 | static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) | |
702 | { | |
703 | struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; | |
56822843 | 704 | u32 stat; |
1c62979e ZW |
705 | int update_cookie = 0; |
706 | int xfer_ld_q = 0; | |
173acc7c ZW |
707 | |
708 | stat = get_sr(fsl_chan); | |
709 | dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", | |
710 | fsl_chan->id, stat); | |
711 | set_sr(fsl_chan, stat); /* Clear the event register */ | |
712 | ||
713 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
714 | if (!stat) | |
715 | return IRQ_NONE; | |
716 | ||
717 | if (stat & FSL_DMA_SR_TE) | |
718 | dev_err(fsl_chan->dev, "Transfer Error!\n"); | |
719 | ||
f79abb62 ZW |
720 | /* Programming Error |
721 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will | |
722 | * triger a PE interrupt. | |
723 | */ | |
724 | if (stat & FSL_DMA_SR_PE) { | |
725 | dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); | |
726 | if (get_bcr(fsl_chan) == 0) { | |
727 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. | |
728 | * Now, update the completed cookie, and continue the | |
729 | * next uncompleted transfer. | |
730 | */ | |
1c62979e ZW |
731 | update_cookie = 1; |
732 | xfer_ld_q = 1; | |
f79abb62 ZW |
733 | } |
734 | stat &= ~FSL_DMA_SR_PE; | |
735 | } | |
736 | ||
173acc7c ZW |
737 | /* If the link descriptor segment transfer finishes, |
738 | * we will recycle the used descriptor. | |
739 | */ | |
740 | if (stat & FSL_DMA_SR_EOSI) { | |
741 | dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); | |
56822843 ZW |
742 | dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n", |
743 | (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan)); | |
173acc7c | 744 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
745 | update_cookie = 1; |
746 | } | |
747 | ||
748 | /* For MPC8349, EOCDI event need to update cookie | |
749 | * and start the next transfer if it exist. | |
750 | */ | |
751 | if (stat & FSL_DMA_SR_EOCDI) { | |
752 | dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); | |
753 | stat &= ~FSL_DMA_SR_EOCDI; | |
754 | update_cookie = 1; | |
755 | xfer_ld_q = 1; | |
173acc7c ZW |
756 | } |
757 | ||
758 | /* If it current transfer is the end-of-transfer, | |
759 | * we should clear the Channel Start bit for | |
760 | * prepare next transfer. | |
761 | */ | |
1c62979e | 762 | if (stat & FSL_DMA_SR_EOLNI) { |
173acc7c ZW |
763 | dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); |
764 | stat &= ~FSL_DMA_SR_EOLNI; | |
1c62979e | 765 | xfer_ld_q = 1; |
173acc7c ZW |
766 | } |
767 | ||
1c62979e ZW |
768 | if (update_cookie) |
769 | fsl_dma_update_completed_cookie(fsl_chan); | |
770 | if (xfer_ld_q) | |
771 | fsl_chan_xfer_ld_queue(fsl_chan); | |
173acc7c ZW |
772 | if (stat) |
773 | dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", | |
774 | stat); | |
775 | ||
776 | dev_dbg(fsl_chan->dev, "event: Exit\n"); | |
777 | tasklet_schedule(&fsl_chan->tasklet); | |
778 | return IRQ_HANDLED; | |
779 | } | |
780 | ||
781 | static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) | |
782 | { | |
783 | struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; | |
784 | u32 gsr; | |
785 | int ch_nr; | |
786 | ||
787 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) | |
788 | : in_le32(fdev->reg_base); | |
789 | ch_nr = (32 - ffs(gsr)) / 8; | |
790 | ||
791 | return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, | |
792 | fdev->chan[ch_nr]) : IRQ_NONE; | |
793 | } | |
794 | ||
795 | static void dma_do_tasklet(unsigned long data) | |
796 | { | |
797 | struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; | |
798 | fsl_chan_ld_cleanup(fsl_chan); | |
799 | } | |
800 | ||
77cd62e8 TT |
801 | static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, |
802 | struct device_node *node, u32 feature, const char *compatible) | |
173acc7c | 803 | { |
173acc7c ZW |
804 | struct fsl_dma_chan *new_fsl_chan; |
805 | int err; | |
806 | ||
173acc7c ZW |
807 | /* alloc channel */ |
808 | new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); | |
809 | if (!new_fsl_chan) { | |
77cd62e8 | 810 | dev_err(fdev->dev, "No free memory for allocating " |
173acc7c | 811 | "dma channels!\n"); |
51ee87f2 | 812 | return -ENOMEM; |
173acc7c ZW |
813 | } |
814 | ||
815 | /* get dma channel register base */ | |
77cd62e8 | 816 | err = of_address_to_resource(node, 0, &new_fsl_chan->reg); |
173acc7c | 817 | if (err) { |
77cd62e8 TT |
818 | dev_err(fdev->dev, "Can't get %s property 'reg'\n", |
819 | node->full_name); | |
51ee87f2 | 820 | goto err_no_reg; |
173acc7c ZW |
821 | } |
822 | ||
77cd62e8 | 823 | new_fsl_chan->feature = feature; |
173acc7c ZW |
824 | |
825 | if (!fdev->feature) | |
826 | fdev->feature = new_fsl_chan->feature; | |
827 | ||
828 | /* If the DMA device's feature is different than its channels', | |
829 | * report the bug. | |
830 | */ | |
831 | WARN_ON(fdev->feature != new_fsl_chan->feature); | |
832 | ||
6527de6d | 833 | new_fsl_chan->dev = fdev->dev; |
173acc7c ZW |
834 | new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, |
835 | new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); | |
836 | ||
837 | new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; | |
f47edc6d | 838 | if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
77cd62e8 | 839 | dev_err(fdev->dev, "There is no %d channel!\n", |
173acc7c ZW |
840 | new_fsl_chan->id); |
841 | err = -EINVAL; | |
51ee87f2 | 842 | goto err_no_chan; |
173acc7c ZW |
843 | } |
844 | fdev->chan[new_fsl_chan->id] = new_fsl_chan; | |
845 | tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, | |
846 | (unsigned long)new_fsl_chan); | |
847 | ||
848 | /* Init the channel */ | |
849 | dma_init(new_fsl_chan); | |
850 | ||
851 | /* Clear cdar registers */ | |
852 | set_cdar(new_fsl_chan, 0); | |
853 | ||
854 | switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { | |
855 | case FSL_DMA_IP_85XX: | |
856 | new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; | |
857 | new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; | |
858 | case FSL_DMA_IP_83XX: | |
859 | new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
860 | new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; | |
861 | } | |
862 | ||
863 | spin_lock_init(&new_fsl_chan->desc_lock); | |
864 | INIT_LIST_HEAD(&new_fsl_chan->ld_queue); | |
865 | ||
866 | new_fsl_chan->common.device = &fdev->common; | |
867 | ||
868 | /* Add the channel to DMA device channel list */ | |
869 | list_add_tail(&new_fsl_chan->common.device_node, | |
870 | &fdev->common.channels); | |
871 | fdev->common.chancnt++; | |
872 | ||
77cd62e8 | 873 | new_fsl_chan->irq = irq_of_parse_and_map(node, 0); |
173acc7c ZW |
874 | if (new_fsl_chan->irq != NO_IRQ) { |
875 | err = request_irq(new_fsl_chan->irq, | |
876 | &fsl_dma_chan_do_interrupt, IRQF_SHARED, | |
877 | "fsldma-channel", new_fsl_chan); | |
878 | if (err) { | |
77cd62e8 TT |
879 | dev_err(fdev->dev, "DMA channel %s request_irq error " |
880 | "with return %d\n", node->full_name, err); | |
51ee87f2 | 881 | goto err_no_irq; |
173acc7c ZW |
882 | } |
883 | } | |
884 | ||
77cd62e8 | 885 | dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, |
169d5f66 PK |
886 | compatible, |
887 | new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); | |
173acc7c ZW |
888 | |
889 | return 0; | |
51ee87f2 | 890 | |
51ee87f2 | 891 | err_no_irq: |
173acc7c | 892 | list_del(&new_fsl_chan->common.device_node); |
51ee87f2 LY |
893 | err_no_chan: |
894 | iounmap(new_fsl_chan->reg_base); | |
895 | err_no_reg: | |
173acc7c ZW |
896 | kfree(new_fsl_chan); |
897 | return err; | |
898 | } | |
899 | ||
77cd62e8 | 900 | static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) |
173acc7c | 901 | { |
6782dfe4 PK |
902 | if (fchan->irq != NO_IRQ) |
903 | free_irq(fchan->irq, fchan); | |
77cd62e8 TT |
904 | list_del(&fchan->common.device_node); |
905 | iounmap(fchan->reg_base); | |
906 | kfree(fchan); | |
173acc7c ZW |
907 | } |
908 | ||
909 | static int __devinit of_fsl_dma_probe(struct of_device *dev, | |
910 | const struct of_device_id *match) | |
911 | { | |
912 | int err; | |
173acc7c | 913 | struct fsl_dma_device *fdev; |
77cd62e8 | 914 | struct device_node *child; |
173acc7c ZW |
915 | |
916 | fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); | |
917 | if (!fdev) { | |
918 | dev_err(&dev->dev, "No enough memory for 'priv'\n"); | |
51ee87f2 | 919 | return -ENOMEM; |
173acc7c ZW |
920 | } |
921 | fdev->dev = &dev->dev; | |
922 | INIT_LIST_HEAD(&fdev->common.channels); | |
923 | ||
924 | /* get DMA controller register base */ | |
925 | err = of_address_to_resource(dev->node, 0, &fdev->reg); | |
926 | if (err) { | |
927 | dev_err(&dev->dev, "Can't get %s property 'reg'\n", | |
928 | dev->node->full_name); | |
51ee87f2 | 929 | goto err_no_reg; |
173acc7c ZW |
930 | } |
931 | ||
932 | dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " | |
56822843 ZW |
933 | "controller at %p...\n", |
934 | match->compatible, (void *)fdev->reg.start); | |
173acc7c ZW |
935 | fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end |
936 | - fdev->reg.start + 1); | |
937 | ||
938 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); | |
939 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
940 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; | |
941 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 942 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c ZW |
943 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
944 | fdev->common.device_is_tx_complete = fsl_dma_is_complete; | |
945 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; | |
173acc7c ZW |
946 | fdev->common.dev = &dev->dev; |
947 | ||
77cd62e8 TT |
948 | fdev->irq = irq_of_parse_and_map(dev->node, 0); |
949 | if (fdev->irq != NO_IRQ) { | |
950 | err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, | |
173acc7c ZW |
951 | "fsldma-device", fdev); |
952 | if (err) { | |
953 | dev_err(&dev->dev, "DMA device request_irq error " | |
954 | "with return %d\n", err); | |
955 | goto err; | |
956 | } | |
957 | } | |
958 | ||
959 | dev_set_drvdata(&(dev->dev), fdev); | |
77cd62e8 TT |
960 | |
961 | /* We cannot use of_platform_bus_probe() because there is no | |
962 | * of_platform_bus_remove. Instead, we manually instantiate every DMA | |
963 | * channel object. | |
964 | */ | |
965 | for_each_child_of_node(dev->node, child) { | |
966 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) | |
967 | fsl_dma_chan_probe(fdev, child, | |
968 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
969 | "fsl,eloplus-dma-channel"); | |
970 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) | |
971 | fsl_dma_chan_probe(fdev, child, | |
972 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
973 | "fsl,elo-dma-channel"); | |
974 | } | |
173acc7c ZW |
975 | |
976 | dma_async_device_register(&fdev->common); | |
977 | return 0; | |
978 | ||
979 | err: | |
980 | iounmap(fdev->reg_base); | |
51ee87f2 | 981 | err_no_reg: |
173acc7c ZW |
982 | kfree(fdev); |
983 | return err; | |
984 | } | |
985 | ||
77cd62e8 TT |
986 | static int of_fsl_dma_remove(struct of_device *of_dev) |
987 | { | |
988 | struct fsl_dma_device *fdev; | |
989 | unsigned int i; | |
990 | ||
991 | fdev = dev_get_drvdata(&of_dev->dev); | |
992 | ||
993 | dma_async_device_unregister(&fdev->common); | |
994 | ||
995 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) | |
996 | if (fdev->chan[i]) | |
997 | fsl_dma_chan_remove(fdev->chan[i]); | |
998 | ||
999 | if (fdev->irq != NO_IRQ) | |
1000 | free_irq(fdev->irq, fdev); | |
1001 | ||
1002 | iounmap(fdev->reg_base); | |
1003 | ||
1004 | kfree(fdev); | |
1005 | dev_set_drvdata(&of_dev->dev, NULL); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
173acc7c | 1010 | static struct of_device_id of_fsl_dma_ids[] = { |
049c9d45 KG |
1011 | { .compatible = "fsl,eloplus-dma", }, |
1012 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1013 | {} |
1014 | }; | |
1015 | ||
1016 | static struct of_platform_driver of_fsl_dma_driver = { | |
77cd62e8 | 1017 | .name = "fsl-elo-dma", |
173acc7c ZW |
1018 | .match_table = of_fsl_dma_ids, |
1019 | .probe = of_fsl_dma_probe, | |
77cd62e8 | 1020 | .remove = of_fsl_dma_remove, |
173acc7c ZW |
1021 | }; |
1022 | ||
1023 | static __init int of_fsl_dma_init(void) | |
1024 | { | |
77cd62e8 TT |
1025 | int ret; |
1026 | ||
1027 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1028 | ||
1029 | ret = of_register_platform_driver(&of_fsl_dma_driver); | |
1030 | if (ret) | |
1031 | pr_err("fsldma: failed to register platform driver\n"); | |
1032 | ||
1033 | return ret; | |
1034 | } | |
1035 | ||
1036 | static void __exit of_fsl_dma_exit(void) | |
1037 | { | |
1038 | of_unregister_platform_driver(&of_fsl_dma_driver); | |
173acc7c ZW |
1039 | } |
1040 | ||
173acc7c | 1041 | subsys_initcall(of_fsl_dma_init); |
77cd62e8 TT |
1042 | module_exit(of_fsl_dma_exit); |
1043 | ||
1044 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1045 | MODULE_LICENSE("GPL"); |