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Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
5af50730 RH |
36 | #include <linux/of_address.h> |
37 | #include <linux/of_irq.h> | |
173acc7c ZW |
38 | #include <linux/of_platform.h> |
39 | ||
d2ebfb33 | 40 | #include "dmaengine.h" |
173acc7c ZW |
41 | #include "fsldma.h" |
42 | ||
b158471e IS |
43 | #define chan_dbg(chan, fmt, arg...) \ |
44 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
45 | #define chan_err(chan, fmt, arg...) \ | |
46 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 47 | |
b158471e | 48 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 49 | |
e8bd84df IS |
50 | /* |
51 | * Register Helpers | |
52 | */ | |
173acc7c | 53 | |
a1c03319 | 54 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 55 | { |
a1c03319 | 56 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
57 | } |
58 | ||
a1c03319 | 59 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 60 | { |
a1c03319 | 61 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
62 | } |
63 | ||
e8bd84df IS |
64 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
65 | { | |
66 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
67 | } | |
68 | ||
69 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
70 | { | |
71 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
72 | } | |
73 | ||
e8bd84df IS |
74 | static u32 get_bcr(struct fsldma_chan *chan) |
75 | { | |
76 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
77 | } | |
78 | ||
79 | /* | |
80 | * Descriptor Helpers | |
81 | */ | |
82 | ||
a1c03319 | 83 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
84 | struct fsl_dma_ld_hw *hw, u32 count) |
85 | { | |
a1c03319 | 86 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
87 | } |
88 | ||
a1c03319 | 89 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 90 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
91 | { |
92 | u64 snoop_bits; | |
93 | ||
a1c03319 | 94 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 95 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 96 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
97 | } |
98 | ||
a1c03319 | 99 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 100 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
101 | { |
102 | u64 snoop_bits; | |
103 | ||
a1c03319 | 104 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 105 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 106 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
107 | } |
108 | ||
a1c03319 | 109 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 110 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
111 | { |
112 | u64 snoop_bits; | |
113 | ||
a1c03319 | 114 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 115 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 116 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
117 | } |
118 | ||
31f4306c | 119 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 120 | { |
e8bd84df | 121 | u64 snoop_bits; |
173acc7c | 122 | |
e8bd84df IS |
123 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
124 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 125 | |
e8bd84df IS |
126 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
127 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
128 | | snoop_bits, 64); | |
173acc7c ZW |
129 | } |
130 | ||
e8bd84df IS |
131 | /* |
132 | * DMA Engine Hardware Control Helpers | |
133 | */ | |
134 | ||
135 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 136 | { |
e8bd84df IS |
137 | /* Reset the channel */ |
138 | DMA_OUT(chan, &chan->regs->mr, 0, 32); | |
139 | ||
140 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
141 | case FSL_DMA_IP_85XX: | |
142 | /* Set the channel to below modes: | |
143 | * EIE - Error interrupt enable | |
e8bd84df IS |
144 | * EOLNIE - End of links interrupt enable |
145 | * BWC - Bandwidth sharing among channels | |
146 | */ | |
147 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC | |
f04cd407 | 148 | | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); |
e8bd84df IS |
149 | break; |
150 | case FSL_DMA_IP_83XX: | |
151 | /* Set the channel to below modes: | |
152 | * EOTIE - End-of-transfer interrupt enable | |
153 | * PRC_RM - PCI read multiple | |
154 | */ | |
155 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE | |
156 | | FSL_DMA_MR_PRC_RM, 32); | |
157 | break; | |
158 | } | |
f79abb62 ZW |
159 | } |
160 | ||
a1c03319 | 161 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 162 | { |
a1c03319 | 163 | u32 sr = get_sr(chan); |
173acc7c ZW |
164 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
165 | } | |
166 | ||
f04cd407 IS |
167 | /* |
168 | * Start the DMA controller | |
169 | * | |
170 | * Preconditions: | |
171 | * - the CDAR register must point to the start descriptor | |
172 | * - the MRn[CS] bit must be cleared | |
173 | */ | |
a1c03319 | 174 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 175 | { |
272ca655 IS |
176 | u32 mode; |
177 | ||
a1c03319 | 178 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 179 | |
f04cd407 IS |
180 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
181 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
182 | mode |= FSL_DMA_MR_EMP_EN; | |
183 | } else { | |
184 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 185 | } |
173acc7c | 186 | |
f04cd407 | 187 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 188 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
189 | } else { |
190 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 191 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 192 | } |
173acc7c | 193 | |
a1c03319 | 194 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
195 | } |
196 | ||
a1c03319 | 197 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 198 | { |
272ca655 | 199 | u32 mode; |
900325a6 DW |
200 | int i; |
201 | ||
a00ae34a | 202 | /* read the mode register */ |
a1c03319 | 203 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 204 | |
a00ae34a IS |
205 | /* |
206 | * The 85xx controller supports channel abort, which will stop | |
207 | * the current transfer. On 83xx, this bit is the transfer error | |
208 | * mask bit, which should not be changed. | |
209 | */ | |
210 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
211 | mode |= FSL_DMA_MR_CA; | |
212 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
213 | ||
214 | mode &= ~FSL_DMA_MR_CA; | |
215 | } | |
216 | ||
217 | /* stop the DMA controller */ | |
218 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
a1c03319 | 219 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 220 | |
a00ae34a | 221 | /* wait for the DMA controller to become idle */ |
900325a6 | 222 | for (i = 0; i < 100; i++) { |
a1c03319 | 223 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
224 | return; |
225 | ||
173acc7c | 226 | udelay(10); |
900325a6 | 227 | } |
272ca655 | 228 | |
9c3a50b7 | 229 | if (!dma_is_idle(chan)) |
b158471e | 230 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
231 | } |
232 | ||
173acc7c ZW |
233 | /** |
234 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 235 | * @chan : Freescale DMA channel |
173acc7c ZW |
236 | * @size : Address loop size, 0 for disable loop |
237 | * | |
238 | * The set source address hold transfer size. The source | |
239 | * address hold or loop transfer size is when the DMA transfer | |
240 | * data from source address (SA), if the loop size is 4, the DMA will | |
241 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
242 | * SA + 1 ... and so on. | |
243 | */ | |
a1c03319 | 244 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 245 | { |
272ca655 IS |
246 | u32 mode; |
247 | ||
a1c03319 | 248 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 249 | |
173acc7c ZW |
250 | switch (size) { |
251 | case 0: | |
272ca655 | 252 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
253 | break; |
254 | case 1: | |
255 | case 2: | |
256 | case 4: | |
257 | case 8: | |
272ca655 | 258 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
259 | break; |
260 | } | |
272ca655 | 261 | |
a1c03319 | 262 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
263 | } |
264 | ||
265 | /** | |
738f5f7e | 266 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 267 | * @chan : Freescale DMA channel |
173acc7c ZW |
268 | * @size : Address loop size, 0 for disable loop |
269 | * | |
270 | * The set destination address hold transfer size. The destination | |
271 | * address hold or loop transfer size is when the DMA transfer | |
272 | * data to destination address (TA), if the loop size is 4, the DMA will | |
273 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
274 | * TA + 1 ... and so on. | |
275 | */ | |
a1c03319 | 276 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 277 | { |
272ca655 IS |
278 | u32 mode; |
279 | ||
a1c03319 | 280 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 281 | |
173acc7c ZW |
282 | switch (size) { |
283 | case 0: | |
272ca655 | 284 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
285 | break; |
286 | case 1: | |
287 | case 2: | |
288 | case 4: | |
289 | case 8: | |
272ca655 | 290 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
291 | break; |
292 | } | |
272ca655 | 293 | |
a1c03319 | 294 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
295 | } |
296 | ||
297 | /** | |
e6c7ecb6 | 298 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 299 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
300 | * @size : Number of bytes to transfer in a single request |
301 | * | |
302 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
303 | * The DMA request count is how many bytes are allowed to transfer before | |
304 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
305 | * operation. | |
173acc7c | 306 | * |
e6c7ecb6 | 307 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 308 | */ |
a1c03319 | 309 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 310 | { |
272ca655 IS |
311 | u32 mode; |
312 | ||
e6c7ecb6 | 313 | BUG_ON(size > 1024); |
272ca655 | 314 | |
a1c03319 | 315 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
316 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
317 | ||
a1c03319 | 318 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 319 | } |
173acc7c | 320 | |
e6c7ecb6 IS |
321 | /** |
322 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 323 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
324 | * @enable : 0 is disabled, 1 is enabled. |
325 | * | |
326 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
327 | * The DMA Request Count feature should be used in addition to this feature | |
328 | * to set the number of bytes to transfer before pausing the channel. | |
329 | */ | |
a1c03319 | 330 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
331 | { |
332 | if (enable) | |
a1c03319 | 333 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 334 | else |
a1c03319 | 335 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
336 | } |
337 | ||
338 | /** | |
339 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 340 | * @chan : Freescale DMA channel |
173acc7c ZW |
341 | * @enable : 0 is disabled, 1 is enabled. |
342 | * | |
343 | * If enable the external start, the channel can be started by an | |
344 | * external DMA start pin. So the dma_start() does not start the | |
345 | * transfer immediately. The DMA channel will wait for the | |
346 | * control pin asserted. | |
347 | */ | |
a1c03319 | 348 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
349 | { |
350 | if (enable) | |
a1c03319 | 351 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 352 | else |
a1c03319 | 353 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
354 | } |
355 | ||
31f4306c | 356 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
357 | { |
358 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
359 | ||
360 | if (list_empty(&chan->ld_pending)) | |
361 | goto out_splice; | |
362 | ||
363 | /* | |
364 | * Add the hardware descriptor to the chain of hardware descriptors | |
365 | * that already exists in memory. | |
366 | * | |
367 | * This will un-set the EOL bit of the existing transaction, and the | |
368 | * last link in this transaction will become the EOL descriptor. | |
369 | */ | |
370 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
371 | ||
372 | /* | |
373 | * Add the software descriptor and all children to the list | |
374 | * of pending transactions | |
375 | */ | |
376 | out_splice: | |
377 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
378 | } | |
379 | ||
173acc7c ZW |
380 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
381 | { | |
a1c03319 | 382 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
383 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
384 | struct fsl_desc_sw *child; | |
173acc7c | 385 | unsigned long flags; |
bbc76560 | 386 | dma_cookie_t cookie = -EINVAL; |
173acc7c | 387 | |
a1c03319 | 388 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 389 | |
9c3a50b7 IS |
390 | /* |
391 | * assign cookies to all of the software descriptors | |
392 | * that make up this transaction | |
393 | */ | |
eda34234 | 394 | list_for_each_entry(child, &desc->tx_list, node) { |
884485e1 | 395 | cookie = dma_cookie_assign(&child->async_tx); |
bcfb7465 IS |
396 | } |
397 | ||
9c3a50b7 | 398 | /* put this transaction onto the tail of the pending queue */ |
a1c03319 | 399 | append_ld_queue(chan, desc); |
173acc7c | 400 | |
a1c03319 | 401 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
402 | |
403 | return cookie; | |
404 | } | |
405 | ||
406 | /** | |
407 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 408 | * @chan : Freescale DMA channel |
173acc7c ZW |
409 | * |
410 | * Return - The descriptor allocated. NULL for failed. | |
411 | */ | |
31f4306c | 412 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 413 | { |
9c3a50b7 | 414 | struct fsl_desc_sw *desc; |
173acc7c | 415 | dma_addr_t pdesc; |
9c3a50b7 IS |
416 | |
417 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
418 | if (!desc) { | |
b158471e | 419 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 420 | return NULL; |
173acc7c ZW |
421 | } |
422 | ||
9c3a50b7 IS |
423 | memset(desc, 0, sizeof(*desc)); |
424 | INIT_LIST_HEAD(&desc->tx_list); | |
425 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
426 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
427 | desc->async_tx.phys = pdesc; | |
428 | ||
0ab09c36 IS |
429 | #ifdef FSL_DMA_LD_DEBUG |
430 | chan_dbg(chan, "LD %p allocated\n", desc); | |
431 | #endif | |
432 | ||
9c3a50b7 | 433 | return desc; |
173acc7c ZW |
434 | } |
435 | ||
173acc7c ZW |
436 | /** |
437 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 438 | * @chan : Freescale DMA channel |
173acc7c ZW |
439 | * |
440 | * This function will create a dma pool for descriptor allocation. | |
441 | * | |
442 | * Return - The number of descriptors allocated. | |
443 | */ | |
a1c03319 | 444 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 445 | { |
a1c03319 | 446 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
447 | |
448 | /* Has this channel already been allocated? */ | |
a1c03319 | 449 | if (chan->desc_pool) |
77cd62e8 | 450 | return 1; |
173acc7c | 451 | |
9c3a50b7 IS |
452 | /* |
453 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
454 | * for meeting FSL DMA specification requirement. |
455 | */ | |
b158471e | 456 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
457 | sizeof(struct fsl_desc_sw), |
458 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 459 | if (!chan->desc_pool) { |
b158471e | 460 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 461 | return -ENOMEM; |
173acc7c ZW |
462 | } |
463 | ||
9c3a50b7 | 464 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
465 | return 1; |
466 | } | |
467 | ||
9c3a50b7 IS |
468 | /** |
469 | * fsldma_free_desc_list - Free all descriptors in a queue | |
470 | * @chan: Freescae DMA channel | |
471 | * @list: the list to free | |
472 | * | |
473 | * LOCKING: must hold chan->desc_lock | |
474 | */ | |
475 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
476 | struct list_head *list) | |
477 | { | |
478 | struct fsl_desc_sw *desc, *_desc; | |
479 | ||
480 | list_for_each_entry_safe(desc, _desc, list, node) { | |
481 | list_del(&desc->node); | |
0ab09c36 IS |
482 | #ifdef FSL_DMA_LD_DEBUG |
483 | chan_dbg(chan, "LD %p free\n", desc); | |
484 | #endif | |
9c3a50b7 IS |
485 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
486 | } | |
487 | } | |
488 | ||
489 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
490 | struct list_head *list) | |
491 | { | |
492 | struct fsl_desc_sw *desc, *_desc; | |
493 | ||
494 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
495 | list_del(&desc->node); | |
0ab09c36 IS |
496 | #ifdef FSL_DMA_LD_DEBUG |
497 | chan_dbg(chan, "LD %p free\n", desc); | |
498 | #endif | |
9c3a50b7 IS |
499 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
500 | } | |
501 | } | |
502 | ||
173acc7c ZW |
503 | /** |
504 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 505 | * @chan : Freescale DMA channel |
173acc7c | 506 | */ |
a1c03319 | 507 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 508 | { |
a1c03319 | 509 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
510 | unsigned long flags; |
511 | ||
b158471e | 512 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 513 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
514 | fsldma_free_desc_list(chan, &chan->ld_pending); |
515 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 516 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 517 | |
9c3a50b7 | 518 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 519 | chan->desc_pool = NULL; |
173acc7c ZW |
520 | } |
521 | ||
2187c269 | 522 | static struct dma_async_tx_descriptor * |
a1c03319 | 523 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 524 | { |
a1c03319 | 525 | struct fsldma_chan *chan; |
2187c269 ZW |
526 | struct fsl_desc_sw *new; |
527 | ||
a1c03319 | 528 | if (!dchan) |
2187c269 ZW |
529 | return NULL; |
530 | ||
a1c03319 | 531 | chan = to_fsl_chan(dchan); |
2187c269 | 532 | |
a1c03319 | 533 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 534 | if (!new) { |
b158471e | 535 | chan_err(chan, "%s\n", msg_ld_oom); |
2187c269 ZW |
536 | return NULL; |
537 | } | |
538 | ||
539 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 540 | new->async_tx.flags = flags; |
2187c269 | 541 | |
f79abb62 | 542 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 543 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 544 | |
31f4306c | 545 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 546 | set_ld_eol(chan, new); |
2187c269 ZW |
547 | |
548 | return &new->async_tx; | |
549 | } | |
550 | ||
31f4306c IS |
551 | static struct dma_async_tx_descriptor * |
552 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
553 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
554 | size_t len, unsigned long flags) |
555 | { | |
a1c03319 | 556 | struct fsldma_chan *chan; |
173acc7c ZW |
557 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
558 | size_t copy; | |
173acc7c | 559 | |
a1c03319 | 560 | if (!dchan) |
173acc7c ZW |
561 | return NULL; |
562 | ||
563 | if (!len) | |
564 | return NULL; | |
565 | ||
a1c03319 | 566 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
567 | |
568 | do { | |
569 | ||
570 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 571 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 572 | if (!new) { |
b158471e | 573 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 574 | goto fail; |
173acc7c | 575 | } |
173acc7c | 576 | |
56822843 | 577 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 578 | |
a1c03319 IS |
579 | set_desc_cnt(chan, &new->hw, copy); |
580 | set_desc_src(chan, &new->hw, dma_src); | |
581 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
582 | |
583 | if (!first) | |
584 | first = new; | |
585 | else | |
a1c03319 | 586 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
587 | |
588 | new->async_tx.cookie = 0; | |
636bdeaa | 589 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
590 | |
591 | prev = new; | |
592 | len -= copy; | |
593 | dma_src += copy; | |
738f5f7e | 594 | dma_dst += copy; |
173acc7c ZW |
595 | |
596 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 597 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
598 | } while (len); |
599 | ||
636bdeaa | 600 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
601 | new->async_tx.cookie = -EBUSY; |
602 | ||
31f4306c | 603 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 604 | set_ld_eol(chan, new); |
173acc7c | 605 | |
2e077f8e IS |
606 | return &first->async_tx; |
607 | ||
608 | fail: | |
609 | if (!first) | |
610 | return NULL; | |
611 | ||
9c3a50b7 | 612 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 613 | return NULL; |
173acc7c ZW |
614 | } |
615 | ||
c1433041 IS |
616 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
617 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
618 | struct scatterlist *src_sg, unsigned int src_nents, | |
619 | unsigned long flags) | |
620 | { | |
621 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
622 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
623 | size_t dst_avail, src_avail; | |
624 | dma_addr_t dst, src; | |
625 | size_t len; | |
626 | ||
627 | /* basic sanity checks */ | |
628 | if (dst_nents == 0 || src_nents == 0) | |
629 | return NULL; | |
630 | ||
631 | if (dst_sg == NULL || src_sg == NULL) | |
632 | return NULL; | |
633 | ||
634 | /* | |
635 | * TODO: should we check that both scatterlists have the same | |
636 | * TODO: number of bytes in total? Is that really an error? | |
637 | */ | |
638 | ||
639 | /* get prepared for the loop */ | |
640 | dst_avail = sg_dma_len(dst_sg); | |
641 | src_avail = sg_dma_len(src_sg); | |
642 | ||
643 | /* run until we are out of scatterlist entries */ | |
644 | while (true) { | |
645 | ||
646 | /* create the largest transaction possible */ | |
647 | len = min_t(size_t, src_avail, dst_avail); | |
648 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
649 | if (len == 0) | |
650 | goto fetch; | |
651 | ||
652 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
653 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
654 | ||
655 | /* allocate and populate the descriptor */ | |
656 | new = fsl_dma_alloc_descriptor(chan); | |
657 | if (!new) { | |
b158471e | 658 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
659 | goto fail; |
660 | } | |
c1433041 IS |
661 | |
662 | set_desc_cnt(chan, &new->hw, len); | |
663 | set_desc_src(chan, &new->hw, src); | |
664 | set_desc_dst(chan, &new->hw, dst); | |
665 | ||
666 | if (!first) | |
667 | first = new; | |
668 | else | |
669 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
670 | ||
671 | new->async_tx.cookie = 0; | |
672 | async_tx_ack(&new->async_tx); | |
673 | prev = new; | |
674 | ||
675 | /* Insert the link descriptor to the LD ring */ | |
676 | list_add_tail(&new->node, &first->tx_list); | |
677 | ||
678 | /* update metadata */ | |
679 | dst_avail -= len; | |
680 | src_avail -= len; | |
681 | ||
682 | fetch: | |
683 | /* fetch the next dst scatterlist entry */ | |
684 | if (dst_avail == 0) { | |
685 | ||
686 | /* no more entries: we're done */ | |
687 | if (dst_nents == 0) | |
688 | break; | |
689 | ||
690 | /* fetch the next entry: if there are no more: done */ | |
691 | dst_sg = sg_next(dst_sg); | |
692 | if (dst_sg == NULL) | |
693 | break; | |
694 | ||
695 | dst_nents--; | |
696 | dst_avail = sg_dma_len(dst_sg); | |
697 | } | |
698 | ||
699 | /* fetch the next src scatterlist entry */ | |
700 | if (src_avail == 0) { | |
701 | ||
702 | /* no more entries: we're done */ | |
703 | if (src_nents == 0) | |
704 | break; | |
705 | ||
706 | /* fetch the next entry: if there are no more: done */ | |
707 | src_sg = sg_next(src_sg); | |
708 | if (src_sg == NULL) | |
709 | break; | |
710 | ||
711 | src_nents--; | |
712 | src_avail = sg_dma_len(src_sg); | |
713 | } | |
714 | } | |
715 | ||
716 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
717 | new->async_tx.cookie = -EBUSY; | |
718 | ||
719 | /* Set End-of-link to the last link descriptor of new list */ | |
720 | set_ld_eol(chan, new); | |
721 | ||
722 | return &first->async_tx; | |
723 | ||
724 | fail: | |
725 | if (!first) | |
726 | return NULL; | |
727 | ||
728 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
729 | return NULL; | |
730 | } | |
731 | ||
bbea0b6e IS |
732 | /** |
733 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
734 | * @chan: DMA channel | |
735 | * @sgl: scatterlist to transfer to/from | |
736 | * @sg_len: number of entries in @scatterlist | |
737 | * @direction: DMA direction | |
738 | * @flags: DMAEngine flags | |
185ecb5f | 739 | * @context: transaction context (ignored) |
bbea0b6e IS |
740 | * |
741 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
742 | * DMA_SLAVE API, this gets the device-specific information from the | |
743 | * chan->private variable. | |
744 | */ | |
745 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 746 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
185ecb5f AB |
747 | enum dma_transfer_direction direction, unsigned long flags, |
748 | void *context) | |
bbea0b6e | 749 | { |
bbea0b6e | 750 | /* |
968f19ae | 751 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 752 | * |
968f19ae IS |
753 | * However, we need to provide the function pointer to allow the |
754 | * device_control() method to work. | |
bbea0b6e | 755 | */ |
bbea0b6e IS |
756 | return NULL; |
757 | } | |
758 | ||
c3635c78 | 759 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 760 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 761 | { |
968f19ae | 762 | struct dma_slave_config *config; |
a1c03319 | 763 | struct fsldma_chan *chan; |
bbea0b6e | 764 | unsigned long flags; |
968f19ae | 765 | int size; |
c3635c78 | 766 | |
a1c03319 | 767 | if (!dchan) |
c3635c78 | 768 | return -EINVAL; |
bbea0b6e | 769 | |
a1c03319 | 770 | chan = to_fsl_chan(dchan); |
bbea0b6e | 771 | |
968f19ae IS |
772 | switch (cmd) { |
773 | case DMA_TERMINATE_ALL: | |
f04cd407 IS |
774 | spin_lock_irqsave(&chan->desc_lock, flags); |
775 | ||
968f19ae IS |
776 | /* Halt the DMA engine */ |
777 | dma_halt(chan); | |
bbea0b6e | 778 | |
968f19ae IS |
779 | /* Remove and free all of the descriptors in the LD queue */ |
780 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
781 | fsldma_free_desc_list(chan, &chan->ld_running); | |
f04cd407 | 782 | chan->idle = true; |
bbea0b6e | 783 | |
968f19ae IS |
784 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
785 | return 0; | |
786 | ||
787 | case DMA_SLAVE_CONFIG: | |
788 | config = (struct dma_slave_config *)arg; | |
789 | ||
790 | /* make sure the channel supports setting burst size */ | |
791 | if (!chan->set_request_count) | |
792 | return -ENXIO; | |
793 | ||
794 | /* we set the controller burst size depending on direction */ | |
db8196df | 795 | if (config->direction == DMA_MEM_TO_DEV) |
968f19ae IS |
796 | size = config->dst_addr_width * config->dst_maxburst; |
797 | else | |
798 | size = config->src_addr_width * config->src_maxburst; | |
799 | ||
800 | chan->set_request_count(chan, size); | |
801 | return 0; | |
802 | ||
803 | case FSLDMA_EXTERNAL_START: | |
804 | ||
805 | /* make sure the channel supports external start */ | |
806 | if (!chan->toggle_ext_start) | |
807 | return -ENXIO; | |
808 | ||
809 | chan->toggle_ext_start(chan, arg); | |
810 | return 0; | |
811 | ||
812 | default: | |
813 | return -ENXIO; | |
814 | } | |
c3635c78 LW |
815 | |
816 | return 0; | |
bbea0b6e IS |
817 | } |
818 | ||
173acc7c | 819 | /** |
9c4d1e7b | 820 | * fsldma_cleanup_descriptor - cleanup and free a single link descriptor |
9c3a50b7 | 821 | * @chan: Freescale DMA channel |
9c4d1e7b | 822 | * @desc: descriptor to cleanup and free |
173acc7c | 823 | * |
9c4d1e7b IS |
824 | * This function is used on a descriptor which has been executed by the DMA |
825 | * controller. It will run any callbacks, submit any dependencies, and then | |
826 | * free the descriptor. | |
173acc7c | 827 | */ |
9c4d1e7b IS |
828 | static void fsldma_cleanup_descriptor(struct fsldma_chan *chan, |
829 | struct fsl_desc_sw *desc) | |
173acc7c | 830 | { |
9c4d1e7b | 831 | struct dma_async_tx_descriptor *txd = &desc->async_tx; |
9c4d1e7b IS |
832 | |
833 | /* Run the link descriptor callback function */ | |
834 | if (txd->callback) { | |
835 | #ifdef FSL_DMA_LD_DEBUG | |
836 | chan_dbg(chan, "LD %p callback\n", desc); | |
837 | #endif | |
838 | txd->callback(txd->callback_param); | |
839 | } | |
173acc7c | 840 | |
9c4d1e7b IS |
841 | /* Run any dependencies */ |
842 | dma_run_dependencies(txd); | |
173acc7c | 843 | |
d38a8c62 | 844 | dma_descriptor_unmap(txd); |
9c4d1e7b IS |
845 | #ifdef FSL_DMA_LD_DEBUG |
846 | chan_dbg(chan, "LD %p free\n", desc); | |
847 | #endif | |
848 | dma_pool_free(chan->desc_pool, desc, txd->phys); | |
173acc7c ZW |
849 | } |
850 | ||
851 | /** | |
9c3a50b7 | 852 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 853 | * @chan : Freescale DMA channel |
9c3a50b7 | 854 | * |
f04cd407 | 855 | * HARDWARE STATE: idle |
dc8d4091 | 856 | * LOCKING: must hold chan->desc_lock |
173acc7c | 857 | */ |
a1c03319 | 858 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 859 | { |
9c3a50b7 | 860 | struct fsl_desc_sw *desc; |
138ef018 | 861 | |
9c3a50b7 IS |
862 | /* |
863 | * If the list of pending descriptors is empty, then we | |
864 | * don't need to do any work at all | |
865 | */ | |
866 | if (list_empty(&chan->ld_pending)) { | |
b158471e | 867 | chan_dbg(chan, "no pending LDs\n"); |
dc8d4091 | 868 | return; |
9c3a50b7 | 869 | } |
173acc7c | 870 | |
9c3a50b7 | 871 | /* |
f04cd407 IS |
872 | * The DMA controller is not idle, which means that the interrupt |
873 | * handler will start any queued transactions when it runs after | |
874 | * this transaction finishes | |
9c3a50b7 | 875 | */ |
f04cd407 | 876 | if (!chan->idle) { |
b158471e | 877 | chan_dbg(chan, "DMA controller still busy\n"); |
dc8d4091 | 878 | return; |
9c3a50b7 IS |
879 | } |
880 | ||
9c3a50b7 IS |
881 | /* |
882 | * If there are some link descriptors which have not been | |
883 | * transferred, we need to start the controller | |
173acc7c | 884 | */ |
173acc7c | 885 | |
9c3a50b7 IS |
886 | /* |
887 | * Move all elements from the queue of pending transactions | |
888 | * onto the list of running transactions | |
889 | */ | |
f04cd407 | 890 | chan_dbg(chan, "idle, starting controller\n"); |
9c3a50b7 IS |
891 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); |
892 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
893 | ||
f04cd407 IS |
894 | /* |
895 | * The 85xx DMA controller doesn't clear the channel start bit | |
896 | * automatically at the end of a transfer. Therefore we must clear | |
897 | * it in software before starting the transfer. | |
898 | */ | |
899 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
900 | u32 mode; | |
901 | ||
902 | mode = DMA_IN(chan, &chan->regs->mr, 32); | |
903 | mode &= ~FSL_DMA_MR_CS; | |
904 | DMA_OUT(chan, &chan->regs->mr, mode, 32); | |
905 | } | |
906 | ||
9c3a50b7 IS |
907 | /* |
908 | * Program the descriptor's address into the DMA controller, | |
909 | * then start the DMA transaction | |
910 | */ | |
911 | set_cdar(chan, desc->async_tx.phys); | |
f04cd407 | 912 | get_cdar(chan); |
138ef018 | 913 | |
9c3a50b7 | 914 | dma_start(chan); |
f04cd407 | 915 | chan->idle = false; |
173acc7c ZW |
916 | } |
917 | ||
918 | /** | |
919 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 920 | * @chan : Freescale DMA channel |
173acc7c | 921 | */ |
a1c03319 | 922 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 923 | { |
a1c03319 | 924 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 IS |
925 | unsigned long flags; |
926 | ||
927 | spin_lock_irqsave(&chan->desc_lock, flags); | |
a1c03319 | 928 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 | 929 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
930 | } |
931 | ||
173acc7c | 932 | /** |
07934481 | 933 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 934 | * @chan : Freescale DMA channel |
173acc7c | 935 | */ |
07934481 | 936 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 937 | dma_cookie_t cookie, |
07934481 | 938 | struct dma_tx_state *txstate) |
173acc7c | 939 | { |
9b0b0bdc | 940 | return dma_cookie_status(dchan, cookie, txstate); |
173acc7c ZW |
941 | } |
942 | ||
d3f620b2 IS |
943 | /*----------------------------------------------------------------------------*/ |
944 | /* Interrupt Handling */ | |
945 | /*----------------------------------------------------------------------------*/ | |
946 | ||
e7a29151 | 947 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 948 | { |
a1c03319 | 949 | struct fsldma_chan *chan = data; |
a1c03319 | 950 | u32 stat; |
173acc7c | 951 | |
9c3a50b7 | 952 | /* save and clear the status register */ |
a1c03319 | 953 | stat = get_sr(chan); |
9c3a50b7 | 954 | set_sr(chan, stat); |
b158471e | 955 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 956 | |
f04cd407 | 957 | /* check that this was really our device */ |
173acc7c ZW |
958 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
959 | if (!stat) | |
960 | return IRQ_NONE; | |
961 | ||
962 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 963 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 964 | |
9c3a50b7 IS |
965 | /* |
966 | * Programming Error | |
f79abb62 | 967 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
d73111c6 | 968 | * trigger a PE interrupt. |
f79abb62 ZW |
969 | */ |
970 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 971 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 972 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
973 | if (get_bcr(chan) != 0) |
974 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
975 | } |
976 | ||
9c3a50b7 IS |
977 | /* |
978 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
979 | * and start the next transfer if it exist. |
980 | */ | |
981 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 982 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 983 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
984 | } |
985 | ||
9c3a50b7 IS |
986 | /* |
987 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
988 | * we should clear the Channel Start bit for |
989 | * prepare next transfer. | |
990 | */ | |
1c62979e | 991 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 992 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 993 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
994 | } |
995 | ||
f04cd407 IS |
996 | /* check that the DMA controller is really idle */ |
997 | if (!dma_is_idle(chan)) | |
998 | chan_err(chan, "irq: controller not idle!\n"); | |
999 | ||
1000 | /* check that we handled all of the bits */ | |
173acc7c | 1001 | if (stat) |
f04cd407 | 1002 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 1003 | |
f04cd407 IS |
1004 | /* |
1005 | * Schedule the tasklet to handle all cleanup of the current | |
1006 | * transaction. It will start a new transaction if there is | |
1007 | * one pending. | |
1008 | */ | |
a1c03319 | 1009 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 1010 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
1011 | return IRQ_HANDLED; |
1012 | } | |
1013 | ||
d3f620b2 IS |
1014 | static void dma_do_tasklet(unsigned long data) |
1015 | { | |
a1c03319 | 1016 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
dc8d4091 IS |
1017 | struct fsl_desc_sw *desc, *_desc; |
1018 | LIST_HEAD(ld_cleanup); | |
f04cd407 IS |
1019 | unsigned long flags; |
1020 | ||
1021 | chan_dbg(chan, "tasklet entry\n"); | |
1022 | ||
f04cd407 | 1023 | spin_lock_irqsave(&chan->desc_lock, flags); |
dc8d4091 IS |
1024 | |
1025 | /* update the cookie if we have some descriptors to cleanup */ | |
1026 | if (!list_empty(&chan->ld_running)) { | |
1027 | dma_cookie_t cookie; | |
1028 | ||
1029 | desc = to_fsl_desc(chan->ld_running.prev); | |
1030 | cookie = desc->async_tx.cookie; | |
f7fbce07 | 1031 | dma_cookie_complete(&desc->async_tx); |
dc8d4091 | 1032 | |
dc8d4091 IS |
1033 | chan_dbg(chan, "completed_cookie=%d\n", cookie); |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * move the descriptors to a temporary list so we can drop the lock | |
1038 | * during the entire cleanup operation | |
1039 | */ | |
1040 | list_splice_tail_init(&chan->ld_running, &ld_cleanup); | |
1041 | ||
1042 | /* the hardware is now idle and ready for more */ | |
f04cd407 | 1043 | chan->idle = true; |
f04cd407 | 1044 | |
dc8d4091 IS |
1045 | /* |
1046 | * Start any pending transactions automatically | |
1047 | * | |
1048 | * In the ideal case, we keep the DMA controller busy while we go | |
1049 | * ahead and free the descriptors below. | |
1050 | */ | |
f04cd407 | 1051 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 IS |
1052 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
1053 | ||
1054 | /* Run the callback for each descriptor, in order */ | |
1055 | list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) { | |
1056 | ||
1057 | /* Remove from the list of transactions */ | |
1058 | list_del(&desc->node); | |
1059 | ||
1060 | /* Run all cleanup for this descriptor */ | |
1061 | fsldma_cleanup_descriptor(chan, desc); | |
1062 | } | |
1063 | ||
f04cd407 | 1064 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1065 | } |
1066 | ||
1067 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1068 | { |
a4f56d4b | 1069 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1070 | struct fsldma_chan *chan; |
1071 | unsigned int handled = 0; | |
1072 | u32 gsr, mask; | |
1073 | int i; | |
173acc7c | 1074 | |
e7a29151 | 1075 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1076 | : in_le32(fdev->regs); |
1077 | mask = 0xff000000; | |
1078 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1079 | |
d3f620b2 IS |
1080 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1081 | chan = fdev->chan[i]; | |
1082 | if (!chan) | |
1083 | continue; | |
1084 | ||
1085 | if (gsr & mask) { | |
1086 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1087 | fsldma_chan_irq(irq, chan); | |
1088 | handled++; | |
1089 | } | |
1090 | ||
1091 | gsr &= ~mask; | |
1092 | mask >>= 8; | |
1093 | } | |
1094 | ||
1095 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1096 | } |
1097 | ||
d3f620b2 | 1098 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1099 | { |
d3f620b2 IS |
1100 | struct fsldma_chan *chan; |
1101 | int i; | |
1102 | ||
1103 | if (fdev->irq != NO_IRQ) { | |
1104 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1105 | free_irq(fdev->irq, fdev); | |
1106 | return; | |
1107 | } | |
1108 | ||
1109 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1110 | chan = fdev->chan[i]; | |
1111 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1112 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1113 | free_irq(chan->irq, chan); |
1114 | } | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1119 | { | |
1120 | struct fsldma_chan *chan; | |
1121 | int ret; | |
1122 | int i; | |
1123 | ||
1124 | /* if we have a per-controller IRQ, use that */ | |
1125 | if (fdev->irq != NO_IRQ) { | |
1126 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1127 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1128 | "fsldma-controller", fdev); | |
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1133 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1134 | chan = fdev->chan[i]; | |
1135 | if (!chan) | |
1136 | continue; | |
1137 | ||
1138 | if (chan->irq == NO_IRQ) { | |
b158471e | 1139 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1140 | ret = -ENODEV; |
1141 | goto out_unwind; | |
1142 | } | |
1143 | ||
b158471e | 1144 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1145 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1146 | "fsldma-chan", chan); | |
1147 | if (ret) { | |
b158471e | 1148 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1149 | goto out_unwind; |
1150 | } | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | ||
1155 | out_unwind: | |
1156 | for (/* none */; i >= 0; i--) { | |
1157 | chan = fdev->chan[i]; | |
1158 | if (!chan) | |
1159 | continue; | |
1160 | ||
1161 | if (chan->irq == NO_IRQ) | |
1162 | continue; | |
1163 | ||
1164 | free_irq(chan->irq, chan); | |
1165 | } | |
1166 | ||
1167 | return ret; | |
173acc7c ZW |
1168 | } |
1169 | ||
a4f56d4b IS |
1170 | /*----------------------------------------------------------------------------*/ |
1171 | /* OpenFirmware Subsystem */ | |
1172 | /*----------------------------------------------------------------------------*/ | |
1173 | ||
463a1f8b | 1174 | static int fsl_dma_chan_probe(struct fsldma_device *fdev, |
77cd62e8 | 1175 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1176 | { |
a1c03319 | 1177 | struct fsldma_chan *chan; |
4ce0e953 | 1178 | struct resource res; |
173acc7c ZW |
1179 | int err; |
1180 | ||
173acc7c | 1181 | /* alloc channel */ |
a1c03319 IS |
1182 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1183 | if (!chan) { | |
e7a29151 IS |
1184 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1185 | err = -ENOMEM; | |
1186 | goto out_return; | |
1187 | } | |
1188 | ||
1189 | /* ioremap registers for use */ | |
a1c03319 IS |
1190 | chan->regs = of_iomap(node, 0); |
1191 | if (!chan->regs) { | |
e7a29151 IS |
1192 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1193 | err = -ENOMEM; | |
a1c03319 | 1194 | goto out_free_chan; |
173acc7c ZW |
1195 | } |
1196 | ||
4ce0e953 | 1197 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1198 | if (err) { |
e7a29151 IS |
1199 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1200 | goto out_iounmap_regs; | |
173acc7c ZW |
1201 | } |
1202 | ||
a1c03319 | 1203 | chan->feature = feature; |
173acc7c | 1204 | if (!fdev->feature) |
a1c03319 | 1205 | fdev->feature = chan->feature; |
173acc7c | 1206 | |
e7a29151 IS |
1207 | /* |
1208 | * If the DMA device's feature is different than the feature | |
1209 | * of its channels, report the bug | |
173acc7c | 1210 | */ |
a1c03319 | 1211 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1212 | |
a1c03319 | 1213 | chan->dev = fdev->dev; |
8de7a7d9 HZ |
1214 | chan->id = (res.start & 0xfff) < 0x300 ? |
1215 | ((res.start - 0x100) & 0xfff) >> 7 : | |
1216 | ((res.start - 0x200) & 0xfff) >> 7; | |
a1c03319 | 1217 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
e7a29151 | 1218 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1219 | err = -EINVAL; |
e7a29151 | 1220 | goto out_iounmap_regs; |
173acc7c | 1221 | } |
173acc7c | 1222 | |
a1c03319 IS |
1223 | fdev->chan[chan->id] = chan; |
1224 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1225 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1226 | |
1227 | /* Initialize the channel */ | |
a1c03319 | 1228 | dma_init(chan); |
173acc7c ZW |
1229 | |
1230 | /* Clear cdar registers */ | |
a1c03319 | 1231 | set_cdar(chan, 0); |
173acc7c | 1232 | |
a1c03319 | 1233 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1234 | case FSL_DMA_IP_85XX: |
a1c03319 | 1235 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1236 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1237 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1238 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1239 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1240 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1241 | } |
1242 | ||
a1c03319 | 1243 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1244 | INIT_LIST_HEAD(&chan->ld_pending); |
1245 | INIT_LIST_HEAD(&chan->ld_running); | |
f04cd407 | 1246 | chan->idle = true; |
173acc7c | 1247 | |
a1c03319 | 1248 | chan->common.device = &fdev->common; |
8ac69546 | 1249 | dma_cookie_init(&chan->common); |
173acc7c | 1250 | |
d3f620b2 | 1251 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1252 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1253 | |
173acc7c | 1254 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1255 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1256 | fdev->common.chancnt++; |
1257 | ||
a1c03319 IS |
1258 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1259 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1260 | |
1261 | return 0; | |
51ee87f2 | 1262 | |
e7a29151 | 1263 | out_iounmap_regs: |
a1c03319 IS |
1264 | iounmap(chan->regs); |
1265 | out_free_chan: | |
1266 | kfree(chan); | |
e7a29151 | 1267 | out_return: |
173acc7c ZW |
1268 | return err; |
1269 | } | |
1270 | ||
a1c03319 | 1271 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1272 | { |
a1c03319 IS |
1273 | irq_dispose_mapping(chan->irq); |
1274 | list_del(&chan->common.device_node); | |
1275 | iounmap(chan->regs); | |
1276 | kfree(chan); | |
173acc7c ZW |
1277 | } |
1278 | ||
463a1f8b | 1279 | static int fsldma_of_probe(struct platform_device *op) |
173acc7c | 1280 | { |
a4f56d4b | 1281 | struct fsldma_device *fdev; |
77cd62e8 | 1282 | struct device_node *child; |
e7a29151 | 1283 | int err; |
173acc7c | 1284 | |
a4f56d4b | 1285 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1286 | if (!fdev) { |
e7a29151 IS |
1287 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1288 | err = -ENOMEM; | |
1289 | goto out_return; | |
173acc7c | 1290 | } |
e7a29151 IS |
1291 | |
1292 | fdev->dev = &op->dev; | |
173acc7c ZW |
1293 | INIT_LIST_HEAD(&fdev->common.channels); |
1294 | ||
e7a29151 | 1295 | /* ioremap the registers for use */ |
61c7a080 | 1296 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1297 | if (!fdev->regs) { |
1298 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1299 | err = -ENOMEM; | |
1300 | goto out_free_fdev; | |
173acc7c ZW |
1301 | } |
1302 | ||
d3f620b2 | 1303 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1304 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1305 | |
173acc7c ZW |
1306 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1307 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1308 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1309 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1310 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1311 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1312 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1313 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1314 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1315 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1316 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1317 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1318 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1319 | fdev->common.dev = &op->dev; |
173acc7c | 1320 | |
e2c8e425 LY |
1321 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1322 | ||
dd3daca1 | 1323 | platform_set_drvdata(op, fdev); |
77cd62e8 | 1324 | |
e7a29151 IS |
1325 | /* |
1326 | * We cannot use of_platform_bus_probe() because there is no | |
1327 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1328 | * channel object. |
1329 | */ | |
61c7a080 | 1330 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1331 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1332 | fsl_dma_chan_probe(fdev, child, |
1333 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1334 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1335 | } |
1336 | ||
1337 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1338 | fsl_dma_chan_probe(fdev, child, |
1339 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1340 | "fsl,elo-dma-channel"); | |
e7a29151 | 1341 | } |
77cd62e8 | 1342 | } |
173acc7c | 1343 | |
d3f620b2 IS |
1344 | /* |
1345 | * Hookup the IRQ handler(s) | |
1346 | * | |
1347 | * If we have a per-controller interrupt, we prefer that to the | |
1348 | * per-channel interrupts to reduce the number of shared interrupt | |
1349 | * handlers on the same IRQ line | |
1350 | */ | |
1351 | err = fsldma_request_irqs(fdev); | |
1352 | if (err) { | |
1353 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1354 | goto out_free_fdev; | |
1355 | } | |
1356 | ||
173acc7c ZW |
1357 | dma_async_device_register(&fdev->common); |
1358 | return 0; | |
1359 | ||
e7a29151 | 1360 | out_free_fdev: |
d3f620b2 | 1361 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1362 | kfree(fdev); |
e7a29151 | 1363 | out_return: |
173acc7c ZW |
1364 | return err; |
1365 | } | |
1366 | ||
2dc11581 | 1367 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1368 | { |
a4f56d4b | 1369 | struct fsldma_device *fdev; |
77cd62e8 TT |
1370 | unsigned int i; |
1371 | ||
dd3daca1 | 1372 | fdev = platform_get_drvdata(op); |
77cd62e8 TT |
1373 | dma_async_device_unregister(&fdev->common); |
1374 | ||
d3f620b2 IS |
1375 | fsldma_free_irqs(fdev); |
1376 | ||
e7a29151 | 1377 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1378 | if (fdev->chan[i]) |
1379 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1380 | } |
77cd62e8 | 1381 | |
e7a29151 | 1382 | iounmap(fdev->regs); |
77cd62e8 | 1383 | kfree(fdev); |
77cd62e8 TT |
1384 | |
1385 | return 0; | |
1386 | } | |
1387 | ||
4b1cf1fa | 1388 | static const struct of_device_id fsldma_of_ids[] = { |
8de7a7d9 | 1389 | { .compatible = "fsl,elo3-dma", }, |
049c9d45 KG |
1390 | { .compatible = "fsl,eloplus-dma", }, |
1391 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1392 | {} |
1393 | }; | |
1394 | ||
8faa7cf8 | 1395 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1396 | .driver = { |
1397 | .name = "fsl-elo-dma", | |
1398 | .owner = THIS_MODULE, | |
1399 | .of_match_table = fsldma_of_ids, | |
1400 | }, | |
1401 | .probe = fsldma_of_probe, | |
1402 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1403 | }; |
1404 | ||
a4f56d4b IS |
1405 | /*----------------------------------------------------------------------------*/ |
1406 | /* Module Init / Exit */ | |
1407 | /*----------------------------------------------------------------------------*/ | |
1408 | ||
1409 | static __init int fsldma_init(void) | |
173acc7c | 1410 | { |
8de7a7d9 | 1411 | pr_info("Freescale Elo series DMA driver\n"); |
00006124 | 1412 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1413 | } |
1414 | ||
a4f56d4b | 1415 | static void __exit fsldma_exit(void) |
77cd62e8 | 1416 | { |
00006124 | 1417 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1418 | } |
1419 | ||
a4f56d4b IS |
1420 | subsys_initcall(fsldma_init); |
1421 | module_exit(fsldma_exit); | |
77cd62e8 | 1422 | |
8de7a7d9 | 1423 | MODULE_DESCRIPTION("Freescale Elo series DMA driver"); |
77cd62e8 | 1424 | MODULE_LICENSE("GPL"); |