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Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
4 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
13 | * The support for MPC8349 DMA contorller is also added. | |
14 | * | |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/dmaengine.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/dmapool.h> | |
35 | #include <linux/of_platform.h> | |
36 | ||
bbea0b6e | 37 | #include <asm/fsldma.h> |
173acc7c ZW |
38 | #include "fsldma.h" |
39 | ||
a1c03319 | 40 | static void dma_init(struct fsldma_chan *chan) |
173acc7c ZW |
41 | { |
42 | /* Reset the channel */ | |
a1c03319 | 43 | DMA_OUT(chan, &chan->regs->mr, 0, 32); |
173acc7c | 44 | |
a1c03319 | 45 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c ZW |
46 | case FSL_DMA_IP_85XX: |
47 | /* Set the channel to below modes: | |
48 | * EIE - Error interrupt enable | |
49 | * EOSIE - End of segments interrupt enable (basic mode) | |
50 | * EOLNIE - End of links interrupt enable | |
51 | */ | |
a1c03319 | 52 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE |
173acc7c ZW |
53 | | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); |
54 | break; | |
55 | case FSL_DMA_IP_83XX: | |
56 | /* Set the channel to below modes: | |
57 | * EOTIE - End-of-transfer interrupt enable | |
a7aea373 | 58 | * PRC_RM - PCI read multiple |
173acc7c | 59 | */ |
a1c03319 | 60 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE |
a7aea373 | 61 | | FSL_DMA_MR_PRC_RM, 32); |
173acc7c ZW |
62 | break; |
63 | } | |
173acc7c ZW |
64 | } |
65 | ||
a1c03319 | 66 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 67 | { |
a1c03319 | 68 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
69 | } |
70 | ||
a1c03319 | 71 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 72 | { |
a1c03319 | 73 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
74 | } |
75 | ||
a1c03319 | 76 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
77 | struct fsl_dma_ld_hw *hw, u32 count) |
78 | { | |
a1c03319 | 79 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
80 | } |
81 | ||
a1c03319 | 82 | static void set_desc_src(struct fsldma_chan *chan, |
173acc7c ZW |
83 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
84 | { | |
85 | u64 snoop_bits; | |
86 | ||
a1c03319 | 87 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 88 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 89 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
90 | } |
91 | ||
a1c03319 | 92 | static void set_desc_dst(struct fsldma_chan *chan, |
738f5f7e | 93 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
94 | { |
95 | u64 snoop_bits; | |
96 | ||
a1c03319 | 97 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 98 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 99 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
100 | } |
101 | ||
a1c03319 | 102 | static void set_desc_next(struct fsldma_chan *chan, |
173acc7c ZW |
103 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
104 | { | |
105 | u64 snoop_bits; | |
106 | ||
a1c03319 | 107 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 108 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 109 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
110 | } |
111 | ||
a1c03319 | 112 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
173acc7c | 113 | { |
a1c03319 | 114 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
173acc7c ZW |
115 | } |
116 | ||
a1c03319 | 117 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
173acc7c | 118 | { |
a1c03319 | 119 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
173acc7c ZW |
120 | } |
121 | ||
a1c03319 | 122 | static dma_addr_t get_ndar(struct fsldma_chan *chan) |
173acc7c | 123 | { |
a1c03319 | 124 | return DMA_IN(chan, &chan->regs->ndar, 64); |
173acc7c ZW |
125 | } |
126 | ||
a1c03319 | 127 | static u32 get_bcr(struct fsldma_chan *chan) |
f79abb62 | 128 | { |
a1c03319 | 129 | return DMA_IN(chan, &chan->regs->bcr, 32); |
f79abb62 ZW |
130 | } |
131 | ||
a1c03319 | 132 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 133 | { |
a1c03319 | 134 | u32 sr = get_sr(chan); |
173acc7c ZW |
135 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
136 | } | |
137 | ||
a1c03319 | 138 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 139 | { |
272ca655 IS |
140 | u32 mode; |
141 | ||
a1c03319 | 142 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 143 | |
a1c03319 IS |
144 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
145 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
146 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
272ca655 IS |
147 | mode |= FSL_DMA_MR_EMP_EN; |
148 | } else { | |
149 | mode &= ~FSL_DMA_MR_EMP_EN; | |
150 | } | |
43a1a3ed | 151 | } |
173acc7c | 152 | |
a1c03319 | 153 | if (chan->feature & FSL_DMA_CHAN_START_EXT) |
272ca655 | 154 | mode |= FSL_DMA_MR_EMS_EN; |
173acc7c | 155 | else |
272ca655 | 156 | mode |= FSL_DMA_MR_CS; |
173acc7c | 157 | |
a1c03319 | 158 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
159 | } |
160 | ||
a1c03319 | 161 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 162 | { |
272ca655 | 163 | u32 mode; |
900325a6 DW |
164 | int i; |
165 | ||
a1c03319 | 166 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 167 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 168 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
169 | |
170 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 171 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 172 | |
900325a6 | 173 | for (i = 0; i < 100; i++) { |
a1c03319 | 174 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
175 | return; |
176 | ||
173acc7c | 177 | udelay(10); |
900325a6 | 178 | } |
272ca655 | 179 | |
9c3a50b7 | 180 | if (!dma_is_idle(chan)) |
a1c03319 | 181 | dev_err(chan->dev, "DMA halt timeout!\n"); |
173acc7c ZW |
182 | } |
183 | ||
a1c03319 | 184 | static void set_ld_eol(struct fsldma_chan *chan, |
173acc7c ZW |
185 | struct fsl_desc_sw *desc) |
186 | { | |
776c8943 IS |
187 | u64 snoop_bits; |
188 | ||
a1c03319 | 189 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
776c8943 IS |
190 | ? FSL_DMA_SNEN : 0; |
191 | ||
a1c03319 IS |
192 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
193 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
776c8943 | 194 | | snoop_bits, 64); |
173acc7c ZW |
195 | } |
196 | ||
173acc7c ZW |
197 | /** |
198 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 199 | * @chan : Freescale DMA channel |
173acc7c ZW |
200 | * @size : Address loop size, 0 for disable loop |
201 | * | |
202 | * The set source address hold transfer size. The source | |
203 | * address hold or loop transfer size is when the DMA transfer | |
204 | * data from source address (SA), if the loop size is 4, the DMA will | |
205 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
206 | * SA + 1 ... and so on. | |
207 | */ | |
a1c03319 | 208 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 209 | { |
272ca655 IS |
210 | u32 mode; |
211 | ||
a1c03319 | 212 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 213 | |
173acc7c ZW |
214 | switch (size) { |
215 | case 0: | |
272ca655 | 216 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
217 | break; |
218 | case 1: | |
219 | case 2: | |
220 | case 4: | |
221 | case 8: | |
272ca655 | 222 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
223 | break; |
224 | } | |
272ca655 | 225 | |
a1c03319 | 226 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
227 | } |
228 | ||
229 | /** | |
738f5f7e | 230 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 231 | * @chan : Freescale DMA channel |
173acc7c ZW |
232 | * @size : Address loop size, 0 for disable loop |
233 | * | |
234 | * The set destination address hold transfer size. The destination | |
235 | * address hold or loop transfer size is when the DMA transfer | |
236 | * data to destination address (TA), if the loop size is 4, the DMA will | |
237 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
238 | * TA + 1 ... and so on. | |
239 | */ | |
a1c03319 | 240 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 241 | { |
272ca655 IS |
242 | u32 mode; |
243 | ||
a1c03319 | 244 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 245 | |
173acc7c ZW |
246 | switch (size) { |
247 | case 0: | |
272ca655 | 248 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
249 | break; |
250 | case 1: | |
251 | case 2: | |
252 | case 4: | |
253 | case 8: | |
272ca655 | 254 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
255 | break; |
256 | } | |
272ca655 | 257 | |
a1c03319 | 258 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
259 | } |
260 | ||
261 | /** | |
e6c7ecb6 | 262 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 263 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
264 | * @size : Number of bytes to transfer in a single request |
265 | * | |
266 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
267 | * The DMA request count is how many bytes are allowed to transfer before | |
268 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
269 | * operation. | |
173acc7c | 270 | * |
e6c7ecb6 | 271 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 272 | */ |
a1c03319 | 273 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 274 | { |
272ca655 IS |
275 | u32 mode; |
276 | ||
e6c7ecb6 | 277 | BUG_ON(size > 1024); |
272ca655 | 278 | |
a1c03319 | 279 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
280 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
281 | ||
a1c03319 | 282 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 283 | } |
173acc7c | 284 | |
e6c7ecb6 IS |
285 | /** |
286 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 287 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
288 | * @enable : 0 is disabled, 1 is enabled. |
289 | * | |
290 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
291 | * The DMA Request Count feature should be used in addition to this feature | |
292 | * to set the number of bytes to transfer before pausing the channel. | |
293 | */ | |
a1c03319 | 294 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
295 | { |
296 | if (enable) | |
a1c03319 | 297 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 298 | else |
a1c03319 | 299 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
300 | } |
301 | ||
302 | /** | |
303 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 304 | * @chan : Freescale DMA channel |
173acc7c ZW |
305 | * @enable : 0 is disabled, 1 is enabled. |
306 | * | |
307 | * If enable the external start, the channel can be started by an | |
308 | * external DMA start pin. So the dma_start() does not start the | |
309 | * transfer immediately. The DMA channel will wait for the | |
310 | * control pin asserted. | |
311 | */ | |
a1c03319 | 312 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
313 | { |
314 | if (enable) | |
a1c03319 | 315 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 316 | else |
a1c03319 | 317 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
318 | } |
319 | ||
9c3a50b7 IS |
320 | static void append_ld_queue(struct fsldma_chan *chan, |
321 | struct fsl_desc_sw *desc) | |
322 | { | |
323 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
324 | ||
325 | if (list_empty(&chan->ld_pending)) | |
326 | goto out_splice; | |
327 | ||
328 | /* | |
329 | * Add the hardware descriptor to the chain of hardware descriptors | |
330 | * that already exists in memory. | |
331 | * | |
332 | * This will un-set the EOL bit of the existing transaction, and the | |
333 | * last link in this transaction will become the EOL descriptor. | |
334 | */ | |
335 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
336 | ||
337 | /* | |
338 | * Add the software descriptor and all children to the list | |
339 | * of pending transactions | |
340 | */ | |
341 | out_splice: | |
342 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
343 | } | |
344 | ||
173acc7c ZW |
345 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
346 | { | |
a1c03319 | 347 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
348 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
349 | struct fsl_desc_sw *child; | |
173acc7c ZW |
350 | unsigned long flags; |
351 | dma_cookie_t cookie; | |
352 | ||
a1c03319 | 353 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 354 | |
9c3a50b7 IS |
355 | /* |
356 | * assign cookies to all of the software descriptors | |
357 | * that make up this transaction | |
358 | */ | |
a1c03319 | 359 | cookie = chan->common.cookie; |
eda34234 | 360 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 IS |
361 | cookie++; |
362 | if (cookie < 0) | |
363 | cookie = 1; | |
364 | ||
6ca3a7a9 | 365 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
366 | } |
367 | ||
a1c03319 | 368 | chan->common.cookie = cookie; |
9c3a50b7 IS |
369 | |
370 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 371 | append_ld_queue(chan, desc); |
173acc7c | 372 | |
a1c03319 | 373 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
374 | |
375 | return cookie; | |
376 | } | |
377 | ||
378 | /** | |
379 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 380 | * @chan : Freescale DMA channel |
173acc7c ZW |
381 | * |
382 | * Return - The descriptor allocated. NULL for failed. | |
383 | */ | |
384 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
a1c03319 | 385 | struct fsldma_chan *chan) |
173acc7c | 386 | { |
9c3a50b7 | 387 | struct fsl_desc_sw *desc; |
173acc7c | 388 | dma_addr_t pdesc; |
9c3a50b7 IS |
389 | |
390 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
391 | if (!desc) { | |
392 | dev_dbg(chan->dev, "out of memory for link desc\n"); | |
393 | return NULL; | |
173acc7c ZW |
394 | } |
395 | ||
9c3a50b7 IS |
396 | memset(desc, 0, sizeof(*desc)); |
397 | INIT_LIST_HEAD(&desc->tx_list); | |
398 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
399 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
400 | desc->async_tx.phys = pdesc; | |
401 | ||
402 | return desc; | |
173acc7c ZW |
403 | } |
404 | ||
405 | ||
406 | /** | |
407 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 408 | * @chan : Freescale DMA channel |
173acc7c ZW |
409 | * |
410 | * This function will create a dma pool for descriptor allocation. | |
411 | * | |
412 | * Return - The number of descriptors allocated. | |
413 | */ | |
a1c03319 | 414 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 415 | { |
a1c03319 | 416 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
417 | |
418 | /* Has this channel already been allocated? */ | |
a1c03319 | 419 | if (chan->desc_pool) |
77cd62e8 | 420 | return 1; |
173acc7c | 421 | |
9c3a50b7 IS |
422 | /* |
423 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
424 | * for meeting FSL DMA specification requirement. |
425 | */ | |
a1c03319 | 426 | chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", |
9c3a50b7 IS |
427 | chan->dev, |
428 | sizeof(struct fsl_desc_sw), | |
429 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 430 | if (!chan->desc_pool) { |
9c3a50b7 IS |
431 | dev_err(chan->dev, "unable to allocate channel %d " |
432 | "descriptor pool\n", chan->id); | |
433 | return -ENOMEM; | |
173acc7c ZW |
434 | } |
435 | ||
9c3a50b7 | 436 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
437 | return 1; |
438 | } | |
439 | ||
9c3a50b7 IS |
440 | /** |
441 | * fsldma_free_desc_list - Free all descriptors in a queue | |
442 | * @chan: Freescae DMA channel | |
443 | * @list: the list to free | |
444 | * | |
445 | * LOCKING: must hold chan->desc_lock | |
446 | */ | |
447 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
448 | struct list_head *list) | |
449 | { | |
450 | struct fsl_desc_sw *desc, *_desc; | |
451 | ||
452 | list_for_each_entry_safe(desc, _desc, list, node) { | |
453 | list_del(&desc->node); | |
454 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
455 | } | |
456 | } | |
457 | ||
458 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
459 | struct list_head *list) | |
460 | { | |
461 | struct fsl_desc_sw *desc, *_desc; | |
462 | ||
463 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
464 | list_del(&desc->node); | |
465 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
466 | } | |
467 | } | |
468 | ||
173acc7c ZW |
469 | /** |
470 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 471 | * @chan : Freescale DMA channel |
173acc7c | 472 | */ |
a1c03319 | 473 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 474 | { |
a1c03319 | 475 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
476 | unsigned long flags; |
477 | ||
a1c03319 IS |
478 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
479 | spin_lock_irqsave(&chan->desc_lock, flags); | |
9c3a50b7 IS |
480 | fsldma_free_desc_list(chan, &chan->ld_pending); |
481 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 482 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 483 | |
9c3a50b7 | 484 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 485 | chan->desc_pool = NULL; |
173acc7c ZW |
486 | } |
487 | ||
2187c269 | 488 | static struct dma_async_tx_descriptor * |
a1c03319 | 489 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 490 | { |
a1c03319 | 491 | struct fsldma_chan *chan; |
2187c269 ZW |
492 | struct fsl_desc_sw *new; |
493 | ||
a1c03319 | 494 | if (!dchan) |
2187c269 ZW |
495 | return NULL; |
496 | ||
a1c03319 | 497 | chan = to_fsl_chan(dchan); |
2187c269 | 498 | |
a1c03319 | 499 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 500 | if (!new) { |
a1c03319 | 501 | dev_err(chan->dev, "No free memory for link descriptor\n"); |
2187c269 ZW |
502 | return NULL; |
503 | } | |
504 | ||
505 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 506 | new->async_tx.flags = flags; |
2187c269 | 507 | |
f79abb62 | 508 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 509 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 510 | |
2187c269 | 511 | /* Set End-of-link to the last link descriptor of new list*/ |
a1c03319 | 512 | set_ld_eol(chan, new); |
2187c269 ZW |
513 | |
514 | return &new->async_tx; | |
515 | } | |
516 | ||
173acc7c | 517 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
a1c03319 | 518 | struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, |
173acc7c ZW |
519 | size_t len, unsigned long flags) |
520 | { | |
a1c03319 | 521 | struct fsldma_chan *chan; |
173acc7c ZW |
522 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
523 | size_t copy; | |
173acc7c | 524 | |
a1c03319 | 525 | if (!dchan) |
173acc7c ZW |
526 | return NULL; |
527 | ||
528 | if (!len) | |
529 | return NULL; | |
530 | ||
a1c03319 | 531 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
532 | |
533 | do { | |
534 | ||
535 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 536 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 537 | if (!new) { |
a1c03319 | 538 | dev_err(chan->dev, |
173acc7c | 539 | "No free memory for link descriptor\n"); |
2e077f8e | 540 | goto fail; |
173acc7c ZW |
541 | } |
542 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 543 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
173acc7c ZW |
544 | #endif |
545 | ||
56822843 | 546 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 547 | |
a1c03319 IS |
548 | set_desc_cnt(chan, &new->hw, copy); |
549 | set_desc_src(chan, &new->hw, dma_src); | |
550 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
551 | |
552 | if (!first) | |
553 | first = new; | |
554 | else | |
a1c03319 | 555 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
556 | |
557 | new->async_tx.cookie = 0; | |
636bdeaa | 558 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
559 | |
560 | prev = new; | |
561 | len -= copy; | |
562 | dma_src += copy; | |
738f5f7e | 563 | dma_dst += copy; |
173acc7c ZW |
564 | |
565 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 566 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
567 | } while (len); |
568 | ||
636bdeaa | 569 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
570 | new->async_tx.cookie = -EBUSY; |
571 | ||
572 | /* Set End-of-link to the last link descriptor of new list*/ | |
a1c03319 | 573 | set_ld_eol(chan, new); |
173acc7c | 574 | |
2e077f8e IS |
575 | return &first->async_tx; |
576 | ||
577 | fail: | |
578 | if (!first) | |
579 | return NULL; | |
580 | ||
9c3a50b7 | 581 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 582 | return NULL; |
173acc7c ZW |
583 | } |
584 | ||
bbea0b6e IS |
585 | /** |
586 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
587 | * @chan: DMA channel | |
588 | * @sgl: scatterlist to transfer to/from | |
589 | * @sg_len: number of entries in @scatterlist | |
590 | * @direction: DMA direction | |
591 | * @flags: DMAEngine flags | |
592 | * | |
593 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
594 | * DMA_SLAVE API, this gets the device-specific information from the | |
595 | * chan->private variable. | |
596 | */ | |
597 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 598 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
599 | enum dma_data_direction direction, unsigned long flags) |
600 | { | |
a1c03319 | 601 | struct fsldma_chan *chan; |
bbea0b6e IS |
602 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; |
603 | struct fsl_dma_slave *slave; | |
bbea0b6e IS |
604 | size_t copy; |
605 | ||
606 | int i; | |
607 | struct scatterlist *sg; | |
608 | size_t sg_used; | |
609 | size_t hw_used; | |
610 | struct fsl_dma_hw_addr *hw; | |
611 | dma_addr_t dma_dst, dma_src; | |
612 | ||
a1c03319 | 613 | if (!dchan) |
bbea0b6e IS |
614 | return NULL; |
615 | ||
a1c03319 | 616 | if (!dchan->private) |
bbea0b6e IS |
617 | return NULL; |
618 | ||
a1c03319 IS |
619 | chan = to_fsl_chan(dchan); |
620 | slave = dchan->private; | |
bbea0b6e IS |
621 | |
622 | if (list_empty(&slave->addresses)) | |
623 | return NULL; | |
624 | ||
625 | hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); | |
626 | hw_used = 0; | |
627 | ||
628 | /* | |
629 | * Build the hardware transaction to copy from the scatterlist to | |
630 | * the hardware, or from the hardware to the scatterlist | |
631 | * | |
632 | * If you are copying from the hardware to the scatterlist and it | |
633 | * takes two hardware entries to fill an entire page, then both | |
634 | * hardware entries will be coalesced into the same page | |
635 | * | |
636 | * If you are copying from the scatterlist to the hardware and a | |
637 | * single page can fill two hardware entries, then the data will | |
638 | * be read out of the page into the first hardware entry, and so on | |
639 | */ | |
640 | for_each_sg(sgl, sg, sg_len, i) { | |
641 | sg_used = 0; | |
642 | ||
643 | /* Loop until the entire scatterlist entry is used */ | |
644 | while (sg_used < sg_dma_len(sg)) { | |
645 | ||
646 | /* | |
647 | * If we've used up the current hardware address/length | |
648 | * pair, we need to load a new one | |
649 | * | |
650 | * This is done in a while loop so that descriptors with | |
651 | * length == 0 will be skipped | |
652 | */ | |
653 | while (hw_used >= hw->length) { | |
654 | ||
655 | /* | |
656 | * If the current hardware entry is the last | |
657 | * entry in the list, we're finished | |
658 | */ | |
659 | if (list_is_last(&hw->entry, &slave->addresses)) | |
660 | goto finished; | |
661 | ||
662 | /* Get the next hardware address/length pair */ | |
663 | hw = list_entry(hw->entry.next, | |
664 | struct fsl_dma_hw_addr, entry); | |
665 | hw_used = 0; | |
666 | } | |
667 | ||
668 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 669 | new = fsl_dma_alloc_descriptor(chan); |
bbea0b6e | 670 | if (!new) { |
a1c03319 | 671 | dev_err(chan->dev, "No free memory for " |
bbea0b6e IS |
672 | "link descriptor\n"); |
673 | goto fail; | |
674 | } | |
675 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 676 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
bbea0b6e IS |
677 | #endif |
678 | ||
679 | /* | |
680 | * Calculate the maximum number of bytes to transfer, | |
681 | * making sure it is less than the DMA controller limit | |
682 | */ | |
683 | copy = min_t(size_t, sg_dma_len(sg) - sg_used, | |
684 | hw->length - hw_used); | |
685 | copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); | |
686 | ||
687 | /* | |
688 | * DMA_FROM_DEVICE | |
689 | * from the hardware to the scatterlist | |
690 | * | |
691 | * DMA_TO_DEVICE | |
692 | * from the scatterlist to the hardware | |
693 | */ | |
694 | if (direction == DMA_FROM_DEVICE) { | |
695 | dma_src = hw->address + hw_used; | |
696 | dma_dst = sg_dma_address(sg) + sg_used; | |
697 | } else { | |
698 | dma_src = sg_dma_address(sg) + sg_used; | |
699 | dma_dst = hw->address + hw_used; | |
700 | } | |
701 | ||
702 | /* Fill in the descriptor */ | |
a1c03319 IS |
703 | set_desc_cnt(chan, &new->hw, copy); |
704 | set_desc_src(chan, &new->hw, dma_src); | |
705 | set_desc_dst(chan, &new->hw, dma_dst); | |
bbea0b6e IS |
706 | |
707 | /* | |
708 | * If this is not the first descriptor, chain the | |
709 | * current descriptor after the previous descriptor | |
710 | */ | |
711 | if (!first) { | |
712 | first = new; | |
713 | } else { | |
a1c03319 | 714 | set_desc_next(chan, &prev->hw, |
bbea0b6e IS |
715 | new->async_tx.phys); |
716 | } | |
717 | ||
718 | new->async_tx.cookie = 0; | |
719 | async_tx_ack(&new->async_tx); | |
720 | ||
721 | prev = new; | |
722 | sg_used += copy; | |
723 | hw_used += copy; | |
724 | ||
725 | /* Insert the link descriptor into the LD ring */ | |
726 | list_add_tail(&new->node, &first->tx_list); | |
727 | } | |
728 | } | |
729 | ||
730 | finished: | |
731 | ||
732 | /* All of the hardware address/length pairs had length == 0 */ | |
733 | if (!first || !new) | |
734 | return NULL; | |
735 | ||
736 | new->async_tx.flags = flags; | |
737 | new->async_tx.cookie = -EBUSY; | |
738 | ||
739 | /* Set End-of-link to the last link descriptor of new list */ | |
a1c03319 | 740 | set_ld_eol(chan, new); |
bbea0b6e IS |
741 | |
742 | /* Enable extra controller features */ | |
a1c03319 IS |
743 | if (chan->set_src_loop_size) |
744 | chan->set_src_loop_size(chan, slave->src_loop_size); | |
bbea0b6e | 745 | |
a1c03319 IS |
746 | if (chan->set_dst_loop_size) |
747 | chan->set_dst_loop_size(chan, slave->dst_loop_size); | |
bbea0b6e | 748 | |
a1c03319 IS |
749 | if (chan->toggle_ext_start) |
750 | chan->toggle_ext_start(chan, slave->external_start); | |
bbea0b6e | 751 | |
a1c03319 IS |
752 | if (chan->toggle_ext_pause) |
753 | chan->toggle_ext_pause(chan, slave->external_pause); | |
bbea0b6e | 754 | |
a1c03319 IS |
755 | if (chan->set_request_count) |
756 | chan->set_request_count(chan, slave->request_count); | |
bbea0b6e IS |
757 | |
758 | return &first->async_tx; | |
759 | ||
760 | fail: | |
761 | /* If first was not set, then we failed to allocate the very first | |
762 | * descriptor, and we're done */ | |
763 | if (!first) | |
764 | return NULL; | |
765 | ||
766 | /* | |
767 | * First is set, so all of the descriptors we allocated have been added | |
768 | * to first->tx_list, INCLUDING "first" itself. Therefore we | |
769 | * must traverse the list backwards freeing each descriptor in turn | |
770 | * | |
771 | * We're re-using variables for the loop, oh well | |
772 | */ | |
9c3a50b7 | 773 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
bbea0b6e IS |
774 | return NULL; |
775 | } | |
776 | ||
a1c03319 | 777 | static void fsl_dma_device_terminate_all(struct dma_chan *dchan) |
bbea0b6e | 778 | { |
a1c03319 | 779 | struct fsldma_chan *chan; |
bbea0b6e IS |
780 | unsigned long flags; |
781 | ||
a1c03319 | 782 | if (!dchan) |
bbea0b6e IS |
783 | return; |
784 | ||
a1c03319 | 785 | chan = to_fsl_chan(dchan); |
bbea0b6e IS |
786 | |
787 | /* Halt the DMA engine */ | |
a1c03319 | 788 | dma_halt(chan); |
bbea0b6e | 789 | |
a1c03319 | 790 | spin_lock_irqsave(&chan->desc_lock, flags); |
bbea0b6e IS |
791 | |
792 | /* Remove and free all of the descriptors in the LD queue */ | |
9c3a50b7 IS |
793 | fsldma_free_desc_list(chan, &chan->ld_pending); |
794 | fsldma_free_desc_list(chan, &chan->ld_running); | |
bbea0b6e | 795 | |
a1c03319 | 796 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
bbea0b6e IS |
797 | } |
798 | ||
173acc7c ZW |
799 | /** |
800 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
a1c03319 | 801 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
802 | * |
803 | * CONTEXT: hardirq | |
173acc7c | 804 | */ |
a1c03319 | 805 | static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) |
173acc7c | 806 | { |
9c3a50b7 IS |
807 | struct fsl_desc_sw *desc; |
808 | unsigned long flags; | |
809 | dma_cookie_t cookie; | |
173acc7c | 810 | |
9c3a50b7 | 811 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 812 | |
9c3a50b7 IS |
813 | if (list_empty(&chan->ld_running)) { |
814 | dev_dbg(chan->dev, "no running descriptors\n"); | |
815 | goto out_unlock; | |
173acc7c | 816 | } |
9c3a50b7 IS |
817 | |
818 | /* Get the last descriptor, update the cookie to that */ | |
819 | desc = to_fsl_desc(chan->ld_running.prev); | |
820 | if (dma_is_idle(chan)) | |
821 | cookie = desc->async_tx.cookie; | |
76bd061f | 822 | else { |
9c3a50b7 | 823 | cookie = desc->async_tx.cookie - 1; |
76bd061f SM |
824 | if (unlikely(cookie < DMA_MIN_COOKIE)) |
825 | cookie = DMA_MAX_COOKIE; | |
826 | } | |
9c3a50b7 IS |
827 | |
828 | chan->completed_cookie = cookie; | |
829 | ||
830 | out_unlock: | |
831 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
832 | } | |
833 | ||
834 | /** | |
835 | * fsldma_desc_status - Check the status of a descriptor | |
836 | * @chan: Freescale DMA channel | |
837 | * @desc: DMA SW descriptor | |
838 | * | |
839 | * This function will return the status of the given descriptor | |
840 | */ | |
841 | static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, | |
842 | struct fsl_desc_sw *desc) | |
843 | { | |
844 | return dma_async_is_complete(desc->async_tx.cookie, | |
845 | chan->completed_cookie, | |
846 | chan->common.cookie); | |
173acc7c ZW |
847 | } |
848 | ||
849 | /** | |
850 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
a1c03319 | 851 | * @chan : Freescale DMA channel |
173acc7c ZW |
852 | * |
853 | * This function clean up the ld_queue of DMA channel. | |
173acc7c | 854 | */ |
a1c03319 | 855 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c ZW |
856 | { |
857 | struct fsl_desc_sw *desc, *_desc; | |
858 | unsigned long flags; | |
859 | ||
a1c03319 | 860 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 861 | |
9c3a50b7 IS |
862 | dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); |
863 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { | |
173acc7c ZW |
864 | dma_async_tx_callback callback; |
865 | void *callback_param; | |
866 | ||
9c3a50b7 | 867 | if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) |
173acc7c ZW |
868 | break; |
869 | ||
9c3a50b7 | 870 | /* Remove from the list of running transactions */ |
173acc7c ZW |
871 | list_del(&desc->node); |
872 | ||
173acc7c | 873 | /* Run the link descriptor callback function */ |
9c3a50b7 IS |
874 | callback = desc->async_tx.callback; |
875 | callback_param = desc->async_tx.callback_param; | |
173acc7c | 876 | if (callback) { |
a1c03319 | 877 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
9c3a50b7 | 878 | dev_dbg(chan->dev, "LD %p callback\n", desc); |
173acc7c | 879 | callback(callback_param); |
a1c03319 | 880 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 881 | } |
9c3a50b7 IS |
882 | |
883 | /* Run any dependencies, then free the descriptor */ | |
884 | dma_run_dependencies(&desc->async_tx); | |
885 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
173acc7c | 886 | } |
9c3a50b7 | 887 | |
a1c03319 | 888 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
889 | } |
890 | ||
891 | /** | |
9c3a50b7 | 892 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 893 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
894 | * |
895 | * This will make sure that any pending transactions will be run. | |
896 | * If the DMA controller is idle, it will be started. Otherwise, | |
897 | * the DMA controller's interrupt handler will start any pending | |
898 | * transactions when it becomes idle. | |
173acc7c | 899 | */ |
a1c03319 | 900 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 901 | { |
9c3a50b7 | 902 | struct fsl_desc_sw *desc; |
173acc7c ZW |
903 | unsigned long flags; |
904 | ||
a1c03319 | 905 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 906 | |
9c3a50b7 IS |
907 | /* |
908 | * If the list of pending descriptors is empty, then we | |
909 | * don't need to do any work at all | |
910 | */ | |
911 | if (list_empty(&chan->ld_pending)) { | |
912 | dev_dbg(chan->dev, "no pending LDs\n"); | |
138ef018 | 913 | goto out_unlock; |
9c3a50b7 | 914 | } |
173acc7c | 915 | |
9c3a50b7 IS |
916 | /* |
917 | * The DMA controller is not idle, which means the interrupt | |
918 | * handler will start any queued transactions when it runs | |
919 | * at the end of the current transaction | |
920 | */ | |
921 | if (!dma_is_idle(chan)) { | |
922 | dev_dbg(chan->dev, "DMA controller still busy\n"); | |
923 | goto out_unlock; | |
924 | } | |
925 | ||
926 | /* | |
927 | * TODO: | |
928 | * make sure the dma_halt() function really un-wedges the | |
929 | * controller as much as possible | |
930 | */ | |
a1c03319 | 931 | dma_halt(chan); |
173acc7c | 932 | |
9c3a50b7 IS |
933 | /* |
934 | * If there are some link descriptors which have not been | |
935 | * transferred, we need to start the controller | |
173acc7c | 936 | */ |
173acc7c | 937 | |
9c3a50b7 IS |
938 | /* |
939 | * Move all elements from the queue of pending transactions | |
940 | * onto the list of running transactions | |
941 | */ | |
942 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
943 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
944 | ||
945 | /* | |
946 | * Program the descriptor's address into the DMA controller, | |
947 | * then start the DMA transaction | |
948 | */ | |
949 | set_cdar(chan, desc->async_tx.phys); | |
950 | dma_start(chan); | |
138ef018 IS |
951 | |
952 | out_unlock: | |
a1c03319 | 953 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
954 | } |
955 | ||
956 | /** | |
957 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 958 | * @chan : Freescale DMA channel |
173acc7c | 959 | */ |
a1c03319 | 960 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 961 | { |
a1c03319 | 962 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
a1c03319 | 963 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
964 | } |
965 | ||
173acc7c ZW |
966 | /** |
967 | * fsl_dma_is_complete - Determine the DMA status | |
a1c03319 | 968 | * @chan : Freescale DMA channel |
173acc7c | 969 | */ |
a1c03319 | 970 | static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan, |
173acc7c ZW |
971 | dma_cookie_t cookie, |
972 | dma_cookie_t *done, | |
973 | dma_cookie_t *used) | |
974 | { | |
a1c03319 | 975 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
976 | dma_cookie_t last_used; |
977 | dma_cookie_t last_complete; | |
978 | ||
a1c03319 | 979 | fsl_chan_ld_cleanup(chan); |
173acc7c | 980 | |
a1c03319 IS |
981 | last_used = dchan->cookie; |
982 | last_complete = chan->completed_cookie; | |
173acc7c ZW |
983 | |
984 | if (done) | |
985 | *done = last_complete; | |
986 | ||
987 | if (used) | |
988 | *used = last_used; | |
989 | ||
990 | return dma_async_is_complete(cookie, last_complete, last_used); | |
991 | } | |
992 | ||
d3f620b2 IS |
993 | /*----------------------------------------------------------------------------*/ |
994 | /* Interrupt Handling */ | |
995 | /*----------------------------------------------------------------------------*/ | |
996 | ||
e7a29151 | 997 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 998 | { |
a1c03319 | 999 | struct fsldma_chan *chan = data; |
1c62979e ZW |
1000 | int update_cookie = 0; |
1001 | int xfer_ld_q = 0; | |
a1c03319 | 1002 | u32 stat; |
173acc7c | 1003 | |
9c3a50b7 | 1004 | /* save and clear the status register */ |
a1c03319 | 1005 | stat = get_sr(chan); |
9c3a50b7 IS |
1006 | set_sr(chan, stat); |
1007 | dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); | |
173acc7c ZW |
1008 | |
1009 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
1010 | if (!stat) | |
1011 | return IRQ_NONE; | |
1012 | ||
1013 | if (stat & FSL_DMA_SR_TE) | |
a1c03319 | 1014 | dev_err(chan->dev, "Transfer Error!\n"); |
173acc7c | 1015 | |
9c3a50b7 IS |
1016 | /* |
1017 | * Programming Error | |
f79abb62 ZW |
1018 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1019 | * triger a PE interrupt. | |
1020 | */ | |
1021 | if (stat & FSL_DMA_SR_PE) { | |
9c3a50b7 | 1022 | dev_dbg(chan->dev, "irq: Programming Error INT\n"); |
a1c03319 | 1023 | if (get_bcr(chan) == 0) { |
f79abb62 ZW |
1024 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. |
1025 | * Now, update the completed cookie, and continue the | |
1026 | * next uncompleted transfer. | |
1027 | */ | |
1c62979e ZW |
1028 | update_cookie = 1; |
1029 | xfer_ld_q = 1; | |
f79abb62 ZW |
1030 | } |
1031 | stat &= ~FSL_DMA_SR_PE; | |
1032 | } | |
1033 | ||
9c3a50b7 IS |
1034 | /* |
1035 | * If the link descriptor segment transfer finishes, | |
173acc7c ZW |
1036 | * we will recycle the used descriptor. |
1037 | */ | |
1038 | if (stat & FSL_DMA_SR_EOSI) { | |
9c3a50b7 IS |
1039 | dev_dbg(chan->dev, "irq: End-of-segments INT\n"); |
1040 | dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", | |
a1c03319 IS |
1041 | (unsigned long long)get_cdar(chan), |
1042 | (unsigned long long)get_ndar(chan)); | |
173acc7c | 1043 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
1044 | update_cookie = 1; |
1045 | } | |
1046 | ||
9c3a50b7 IS |
1047 | /* |
1048 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1049 | * and start the next transfer if it exist. |
1050 | */ | |
1051 | if (stat & FSL_DMA_SR_EOCDI) { | |
9c3a50b7 | 1052 | dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); |
1c62979e ZW |
1053 | stat &= ~FSL_DMA_SR_EOCDI; |
1054 | update_cookie = 1; | |
1055 | xfer_ld_q = 1; | |
173acc7c ZW |
1056 | } |
1057 | ||
9c3a50b7 IS |
1058 | /* |
1059 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1060 | * we should clear the Channel Start bit for |
1061 | * prepare next transfer. | |
1062 | */ | |
1c62979e | 1063 | if (stat & FSL_DMA_SR_EOLNI) { |
9c3a50b7 | 1064 | dev_dbg(chan->dev, "irq: End-of-link INT\n"); |
173acc7c | 1065 | stat &= ~FSL_DMA_SR_EOLNI; |
1c62979e | 1066 | xfer_ld_q = 1; |
173acc7c ZW |
1067 | } |
1068 | ||
1c62979e | 1069 | if (update_cookie) |
a1c03319 | 1070 | fsl_dma_update_completed_cookie(chan); |
1c62979e | 1071 | if (xfer_ld_q) |
a1c03319 | 1072 | fsl_chan_xfer_ld_queue(chan); |
173acc7c | 1073 | if (stat) |
9c3a50b7 | 1074 | dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); |
173acc7c | 1075 | |
9c3a50b7 | 1076 | dev_dbg(chan->dev, "irq: Exit\n"); |
a1c03319 | 1077 | tasklet_schedule(&chan->tasklet); |
173acc7c ZW |
1078 | return IRQ_HANDLED; |
1079 | } | |
1080 | ||
d3f620b2 IS |
1081 | static void dma_do_tasklet(unsigned long data) |
1082 | { | |
a1c03319 IS |
1083 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
1084 | fsl_chan_ld_cleanup(chan); | |
d3f620b2 IS |
1085 | } |
1086 | ||
1087 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1088 | { |
a4f56d4b | 1089 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1090 | struct fsldma_chan *chan; |
1091 | unsigned int handled = 0; | |
1092 | u32 gsr, mask; | |
1093 | int i; | |
173acc7c | 1094 | |
e7a29151 | 1095 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1096 | : in_le32(fdev->regs); |
1097 | mask = 0xff000000; | |
1098 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1099 | |
d3f620b2 IS |
1100 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1101 | chan = fdev->chan[i]; | |
1102 | if (!chan) | |
1103 | continue; | |
1104 | ||
1105 | if (gsr & mask) { | |
1106 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1107 | fsldma_chan_irq(irq, chan); | |
1108 | handled++; | |
1109 | } | |
1110 | ||
1111 | gsr &= ~mask; | |
1112 | mask >>= 8; | |
1113 | } | |
1114 | ||
1115 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1116 | } |
1117 | ||
d3f620b2 | 1118 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1119 | { |
d3f620b2 IS |
1120 | struct fsldma_chan *chan; |
1121 | int i; | |
1122 | ||
1123 | if (fdev->irq != NO_IRQ) { | |
1124 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1125 | free_irq(fdev->irq, fdev); | |
1126 | return; | |
1127 | } | |
1128 | ||
1129 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1130 | chan = fdev->chan[i]; | |
1131 | if (chan && chan->irq != NO_IRQ) { | |
1132 | dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); | |
1133 | free_irq(chan->irq, chan); | |
1134 | } | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1139 | { | |
1140 | struct fsldma_chan *chan; | |
1141 | int ret; | |
1142 | int i; | |
1143 | ||
1144 | /* if we have a per-controller IRQ, use that */ | |
1145 | if (fdev->irq != NO_IRQ) { | |
1146 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1147 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1148 | "fsldma-controller", fdev); | |
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1153 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1154 | chan = fdev->chan[i]; | |
1155 | if (!chan) | |
1156 | continue; | |
1157 | ||
1158 | if (chan->irq == NO_IRQ) { | |
1159 | dev_err(fdev->dev, "no interrupts property defined for " | |
1160 | "DMA channel %d. Please fix your " | |
1161 | "device tree\n", chan->id); | |
1162 | ret = -ENODEV; | |
1163 | goto out_unwind; | |
1164 | } | |
1165 | ||
1166 | dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); | |
1167 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, | |
1168 | "fsldma-chan", chan); | |
1169 | if (ret) { | |
1170 | dev_err(fdev->dev, "unable to request IRQ for DMA " | |
1171 | "channel %d\n", chan->id); | |
1172 | goto out_unwind; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | return 0; | |
1177 | ||
1178 | out_unwind: | |
1179 | for (/* none */; i >= 0; i--) { | |
1180 | chan = fdev->chan[i]; | |
1181 | if (!chan) | |
1182 | continue; | |
1183 | ||
1184 | if (chan->irq == NO_IRQ) | |
1185 | continue; | |
1186 | ||
1187 | free_irq(chan->irq, chan); | |
1188 | } | |
1189 | ||
1190 | return ret; | |
173acc7c ZW |
1191 | } |
1192 | ||
a4f56d4b IS |
1193 | /*----------------------------------------------------------------------------*/ |
1194 | /* OpenFirmware Subsystem */ | |
1195 | /*----------------------------------------------------------------------------*/ | |
1196 | ||
1197 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1198 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1199 | { |
a1c03319 | 1200 | struct fsldma_chan *chan; |
4ce0e953 | 1201 | struct resource res; |
173acc7c ZW |
1202 | int err; |
1203 | ||
173acc7c | 1204 | /* alloc channel */ |
a1c03319 IS |
1205 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1206 | if (!chan) { | |
e7a29151 IS |
1207 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1208 | err = -ENOMEM; | |
1209 | goto out_return; | |
1210 | } | |
1211 | ||
1212 | /* ioremap registers for use */ | |
a1c03319 IS |
1213 | chan->regs = of_iomap(node, 0); |
1214 | if (!chan->regs) { | |
e7a29151 IS |
1215 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1216 | err = -ENOMEM; | |
a1c03319 | 1217 | goto out_free_chan; |
173acc7c ZW |
1218 | } |
1219 | ||
4ce0e953 | 1220 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1221 | if (err) { |
e7a29151 IS |
1222 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1223 | goto out_iounmap_regs; | |
173acc7c ZW |
1224 | } |
1225 | ||
a1c03319 | 1226 | chan->feature = feature; |
173acc7c | 1227 | if (!fdev->feature) |
a1c03319 | 1228 | fdev->feature = chan->feature; |
173acc7c | 1229 | |
e7a29151 IS |
1230 | /* |
1231 | * If the DMA device's feature is different than the feature | |
1232 | * of its channels, report the bug | |
173acc7c | 1233 | */ |
a1c03319 | 1234 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1235 | |
a1c03319 IS |
1236 | chan->dev = fdev->dev; |
1237 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1238 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1239 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1240 | err = -EINVAL; |
e7a29151 | 1241 | goto out_iounmap_regs; |
173acc7c | 1242 | } |
173acc7c | 1243 | |
a1c03319 IS |
1244 | fdev->chan[chan->id] = chan; |
1245 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
e7a29151 IS |
1246 | |
1247 | /* Initialize the channel */ | |
a1c03319 | 1248 | dma_init(chan); |
173acc7c ZW |
1249 | |
1250 | /* Clear cdar registers */ | |
a1c03319 | 1251 | set_cdar(chan, 0); |
173acc7c | 1252 | |
a1c03319 | 1253 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1254 | case FSL_DMA_IP_85XX: |
a1c03319 | 1255 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1256 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1257 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1258 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1259 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1260 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1261 | } |
1262 | ||
a1c03319 | 1263 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1264 | INIT_LIST_HEAD(&chan->ld_pending); |
1265 | INIT_LIST_HEAD(&chan->ld_running); | |
173acc7c | 1266 | |
a1c03319 | 1267 | chan->common.device = &fdev->common; |
173acc7c | 1268 | |
d3f620b2 | 1269 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1270 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1271 | |
173acc7c | 1272 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1273 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1274 | fdev->common.chancnt++; |
1275 | ||
a1c03319 IS |
1276 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1277 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1278 | |
1279 | return 0; | |
51ee87f2 | 1280 | |
e7a29151 | 1281 | out_iounmap_regs: |
a1c03319 IS |
1282 | iounmap(chan->regs); |
1283 | out_free_chan: | |
1284 | kfree(chan); | |
e7a29151 | 1285 | out_return: |
173acc7c ZW |
1286 | return err; |
1287 | } | |
1288 | ||
a1c03319 | 1289 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1290 | { |
a1c03319 IS |
1291 | irq_dispose_mapping(chan->irq); |
1292 | list_del(&chan->common.device_node); | |
1293 | iounmap(chan->regs); | |
1294 | kfree(chan); | |
173acc7c ZW |
1295 | } |
1296 | ||
e7a29151 | 1297 | static int __devinit fsldma_of_probe(struct of_device *op, |
173acc7c ZW |
1298 | const struct of_device_id *match) |
1299 | { | |
a4f56d4b | 1300 | struct fsldma_device *fdev; |
77cd62e8 | 1301 | struct device_node *child; |
e7a29151 | 1302 | int err; |
173acc7c | 1303 | |
a4f56d4b | 1304 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1305 | if (!fdev) { |
e7a29151 IS |
1306 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1307 | err = -ENOMEM; | |
1308 | goto out_return; | |
173acc7c | 1309 | } |
e7a29151 IS |
1310 | |
1311 | fdev->dev = &op->dev; | |
173acc7c ZW |
1312 | INIT_LIST_HEAD(&fdev->common.channels); |
1313 | ||
e7a29151 IS |
1314 | /* ioremap the registers for use */ |
1315 | fdev->regs = of_iomap(op->node, 0); | |
1316 | if (!fdev->regs) { | |
1317 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1318 | err = -ENOMEM; | |
1319 | goto out_free_fdev; | |
173acc7c ZW |
1320 | } |
1321 | ||
d3f620b2 IS |
1322 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
1323 | fdev->irq = irq_of_parse_and_map(op->node, 0); | |
1324 | ||
173acc7c ZW |
1325 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1326 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
bbea0b6e | 1327 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1328 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1329 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1330 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c ZW |
1331 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
1332 | fdev->common.device_is_tx_complete = fsl_dma_is_complete; | |
1333 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; | |
bbea0b6e IS |
1334 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
1335 | fdev->common.device_terminate_all = fsl_dma_device_terminate_all; | |
e7a29151 | 1336 | fdev->common.dev = &op->dev; |
173acc7c | 1337 | |
e7a29151 | 1338 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1339 | |
e7a29151 IS |
1340 | /* |
1341 | * We cannot use of_platform_bus_probe() because there is no | |
1342 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1343 | * channel object. |
1344 | */ | |
e7a29151 IS |
1345 | for_each_child_of_node(op->node, child) { |
1346 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { | |
77cd62e8 TT |
1347 | fsl_dma_chan_probe(fdev, child, |
1348 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1349 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1350 | } |
1351 | ||
1352 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1353 | fsl_dma_chan_probe(fdev, child, |
1354 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1355 | "fsl,elo-dma-channel"); | |
e7a29151 | 1356 | } |
77cd62e8 | 1357 | } |
173acc7c | 1358 | |
d3f620b2 IS |
1359 | /* |
1360 | * Hookup the IRQ handler(s) | |
1361 | * | |
1362 | * If we have a per-controller interrupt, we prefer that to the | |
1363 | * per-channel interrupts to reduce the number of shared interrupt | |
1364 | * handlers on the same IRQ line | |
1365 | */ | |
1366 | err = fsldma_request_irqs(fdev); | |
1367 | if (err) { | |
1368 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1369 | goto out_free_fdev; | |
1370 | } | |
1371 | ||
173acc7c ZW |
1372 | dma_async_device_register(&fdev->common); |
1373 | return 0; | |
1374 | ||
e7a29151 | 1375 | out_free_fdev: |
d3f620b2 | 1376 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1377 | kfree(fdev); |
e7a29151 | 1378 | out_return: |
173acc7c ZW |
1379 | return err; |
1380 | } | |
1381 | ||
e7a29151 | 1382 | static int fsldma_of_remove(struct of_device *op) |
77cd62e8 | 1383 | { |
a4f56d4b | 1384 | struct fsldma_device *fdev; |
77cd62e8 TT |
1385 | unsigned int i; |
1386 | ||
e7a29151 | 1387 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1388 | dma_async_device_unregister(&fdev->common); |
1389 | ||
d3f620b2 IS |
1390 | fsldma_free_irqs(fdev); |
1391 | ||
e7a29151 | 1392 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1393 | if (fdev->chan[i]) |
1394 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1395 | } |
77cd62e8 | 1396 | |
e7a29151 IS |
1397 | iounmap(fdev->regs); |
1398 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1399 | kfree(fdev); |
77cd62e8 TT |
1400 | |
1401 | return 0; | |
1402 | } | |
1403 | ||
4b1cf1fa | 1404 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1405 | { .compatible = "fsl,eloplus-dma", }, |
1406 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1407 | {} |
1408 | }; | |
1409 | ||
a4f56d4b IS |
1410 | static struct of_platform_driver fsldma_of_driver = { |
1411 | .name = "fsl-elo-dma", | |
1412 | .match_table = fsldma_of_ids, | |
1413 | .probe = fsldma_of_probe, | |
1414 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1415 | }; |
1416 | ||
a4f56d4b IS |
1417 | /*----------------------------------------------------------------------------*/ |
1418 | /* Module Init / Exit */ | |
1419 | /*----------------------------------------------------------------------------*/ | |
1420 | ||
1421 | static __init int fsldma_init(void) | |
173acc7c | 1422 | { |
77cd62e8 TT |
1423 | int ret; |
1424 | ||
1425 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1426 | ||
a4f56d4b | 1427 | ret = of_register_platform_driver(&fsldma_of_driver); |
77cd62e8 TT |
1428 | if (ret) |
1429 | pr_err("fsldma: failed to register platform driver\n"); | |
1430 | ||
1431 | return ret; | |
1432 | } | |
1433 | ||
a4f56d4b | 1434 | static void __exit fsldma_exit(void) |
77cd62e8 | 1435 | { |
a4f56d4b | 1436 | of_unregister_platform_driver(&fsldma_of_driver); |
173acc7c ZW |
1437 | } |
1438 | ||
a4f56d4b IS |
1439 | subsys_initcall(fsldma_init); |
1440 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1441 | |
1442 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1443 | MODULE_LICENSE("GPL"); |