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2b49e0c5 AS |
1 | /* |
2 | * Driver for the High Speed UART DMA | |
3 | * | |
4 | * Copyright (C) 2015 Intel Corporation | |
5 | * | |
6 | * Partially based on the bits found in drivers/tty/serial/mfd.c. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __DMA_HSU_H__ | |
14 | #define __DMA_HSU_H__ | |
15 | ||
16 | #include <linux/spinlock.h> | |
17 | #include <linux/dma/hsu.h> | |
18 | ||
19 | #include "../virt-dma.h" | |
20 | ||
21 | #define HSU_CH_SR 0x00 /* channel status */ | |
22 | #define HSU_CH_CR 0x04 /* channel control */ | |
23 | #define HSU_CH_DCR 0x08 /* descriptor control */ | |
24 | #define HSU_CH_BSR 0x10 /* FIFO buffer size */ | |
25 | #define HSU_CH_MTSR 0x14 /* minimum transfer size */ | |
26 | #define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */ | |
27 | #define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */ | |
28 | #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */ | |
29 | #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */ | |
30 | #define HSU_CH_D1SAR 0x28 | |
31 | #define HSU_CH_D1TSR 0x2c | |
32 | #define HSU_CH_D2SAR 0x30 | |
33 | #define HSU_CH_D2TSR 0x34 | |
34 | #define HSU_CH_D3SAR 0x38 | |
35 | #define HSU_CH_D3TSR 0x3c | |
36 | ||
37 | #define HSU_DMA_CHAN_NR_DESC 4 | |
38 | #define HSU_DMA_CHAN_LENGTH 0x40 | |
39 | ||
40 | /* Bits in HSU_CH_SR */ | |
41 | #define HSU_CH_SR_DESCTO(x) BIT(8 + (x)) | |
42 | #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8)) | |
43 | #define HSU_CH_SR_CHE BIT(15) | |
44 | ||
45 | /* Bits in HSU_CH_CR */ | |
46 | #define HSU_CH_CR_CHA BIT(0) | |
47 | #define HSU_CH_CR_CHD BIT(1) | |
48 | ||
49 | /* Bits in HSU_CH_DCR */ | |
50 | #define HSU_CH_DCR_DESCA(x) BIT(0 + (x)) | |
51 | #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x)) | |
52 | #define HSU_CH_DCR_CHSOTO BIT(14) | |
53 | #define HSU_CH_DCR_CHSOE BIT(15) | |
54 | #define HSU_CH_DCR_CHDI(x) BIT(16 + (x)) | |
55 | #define HSU_CH_DCR_CHEI BIT(23) | |
56 | #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x)) | |
57 | ||
58 | struct hsu_dma_sg { | |
59 | dma_addr_t addr; | |
60 | unsigned int len; | |
61 | }; | |
62 | ||
63 | struct hsu_dma_desc { | |
64 | struct virt_dma_desc vdesc; | |
65 | enum dma_transfer_direction direction; | |
66 | struct hsu_dma_sg *sg; | |
67 | unsigned int nents; | |
68 | unsigned int active; | |
69 | enum dma_status status; | |
70 | }; | |
71 | ||
72 | static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc) | |
73 | { | |
74 | return container_of(vdesc, struct hsu_dma_desc, vdesc); | |
75 | } | |
76 | ||
77 | struct hsu_dma_chan { | |
78 | struct virt_dma_chan vchan; | |
79 | ||
80 | void __iomem *reg; | |
81 | spinlock_t lock; | |
82 | ||
83 | /* hardware configuration */ | |
84 | enum dma_transfer_direction direction; | |
85 | struct dma_slave_config config; | |
86 | ||
87 | struct hsu_dma_desc *desc; | |
88 | }; | |
89 | ||
90 | static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan) | |
91 | { | |
92 | return container_of(chan, struct hsu_dma_chan, vchan.chan); | |
93 | } | |
94 | ||
95 | static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset) | |
96 | { | |
97 | return readl(hsuc->reg + offset); | |
98 | } | |
99 | ||
100 | static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset, | |
101 | u32 value) | |
102 | { | |
103 | writel(value, hsuc->reg + offset); | |
104 | } | |
105 | ||
106 | struct hsu_dma { | |
107 | struct dma_device dma; | |
108 | ||
109 | /* channels */ | |
110 | struct hsu_dma_chan *chan; | |
111 | }; | |
112 | ||
113 | static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev) | |
114 | { | |
115 | return container_of(ddev, struct hsu_dma, dma); | |
116 | } | |
117 | ||
118 | #endif /* __DMA_HSU_H__ */ |