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Commit | Line | Data |
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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
9e15db7c | 8 | * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> |
1f1846c6 SH |
9 | * |
10 | * The code contained herein is licensed under the GNU General Public | |
11 | * License. You may obtain a copy of the GNU General Public License | |
12 | * Version 2 or later at the following locations: | |
13 | * | |
14 | * http://www.opensource.org/licenses/gpl-license.html | |
15 | * http://www.gnu.org/copyleft/gpl.html | |
16 | */ | |
17 | #include <linux/init.h> | |
f8de8f4c | 18 | #include <linux/module.h> |
1f1846c6 SH |
19 | #include <linux/types.h> |
20 | #include <linux/mm.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/platform_device.h> | |
6bd08127 | 27 | #include <linux/clk.h> |
1f1846c6 | 28 | #include <linux/dmaengine.h> |
5170c051 | 29 | #include <linux/module.h> |
1f1846c6 SH |
30 | |
31 | #include <asm/irq.h> | |
6bd08127 | 32 | #include <mach/dma.h> |
1f1846c6 SH |
33 | #include <mach/hardware.h> |
34 | ||
d2ebfb33 | 35 | #include "dmaengine.h" |
9e15db7c | 36 | #define IMXDMA_MAX_CHAN_DESCRIPTORS 16 |
6bd08127 JM |
37 | #define IMX_DMA_CHANNELS 16 |
38 | ||
6bd08127 JM |
39 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) |
40 | #define IMX_DMA_MEMSIZE_32 (0 << 4) | |
41 | #define IMX_DMA_MEMSIZE_8 (1 << 4) | |
42 | #define IMX_DMA_MEMSIZE_16 (2 << 4) | |
43 | #define IMX_DMA_TYPE_LINEAR (0 << 10) | |
44 | #define IMX_DMA_TYPE_2D (1 << 10) | |
45 | #define IMX_DMA_TYPE_FIFO (2 << 10) | |
46 | ||
47 | #define IMX_DMA_ERR_BURST (1 << 0) | |
48 | #define IMX_DMA_ERR_REQUEST (1 << 1) | |
49 | #define IMX_DMA_ERR_TRANSFER (1 << 2) | |
50 | #define IMX_DMA_ERR_BUFFER (1 << 3) | |
51 | #define IMX_DMA_ERR_TIMEOUT (1 << 4) | |
52 | ||
53 | #define DMA_DCR 0x00 /* Control Register */ | |
54 | #define DMA_DISR 0x04 /* Interrupt status Register */ | |
55 | #define DMA_DIMR 0x08 /* Interrupt mask Register */ | |
56 | #define DMA_DBTOSR 0x0c /* Burst timeout status Register */ | |
57 | #define DMA_DRTOSR 0x10 /* Request timeout Register */ | |
58 | #define DMA_DSESR 0x14 /* Transfer Error Status Register */ | |
59 | #define DMA_DBOSR 0x18 /* Buffer overflow status Register */ | |
60 | #define DMA_DBTOCR 0x1c /* Burst timeout control Register */ | |
61 | #define DMA_WSRA 0x40 /* W-Size Register A */ | |
62 | #define DMA_XSRA 0x44 /* X-Size Register A */ | |
63 | #define DMA_YSRA 0x48 /* Y-Size Register A */ | |
64 | #define DMA_WSRB 0x4c /* W-Size Register B */ | |
65 | #define DMA_XSRB 0x50 /* X-Size Register B */ | |
66 | #define DMA_YSRB 0x54 /* Y-Size Register B */ | |
67 | #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */ | |
68 | #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */ | |
69 | #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */ | |
70 | #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ | |
71 | #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */ | |
72 | #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */ | |
73 | #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */ | |
74 | #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */ | |
75 | #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */ | |
76 | ||
77 | #define DCR_DRST (1<<1) | |
78 | #define DCR_DEN (1<<0) | |
79 | #define DBTOCR_EN (1<<15) | |
80 | #define DBTOCR_CNT(x) ((x) & 0x7fff) | |
81 | #define CNTR_CNT(x) ((x) & 0xffffff) | |
82 | #define CCR_ACRPT (1<<14) | |
83 | #define CCR_DMOD_LINEAR (0x0 << 12) | |
84 | #define CCR_DMOD_2D (0x1 << 12) | |
85 | #define CCR_DMOD_FIFO (0x2 << 12) | |
86 | #define CCR_DMOD_EOBFIFO (0x3 << 12) | |
87 | #define CCR_SMOD_LINEAR (0x0 << 10) | |
88 | #define CCR_SMOD_2D (0x1 << 10) | |
89 | #define CCR_SMOD_FIFO (0x2 << 10) | |
90 | #define CCR_SMOD_EOBFIFO (0x3 << 10) | |
91 | #define CCR_MDIR_DEC (1<<9) | |
92 | #define CCR_MSEL_B (1<<8) | |
93 | #define CCR_DSIZ_32 (0x0 << 6) | |
94 | #define CCR_DSIZ_8 (0x1 << 6) | |
95 | #define CCR_DSIZ_16 (0x2 << 6) | |
96 | #define CCR_SSIZ_32 (0x0 << 4) | |
97 | #define CCR_SSIZ_8 (0x1 << 4) | |
98 | #define CCR_SSIZ_16 (0x2 << 4) | |
99 | #define CCR_REN (1<<3) | |
100 | #define CCR_RPT (1<<2) | |
101 | #define CCR_FRC (1<<1) | |
102 | #define CCR_CEN (1<<0) | |
103 | #define RTOR_EN (1<<15) | |
104 | #define RTOR_CLK (1<<14) | |
105 | #define RTOR_PSC (1<<13) | |
9e15db7c JM |
106 | |
107 | enum imxdma_prep_type { | |
108 | IMXDMA_DESC_MEMCPY, | |
109 | IMXDMA_DESC_INTERLEAVED, | |
110 | IMXDMA_DESC_SLAVE_SG, | |
111 | IMXDMA_DESC_CYCLIC, | |
112 | }; | |
113 | ||
114 | struct imxdma_desc { | |
115 | struct list_head node; | |
116 | struct dma_async_tx_descriptor desc; | |
117 | enum dma_status status; | |
118 | dma_addr_t src; | |
119 | dma_addr_t dest; | |
120 | size_t len; | |
2efc3449 | 121 | enum dma_transfer_direction direction; |
9e15db7c JM |
122 | enum imxdma_prep_type type; |
123 | /* For memcpy and interleaved */ | |
124 | unsigned int config_port; | |
125 | unsigned int config_mem; | |
126 | /* For interleaved transfers */ | |
127 | unsigned int x; | |
128 | unsigned int y; | |
129 | unsigned int w; | |
130 | /* For slave sg and cyclic */ | |
131 | struct scatterlist *sg; | |
132 | unsigned int sgcount; | |
133 | }; | |
134 | ||
1f1846c6 | 135 | struct imxdma_channel { |
2d9c2fc5 JM |
136 | int hw_chaining; |
137 | struct timer_list watchdog; | |
1f1846c6 SH |
138 | struct imxdma_engine *imxdma; |
139 | unsigned int channel; | |
1f1846c6 | 140 | |
9e15db7c JM |
141 | struct tasklet_struct dma_tasklet; |
142 | struct list_head ld_free; | |
143 | struct list_head ld_queue; | |
144 | struct list_head ld_active; | |
145 | int descs_allocated; | |
1f1846c6 SH |
146 | enum dma_slave_buswidth word_size; |
147 | dma_addr_t per_address; | |
148 | u32 watermark_level; | |
149 | struct dma_chan chan; | |
150 | spinlock_t lock; | |
151 | struct dma_async_tx_descriptor desc; | |
1f1846c6 SH |
152 | enum dma_status status; |
153 | int dma_request; | |
154 | struct scatterlist *sg_list; | |
359291a1 JM |
155 | u32 ccr_from_device; |
156 | u32 ccr_to_device; | |
1f1846c6 SH |
157 | }; |
158 | ||
1f1846c6 SH |
159 | struct imxdma_engine { |
160 | struct device *dev; | |
1e070a60 | 161 | struct device_dma_parameters dma_parms; |
1f1846c6 | 162 | struct dma_device dma_device; |
6bd08127 | 163 | struct imxdma_channel channel[IMX_DMA_CHANNELS]; |
1f1846c6 SH |
164 | }; |
165 | ||
166 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) | |
167 | { | |
168 | return container_of(chan, struct imxdma_channel, chan); | |
169 | } | |
170 | ||
9e15db7c | 171 | static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac) |
1f1846c6 | 172 | { |
9e15db7c JM |
173 | struct imxdma_desc *desc; |
174 | ||
175 | if (!list_empty(&imxdmac->ld_active)) { | |
176 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, | |
177 | node); | |
178 | if (desc->type == IMXDMA_DESC_CYCLIC) | |
179 | return true; | |
180 | } | |
181 | return false; | |
1f1846c6 SH |
182 | } |
183 | ||
6bd08127 JM |
184 | /* TODO: put this inside any struct */ |
185 | static void __iomem *imx_dmav1_baseaddr; | |
186 | static struct clk *dma_clk; | |
187 | ||
188 | static void imx_dmav1_writel(unsigned val, unsigned offset) | |
189 | { | |
190 | __raw_writel(val, imx_dmav1_baseaddr + offset); | |
191 | } | |
192 | ||
193 | static unsigned imx_dmav1_readl(unsigned offset) | |
1f1846c6 | 194 | { |
6bd08127 JM |
195 | return __raw_readl(imx_dmav1_baseaddr + offset); |
196 | } | |
1f1846c6 | 197 | |
2d9c2fc5 | 198 | static int imxdma_hw_chain(struct imxdma_channel *imxdmac) |
6bd08127 JM |
199 | { |
200 | if (cpu_is_mx27()) | |
2d9c2fc5 | 201 | return imxdmac->hw_chaining; |
6bd08127 JM |
202 | else |
203 | return 0; | |
204 | } | |
205 | ||
206 | /* | |
207 | * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation | |
208 | */ | |
2efc3449 | 209 | static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg) |
6bd08127 | 210 | { |
2efc3449 | 211 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
6bd08127 JM |
212 | unsigned long now; |
213 | ||
6b0e2f55 JM |
214 | now = min(d->len, sg->length); |
215 | if (d->len != IMX_DMA_LENGTH_LOOP) | |
216 | d->len -= now; | |
6bd08127 | 217 | |
2efc3449 | 218 | if (d->direction == DMA_DEV_TO_MEM) |
6bd08127 JM |
219 | imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel)); |
220 | else | |
221 | imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel)); | |
222 | ||
223 | imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel)); | |
224 | ||
225 | pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " | |
226 | "size 0x%08x\n", imxdmac->channel, | |
227 | imx_dmav1_readl(DMA_DAR(imxdmac->channel)), | |
228 | imx_dmav1_readl(DMA_SAR(imxdmac->channel)), | |
229 | imx_dmav1_readl(DMA_CNTR(imxdmac->channel))); | |
230 | ||
231 | return now; | |
232 | } | |
233 | ||
2efc3449 | 234 | static void imxdma_enable_hw(struct imxdma_desc *d) |
6bd08127 | 235 | { |
2efc3449 | 236 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); |
6bd08127 JM |
237 | int channel = imxdmac->channel; |
238 | unsigned long flags; | |
239 | ||
240 | pr_debug("imxdma%d: imx_dma_enable\n", channel); | |
241 | ||
6bd08127 JM |
242 | local_irq_save(flags); |
243 | ||
244 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
245 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); | |
246 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | | |
247 | CCR_ACRPT, DMA_CCR(channel)); | |
248 | ||
249 | if ((cpu_is_mx21() || cpu_is_mx27()) && | |
2d9c2fc5 | 250 | d->sg && imxdma_hw_chain(imxdmac)) { |
833bc03b JM |
251 | d->sg = sg_next(d->sg); |
252 | if (d->sg) { | |
6bd08127 | 253 | u32 tmp; |
833bc03b | 254 | imxdma_sg_next(d, d->sg); |
6bd08127 JM |
255 | tmp = imx_dmav1_readl(DMA_CCR(channel)); |
256 | imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, | |
257 | DMA_CCR(channel)); | |
258 | } | |
259 | } | |
6bd08127 JM |
260 | |
261 | local_irq_restore(flags); | |
262 | } | |
263 | ||
264 | static void imxdma_disable_hw(struct imxdma_channel *imxdmac) | |
265 | { | |
266 | int channel = imxdmac->channel; | |
267 | unsigned long flags; | |
268 | ||
269 | pr_debug("imxdma%d: imx_dma_disable\n", channel); | |
270 | ||
2d9c2fc5 JM |
271 | if (imxdma_hw_chain(imxdmac)) |
272 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
273 | |
274 | local_irq_save(flags); | |
275 | imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); | |
276 | imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, | |
277 | DMA_CCR(channel)); | |
278 | imx_dmav1_writel(1 << channel, DMA_DISR); | |
6bd08127 JM |
279 | local_irq_restore(flags); |
280 | } | |
281 | ||
6bd08127 | 282 | static void imxdma_watchdog(unsigned long data) |
1f1846c6 | 283 | { |
6bd08127 JM |
284 | struct imxdma_channel *imxdmac = (struct imxdma_channel *)data; |
285 | int channel = imxdmac->channel; | |
1f1846c6 | 286 | |
6bd08127 | 287 | imx_dmav1_writel(0, DMA_CCR(channel)); |
6bd08127 JM |
288 | |
289 | /* Tasklet watchdog error handler */ | |
9e15db7c | 290 | tasklet_schedule(&imxdmac->dma_tasklet); |
6bd08127 JM |
291 | pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel); |
292 | } | |
293 | ||
294 | static irqreturn_t imxdma_err_handler(int irq, void *dev_id) | |
295 | { | |
296 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
297 | unsigned int err_mask; |
298 | int i, disr; | |
299 | int errcode; | |
300 | ||
301 | disr = imx_dmav1_readl(DMA_DISR); | |
302 | ||
303 | err_mask = imx_dmav1_readl(DMA_DBTOSR) | | |
304 | imx_dmav1_readl(DMA_DRTOSR) | | |
305 | imx_dmav1_readl(DMA_DSESR) | | |
306 | imx_dmav1_readl(DMA_DBOSR); | |
307 | ||
308 | if (!err_mask) | |
309 | return IRQ_HANDLED; | |
310 | ||
311 | imx_dmav1_writel(disr & err_mask, DMA_DISR); | |
312 | ||
313 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
314 | if (!(err_mask & (1 << i))) | |
315 | continue; | |
6bd08127 JM |
316 | errcode = 0; |
317 | ||
318 | if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { | |
319 | imx_dmav1_writel(1 << i, DMA_DBTOSR); | |
320 | errcode |= IMX_DMA_ERR_BURST; | |
321 | } | |
322 | if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { | |
323 | imx_dmav1_writel(1 << i, DMA_DRTOSR); | |
324 | errcode |= IMX_DMA_ERR_REQUEST; | |
325 | } | |
326 | if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { | |
327 | imx_dmav1_writel(1 << i, DMA_DSESR); | |
328 | errcode |= IMX_DMA_ERR_TRANSFER; | |
329 | } | |
330 | if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { | |
331 | imx_dmav1_writel(1 << i, DMA_DBOSR); | |
332 | errcode |= IMX_DMA_ERR_BUFFER; | |
333 | } | |
334 | /* Tasklet error handler */ | |
335 | tasklet_schedule(&imxdma->channel[i].dma_tasklet); | |
336 | ||
337 | printk(KERN_WARNING | |
338 | "DMA timeout on channel %d -%s%s%s%s\n", i, | |
339 | errcode & IMX_DMA_ERR_BURST ? " burst" : "", | |
340 | errcode & IMX_DMA_ERR_REQUEST ? " request" : "", | |
341 | errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "", | |
342 | errcode & IMX_DMA_ERR_BUFFER ? " buffer" : ""); | |
343 | } | |
344 | return IRQ_HANDLED; | |
1f1846c6 SH |
345 | } |
346 | ||
6bd08127 | 347 | static void dma_irq_handle_channel(struct imxdma_channel *imxdmac) |
1f1846c6 | 348 | { |
6bd08127 | 349 | int chno = imxdmac->channel; |
2efc3449 | 350 | struct imxdma_desc *desc; |
6bd08127 | 351 | |
833bc03b JM |
352 | spin_lock(&imxdmac->lock); |
353 | if (list_empty(&imxdmac->ld_active)) { | |
354 | spin_unlock(&imxdmac->lock); | |
355 | goto out; | |
356 | } | |
2efc3449 | 357 | |
833bc03b JM |
358 | desc = list_first_entry(&imxdmac->ld_active, |
359 | struct imxdma_desc, | |
360 | node); | |
361 | spin_unlock(&imxdmac->lock); | |
2efc3449 | 362 | |
833bc03b JM |
363 | if (desc->sg) { |
364 | u32 tmp; | |
365 | desc->sg = sg_next(desc->sg); | |
2efc3449 | 366 | |
833bc03b JM |
367 | if (desc->sg) { |
368 | imxdma_sg_next(desc, desc->sg); | |
6bd08127 JM |
369 | |
370 | tmp = imx_dmav1_readl(DMA_CCR(chno)); | |
371 | ||
2d9c2fc5 | 372 | if (imxdma_hw_chain(imxdmac)) { |
6bd08127 JM |
373 | /* FIXME: The timeout should probably be |
374 | * configurable | |
375 | */ | |
2d9c2fc5 | 376 | mod_timer(&imxdmac->watchdog, |
6bd08127 JM |
377 | jiffies + msecs_to_jiffies(500)); |
378 | ||
379 | tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; | |
380 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
381 | } else { | |
382 | imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); | |
383 | tmp |= CCR_CEN; | |
384 | } | |
385 | ||
386 | imx_dmav1_writel(tmp, DMA_CCR(chno)); | |
387 | ||
388 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
389 | /* Tasklet progression */ | |
390 | tasklet_schedule(&imxdmac->dma_tasklet); | |
1f1846c6 | 391 | |
6bd08127 JM |
392 | return; |
393 | } | |
394 | ||
2d9c2fc5 JM |
395 | if (imxdma_hw_chain(imxdmac)) { |
396 | del_timer(&imxdmac->watchdog); | |
6bd08127 JM |
397 | return; |
398 | } | |
399 | } | |
400 | ||
2efc3449 | 401 | out: |
6bd08127 | 402 | imx_dmav1_writel(0, DMA_CCR(chno)); |
6bd08127 | 403 | /* Tasklet irq */ |
9e15db7c JM |
404 | tasklet_schedule(&imxdmac->dma_tasklet); |
405 | } | |
406 | ||
6bd08127 JM |
407 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
408 | { | |
409 | struct imxdma_engine *imxdma = dev_id; | |
6bd08127 JM |
410 | int i, disr; |
411 | ||
412 | if (cpu_is_mx21() || cpu_is_mx27()) | |
413 | imxdma_err_handler(irq, dev_id); | |
414 | ||
415 | disr = imx_dmav1_readl(DMA_DISR); | |
416 | ||
417 | pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", | |
418 | disr); | |
419 | ||
420 | imx_dmav1_writel(disr, DMA_DISR); | |
421 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { | |
2d9c2fc5 | 422 | if (disr & (1 << i)) |
6bd08127 | 423 | dma_irq_handle_channel(&imxdma->channel[i]); |
6bd08127 JM |
424 | } |
425 | ||
426 | return IRQ_HANDLED; | |
427 | } | |
428 | ||
9e15db7c JM |
429 | static int imxdma_xfer_desc(struct imxdma_desc *d) |
430 | { | |
431 | struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan); | |
3b4b6dfc | 432 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
9e15db7c JM |
433 | |
434 | /* Configure and enable */ | |
435 | switch (d->type) { | |
436 | case IMXDMA_DESC_MEMCPY: | |
3b4b6dfc JM |
437 | imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel)); |
438 | imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel)); | |
439 | imx_dmav1_writel(d->config_mem | (d->config_port << 2), | |
440 | DMA_CCR(imxdmac->channel)); | |
6bd08127 | 441 | |
3b4b6dfc JM |
442 | imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel)); |
443 | ||
444 | dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x " | |
445 | "dma_length=%d\n", __func__, imxdmac->channel, | |
446 | d->dest, d->src, d->len); | |
447 | ||
448 | break; | |
6bd08127 | 449 | /* Cyclic transfer is the same as slave_sg with special sg configuration. */ |
9e15db7c | 450 | case IMXDMA_DESC_CYCLIC: |
9e15db7c | 451 | case IMXDMA_DESC_SLAVE_SG: |
359291a1 JM |
452 | if (d->direction == DMA_DEV_TO_MEM) { |
453 | imx_dmav1_writel(imxdmac->per_address, | |
454 | DMA_SAR(imxdmac->channel)); | |
455 | imx_dmav1_writel(imxdmac->ccr_from_device, | |
456 | DMA_CCR(imxdmac->channel)); | |
457 | ||
458 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
459 | "total length=%d dev_addr=0x%08x (dev2mem)\n", | |
460 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
461 | d->len, imxdmac->per_address); | |
462 | } else if (d->direction == DMA_MEM_TO_DEV) { | |
463 | imx_dmav1_writel(imxdmac->per_address, | |
464 | DMA_DAR(imxdmac->channel)); | |
465 | imx_dmav1_writel(imxdmac->ccr_to_device, | |
466 | DMA_CCR(imxdmac->channel)); | |
467 | ||
468 | dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d " | |
469 | "total length=%d dev_addr=0x%08x (mem2dev)\n", | |
470 | __func__, imxdmac->channel, d->sg, d->sgcount, | |
471 | d->len, imxdmac->per_address); | |
472 | } else { | |
473 | dev_err(imxdma->dev, "%s channel: %d bad dma mode\n", | |
474 | __func__, imxdmac->channel); | |
475 | return -EINVAL; | |
476 | } | |
477 | ||
478 | imxdma_sg_next(d, d->sg); | |
479 | ||
9e15db7c JM |
480 | break; |
481 | default: | |
482 | return -EINVAL; | |
483 | } | |
2efc3449 | 484 | imxdma_enable_hw(d); |
9e15db7c JM |
485 | return 0; |
486 | } | |
487 | ||
488 | static void imxdma_tasklet(unsigned long data) | |
489 | { | |
490 | struct imxdma_channel *imxdmac = (void *)data; | |
491 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
492 | struct imxdma_desc *desc; | |
493 | ||
494 | spin_lock(&imxdmac->lock); | |
495 | ||
496 | if (list_empty(&imxdmac->ld_active)) { | |
497 | /* Someone might have called terminate all */ | |
498 | goto out; | |
499 | } | |
500 | desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node); | |
501 | ||
502 | if (desc->desc.callback) | |
503 | desc->desc.callback(desc->desc.callback_param); | |
504 | ||
1f3d6dc0 | 505 | dma_cookie_complete(&desc->desc); |
9e15db7c JM |
506 | |
507 | /* If we are dealing with a cyclic descriptor keep it on ld_active */ | |
508 | if (imxdma_chan_is_doing_cyclic(imxdmac)) | |
509 | goto out; | |
510 | ||
511 | list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free); | |
512 | ||
513 | if (!list_empty(&imxdmac->ld_queue)) { | |
514 | desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc, | |
515 | node); | |
516 | list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active); | |
517 | if (imxdma_xfer_desc(desc) < 0) | |
518 | dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n", | |
519 | __func__, imxdmac->channel); | |
520 | } | |
521 | out: | |
522 | spin_unlock(&imxdmac->lock); | |
1f1846c6 SH |
523 | } |
524 | ||
525 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
526 | unsigned long arg) | |
527 | { | |
528 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
529 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
9e15db7c | 530 | unsigned long flags; |
1f1846c6 SH |
531 | unsigned int mode = 0; |
532 | ||
533 | switch (cmd) { | |
534 | case DMA_TERMINATE_ALL: | |
6bd08127 | 535 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
536 | |
537 | spin_lock_irqsave(&imxdmac->lock, flags); | |
538 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); | |
539 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
540 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
541 | return 0; |
542 | case DMA_SLAVE_CONFIG: | |
db8196df | 543 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
544 | imxdmac->per_address = dmaengine_cfg->src_addr; |
545 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
546 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
547 | } else { | |
548 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
549 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
550 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
551 | } | |
552 | ||
553 | switch (imxdmac->word_size) { | |
554 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
555 | mode = IMX_DMA_MEMSIZE_8; | |
556 | break; | |
557 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
558 | mode = IMX_DMA_MEMSIZE_16; | |
559 | break; | |
560 | default: | |
561 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
562 | mode = IMX_DMA_MEMSIZE_32; | |
563 | break; | |
564 | } | |
1f1846c6 | 565 | |
2d9c2fc5 JM |
566 | imxdmac->hw_chaining = 1; |
567 | if (!imxdma_hw_chain(imxdmac)) | |
bdc0c753 | 568 | return -EINVAL; |
359291a1 | 569 | imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) | |
bdc0c753 JM |
570 | ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) | |
571 | CCR_REN; | |
359291a1 | 572 | imxdmac->ccr_to_device = |
bdc0c753 JM |
573 | (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) | |
574 | ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN; | |
575 | imx_dmav1_writel(imxdmac->dma_request, | |
576 | DMA_RSSR(imxdmac->channel)); | |
577 | ||
6bd08127 JM |
578 | /* Set burst length */ |
579 | imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size, | |
580 | DMA_BLR(imxdmac->channel)); | |
1f1846c6 SH |
581 | |
582 | return 0; | |
583 | default: | |
584 | return -ENOSYS; | |
585 | } | |
586 | ||
587 | return -EINVAL; | |
588 | } | |
589 | ||
590 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
591 | dma_cookie_t cookie, | |
592 | struct dma_tx_state *txstate) | |
593 | { | |
96a2af41 | 594 | return dma_cookie_status(chan, cookie, txstate); |
1f1846c6 SH |
595 | } |
596 | ||
597 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
598 | { | |
599 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
600 | dma_cookie_t cookie; | |
9e15db7c | 601 | unsigned long flags; |
1f1846c6 | 602 | |
9e15db7c | 603 | spin_lock_irqsave(&imxdmac->lock, flags); |
884485e1 | 604 | cookie = dma_cookie_assign(tx); |
9e15db7c | 605 | spin_unlock_irqrestore(&imxdmac->lock, flags); |
1f1846c6 SH |
606 | |
607 | return cookie; | |
608 | } | |
609 | ||
610 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
611 | { | |
612 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
613 | struct imx_dma_data *data = chan->private; | |
614 | ||
6c05f091 JM |
615 | if (data != NULL) |
616 | imxdmac->dma_request = data->dma_request; | |
1f1846c6 | 617 | |
9e15db7c JM |
618 | while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) { |
619 | struct imxdma_desc *desc; | |
1f1846c6 | 620 | |
9e15db7c JM |
621 | desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
622 | if (!desc) | |
623 | break; | |
624 | __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor)); | |
625 | dma_async_tx_descriptor_init(&desc->desc, chan); | |
626 | desc->desc.tx_submit = imxdma_tx_submit; | |
627 | /* txd.flags will be overwritten in prep funcs */ | |
628 | desc->desc.flags = DMA_CTRL_ACK; | |
629 | desc->status = DMA_SUCCESS; | |
630 | ||
631 | list_add_tail(&desc->node, &imxdmac->ld_free); | |
632 | imxdmac->descs_allocated++; | |
633 | } | |
1f1846c6 | 634 | |
9e15db7c JM |
635 | if (!imxdmac->descs_allocated) |
636 | return -ENOMEM; | |
637 | ||
638 | return imxdmac->descs_allocated; | |
1f1846c6 SH |
639 | } |
640 | ||
641 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
642 | { | |
643 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
9e15db7c JM |
644 | struct imxdma_desc *desc, *_desc; |
645 | unsigned long flags; | |
646 | ||
647 | spin_lock_irqsave(&imxdmac->lock, flags); | |
1f1846c6 | 648 | |
6bd08127 | 649 | imxdma_disable_hw(imxdmac); |
9e15db7c JM |
650 | list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free); |
651 | list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free); | |
652 | ||
653 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
654 | ||
655 | list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) { | |
656 | kfree(desc); | |
657 | imxdmac->descs_allocated--; | |
658 | } | |
659 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
1f1846c6 SH |
660 | |
661 | if (imxdmac->sg_list) { | |
662 | kfree(imxdmac->sg_list); | |
663 | imxdmac->sg_list = NULL; | |
664 | } | |
665 | } | |
666 | ||
667 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
668 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 669 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 670 | unsigned long flags, void *context) |
1f1846c6 SH |
671 | { |
672 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
673 | struct scatterlist *sg; | |
9e15db7c JM |
674 | int i, dma_length = 0; |
675 | struct imxdma_desc *desc; | |
1f1846c6 | 676 | |
9e15db7c JM |
677 | if (list_empty(&imxdmac->ld_free) || |
678 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 SH |
679 | return NULL; |
680 | ||
9e15db7c | 681 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
682 | |
683 | for_each_sg(sgl, sg, sg_len, i) { | |
684 | dma_length += sg->length; | |
685 | } | |
686 | ||
d07102a1 SH |
687 | switch (imxdmac->word_size) { |
688 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
689 | if (sgl->length & 3 || sgl->dma_address & 3) | |
690 | return NULL; | |
691 | break; | |
692 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
693 | if (sgl->length & 1 || sgl->dma_address & 1) | |
694 | return NULL; | |
695 | break; | |
696 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
697 | break; | |
698 | default: | |
699 | return NULL; | |
700 | } | |
701 | ||
9e15db7c JM |
702 | desc->type = IMXDMA_DESC_SLAVE_SG; |
703 | desc->sg = sgl; | |
704 | desc->sgcount = sg_len; | |
705 | desc->len = dma_length; | |
2efc3449 | 706 | desc->direction = direction; |
9e15db7c | 707 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
708 | desc->src = imxdmac->per_address; |
709 | } else { | |
9e15db7c JM |
710 | desc->dest = imxdmac->per_address; |
711 | } | |
712 | desc->desc.callback = NULL; | |
713 | desc->desc.callback_param = NULL; | |
1f1846c6 | 714 | |
9e15db7c | 715 | return &desc->desc; |
1f1846c6 SH |
716 | } |
717 | ||
718 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
719 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f AB |
720 | size_t period_len, enum dma_transfer_direction direction, |
721 | void *context) | |
1f1846c6 SH |
722 | { |
723 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
724 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c JM |
725 | struct imxdma_desc *desc; |
726 | int i; | |
1f1846c6 | 727 | unsigned int periods = buf_len / period_len; |
1f1846c6 SH |
728 | |
729 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
730 | __func__, imxdmac->channel, buf_len, period_len); | |
731 | ||
9e15db7c JM |
732 | if (list_empty(&imxdmac->ld_free) || |
733 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
1f1846c6 | 734 | return NULL; |
1f1846c6 | 735 | |
9e15db7c | 736 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
1f1846c6 SH |
737 | |
738 | if (imxdmac->sg_list) | |
739 | kfree(imxdmac->sg_list); | |
740 | ||
741 | imxdmac->sg_list = kcalloc(periods + 1, | |
742 | sizeof(struct scatterlist), GFP_KERNEL); | |
743 | if (!imxdmac->sg_list) | |
744 | return NULL; | |
745 | ||
746 | sg_init_table(imxdmac->sg_list, periods); | |
747 | ||
748 | for (i = 0; i < periods; i++) { | |
749 | imxdmac->sg_list[i].page_link = 0; | |
750 | imxdmac->sg_list[i].offset = 0; | |
751 | imxdmac->sg_list[i].dma_address = dma_addr; | |
752 | imxdmac->sg_list[i].length = period_len; | |
753 | dma_addr += period_len; | |
754 | } | |
755 | ||
756 | /* close the loop */ | |
757 | imxdmac->sg_list[periods].offset = 0; | |
758 | imxdmac->sg_list[periods].length = 0; | |
759 | imxdmac->sg_list[periods].page_link = | |
760 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
761 | ||
9e15db7c JM |
762 | desc->type = IMXDMA_DESC_CYCLIC; |
763 | desc->sg = imxdmac->sg_list; | |
764 | desc->sgcount = periods; | |
765 | desc->len = IMX_DMA_LENGTH_LOOP; | |
2efc3449 | 766 | desc->direction = direction; |
9e15db7c | 767 | if (direction == DMA_DEV_TO_MEM) { |
9e15db7c JM |
768 | desc->src = imxdmac->per_address; |
769 | } else { | |
9e15db7c JM |
770 | desc->dest = imxdmac->per_address; |
771 | } | |
772 | desc->desc.callback = NULL; | |
773 | desc->desc.callback_param = NULL; | |
1f1846c6 | 774 | |
9e15db7c | 775 | return &desc->desc; |
1f1846c6 SH |
776 | } |
777 | ||
6c05f091 JM |
778 | static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy( |
779 | struct dma_chan *chan, dma_addr_t dest, | |
780 | dma_addr_t src, size_t len, unsigned long flags) | |
781 | { | |
782 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
783 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
9e15db7c | 784 | struct imxdma_desc *desc; |
6c05f091 JM |
785 | |
786 | dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n", | |
787 | __func__, imxdmac->channel, src, dest, len); | |
788 | ||
9e15db7c JM |
789 | if (list_empty(&imxdmac->ld_free) || |
790 | imxdma_chan_is_doing_cyclic(imxdmac)) | |
6c05f091 | 791 | return NULL; |
6c05f091 | 792 | |
9e15db7c | 793 | desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node); |
6c05f091 | 794 | |
9e15db7c JM |
795 | desc->type = IMXDMA_DESC_MEMCPY; |
796 | desc->src = src; | |
797 | desc->dest = dest; | |
798 | desc->len = len; | |
2efc3449 | 799 | desc->direction = DMA_MEM_TO_MEM; |
9e15db7c JM |
800 | desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; |
801 | desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR; | |
802 | desc->desc.callback = NULL; | |
803 | desc->desc.callback_param = NULL; | |
6c05f091 | 804 | |
9e15db7c | 805 | return &desc->desc; |
6c05f091 JM |
806 | } |
807 | ||
1f1846c6 SH |
808 | static void imxdma_issue_pending(struct dma_chan *chan) |
809 | { | |
5b316876 | 810 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
9e15db7c JM |
811 | struct imxdma_engine *imxdma = imxdmac->imxdma; |
812 | struct imxdma_desc *desc; | |
813 | unsigned long flags; | |
814 | ||
815 | spin_lock_irqsave(&imxdmac->lock, flags); | |
816 | if (list_empty(&imxdmac->ld_active) && | |
817 | !list_empty(&imxdmac->ld_queue)) { | |
818 | desc = list_first_entry(&imxdmac->ld_queue, | |
819 | struct imxdma_desc, node); | |
820 | ||
821 | if (imxdma_xfer_desc(desc) < 0) { | |
822 | dev_warn(imxdma->dev, | |
823 | "%s: channel: %d couldn't issue DMA xfer\n", | |
824 | __func__, imxdmac->channel); | |
825 | } else { | |
826 | list_move_tail(imxdmac->ld_queue.next, | |
827 | &imxdmac->ld_active); | |
828 | } | |
829 | } | |
830 | spin_unlock_irqrestore(&imxdmac->lock, flags); | |
1f1846c6 SH |
831 | } |
832 | ||
833 | static int __init imxdma_probe(struct platform_device *pdev) | |
6bd08127 | 834 | { |
1f1846c6 SH |
835 | struct imxdma_engine *imxdma; |
836 | int ret, i; | |
837 | ||
6bd08127 JM |
838 | if (cpu_is_mx1()) |
839 | imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); | |
840 | else if (cpu_is_mx21()) | |
841 | imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); | |
842 | else if (cpu_is_mx27()) | |
843 | imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); | |
844 | else | |
845 | return 0; | |
846 | ||
847 | dma_clk = clk_get(NULL, "dma"); | |
848 | if (IS_ERR(dma_clk)) | |
849 | return PTR_ERR(dma_clk); | |
850 | clk_enable(dma_clk); | |
851 | ||
852 | /* reset DMA module */ | |
853 | imx_dmav1_writel(DCR_DRST, DMA_DCR); | |
854 | ||
855 | if (cpu_is_mx1()) { | |
856 | ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma); | |
857 | if (ret) { | |
858 | pr_crit("Can't register IRQ for DMA\n"); | |
859 | return ret; | |
860 | } | |
861 | ||
862 | ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma); | |
863 | if (ret) { | |
864 | pr_crit("Can't register ERRIRQ for DMA\n"); | |
865 | free_irq(MX1_DMA_INT, NULL); | |
866 | return ret; | |
867 | } | |
868 | } | |
869 | ||
870 | /* enable DMA module */ | |
871 | imx_dmav1_writel(DCR_DEN, DMA_DCR); | |
872 | ||
873 | /* clear all interrupts */ | |
874 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); | |
875 | ||
876 | /* disable interrupts */ | |
877 | imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); | |
878 | ||
1f1846c6 SH |
879 | imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); |
880 | if (!imxdma) | |
881 | return -ENOMEM; | |
882 | ||
883 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
884 | ||
f8a356ff SH |
885 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
886 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
6c05f091 | 887 | dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask); |
f8a356ff | 888 | |
1f1846c6 | 889 | /* Initialize channel parameters */ |
6bd08127 | 890 | for (i = 0; i < IMX_DMA_CHANNELS; i++) { |
1f1846c6 | 891 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
2d9c2fc5 | 892 | |
6bd08127 JM |
893 | if (cpu_is_mx21() || cpu_is_mx27()) { |
894 | ret = request_irq(MX2x_INT_DMACH0 + i, | |
895 | dma_irq_handler, 0, "DMA", imxdma); | |
896 | if (ret) { | |
897 | pr_crit("Can't register IRQ %d for DMA channel %d\n", | |
898 | MX2x_INT_DMACH0 + i, i); | |
899 | goto err_init; | |
900 | } | |
2d9c2fc5 JM |
901 | init_timer(&imxdmac->watchdog); |
902 | imxdmac->watchdog.function = &imxdma_watchdog; | |
903 | imxdmac->watchdog.data = (unsigned long)imxdmac; | |
8267f16e | 904 | } |
1f1846c6 | 905 | |
1f1846c6 SH |
906 | imxdmac->imxdma = imxdma; |
907 | spin_lock_init(&imxdmac->lock); | |
908 | ||
9e15db7c JM |
909 | INIT_LIST_HEAD(&imxdmac->ld_queue); |
910 | INIT_LIST_HEAD(&imxdmac->ld_free); | |
911 | INIT_LIST_HEAD(&imxdmac->ld_active); | |
912 | ||
913 | tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet, | |
914 | (unsigned long)imxdmac); | |
1f1846c6 | 915 | imxdmac->chan.device = &imxdma->dma_device; |
8ac69546 | 916 | dma_cookie_init(&imxdmac->chan); |
1f1846c6 SH |
917 | imxdmac->channel = i; |
918 | ||
919 | /* Add the channel to the DMAC list */ | |
9e15db7c JM |
920 | list_add_tail(&imxdmac->chan.device_node, |
921 | &imxdma->dma_device.channels); | |
1f1846c6 SH |
922 | } |
923 | ||
924 | imxdma->dev = &pdev->dev; | |
925 | imxdma->dma_device.dev = &pdev->dev; | |
926 | ||
927 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
928 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
929 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
930 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
931 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
6c05f091 | 932 | imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy; |
1f1846c6 SH |
933 | imxdma->dma_device.device_control = imxdma_control; |
934 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
935 | ||
936 | platform_set_drvdata(pdev, imxdma); | |
937 | ||
6c05f091 | 938 | imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */ |
1e070a60 SH |
939 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
940 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
941 | ||
1f1846c6 SH |
942 | ret = dma_async_device_register(&imxdma->dma_device); |
943 | if (ret) { | |
944 | dev_err(&pdev->dev, "unable to register\n"); | |
945 | goto err_init; | |
946 | } | |
947 | ||
948 | return 0; | |
949 | ||
950 | err_init: | |
6bd08127 JM |
951 | |
952 | if (cpu_is_mx21() || cpu_is_mx27()) { | |
953 | while (--i >= 0) | |
954 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
955 | } else if cpu_is_mx1() { | |
956 | free_irq(MX1_DMA_INT, NULL); | |
957 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
958 | } |
959 | ||
960 | kfree(imxdma); | |
961 | return ret; | |
962 | } | |
963 | ||
964 | static int __exit imxdma_remove(struct platform_device *pdev) | |
965 | { | |
966 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
967 | int i; | |
968 | ||
969 | dma_async_device_unregister(&imxdma->dma_device); | |
970 | ||
6bd08127 JM |
971 | if (cpu_is_mx21() || cpu_is_mx27()) { |
972 | for (i = 0; i < IMX_DMA_CHANNELS; i++) | |
973 | free_irq(MX2x_INT_DMACH0 + i, NULL); | |
974 | } else if cpu_is_mx1() { | |
975 | free_irq(MX1_DMA_INT, NULL); | |
976 | free_irq(MX1_DMA_ERR, NULL); | |
1f1846c6 SH |
977 | } |
978 | ||
979 | kfree(imxdma); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | static struct platform_driver imxdma_driver = { | |
985 | .driver = { | |
986 | .name = "imx-dma", | |
987 | }, | |
988 | .remove = __exit_p(imxdma_remove), | |
989 | }; | |
990 | ||
991 | static int __init imxdma_module_init(void) | |
992 | { | |
993 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
994 | } | |
995 | subsys_initcall(imxdma_module_init); | |
996 | ||
997 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
998 | MODULE_DESCRIPTION("i.MX dma driver"); | |
999 | MODULE_LICENSE("GPL"); |