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1f1846c6 SH |
1 | /* |
2 | * drivers/dma/imx-dma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale i.MX DMA engine | |
5 | * found on i.MX1/21/27 | |
6 | * | |
7 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
8 | * | |
9 | * The code contained herein is licensed under the GNU General Public | |
10 | * License. You may obtain a copy of the GNU General Public License | |
11 | * Version 2 or later at the following locations: | |
12 | * | |
13 | * http://www.opensource.org/licenses/gpl-license.html | |
14 | * http://www.gnu.org/copyleft/gpl.html | |
15 | */ | |
16 | #include <linux/init.h> | |
f8de8f4c | 17 | #include <linux/module.h> |
1f1846c6 SH |
18 | #include <linux/types.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/dmaengine.h> | |
5c45ad77 | 27 | #include <linux/module.h> |
1f1846c6 SH |
28 | |
29 | #include <asm/irq.h> | |
30 | #include <mach/dma-v1.h> | |
31 | #include <mach/hardware.h> | |
32 | ||
33 | struct imxdma_channel { | |
34 | struct imxdma_engine *imxdma; | |
35 | unsigned int channel; | |
36 | unsigned int imxdma_channel; | |
37 | ||
38 | enum dma_slave_buswidth word_size; | |
39 | dma_addr_t per_address; | |
40 | u32 watermark_level; | |
41 | struct dma_chan chan; | |
42 | spinlock_t lock; | |
43 | struct dma_async_tx_descriptor desc; | |
1f1846c6 SH |
44 | enum dma_status status; |
45 | int dma_request; | |
46 | struct scatterlist *sg_list; | |
47 | }; | |
48 | ||
49 | #define MAX_DMA_CHANNELS 8 | |
50 | ||
51 | struct imxdma_engine { | |
52 | struct device *dev; | |
1e070a60 | 53 | struct device_dma_parameters dma_parms; |
1f1846c6 SH |
54 | struct dma_device dma_device; |
55 | struct imxdma_channel channel[MAX_DMA_CHANNELS]; | |
56 | }; | |
57 | ||
58 | static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan) | |
59 | { | |
60 | return container_of(chan, struct imxdma_channel, chan); | |
61 | } | |
62 | ||
63 | static void imxdma_handle(struct imxdma_channel *imxdmac) | |
64 | { | |
65 | if (imxdmac->desc.callback) | |
66 | imxdmac->desc.callback(imxdmac->desc.callback_param); | |
4d4e58de | 67 | imxdmac->chan.completed_cookie = imxdmac->desc.cookie; |
1f1846c6 SH |
68 | } |
69 | ||
70 | static void imxdma_irq_handler(int channel, void *data) | |
71 | { | |
72 | struct imxdma_channel *imxdmac = data; | |
73 | ||
74 | imxdmac->status = DMA_SUCCESS; | |
75 | imxdma_handle(imxdmac); | |
76 | } | |
77 | ||
78 | static void imxdma_err_handler(int channel, void *data, int error) | |
79 | { | |
80 | struct imxdma_channel *imxdmac = data; | |
81 | ||
82 | imxdmac->status = DMA_ERROR; | |
83 | imxdma_handle(imxdmac); | |
84 | } | |
85 | ||
86 | static void imxdma_progression(int channel, void *data, | |
87 | struct scatterlist *sg) | |
88 | { | |
89 | struct imxdma_channel *imxdmac = data; | |
90 | ||
91 | imxdmac->status = DMA_SUCCESS; | |
92 | imxdma_handle(imxdmac); | |
93 | } | |
94 | ||
95 | static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
96 | unsigned long arg) | |
97 | { | |
98 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
99 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
100 | int ret; | |
101 | unsigned int mode = 0; | |
102 | ||
103 | switch (cmd) { | |
104 | case DMA_TERMINATE_ALL: | |
105 | imxdmac->status = DMA_ERROR; | |
106 | imx_dma_disable(imxdmac->imxdma_channel); | |
107 | return 0; | |
108 | case DMA_SLAVE_CONFIG: | |
db8196df | 109 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1f1846c6 SH |
110 | imxdmac->per_address = dmaengine_cfg->src_addr; |
111 | imxdmac->watermark_level = dmaengine_cfg->src_maxburst; | |
112 | imxdmac->word_size = dmaengine_cfg->src_addr_width; | |
113 | } else { | |
114 | imxdmac->per_address = dmaengine_cfg->dst_addr; | |
115 | imxdmac->watermark_level = dmaengine_cfg->dst_maxburst; | |
116 | imxdmac->word_size = dmaengine_cfg->dst_addr_width; | |
117 | } | |
118 | ||
119 | switch (imxdmac->word_size) { | |
120 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
121 | mode = IMX_DMA_MEMSIZE_8; | |
122 | break; | |
123 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
124 | mode = IMX_DMA_MEMSIZE_16; | |
125 | break; | |
126 | default: | |
127 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
128 | mode = IMX_DMA_MEMSIZE_32; | |
129 | break; | |
130 | } | |
131 | ret = imx_dma_config_channel(imxdmac->imxdma_channel, | |
132 | mode | IMX_DMA_TYPE_FIFO, | |
133 | IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, | |
134 | imxdmac->dma_request, 1); | |
135 | ||
136 | if (ret) | |
137 | return ret; | |
138 | ||
6584cb88 SH |
139 | imx_dma_config_burstlen(imxdmac->imxdma_channel, |
140 | imxdmac->watermark_level * imxdmac->word_size); | |
1f1846c6 SH |
141 | |
142 | return 0; | |
143 | default: | |
144 | return -ENOSYS; | |
145 | } | |
146 | ||
147 | return -EINVAL; | |
148 | } | |
149 | ||
150 | static enum dma_status imxdma_tx_status(struct dma_chan *chan, | |
151 | dma_cookie_t cookie, | |
152 | struct dma_tx_state *txstate) | |
153 | { | |
154 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
155 | dma_cookie_t last_used; | |
156 | enum dma_status ret; | |
157 | ||
158 | last_used = chan->cookie; | |
159 | ||
4d4e58de RKAL |
160 | ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used); |
161 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0); | |
1f1846c6 SH |
162 | |
163 | return ret; | |
164 | } | |
165 | ||
166 | static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma) | |
167 | { | |
168 | dma_cookie_t cookie = imxdma->chan.cookie; | |
169 | ||
170 | if (++cookie < 0) | |
171 | cookie = 1; | |
172 | ||
173 | imxdma->chan.cookie = cookie; | |
174 | imxdma->desc.cookie = cookie; | |
175 | ||
176 | return cookie; | |
177 | } | |
178 | ||
179 | static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
180 | { | |
181 | struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan); | |
182 | dma_cookie_t cookie; | |
183 | ||
184 | spin_lock_irq(&imxdmac->lock); | |
185 | ||
186 | cookie = imxdma_assign_cookie(imxdmac); | |
187 | ||
1f1846c6 SH |
188 | spin_unlock_irq(&imxdmac->lock); |
189 | ||
190 | return cookie; | |
191 | } | |
192 | ||
193 | static int imxdma_alloc_chan_resources(struct dma_chan *chan) | |
194 | { | |
195 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
196 | struct imx_dma_data *data = chan->private; | |
197 | ||
198 | imxdmac->dma_request = data->dma_request; | |
199 | ||
200 | dma_async_tx_descriptor_init(&imxdmac->desc, chan); | |
201 | imxdmac->desc.tx_submit = imxdma_tx_submit; | |
202 | /* txd.flags will be overwritten in prep funcs */ | |
203 | imxdmac->desc.flags = DMA_CTRL_ACK; | |
204 | ||
205 | imxdmac->status = DMA_SUCCESS; | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static void imxdma_free_chan_resources(struct dma_chan *chan) | |
211 | { | |
212 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
213 | ||
214 | imx_dma_disable(imxdmac->imxdma_channel); | |
215 | ||
216 | if (imxdmac->sg_list) { | |
217 | kfree(imxdmac->sg_list); | |
218 | imxdmac->sg_list = NULL; | |
219 | } | |
220 | } | |
221 | ||
222 | static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( | |
223 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 224 | unsigned int sg_len, enum dma_transfer_direction direction, |
1f1846c6 SH |
225 | unsigned long flags) |
226 | { | |
227 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
228 | struct scatterlist *sg; | |
229 | int i, ret, dma_length = 0; | |
230 | unsigned int dmamode; | |
231 | ||
232 | if (imxdmac->status == DMA_IN_PROGRESS) | |
233 | return NULL; | |
234 | ||
235 | imxdmac->status = DMA_IN_PROGRESS; | |
236 | ||
237 | for_each_sg(sgl, sg, sg_len, i) { | |
238 | dma_length += sg->length; | |
239 | } | |
240 | ||
db8196df | 241 | if (direction == DMA_DEV_TO_MEM) |
1f1846c6 SH |
242 | dmamode = DMA_MODE_READ; |
243 | else | |
244 | dmamode = DMA_MODE_WRITE; | |
245 | ||
d07102a1 SH |
246 | switch (imxdmac->word_size) { |
247 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
248 | if (sgl->length & 3 || sgl->dma_address & 3) | |
249 | return NULL; | |
250 | break; | |
251 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
252 | if (sgl->length & 1 || sgl->dma_address & 1) | |
253 | return NULL; | |
254 | break; | |
255 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
256 | break; | |
257 | default: | |
258 | return NULL; | |
259 | } | |
260 | ||
1f1846c6 SH |
261 | ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len, |
262 | dma_length, imxdmac->per_address, dmamode); | |
263 | if (ret) | |
264 | return NULL; | |
265 | ||
266 | return &imxdmac->desc; | |
267 | } | |
268 | ||
269 | static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( | |
270 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
db8196df | 271 | size_t period_len, enum dma_transfer_direction direction) |
1f1846c6 SH |
272 | { |
273 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); | |
274 | struct imxdma_engine *imxdma = imxdmac->imxdma; | |
275 | int i, ret; | |
276 | unsigned int periods = buf_len / period_len; | |
277 | unsigned int dmamode; | |
278 | ||
279 | dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n", | |
280 | __func__, imxdmac->channel, buf_len, period_len); | |
281 | ||
282 | if (imxdmac->status == DMA_IN_PROGRESS) | |
283 | return NULL; | |
284 | imxdmac->status = DMA_IN_PROGRESS; | |
285 | ||
286 | ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel, | |
287 | imxdma_progression); | |
288 | if (ret) { | |
289 | dev_err(imxdma->dev, "Failed to setup the DMA handler\n"); | |
290 | return NULL; | |
291 | } | |
292 | ||
293 | if (imxdmac->sg_list) | |
294 | kfree(imxdmac->sg_list); | |
295 | ||
296 | imxdmac->sg_list = kcalloc(periods + 1, | |
297 | sizeof(struct scatterlist), GFP_KERNEL); | |
298 | if (!imxdmac->sg_list) | |
299 | return NULL; | |
300 | ||
301 | sg_init_table(imxdmac->sg_list, periods); | |
302 | ||
303 | for (i = 0; i < periods; i++) { | |
304 | imxdmac->sg_list[i].page_link = 0; | |
305 | imxdmac->sg_list[i].offset = 0; | |
306 | imxdmac->sg_list[i].dma_address = dma_addr; | |
307 | imxdmac->sg_list[i].length = period_len; | |
308 | dma_addr += period_len; | |
309 | } | |
310 | ||
311 | /* close the loop */ | |
312 | imxdmac->sg_list[periods].offset = 0; | |
313 | imxdmac->sg_list[periods].length = 0; | |
314 | imxdmac->sg_list[periods].page_link = | |
315 | ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; | |
316 | ||
db8196df | 317 | if (direction == DMA_DEV_TO_MEM) |
1f1846c6 SH |
318 | dmamode = DMA_MODE_READ; |
319 | else | |
320 | dmamode = DMA_MODE_WRITE; | |
321 | ||
322 | ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods, | |
323 | IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode); | |
324 | if (ret) | |
325 | return NULL; | |
326 | ||
327 | return &imxdmac->desc; | |
328 | } | |
329 | ||
330 | static void imxdma_issue_pending(struct dma_chan *chan) | |
331 | { | |
5b316876 SH |
332 | struct imxdma_channel *imxdmac = to_imxdma_chan(chan); |
333 | ||
334 | if (imxdmac->status == DMA_IN_PROGRESS) | |
335 | imx_dma_enable(imxdmac->imxdma_channel); | |
1f1846c6 SH |
336 | } |
337 | ||
338 | static int __init imxdma_probe(struct platform_device *pdev) | |
339 | { | |
340 | struct imxdma_engine *imxdma; | |
341 | int ret, i; | |
342 | ||
343 | imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL); | |
344 | if (!imxdma) | |
345 | return -ENOMEM; | |
346 | ||
347 | INIT_LIST_HEAD(&imxdma->dma_device.channels); | |
348 | ||
f8a356ff SH |
349 | dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask); |
350 | dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask); | |
351 | ||
1f1846c6 SH |
352 | /* Initialize channel parameters */ |
353 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
354 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; | |
355 | ||
356 | imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine", | |
357 | DMA_PRIO_MEDIUM); | |
8267f16e SH |
358 | if ((int)imxdmac->channel < 0) { |
359 | ret = -ENODEV; | |
1f1846c6 | 360 | goto err_init; |
8267f16e | 361 | } |
1f1846c6 SH |
362 | |
363 | imx_dma_setup_handlers(imxdmac->imxdma_channel, | |
364 | imxdma_irq_handler, imxdma_err_handler, imxdmac); | |
365 | ||
366 | imxdmac->imxdma = imxdma; | |
367 | spin_lock_init(&imxdmac->lock); | |
368 | ||
1f1846c6 | 369 | imxdmac->chan.device = &imxdma->dma_device; |
1f1846c6 SH |
370 | imxdmac->channel = i; |
371 | ||
372 | /* Add the channel to the DMAC list */ | |
373 | list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels); | |
374 | } | |
375 | ||
376 | imxdma->dev = &pdev->dev; | |
377 | imxdma->dma_device.dev = &pdev->dev; | |
378 | ||
379 | imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources; | |
380 | imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources; | |
381 | imxdma->dma_device.device_tx_status = imxdma_tx_status; | |
382 | imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg; | |
383 | imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic; | |
384 | imxdma->dma_device.device_control = imxdma_control; | |
385 | imxdma->dma_device.device_issue_pending = imxdma_issue_pending; | |
386 | ||
387 | platform_set_drvdata(pdev, imxdma); | |
388 | ||
1e070a60 SH |
389 | imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms; |
390 | dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff); | |
391 | ||
1f1846c6 SH |
392 | ret = dma_async_device_register(&imxdma->dma_device); |
393 | if (ret) { | |
394 | dev_err(&pdev->dev, "unable to register\n"); | |
395 | goto err_init; | |
396 | } | |
397 | ||
398 | return 0; | |
399 | ||
400 | err_init: | |
cbeae418 | 401 | while (--i >= 0) { |
1f1846c6 SH |
402 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; |
403 | imx_dma_free(imxdmac->imxdma_channel); | |
404 | } | |
405 | ||
406 | kfree(imxdma); | |
407 | return ret; | |
408 | } | |
409 | ||
410 | static int __exit imxdma_remove(struct platform_device *pdev) | |
411 | { | |
412 | struct imxdma_engine *imxdma = platform_get_drvdata(pdev); | |
413 | int i; | |
414 | ||
415 | dma_async_device_unregister(&imxdma->dma_device); | |
416 | ||
417 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
418 | struct imxdma_channel *imxdmac = &imxdma->channel[i]; | |
419 | ||
420 | imx_dma_free(imxdmac->imxdma_channel); | |
421 | } | |
422 | ||
423 | kfree(imxdma); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
428 | static struct platform_driver imxdma_driver = { | |
429 | .driver = { | |
430 | .name = "imx-dma", | |
431 | }, | |
432 | .remove = __exit_p(imxdma_remove), | |
433 | }; | |
434 | ||
435 | static int __init imxdma_module_init(void) | |
436 | { | |
437 | return platform_driver_probe(&imxdma_driver, imxdma_probe); | |
438 | } | |
439 | subsys_initcall(imxdma_module_init); | |
440 | ||
441 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
442 | MODULE_DESCRIPTION("i.MX dma driver"); | |
443 | MODULE_LICENSE("GPL"); |