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1ec1e82f SH |
1 | /* |
2 | * drivers/dma/imx-sdma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale Smart DMA engine | |
5 | * | |
6 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
7 | * | |
8 | * Based on code from Freescale: | |
9 | * | |
10 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
11 | * | |
12 | * The code contained herein is licensed under the GNU General Public | |
13 | * License. You may obtain a copy of the GNU General Public License | |
14 | * Version 2 or later at the following locations: | |
15 | * | |
16 | * http://www.opensource.org/licenses/gpl-license.html | |
17 | * http://www.gnu.org/copyleft/gpl.html | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
1d069bfa | 21 | #include <linux/iopoll.h> |
f8de8f4c | 22 | #include <linux/module.h> |
1ec1e82f | 23 | #include <linux/types.h> |
0bbc1413 | 24 | #include <linux/bitops.h> |
1ec1e82f SH |
25 | #include <linux/mm.h> |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/clk.h> | |
2ccaef05 | 28 | #include <linux/delay.h> |
1ec1e82f SH |
29 | #include <linux/sched.h> |
30 | #include <linux/semaphore.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/device.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/firmware.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/dmaengine.h> | |
580975d7 | 38 | #include <linux/of.h> |
8391ecf4 | 39 | #include <linux/of_address.h> |
580975d7 | 40 | #include <linux/of_device.h> |
9479e17c | 41 | #include <linux/of_dma.h> |
1ec1e82f SH |
42 | |
43 | #include <asm/irq.h> | |
82906b13 AB |
44 | #include <linux/platform_data/dma-imx-sdma.h> |
45 | #include <linux/platform_data/dma-imx.h> | |
d078cd1b ZW |
46 | #include <linux/regmap.h> |
47 | #include <linux/mfd/syscon.h> | |
48 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
1ec1e82f | 49 | |
d2ebfb33 RKAL |
50 | #include "dmaengine.h" |
51 | ||
1ec1e82f SH |
52 | /* SDMA registers */ |
53 | #define SDMA_H_C0PTR 0x000 | |
54 | #define SDMA_H_INTR 0x004 | |
55 | #define SDMA_H_STATSTOP 0x008 | |
56 | #define SDMA_H_START 0x00c | |
57 | #define SDMA_H_EVTOVR 0x010 | |
58 | #define SDMA_H_DSPOVR 0x014 | |
59 | #define SDMA_H_HOSTOVR 0x018 | |
60 | #define SDMA_H_EVTPEND 0x01c | |
61 | #define SDMA_H_DSPENBL 0x020 | |
62 | #define SDMA_H_RESET 0x024 | |
63 | #define SDMA_H_EVTERR 0x028 | |
64 | #define SDMA_H_INTRMSK 0x02c | |
65 | #define SDMA_H_PSW 0x030 | |
66 | #define SDMA_H_EVTERRDBG 0x034 | |
67 | #define SDMA_H_CONFIG 0x038 | |
68 | #define SDMA_ONCE_ENB 0x040 | |
69 | #define SDMA_ONCE_DATA 0x044 | |
70 | #define SDMA_ONCE_INSTR 0x048 | |
71 | #define SDMA_ONCE_STAT 0x04c | |
72 | #define SDMA_ONCE_CMD 0x050 | |
73 | #define SDMA_EVT_MIRROR 0x054 | |
74 | #define SDMA_ILLINSTADDR 0x058 | |
75 | #define SDMA_CHN0ADDR 0x05c | |
76 | #define SDMA_ONCE_RTB 0x060 | |
77 | #define SDMA_XTRIG_CONF1 0x070 | |
78 | #define SDMA_XTRIG_CONF2 0x074 | |
62550cd7 SG |
79 | #define SDMA_CHNENBL0_IMX35 0x200 |
80 | #define SDMA_CHNENBL0_IMX31 0x080 | |
1ec1e82f SH |
81 | #define SDMA_CHNPRI_0 0x100 |
82 | ||
83 | /* | |
84 | * Buffer descriptor status values. | |
85 | */ | |
86 | #define BD_DONE 0x01 | |
87 | #define BD_WRAP 0x02 | |
88 | #define BD_CONT 0x04 | |
89 | #define BD_INTR 0x08 | |
90 | #define BD_RROR 0x10 | |
91 | #define BD_LAST 0x20 | |
92 | #define BD_EXTD 0x80 | |
93 | ||
94 | /* | |
95 | * Data Node descriptor status values. | |
96 | */ | |
97 | #define DND_END_OF_FRAME 0x80 | |
98 | #define DND_END_OF_XFER 0x40 | |
99 | #define DND_DONE 0x20 | |
100 | #define DND_UNUSED 0x01 | |
101 | ||
102 | /* | |
103 | * IPCV2 descriptor status values. | |
104 | */ | |
105 | #define BD_IPCV2_END_OF_FRAME 0x40 | |
106 | ||
107 | #define IPCV2_MAX_NODES 50 | |
108 | /* | |
109 | * Error bit set in the CCB status field by the SDMA, | |
110 | * in setbd routine, in case of a transfer error | |
111 | */ | |
112 | #define DATA_ERROR 0x10000000 | |
113 | ||
114 | /* | |
115 | * Buffer descriptor commands. | |
116 | */ | |
117 | #define C0_ADDR 0x01 | |
118 | #define C0_LOAD 0x02 | |
119 | #define C0_DUMP 0x03 | |
120 | #define C0_SETCTX 0x07 | |
121 | #define C0_GETCTX 0x03 | |
122 | #define C0_SETDM 0x01 | |
123 | #define C0_SETPM 0x04 | |
124 | #define C0_GETDM 0x02 | |
125 | #define C0_GETPM 0x08 | |
126 | /* | |
127 | * Change endianness indicator in the BD command field | |
128 | */ | |
129 | #define CHANGE_ENDIANNESS 0x80 | |
130 | ||
8391ecf4 SW |
131 | /* |
132 | * p_2_p watermark_level description | |
133 | * Bits Name Description | |
134 | * 0-7 Lower WML Lower watermark level | |
135 | * 8 PS 1: Pad Swallowing | |
136 | * 0: No Pad Swallowing | |
137 | * 9 PA 1: Pad Adding | |
138 | * 0: No Pad Adding | |
139 | * 10 SPDIF If this bit is set both source | |
140 | * and destination are on SPBA | |
141 | * 11 Source Bit(SP) 1: Source on SPBA | |
142 | * 0: Source on AIPS | |
143 | * 12 Destination Bit(DP) 1: Destination on SPBA | |
144 | * 0: Destination on AIPS | |
145 | * 13-15 --------- MUST BE 0 | |
146 | * 16-23 Higher WML HWML | |
147 | * 24-27 N Total number of samples after | |
148 | * which Pad adding/Swallowing | |
149 | * must be done. It must be odd. | |
150 | * 28 Lower WML Event(LWE) SDMA events reg to check for | |
151 | * LWML event mask | |
152 | * 0: LWE in EVENTS register | |
153 | * 1: LWE in EVENTS2 register | |
154 | * 29 Higher WML Event(HWE) SDMA events reg to check for | |
155 | * HWML event mask | |
156 | * 0: HWE in EVENTS register | |
157 | * 1: HWE in EVENTS2 register | |
158 | * 30 --------- MUST BE 0 | |
159 | * 31 CONT 1: Amount of samples to be | |
160 | * transferred is unknown and | |
161 | * script will keep on | |
162 | * transferring samples as long as | |
163 | * both events are detected and | |
164 | * script must be manually stopped | |
165 | * by the application | |
166 | * 0: The amount of samples to be | |
167 | * transferred is equal to the | |
168 | * count field of mode word | |
169 | */ | |
170 | #define SDMA_WATERMARK_LEVEL_LWML 0xFF | |
171 | #define SDMA_WATERMARK_LEVEL_PS BIT(8) | |
172 | #define SDMA_WATERMARK_LEVEL_PA BIT(9) | |
173 | #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10) | |
174 | #define SDMA_WATERMARK_LEVEL_SP BIT(11) | |
175 | #define SDMA_WATERMARK_LEVEL_DP BIT(12) | |
176 | #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16) | |
177 | #define SDMA_WATERMARK_LEVEL_LWE BIT(28) | |
178 | #define SDMA_WATERMARK_LEVEL_HWE BIT(29) | |
179 | #define SDMA_WATERMARK_LEVEL_CONT BIT(31) | |
180 | ||
f9d4a398 NC |
181 | #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
182 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
183 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
184 | ||
185 | #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \ | |
186 | BIT(DMA_MEM_TO_DEV) | \ | |
187 | BIT(DMA_DEV_TO_DEV)) | |
188 | ||
1ec1e82f SH |
189 | /* |
190 | * Mode/Count of data node descriptors - IPCv2 | |
191 | */ | |
192 | struct sdma_mode_count { | |
193 | u32 count : 16; /* size of the buffer pointed by this BD */ | |
194 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ | |
e4b75760 | 195 | u32 command : 8; /* command mostly used for channel 0 */ |
1ec1e82f SH |
196 | }; |
197 | ||
198 | /* | |
199 | * Buffer descriptor | |
200 | */ | |
201 | struct sdma_buffer_descriptor { | |
202 | struct sdma_mode_count mode; | |
203 | u32 buffer_addr; /* address of the buffer described */ | |
204 | u32 ext_buffer_addr; /* extended buffer address */ | |
205 | } __attribute__ ((packed)); | |
206 | ||
207 | /** | |
208 | * struct sdma_channel_control - Channel control Block | |
209 | * | |
210 | * @current_bd_ptr current buffer descriptor processed | |
211 | * @base_bd_ptr first element of buffer descriptor array | |
212 | * @unused padding. The SDMA engine expects an array of 128 byte | |
213 | * control blocks | |
214 | */ | |
215 | struct sdma_channel_control { | |
216 | u32 current_bd_ptr; | |
217 | u32 base_bd_ptr; | |
218 | u32 unused[2]; | |
219 | } __attribute__ ((packed)); | |
220 | ||
221 | /** | |
222 | * struct sdma_state_registers - SDMA context for a channel | |
223 | * | |
224 | * @pc: program counter | |
225 | * @t: test bit: status of arithmetic & test instruction | |
226 | * @rpc: return program counter | |
227 | * @sf: source fault while loading data | |
228 | * @spc: loop start program counter | |
229 | * @df: destination fault while storing data | |
230 | * @epc: loop end program counter | |
231 | * @lm: loop mode | |
232 | */ | |
233 | struct sdma_state_registers { | |
234 | u32 pc :14; | |
235 | u32 unused1: 1; | |
236 | u32 t : 1; | |
237 | u32 rpc :14; | |
238 | u32 unused0: 1; | |
239 | u32 sf : 1; | |
240 | u32 spc :14; | |
241 | u32 unused2: 1; | |
242 | u32 df : 1; | |
243 | u32 epc :14; | |
244 | u32 lm : 2; | |
245 | } __attribute__ ((packed)); | |
246 | ||
247 | /** | |
248 | * struct sdma_context_data - sdma context specific to a channel | |
249 | * | |
250 | * @channel_state: channel state bits | |
251 | * @gReg: general registers | |
252 | * @mda: burst dma destination address register | |
253 | * @msa: burst dma source address register | |
254 | * @ms: burst dma status register | |
255 | * @md: burst dma data register | |
256 | * @pda: peripheral dma destination address register | |
257 | * @psa: peripheral dma source address register | |
258 | * @ps: peripheral dma status register | |
259 | * @pd: peripheral dma data register | |
260 | * @ca: CRC polynomial register | |
261 | * @cs: CRC accumulator register | |
262 | * @dda: dedicated core destination address register | |
263 | * @dsa: dedicated core source address register | |
264 | * @ds: dedicated core status register | |
265 | * @dd: dedicated core data register | |
266 | */ | |
267 | struct sdma_context_data { | |
268 | struct sdma_state_registers channel_state; | |
269 | u32 gReg[8]; | |
270 | u32 mda; | |
271 | u32 msa; | |
272 | u32 ms; | |
273 | u32 md; | |
274 | u32 pda; | |
275 | u32 psa; | |
276 | u32 ps; | |
277 | u32 pd; | |
278 | u32 ca; | |
279 | u32 cs; | |
280 | u32 dda; | |
281 | u32 dsa; | |
282 | u32 ds; | |
283 | u32 dd; | |
284 | u32 scratch0; | |
285 | u32 scratch1; | |
286 | u32 scratch2; | |
287 | u32 scratch3; | |
288 | u32 scratch4; | |
289 | u32 scratch5; | |
290 | u32 scratch6; | |
291 | u32 scratch7; | |
292 | } __attribute__ ((packed)); | |
293 | ||
294 | #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) | |
295 | ||
296 | struct sdma_engine; | |
297 | ||
298 | /** | |
299 | * struct sdma_channel - housekeeping for a SDMA channel | |
300 | * | |
301 | * @sdma pointer to the SDMA engine for this channel | |
23889c63 | 302 | * @channel the channel number, matches dmaengine chan_id + 1 |
1ec1e82f SH |
303 | * @direction transfer type. Needed for setting SDMA script |
304 | * @peripheral_type Peripheral type. Needed for setting SDMA script | |
305 | * @event_id0 aka dma request line | |
306 | * @event_id1 for channels that use 2 events | |
307 | * @word_size peripheral access size | |
308 | * @buf_tail ID of the buffer that was processed | |
85f57752 | 309 | * @buf_ptail ID of the previous buffer that was processed |
1ec1e82f SH |
310 | * @num_bd max NUM_BD. number of descriptors currently handling |
311 | */ | |
312 | struct sdma_channel { | |
313 | struct sdma_engine *sdma; | |
314 | unsigned int channel; | |
db8196df | 315 | enum dma_transfer_direction direction; |
1ec1e82f SH |
316 | enum sdma_peripheral_type peripheral_type; |
317 | unsigned int event_id0; | |
318 | unsigned int event_id1; | |
319 | enum dma_slave_buswidth word_size; | |
320 | unsigned int buf_tail; | |
85f57752 | 321 | unsigned int buf_ptail; |
1ec1e82f | 322 | unsigned int num_bd; |
d1a792f3 | 323 | unsigned int period_len; |
1ec1e82f SH |
324 | struct sdma_buffer_descriptor *bd; |
325 | dma_addr_t bd_phys; | |
326 | unsigned int pc_from_device, pc_to_device; | |
8391ecf4 | 327 | unsigned int device_to_device; |
1ec1e82f | 328 | unsigned long flags; |
8391ecf4 | 329 | dma_addr_t per_address, per_address2; |
0bbc1413 RZ |
330 | unsigned long event_mask[2]; |
331 | unsigned long watermark_level; | |
1ec1e82f SH |
332 | u32 shp_addr, per_addr; |
333 | struct dma_chan chan; | |
334 | spinlock_t lock; | |
335 | struct dma_async_tx_descriptor desc; | |
1ec1e82f | 336 | enum dma_status status; |
ab59a510 HS |
337 | unsigned int chn_count; |
338 | unsigned int chn_real_count; | |
abd9ccc8 | 339 | struct tasklet_struct tasklet; |
0b351865 | 340 | struct imx_dma_data data; |
2746e2c3 | 341 | bool enabled; |
1ec1e82f SH |
342 | }; |
343 | ||
0bbc1413 | 344 | #define IMX_DMA_SG_LOOP BIT(0) |
1ec1e82f SH |
345 | |
346 | #define MAX_DMA_CHANNELS 32 | |
347 | #define MXC_SDMA_DEFAULT_PRIORITY 1 | |
348 | #define MXC_SDMA_MIN_PRIORITY 1 | |
349 | #define MXC_SDMA_MAX_PRIORITY 7 | |
350 | ||
1ec1e82f SH |
351 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
352 | ||
353 | /** | |
354 | * struct sdma_firmware_header - Layout of the firmware image | |
355 | * | |
356 | * @magic "SDMA" | |
357 | * @version_major increased whenever layout of struct sdma_script_start_addrs | |
358 | * changes. | |
359 | * @version_minor firmware minor version (for binary compatible changes) | |
360 | * @script_addrs_start offset of struct sdma_script_start_addrs in this image | |
361 | * @num_script_addrs Number of script addresses in this image | |
362 | * @ram_code_start offset of SDMA ram image in this firmware image | |
363 | * @ram_code_size size of SDMA ram image | |
364 | * @script_addrs Stores the start address of the SDMA scripts | |
365 | * (in SDMA memory space) | |
366 | */ | |
367 | struct sdma_firmware_header { | |
368 | u32 magic; | |
369 | u32 version_major; | |
370 | u32 version_minor; | |
371 | u32 script_addrs_start; | |
372 | u32 num_script_addrs; | |
373 | u32 ram_code_start; | |
374 | u32 ram_code_size; | |
375 | }; | |
376 | ||
17bba72f SH |
377 | struct sdma_driver_data { |
378 | int chnenbl0; | |
379 | int num_events; | |
dcfec3c0 | 380 | struct sdma_script_start_addrs *script_addrs; |
62550cd7 SG |
381 | }; |
382 | ||
1ec1e82f SH |
383 | struct sdma_engine { |
384 | struct device *dev; | |
b9b3f82f | 385 | struct device_dma_parameters dma_parms; |
1ec1e82f SH |
386 | struct sdma_channel channel[MAX_DMA_CHANNELS]; |
387 | struct sdma_channel_control *channel_control; | |
388 | void __iomem *regs; | |
1ec1e82f SH |
389 | struct sdma_context_data *context; |
390 | dma_addr_t context_phys; | |
391 | struct dma_device dma_device; | |
7560e3f3 SH |
392 | struct clk *clk_ipg; |
393 | struct clk *clk_ahb; | |
2ccaef05 | 394 | spinlock_t channel_0_lock; |
cd72b846 | 395 | u32 script_number; |
1ec1e82f | 396 | struct sdma_script_start_addrs *script_addrs; |
17bba72f | 397 | const struct sdma_driver_data *drvdata; |
8391ecf4 SW |
398 | u32 spba_start_addr; |
399 | u32 spba_end_addr; | |
5bb9dbb5 | 400 | unsigned int irq; |
17bba72f SH |
401 | }; |
402 | ||
e9fd58de | 403 | static struct sdma_driver_data sdma_imx31 = { |
17bba72f SH |
404 | .chnenbl0 = SDMA_CHNENBL0_IMX31, |
405 | .num_events = 32, | |
406 | }; | |
407 | ||
dcfec3c0 SH |
408 | static struct sdma_script_start_addrs sdma_script_imx25 = { |
409 | .ap_2_ap_addr = 729, | |
410 | .uart_2_mcu_addr = 904, | |
411 | .per_2_app_addr = 1255, | |
412 | .mcu_2_app_addr = 834, | |
413 | .uartsh_2_mcu_addr = 1120, | |
414 | .per_2_shp_addr = 1329, | |
415 | .mcu_2_shp_addr = 1048, | |
416 | .ata_2_mcu_addr = 1560, | |
417 | .mcu_2_ata_addr = 1479, | |
418 | .app_2_per_addr = 1189, | |
419 | .app_2_mcu_addr = 770, | |
420 | .shp_2_per_addr = 1407, | |
421 | .shp_2_mcu_addr = 979, | |
422 | }; | |
423 | ||
e9fd58de | 424 | static struct sdma_driver_data sdma_imx25 = { |
dcfec3c0 SH |
425 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
426 | .num_events = 48, | |
427 | .script_addrs = &sdma_script_imx25, | |
428 | }; | |
429 | ||
e9fd58de | 430 | static struct sdma_driver_data sdma_imx35 = { |
17bba72f SH |
431 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
432 | .num_events = 48, | |
1ec1e82f SH |
433 | }; |
434 | ||
dcfec3c0 SH |
435 | static struct sdma_script_start_addrs sdma_script_imx51 = { |
436 | .ap_2_ap_addr = 642, | |
437 | .uart_2_mcu_addr = 817, | |
438 | .mcu_2_app_addr = 747, | |
439 | .mcu_2_shp_addr = 961, | |
440 | .ata_2_mcu_addr = 1473, | |
441 | .mcu_2_ata_addr = 1392, | |
442 | .app_2_per_addr = 1033, | |
443 | .app_2_mcu_addr = 683, | |
444 | .shp_2_per_addr = 1251, | |
445 | .shp_2_mcu_addr = 892, | |
446 | }; | |
447 | ||
e9fd58de | 448 | static struct sdma_driver_data sdma_imx51 = { |
dcfec3c0 SH |
449 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
450 | .num_events = 48, | |
451 | .script_addrs = &sdma_script_imx51, | |
452 | }; | |
453 | ||
454 | static struct sdma_script_start_addrs sdma_script_imx53 = { | |
455 | .ap_2_ap_addr = 642, | |
456 | .app_2_mcu_addr = 683, | |
457 | .mcu_2_app_addr = 747, | |
458 | .uart_2_mcu_addr = 817, | |
459 | .shp_2_mcu_addr = 891, | |
460 | .mcu_2_shp_addr = 960, | |
461 | .uartsh_2_mcu_addr = 1032, | |
462 | .spdif_2_mcu_addr = 1100, | |
463 | .mcu_2_spdif_addr = 1134, | |
464 | .firi_2_mcu_addr = 1193, | |
465 | .mcu_2_firi_addr = 1290, | |
466 | }; | |
467 | ||
e9fd58de | 468 | static struct sdma_driver_data sdma_imx53 = { |
dcfec3c0 SH |
469 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
470 | .num_events = 48, | |
471 | .script_addrs = &sdma_script_imx53, | |
472 | }; | |
473 | ||
474 | static struct sdma_script_start_addrs sdma_script_imx6q = { | |
475 | .ap_2_ap_addr = 642, | |
476 | .uart_2_mcu_addr = 817, | |
477 | .mcu_2_app_addr = 747, | |
478 | .per_2_per_addr = 6331, | |
479 | .uartsh_2_mcu_addr = 1032, | |
480 | .mcu_2_shp_addr = 960, | |
481 | .app_2_mcu_addr = 683, | |
482 | .shp_2_mcu_addr = 891, | |
483 | .spdif_2_mcu_addr = 1100, | |
484 | .mcu_2_spdif_addr = 1134, | |
485 | }; | |
486 | ||
e9fd58de | 487 | static struct sdma_driver_data sdma_imx6q = { |
dcfec3c0 SH |
488 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
489 | .num_events = 48, | |
490 | .script_addrs = &sdma_script_imx6q, | |
491 | }; | |
492 | ||
b7d2648a FE |
493 | static struct sdma_script_start_addrs sdma_script_imx7d = { |
494 | .ap_2_ap_addr = 644, | |
495 | .uart_2_mcu_addr = 819, | |
496 | .mcu_2_app_addr = 749, | |
497 | .uartsh_2_mcu_addr = 1034, | |
498 | .mcu_2_shp_addr = 962, | |
499 | .app_2_mcu_addr = 685, | |
500 | .shp_2_mcu_addr = 893, | |
501 | .spdif_2_mcu_addr = 1102, | |
502 | .mcu_2_spdif_addr = 1136, | |
503 | }; | |
504 | ||
505 | static struct sdma_driver_data sdma_imx7d = { | |
506 | .chnenbl0 = SDMA_CHNENBL0_IMX35, | |
507 | .num_events = 48, | |
508 | .script_addrs = &sdma_script_imx7d, | |
509 | }; | |
510 | ||
afe7cded | 511 | static const struct platform_device_id sdma_devtypes[] = { |
62550cd7 | 512 | { |
dcfec3c0 SH |
513 | .name = "imx25-sdma", |
514 | .driver_data = (unsigned long)&sdma_imx25, | |
515 | }, { | |
62550cd7 | 516 | .name = "imx31-sdma", |
17bba72f | 517 | .driver_data = (unsigned long)&sdma_imx31, |
62550cd7 SG |
518 | }, { |
519 | .name = "imx35-sdma", | |
17bba72f | 520 | .driver_data = (unsigned long)&sdma_imx35, |
dcfec3c0 SH |
521 | }, { |
522 | .name = "imx51-sdma", | |
523 | .driver_data = (unsigned long)&sdma_imx51, | |
524 | }, { | |
525 | .name = "imx53-sdma", | |
526 | .driver_data = (unsigned long)&sdma_imx53, | |
527 | }, { | |
528 | .name = "imx6q-sdma", | |
529 | .driver_data = (unsigned long)&sdma_imx6q, | |
b7d2648a FE |
530 | }, { |
531 | .name = "imx7d-sdma", | |
532 | .driver_data = (unsigned long)&sdma_imx7d, | |
62550cd7 SG |
533 | }, { |
534 | /* sentinel */ | |
535 | } | |
536 | }; | |
537 | MODULE_DEVICE_TABLE(platform, sdma_devtypes); | |
538 | ||
580975d7 | 539 | static const struct of_device_id sdma_dt_ids[] = { |
dcfec3c0 SH |
540 | { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, |
541 | { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, | |
542 | { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, | |
17bba72f | 543 | { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, |
dcfec3c0 | 544 | { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, |
63edea16 | 545 | { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, |
b7d2648a | 546 | { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, }, |
580975d7 SG |
547 | { /* sentinel */ } |
548 | }; | |
549 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); | |
550 | ||
0bbc1413 RZ |
551 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
552 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ | |
553 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ | |
1ec1e82f SH |
554 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
555 | ||
556 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) | |
557 | { | |
17bba72f | 558 | u32 chnenbl0 = sdma->drvdata->chnenbl0; |
1ec1e82f SH |
559 | return chnenbl0 + event * 4; |
560 | } | |
561 | ||
562 | static int sdma_config_ownership(struct sdma_channel *sdmac, | |
563 | bool event_override, bool mcu_override, bool dsp_override) | |
564 | { | |
565 | struct sdma_engine *sdma = sdmac->sdma; | |
566 | int channel = sdmac->channel; | |
0bbc1413 | 567 | unsigned long evt, mcu, dsp; |
1ec1e82f SH |
568 | |
569 | if (event_override && mcu_override && dsp_override) | |
570 | return -EINVAL; | |
571 | ||
c4b56857 RZ |
572 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
573 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); | |
574 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
575 | |
576 | if (dsp_override) | |
0bbc1413 | 577 | __clear_bit(channel, &dsp); |
1ec1e82f | 578 | else |
0bbc1413 | 579 | __set_bit(channel, &dsp); |
1ec1e82f SH |
580 | |
581 | if (event_override) | |
0bbc1413 | 582 | __clear_bit(channel, &evt); |
1ec1e82f | 583 | else |
0bbc1413 | 584 | __set_bit(channel, &evt); |
1ec1e82f SH |
585 | |
586 | if (mcu_override) | |
0bbc1413 | 587 | __clear_bit(channel, &mcu); |
1ec1e82f | 588 | else |
0bbc1413 | 589 | __set_bit(channel, &mcu); |
1ec1e82f | 590 | |
c4b56857 RZ |
591 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
592 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); | |
593 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
594 | |
595 | return 0; | |
596 | } | |
597 | ||
b9a59166 RZ |
598 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
599 | { | |
2746e2c3 TB |
600 | unsigned long flags; |
601 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
602 | ||
0bbc1413 | 603 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
2746e2c3 TB |
604 | |
605 | spin_lock_irqsave(&sdmac->lock, flags); | |
606 | sdmac->enabled = true; | |
607 | spin_unlock_irqrestore(&sdmac->lock, flags); | |
b9a59166 RZ |
608 | } |
609 | ||
1ec1e82f | 610 | /* |
2ccaef05 | 611 | * sdma_run_channel0 - run a channel and wait till it's done |
1ec1e82f | 612 | */ |
2ccaef05 | 613 | static int sdma_run_channel0(struct sdma_engine *sdma) |
1ec1e82f | 614 | { |
1ec1e82f | 615 | int ret; |
1d069bfa | 616 | u32 reg; |
1ec1e82f | 617 | |
2ccaef05 | 618 | sdma_enable_channel(sdma, 0); |
1ec1e82f | 619 | |
1d069bfa MO |
620 | ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, |
621 | reg, !(reg & 1), 1, 500); | |
622 | if (ret) | |
2ccaef05 | 623 | dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); |
1ec1e82f | 624 | |
855832e4 RG |
625 | /* Set bits of CONFIG register with dynamic context switching */ |
626 | if (readl(sdma->regs + SDMA_H_CONFIG) == 0) | |
627 | writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); | |
628 | ||
1d069bfa | 629 | return ret; |
1ec1e82f SH |
630 | } |
631 | ||
632 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, | |
633 | u32 address) | |
634 | { | |
635 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
636 | void *buf_virt; | |
637 | dma_addr_t buf_phys; | |
638 | int ret; | |
2ccaef05 | 639 | unsigned long flags; |
73eab978 | 640 | |
1ec1e82f SH |
641 | buf_virt = dma_alloc_coherent(NULL, |
642 | size, | |
643 | &buf_phys, GFP_KERNEL); | |
73eab978 | 644 | if (!buf_virt) { |
2ccaef05 | 645 | return -ENOMEM; |
73eab978 | 646 | } |
1ec1e82f | 647 | |
2ccaef05 RZ |
648 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
649 | ||
1ec1e82f SH |
650 | bd0->mode.command = C0_SETPM; |
651 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
652 | bd0->mode.count = size / 2; | |
653 | bd0->buffer_addr = buf_phys; | |
654 | bd0->ext_buffer_addr = address; | |
655 | ||
656 | memcpy(buf_virt, buf, size); | |
657 | ||
2ccaef05 | 658 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 659 | |
2ccaef05 | 660 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
1ec1e82f | 661 | |
2ccaef05 | 662 | dma_free_coherent(NULL, size, buf_virt, buf_phys); |
73eab978 | 663 | |
1ec1e82f SH |
664 | return ret; |
665 | } | |
666 | ||
667 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) | |
668 | { | |
669 | struct sdma_engine *sdma = sdmac->sdma; | |
670 | int channel = sdmac->channel; | |
0bbc1413 | 671 | unsigned long val; |
1ec1e82f SH |
672 | u32 chnenbl = chnenbl_ofs(sdma, event); |
673 | ||
c4b56857 | 674 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 675 | __set_bit(channel, &val); |
c4b56857 | 676 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
677 | } |
678 | ||
679 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) | |
680 | { | |
681 | struct sdma_engine *sdma = sdmac->sdma; | |
682 | int channel = sdmac->channel; | |
683 | u32 chnenbl = chnenbl_ofs(sdma, event); | |
0bbc1413 | 684 | unsigned long val; |
1ec1e82f | 685 | |
c4b56857 | 686 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 687 | __clear_bit(channel, &val); |
c4b56857 | 688 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
689 | } |
690 | ||
d1a792f3 | 691 | static void sdma_update_channel_loop(struct sdma_channel *sdmac) |
1ec1e82f SH |
692 | { |
693 | struct sdma_buffer_descriptor *bd; | |
5881826d NH |
694 | int error = 0; |
695 | enum dma_status old_status = sdmac->status; | |
2746e2c3 TB |
696 | unsigned long flags; |
697 | ||
698 | spin_lock_irqsave(&sdmac->lock, flags); | |
699 | if (!sdmac->enabled) { | |
700 | spin_unlock_irqrestore(&sdmac->lock, flags); | |
701 | return; | |
702 | } | |
703 | spin_unlock_irqrestore(&sdmac->lock, flags); | |
1ec1e82f SH |
704 | |
705 | /* | |
706 | * loop mode. Iterate over descriptors, re-setup them and | |
707 | * call callback function. | |
708 | */ | |
709 | while (1) { | |
710 | bd = &sdmac->bd[sdmac->buf_tail]; | |
711 | ||
712 | if (bd->mode.status & BD_DONE) | |
713 | break; | |
714 | ||
5881826d NH |
715 | if (bd->mode.status & BD_RROR) { |
716 | bd->mode.status &= ~BD_RROR; | |
1ec1e82f | 717 | sdmac->status = DMA_ERROR; |
5881826d NH |
718 | error = -EIO; |
719 | } | |
1ec1e82f | 720 | |
5881826d NH |
721 | /* |
722 | * We use bd->mode.count to calculate the residue, since contains | |
723 | * the number of bytes present in the current buffer descriptor. | |
724 | */ | |
725 | ||
726 | sdmac->chn_real_count = bd->mode.count; | |
1ec1e82f | 727 | bd->mode.status |= BD_DONE; |
5881826d | 728 | bd->mode.count = sdmac->period_len; |
85f57752 NH |
729 | sdmac->buf_ptail = sdmac->buf_tail; |
730 | sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd; | |
15f30f51 NH |
731 | |
732 | /* | |
733 | * The callback is called from the interrupt context in order | |
734 | * to reduce latency and to avoid the risk of altering the | |
735 | * SDMA transaction status by the time the client tasklet is | |
736 | * executed. | |
737 | */ | |
738 | ||
553911c6 | 739 | dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); |
15f30f51 | 740 | |
5881826d NH |
741 | if (error) |
742 | sdmac->status = old_status; | |
1ec1e82f SH |
743 | } |
744 | } | |
745 | ||
15f30f51 | 746 | static void mxc_sdma_handle_channel_normal(unsigned long data) |
1ec1e82f | 747 | { |
15f30f51 | 748 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
1ec1e82f SH |
749 | struct sdma_buffer_descriptor *bd; |
750 | int i, error = 0; | |
751 | ||
ab59a510 | 752 | sdmac->chn_real_count = 0; |
1ec1e82f SH |
753 | /* |
754 | * non loop mode. Iterate over all descriptors, collect | |
755 | * errors and call callback function | |
756 | */ | |
757 | for (i = 0; i < sdmac->num_bd; i++) { | |
758 | bd = &sdmac->bd[i]; | |
759 | ||
760 | if (bd->mode.status & (BD_DONE | BD_RROR)) | |
761 | error = -EIO; | |
ab59a510 | 762 | sdmac->chn_real_count += bd->mode.count; |
1ec1e82f SH |
763 | } |
764 | ||
765 | if (error) | |
766 | sdmac->status = DMA_ERROR; | |
767 | else | |
409bff6a | 768 | sdmac->status = DMA_COMPLETE; |
1ec1e82f | 769 | |
f7fbce07 | 770 | dma_cookie_complete(&sdmac->desc); |
48dc77e2 DJ |
771 | |
772 | dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL); | |
1ec1e82f SH |
773 | } |
774 | ||
1ec1e82f SH |
775 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) |
776 | { | |
777 | struct sdma_engine *sdma = dev_id; | |
0bbc1413 | 778 | unsigned long stat; |
1ec1e82f | 779 | |
c4b56857 RZ |
780 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
781 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); | |
1d069bfa MO |
782 | /* channel 0 is special and not handled here, see run_channel0() */ |
783 | stat &= ~1; | |
1ec1e82f SH |
784 | |
785 | while (stat) { | |
786 | int channel = fls(stat) - 1; | |
787 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
788 | ||
d1a792f3 RKAL |
789 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
790 | sdma_update_channel_loop(sdmac); | |
15f30f51 NH |
791 | else |
792 | tasklet_schedule(&sdmac->tasklet); | |
1ec1e82f | 793 | |
0bbc1413 | 794 | __clear_bit(channel, &stat); |
1ec1e82f SH |
795 | } |
796 | ||
797 | return IRQ_HANDLED; | |
798 | } | |
799 | ||
800 | /* | |
801 | * sets the pc of SDMA script according to the peripheral type | |
802 | */ | |
803 | static void sdma_get_pc(struct sdma_channel *sdmac, | |
804 | enum sdma_peripheral_type peripheral_type) | |
805 | { | |
806 | struct sdma_engine *sdma = sdmac->sdma; | |
807 | int per_2_emi = 0, emi_2_per = 0; | |
808 | /* | |
809 | * These are needed once we start to support transfers between | |
810 | * two peripherals or memory-to-memory transfers | |
811 | */ | |
0d605ba0 | 812 | int per_2_per = 0; |
1ec1e82f SH |
813 | |
814 | sdmac->pc_from_device = 0; | |
815 | sdmac->pc_to_device = 0; | |
8391ecf4 | 816 | sdmac->device_to_device = 0; |
1ec1e82f SH |
817 | |
818 | switch (peripheral_type) { | |
819 | case IMX_DMATYPE_MEMORY: | |
1ec1e82f SH |
820 | break; |
821 | case IMX_DMATYPE_DSP: | |
822 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; | |
823 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; | |
824 | break; | |
825 | case IMX_DMATYPE_FIRI: | |
826 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; | |
827 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; | |
828 | break; | |
829 | case IMX_DMATYPE_UART: | |
830 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; | |
831 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
832 | break; | |
833 | case IMX_DMATYPE_UART_SP: | |
834 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; | |
835 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
836 | break; | |
837 | case IMX_DMATYPE_ATA: | |
838 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; | |
839 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; | |
840 | break; | |
841 | case IMX_DMATYPE_CSPI: | |
842 | case IMX_DMATYPE_EXT: | |
843 | case IMX_DMATYPE_SSI: | |
29aebfde | 844 | case IMX_DMATYPE_SAI: |
1ec1e82f SH |
845 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; |
846 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
847 | break; | |
1a895578 NC |
848 | case IMX_DMATYPE_SSI_DUAL: |
849 | per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; | |
850 | emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; | |
851 | break; | |
1ec1e82f SH |
852 | case IMX_DMATYPE_SSI_SP: |
853 | case IMX_DMATYPE_MMC: | |
854 | case IMX_DMATYPE_SDHC: | |
855 | case IMX_DMATYPE_CSPI_SP: | |
856 | case IMX_DMATYPE_ESAI: | |
857 | case IMX_DMATYPE_MSHC_SP: | |
858 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
859 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
860 | break; | |
861 | case IMX_DMATYPE_ASRC: | |
862 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; | |
863 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; | |
864 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
865 | break; | |
f892afb0 NC |
866 | case IMX_DMATYPE_ASRC_SP: |
867 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
868 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
869 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
870 | break; | |
1ec1e82f SH |
871 | case IMX_DMATYPE_MSHC: |
872 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; | |
873 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; | |
874 | break; | |
875 | case IMX_DMATYPE_CCM: | |
876 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; | |
877 | break; | |
878 | case IMX_DMATYPE_SPDIF: | |
879 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; | |
880 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; | |
881 | break; | |
882 | case IMX_DMATYPE_IPU_MEMORY: | |
883 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; | |
884 | break; | |
885 | default: | |
886 | break; | |
887 | } | |
888 | ||
889 | sdmac->pc_from_device = per_2_emi; | |
890 | sdmac->pc_to_device = emi_2_per; | |
8391ecf4 | 891 | sdmac->device_to_device = per_2_per; |
1ec1e82f SH |
892 | } |
893 | ||
894 | static int sdma_load_context(struct sdma_channel *sdmac) | |
895 | { | |
896 | struct sdma_engine *sdma = sdmac->sdma; | |
897 | int channel = sdmac->channel; | |
898 | int load_address; | |
899 | struct sdma_context_data *context = sdma->context; | |
900 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
901 | int ret; | |
2ccaef05 | 902 | unsigned long flags; |
1ec1e82f | 903 | |
8391ecf4 | 904 | if (sdmac->direction == DMA_DEV_TO_MEM) |
1ec1e82f | 905 | load_address = sdmac->pc_from_device; |
8391ecf4 SW |
906 | else if (sdmac->direction == DMA_DEV_TO_DEV) |
907 | load_address = sdmac->device_to_device; | |
908 | else | |
1ec1e82f | 909 | load_address = sdmac->pc_to_device; |
1ec1e82f SH |
910 | |
911 | if (load_address < 0) | |
912 | return load_address; | |
913 | ||
914 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); | |
0bbc1413 | 915 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
1ec1e82f SH |
916 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
917 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); | |
0bbc1413 RZ |
918 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
919 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); | |
1ec1e82f | 920 | |
2ccaef05 | 921 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
73eab978 | 922 | |
1ec1e82f SH |
923 | memset(context, 0, sizeof(*context)); |
924 | context->channel_state.pc = load_address; | |
925 | ||
926 | /* Send by context the event mask,base address for peripheral | |
927 | * and watermark level | |
928 | */ | |
0bbc1413 RZ |
929 | context->gReg[0] = sdmac->event_mask[1]; |
930 | context->gReg[1] = sdmac->event_mask[0]; | |
1ec1e82f SH |
931 | context->gReg[2] = sdmac->per_addr; |
932 | context->gReg[6] = sdmac->shp_addr; | |
933 | context->gReg[7] = sdmac->watermark_level; | |
934 | ||
935 | bd0->mode.command = C0_SETDM; | |
936 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
937 | bd0->mode.count = sizeof(*context) / 4; | |
938 | bd0->buffer_addr = sdma->context_phys; | |
939 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; | |
2ccaef05 | 940 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 941 | |
2ccaef05 | 942 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
73eab978 | 943 | |
1ec1e82f SH |
944 | return ret; |
945 | } | |
946 | ||
7b350ab0 MR |
947 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
948 | { | |
949 | return container_of(chan, struct sdma_channel, chan); | |
950 | } | |
951 | ||
952 | static int sdma_disable_channel(struct dma_chan *chan) | |
1ec1e82f | 953 | { |
7b350ab0 | 954 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1ec1e82f SH |
955 | struct sdma_engine *sdma = sdmac->sdma; |
956 | int channel = sdmac->channel; | |
2746e2c3 | 957 | unsigned long flags; |
1ec1e82f | 958 | |
0bbc1413 | 959 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
1ec1e82f | 960 | sdmac->status = DMA_ERROR; |
7b350ab0 | 961 | |
2746e2c3 TB |
962 | spin_lock_irqsave(&sdmac->lock, flags); |
963 | sdmac->enabled = false; | |
964 | spin_unlock_irqrestore(&sdmac->lock, flags); | |
965 | ||
7b350ab0 | 966 | return 0; |
1ec1e82f SH |
967 | } |
968 | ||
7f3ff14b JW |
969 | static int sdma_disable_channel_with_delay(struct dma_chan *chan) |
970 | { | |
971 | sdma_disable_channel(chan); | |
972 | ||
973 | /* | |
974 | * According to NXP R&D team a delay of one BD SDMA cost time | |
975 | * (maximum is 1ms) should be added after disable of the channel | |
976 | * bit, to ensure SDMA core has really been stopped after SDMA | |
977 | * clients call .device_terminate_all. | |
978 | */ | |
979 | mdelay(1); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
8391ecf4 SW |
984 | static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) |
985 | { | |
986 | struct sdma_engine *sdma = sdmac->sdma; | |
987 | ||
988 | int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; | |
989 | int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; | |
990 | ||
991 | set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); | |
992 | set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); | |
993 | ||
994 | if (sdmac->event_id0 > 31) | |
995 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; | |
996 | ||
997 | if (sdmac->event_id1 > 31) | |
998 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; | |
999 | ||
1000 | /* | |
1001 | * If LWML(src_maxburst) > HWML(dst_maxburst), we need | |
1002 | * swap LWML and HWML of INFO(A.3.2.5.1), also need swap | |
1003 | * r0(event_mask[1]) and r1(event_mask[0]). | |
1004 | */ | |
1005 | if (lwml > hwml) { | |
1006 | sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | | |
1007 | SDMA_WATERMARK_LEVEL_HWML); | |
1008 | sdmac->watermark_level |= hwml; | |
1009 | sdmac->watermark_level |= lwml << 16; | |
1010 | swap(sdmac->event_mask[0], sdmac->event_mask[1]); | |
1011 | } | |
1012 | ||
1013 | if (sdmac->per_address2 >= sdma->spba_start_addr && | |
1014 | sdmac->per_address2 <= sdma->spba_end_addr) | |
1015 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; | |
1016 | ||
1017 | if (sdmac->per_address >= sdma->spba_start_addr && | |
1018 | sdmac->per_address <= sdma->spba_end_addr) | |
1019 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; | |
1020 | ||
1021 | sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; | |
1022 | } | |
1023 | ||
7b350ab0 | 1024 | static int sdma_config_channel(struct dma_chan *chan) |
1ec1e82f | 1025 | { |
7b350ab0 | 1026 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1ec1e82f SH |
1027 | int ret; |
1028 | ||
7b350ab0 | 1029 | sdma_disable_channel(chan); |
1ec1e82f | 1030 | |
0bbc1413 RZ |
1031 | sdmac->event_mask[0] = 0; |
1032 | sdmac->event_mask[1] = 0; | |
1ec1e82f SH |
1033 | sdmac->shp_addr = 0; |
1034 | sdmac->per_addr = 0; | |
1035 | ||
1036 | if (sdmac->event_id0) { | |
17bba72f | 1037 | if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) |
1ec1e82f SH |
1038 | return -EINVAL; |
1039 | sdma_event_enable(sdmac, sdmac->event_id0); | |
1040 | } | |
1041 | ||
8391ecf4 SW |
1042 | if (sdmac->event_id1) { |
1043 | if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) | |
1044 | return -EINVAL; | |
1045 | sdma_event_enable(sdmac, sdmac->event_id1); | |
1046 | } | |
1047 | ||
1ec1e82f SH |
1048 | switch (sdmac->peripheral_type) { |
1049 | case IMX_DMATYPE_DSP: | |
1050 | sdma_config_ownership(sdmac, false, true, true); | |
1051 | break; | |
1052 | case IMX_DMATYPE_MEMORY: | |
1053 | sdma_config_ownership(sdmac, false, true, false); | |
1054 | break; | |
1055 | default: | |
1056 | sdma_config_ownership(sdmac, true, true, false); | |
1057 | break; | |
1058 | } | |
1059 | ||
1060 | sdma_get_pc(sdmac, sdmac->peripheral_type); | |
1061 | ||
1062 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && | |
1063 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { | |
1064 | /* Handle multiple event channels differently */ | |
1065 | if (sdmac->event_id1) { | |
8391ecf4 SW |
1066 | if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || |
1067 | sdmac->peripheral_type == IMX_DMATYPE_ASRC) | |
1068 | sdma_set_watermarklevel_for_p2p(sdmac); | |
1069 | } else | |
0bbc1413 | 1070 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
8391ecf4 | 1071 | |
1ec1e82f SH |
1072 | /* Address */ |
1073 | sdmac->shp_addr = sdmac->per_address; | |
8391ecf4 | 1074 | sdmac->per_addr = sdmac->per_address2; |
1ec1e82f SH |
1075 | } else { |
1076 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ | |
1077 | } | |
1078 | ||
1079 | ret = sdma_load_context(sdmac); | |
1080 | ||
1081 | return ret; | |
1082 | } | |
1083 | ||
1084 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, | |
1085 | unsigned int priority) | |
1086 | { | |
1087 | struct sdma_engine *sdma = sdmac->sdma; | |
1088 | int channel = sdmac->channel; | |
1089 | ||
1090 | if (priority < MXC_SDMA_MIN_PRIORITY | |
1091 | || priority > MXC_SDMA_MAX_PRIORITY) { | |
1092 | return -EINVAL; | |
1093 | } | |
1094 | ||
c4b56857 | 1095 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
1ec1e82f SH |
1096 | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | static int sdma_request_channel(struct sdma_channel *sdmac) | |
1101 | { | |
1102 | struct sdma_engine *sdma = sdmac->sdma; | |
1103 | int channel = sdmac->channel; | |
1104 | int ret = -EBUSY; | |
1105 | ||
9f92d223 JP |
1106 | sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, |
1107 | GFP_KERNEL); | |
1ec1e82f SH |
1108 | if (!sdmac->bd) { |
1109 | ret = -ENOMEM; | |
1110 | goto out; | |
1111 | } | |
1112 | ||
1ec1e82f SH |
1113 | sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; |
1114 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1115 | ||
1ec1e82f | 1116 | sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); |
1ec1e82f SH |
1117 | return 0; |
1118 | out: | |
1119 | ||
1120 | return ret; | |
1121 | } | |
1122 | ||
1ec1e82f SH |
1123 | static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) |
1124 | { | |
f69f2e26 | 1125 | unsigned long flags; |
1ec1e82f | 1126 | struct sdma_channel *sdmac = to_sdma_chan(tx->chan); |
1ec1e82f SH |
1127 | dma_cookie_t cookie; |
1128 | ||
f69f2e26 | 1129 | spin_lock_irqsave(&sdmac->lock, flags); |
1ec1e82f | 1130 | |
884485e1 | 1131 | cookie = dma_cookie_assign(tx); |
1ec1e82f | 1132 | |
f69f2e26 | 1133 | spin_unlock_irqrestore(&sdmac->lock, flags); |
1ec1e82f SH |
1134 | |
1135 | return cookie; | |
1136 | } | |
1137 | ||
1138 | static int sdma_alloc_chan_resources(struct dma_chan *chan) | |
1139 | { | |
1140 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1141 | struct imx_dma_data *data = chan->private; | |
1142 | int prio, ret; | |
1143 | ||
1ec1e82f SH |
1144 | if (!data) |
1145 | return -EINVAL; | |
1146 | ||
1147 | switch (data->priority) { | |
1148 | case DMA_PRIO_HIGH: | |
1149 | prio = 3; | |
1150 | break; | |
1151 | case DMA_PRIO_MEDIUM: | |
1152 | prio = 2; | |
1153 | break; | |
1154 | case DMA_PRIO_LOW: | |
1155 | default: | |
1156 | prio = 1; | |
1157 | break; | |
1158 | } | |
1159 | ||
1160 | sdmac->peripheral_type = data->peripheral_type; | |
1161 | sdmac->event_id0 = data->dma_request; | |
8391ecf4 | 1162 | sdmac->event_id1 = data->dma_request2; |
c2c744d3 | 1163 | |
b93edcdd FE |
1164 | ret = clk_enable(sdmac->sdma->clk_ipg); |
1165 | if (ret) | |
1166 | return ret; | |
1167 | ret = clk_enable(sdmac->sdma->clk_ahb); | |
1168 | if (ret) | |
1169 | goto disable_clk_ipg; | |
c2c744d3 | 1170 | |
3bb5e7ca | 1171 | ret = sdma_request_channel(sdmac); |
1ec1e82f | 1172 | if (ret) |
b93edcdd | 1173 | goto disable_clk_ahb; |
1ec1e82f | 1174 | |
3bb5e7ca | 1175 | ret = sdma_set_channel_priority(sdmac, prio); |
1ec1e82f | 1176 | if (ret) |
b93edcdd | 1177 | goto disable_clk_ahb; |
1ec1e82f SH |
1178 | |
1179 | dma_async_tx_descriptor_init(&sdmac->desc, chan); | |
1180 | sdmac->desc.tx_submit = sdma_tx_submit; | |
1181 | /* txd.flags will be overwritten in prep funcs */ | |
1182 | sdmac->desc.flags = DMA_CTRL_ACK; | |
1183 | ||
1184 | return 0; | |
b93edcdd FE |
1185 | |
1186 | disable_clk_ahb: | |
1187 | clk_disable(sdmac->sdma->clk_ahb); | |
1188 | disable_clk_ipg: | |
1189 | clk_disable(sdmac->sdma->clk_ipg); | |
1190 | return ret; | |
1ec1e82f SH |
1191 | } |
1192 | ||
1193 | static void sdma_free_chan_resources(struct dma_chan *chan) | |
1194 | { | |
1195 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1196 | struct sdma_engine *sdma = sdmac->sdma; | |
1197 | ||
7b350ab0 | 1198 | sdma_disable_channel(chan); |
1ec1e82f SH |
1199 | |
1200 | if (sdmac->event_id0) | |
1201 | sdma_event_disable(sdmac, sdmac->event_id0); | |
1202 | if (sdmac->event_id1) | |
1203 | sdma_event_disable(sdmac, sdmac->event_id1); | |
1204 | ||
1205 | sdmac->event_id0 = 0; | |
1206 | sdmac->event_id1 = 0; | |
1207 | ||
1208 | sdma_set_channel_priority(sdmac, 0); | |
1209 | ||
1210 | dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); | |
1211 | ||
7560e3f3 SH |
1212 | clk_disable(sdma->clk_ipg); |
1213 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1214 | } |
1215 | ||
1216 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( | |
1217 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1218 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1219 | unsigned long flags, void *context) |
1ec1e82f SH |
1220 | { |
1221 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1222 | struct sdma_engine *sdma = sdmac->sdma; | |
1223 | int ret, i, count; | |
23889c63 | 1224 | int channel = sdmac->channel; |
1ec1e82f SH |
1225 | struct scatterlist *sg; |
1226 | ||
1227 | if (sdmac->status == DMA_IN_PROGRESS) | |
1228 | return NULL; | |
1229 | sdmac->status = DMA_IN_PROGRESS; | |
1230 | ||
1231 | sdmac->flags = 0; | |
1232 | ||
8e2e27c7 | 1233 | sdmac->buf_tail = 0; |
85f57752 NH |
1234 | sdmac->buf_ptail = 0; |
1235 | sdmac->chn_real_count = 0; | |
8e2e27c7 | 1236 | |
1ec1e82f SH |
1237 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", |
1238 | sg_len, channel); | |
1239 | ||
1240 | sdmac->direction = direction; | |
1241 | ret = sdma_load_context(sdmac); | |
1242 | if (ret) | |
1243 | goto err_out; | |
1244 | ||
1245 | if (sg_len > NUM_BD) { | |
1246 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1247 | channel, sg_len, NUM_BD); | |
1248 | ret = -EINVAL; | |
1249 | goto err_out; | |
1250 | } | |
1251 | ||
ab59a510 | 1252 | sdmac->chn_count = 0; |
1ec1e82f SH |
1253 | for_each_sg(sgl, sg, sg_len, i) { |
1254 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1255 | int param; | |
1256 | ||
d2f5c276 | 1257 | bd->buffer_addr = sg->dma_address; |
1ec1e82f | 1258 | |
fdaf9c4b | 1259 | count = sg_dma_len(sg); |
1ec1e82f SH |
1260 | |
1261 | if (count > 0xffff) { | |
1262 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", | |
1263 | channel, count, 0xffff); | |
1264 | ret = -EINVAL; | |
1265 | goto err_out; | |
1266 | } | |
1267 | ||
1268 | bd->mode.count = count; | |
ab59a510 | 1269 | sdmac->chn_count += count; |
1ec1e82f SH |
1270 | |
1271 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { | |
1272 | ret = -EINVAL; | |
1273 | goto err_out; | |
1274 | } | |
1fa81c27 SH |
1275 | |
1276 | switch (sdmac->word_size) { | |
1277 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1ec1e82f | 1278 | bd->mode.command = 0; |
1fa81c27 SH |
1279 | if (count & 3 || sg->dma_address & 3) |
1280 | return NULL; | |
1281 | break; | |
1282 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1283 | bd->mode.command = 2; | |
1284 | if (count & 1 || sg->dma_address & 1) | |
1285 | return NULL; | |
1286 | break; | |
1287 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1288 | bd->mode.command = 1; | |
1289 | break; | |
1290 | default: | |
1291 | return NULL; | |
1292 | } | |
1ec1e82f SH |
1293 | |
1294 | param = BD_DONE | BD_EXTD | BD_CONT; | |
1295 | ||
341b9419 | 1296 | if (i + 1 == sg_len) { |
1ec1e82f | 1297 | param |= BD_INTR; |
341b9419 SG |
1298 | param |= BD_LAST; |
1299 | param &= ~BD_CONT; | |
1ec1e82f SH |
1300 | } |
1301 | ||
c3cc74b2 OJ |
1302 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1303 | i, count, (u64)sg->dma_address, | |
1ec1e82f SH |
1304 | param & BD_WRAP ? "wrap" : "", |
1305 | param & BD_INTR ? " intr" : ""); | |
1306 | ||
1307 | bd->mode.status = param; | |
1308 | } | |
1309 | ||
1310 | sdmac->num_bd = sg_len; | |
1311 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1312 | ||
1313 | return &sdmac->desc; | |
1314 | err_out: | |
4b2ce9dd | 1315 | sdmac->status = DMA_ERROR; |
1ec1e82f SH |
1316 | return NULL; |
1317 | } | |
1318 | ||
1319 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( | |
1320 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 1321 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 1322 | unsigned long flags) |
1ec1e82f SH |
1323 | { |
1324 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1325 | struct sdma_engine *sdma = sdmac->sdma; | |
1326 | int num_periods = buf_len / period_len; | |
23889c63 | 1327 | int channel = sdmac->channel; |
1ec1e82f SH |
1328 | int ret, i = 0, buf = 0; |
1329 | ||
1330 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); | |
1331 | ||
1332 | if (sdmac->status == DMA_IN_PROGRESS) | |
1333 | return NULL; | |
1334 | ||
1335 | sdmac->status = DMA_IN_PROGRESS; | |
1336 | ||
8e2e27c7 | 1337 | sdmac->buf_tail = 0; |
85f57752 NH |
1338 | sdmac->buf_ptail = 0; |
1339 | sdmac->chn_real_count = 0; | |
d1a792f3 | 1340 | sdmac->period_len = period_len; |
8e2e27c7 | 1341 | |
1ec1e82f SH |
1342 | sdmac->flags |= IMX_DMA_SG_LOOP; |
1343 | sdmac->direction = direction; | |
1344 | ret = sdma_load_context(sdmac); | |
1345 | if (ret) | |
1346 | goto err_out; | |
1347 | ||
1348 | if (num_periods > NUM_BD) { | |
1349 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1350 | channel, num_periods, NUM_BD); | |
1351 | goto err_out; | |
1352 | } | |
1353 | ||
1354 | if (period_len > 0xffff) { | |
ba6ab3b3 | 1355 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", |
1ec1e82f SH |
1356 | channel, period_len, 0xffff); |
1357 | goto err_out; | |
1358 | } | |
1359 | ||
1360 | while (buf < buf_len) { | |
1361 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1362 | int param; | |
1363 | ||
1364 | bd->buffer_addr = dma_addr; | |
1365 | ||
1366 | bd->mode.count = period_len; | |
1367 | ||
1368 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1369 | goto err_out; | |
1370 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1371 | bd->mode.command = 0; | |
1372 | else | |
1373 | bd->mode.command = sdmac->word_size; | |
1374 | ||
1375 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; | |
1376 | if (i + 1 == num_periods) | |
1377 | param |= BD_WRAP; | |
1378 | ||
ba6ab3b3 | 1379 | dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", |
c3cc74b2 | 1380 | i, period_len, (u64)dma_addr, |
1ec1e82f SH |
1381 | param & BD_WRAP ? "wrap" : "", |
1382 | param & BD_INTR ? " intr" : ""); | |
1383 | ||
1384 | bd->mode.status = param; | |
1385 | ||
1386 | dma_addr += period_len; | |
1387 | buf += period_len; | |
1388 | ||
1389 | i++; | |
1390 | } | |
1391 | ||
1392 | sdmac->num_bd = num_periods; | |
1393 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1394 | ||
1395 | return &sdmac->desc; | |
1396 | err_out: | |
1397 | sdmac->status = DMA_ERROR; | |
1398 | return NULL; | |
1399 | } | |
1400 | ||
7b350ab0 MR |
1401 | static int sdma_config(struct dma_chan *chan, |
1402 | struct dma_slave_config *dmaengine_cfg) | |
1ec1e82f SH |
1403 | { |
1404 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1ec1e82f | 1405 | |
7b350ab0 MR |
1406 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1407 | sdmac->per_address = dmaengine_cfg->src_addr; | |
1408 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * | |
1409 | dmaengine_cfg->src_addr_width; | |
1410 | sdmac->word_size = dmaengine_cfg->src_addr_width; | |
8391ecf4 SW |
1411 | } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) { |
1412 | sdmac->per_address2 = dmaengine_cfg->src_addr; | |
1413 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1414 | sdmac->watermark_level = dmaengine_cfg->src_maxburst & | |
1415 | SDMA_WATERMARK_LEVEL_LWML; | |
1416 | sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & | |
1417 | SDMA_WATERMARK_LEVEL_HWML; | |
1418 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
7b350ab0 MR |
1419 | } else { |
1420 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
1421 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * | |
1422 | dmaengine_cfg->dst_addr_width; | |
1423 | sdmac->word_size = dmaengine_cfg->dst_addr_width; | |
1424 | } | |
1425 | sdmac->direction = dmaengine_cfg->direction; | |
1426 | return sdma_config_channel(chan); | |
1ec1e82f SH |
1427 | } |
1428 | ||
1429 | static enum dma_status sdma_tx_status(struct dma_chan *chan, | |
e8e3a790 AS |
1430 | dma_cookie_t cookie, |
1431 | struct dma_tx_state *txstate) | |
1ec1e82f SH |
1432 | { |
1433 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
d1a792f3 RKAL |
1434 | u32 residue; |
1435 | ||
1436 | if (sdmac->flags & IMX_DMA_SG_LOOP) | |
85f57752 | 1437 | residue = (sdmac->num_bd - sdmac->buf_ptail) * |
5881826d | 1438 | sdmac->period_len - sdmac->chn_real_count; |
d1a792f3 RKAL |
1439 | else |
1440 | residue = sdmac->chn_count - sdmac->chn_real_count; | |
1ec1e82f | 1441 | |
e8e3a790 | 1442 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
d1a792f3 | 1443 | residue); |
1ec1e82f | 1444 | |
8a965911 | 1445 | return sdmac->status; |
1ec1e82f SH |
1446 | } |
1447 | ||
1448 | static void sdma_issue_pending(struct dma_chan *chan) | |
1449 | { | |
2b4f130e SH |
1450 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1451 | struct sdma_engine *sdma = sdmac->sdma; | |
1452 | ||
1453 | if (sdmac->status == DMA_IN_PROGRESS) | |
1454 | sdma_enable_channel(sdma, sdmac->channel); | |
1ec1e82f SH |
1455 | } |
1456 | ||
5b28aa31 | 1457 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
cd72b846 | 1458 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 |
a572460b | 1459 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41 |
b7d2648a | 1460 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42 |
5b28aa31 SH |
1461 | |
1462 | static void sdma_add_scripts(struct sdma_engine *sdma, | |
1463 | const struct sdma_script_start_addrs *addr) | |
1464 | { | |
1465 | s32 *addr_arr = (u32 *)addr; | |
1466 | s32 *saddr_arr = (u32 *)sdma->script_addrs; | |
1467 | int i; | |
1468 | ||
70dabaed NC |
1469 | /* use the default firmware in ROM if missing external firmware */ |
1470 | if (!sdma->script_number) | |
1471 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1472 | ||
cd72b846 | 1473 | for (i = 0; i < sdma->script_number; i++) |
5b28aa31 SH |
1474 | if (addr_arr[i] > 0) |
1475 | saddr_arr[i] = addr_arr[i]; | |
1476 | } | |
1477 | ||
7b4b88e0 | 1478 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
5b28aa31 | 1479 | { |
7b4b88e0 | 1480 | struct sdma_engine *sdma = context; |
5b28aa31 | 1481 | const struct sdma_firmware_header *header; |
5b28aa31 SH |
1482 | const struct sdma_script_start_addrs *addr; |
1483 | unsigned short *ram_code; | |
1484 | ||
7b4b88e0 | 1485 | if (!fw) { |
0f927a11 SH |
1486 | dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); |
1487 | /* In this case we just use the ROM firmware. */ | |
7b4b88e0 SH |
1488 | return; |
1489 | } | |
5b28aa31 SH |
1490 | |
1491 | if (fw->size < sizeof(*header)) | |
1492 | goto err_firmware; | |
1493 | ||
1494 | header = (struct sdma_firmware_header *)fw->data; | |
1495 | ||
1496 | if (header->magic != SDMA_FIRMWARE_MAGIC) | |
1497 | goto err_firmware; | |
1498 | if (header->ram_code_start + header->ram_code_size > fw->size) | |
1499 | goto err_firmware; | |
cd72b846 | 1500 | switch (header->version_major) { |
681d15ec AV |
1501 | case 1: |
1502 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1503 | break; | |
1504 | case 2: | |
1505 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; | |
1506 | break; | |
a572460b FE |
1507 | case 3: |
1508 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; | |
1509 | break; | |
b7d2648a FE |
1510 | case 4: |
1511 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; | |
1512 | break; | |
681d15ec AV |
1513 | default: |
1514 | dev_err(sdma->dev, "unknown firmware version\n"); | |
1515 | goto err_firmware; | |
cd72b846 | 1516 | } |
5b28aa31 SH |
1517 | |
1518 | addr = (void *)header + header->script_addrs_start; | |
1519 | ram_code = (void *)header + header->ram_code_start; | |
1520 | ||
7560e3f3 SH |
1521 | clk_enable(sdma->clk_ipg); |
1522 | clk_enable(sdma->clk_ahb); | |
5b28aa31 SH |
1523 | /* download the RAM image for SDMA */ |
1524 | sdma_load_script(sdma, ram_code, | |
1525 | header->ram_code_size, | |
6866fd3b | 1526 | addr->ram_code_start_addr); |
7560e3f3 SH |
1527 | clk_disable(sdma->clk_ipg); |
1528 | clk_disable(sdma->clk_ahb); | |
5b28aa31 SH |
1529 | |
1530 | sdma_add_scripts(sdma, addr); | |
1531 | ||
1532 | dev_info(sdma->dev, "loaded firmware %d.%d\n", | |
1533 | header->version_major, | |
1534 | header->version_minor); | |
1535 | ||
1536 | err_firmware: | |
1537 | release_firmware(fw); | |
7b4b88e0 SH |
1538 | } |
1539 | ||
d078cd1b ZW |
1540 | #define EVENT_REMAP_CELLS 3 |
1541 | ||
29f493da | 1542 | static int sdma_event_remap(struct sdma_engine *sdma) |
d078cd1b ZW |
1543 | { |
1544 | struct device_node *np = sdma->dev->of_node; | |
1545 | struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0); | |
1546 | struct property *event_remap; | |
1547 | struct regmap *gpr; | |
1548 | char propname[] = "fsl,sdma-event-remap"; | |
1549 | u32 reg, val, shift, num_map, i; | |
1550 | int ret = 0; | |
1551 | ||
1552 | if (IS_ERR(np) || IS_ERR(gpr_np)) | |
1553 | goto out; | |
1554 | ||
1555 | event_remap = of_find_property(np, propname, NULL); | |
1556 | num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; | |
1557 | if (!num_map) { | |
ce078af7 | 1558 | dev_dbg(sdma->dev, "no event needs to be remapped\n"); |
d078cd1b ZW |
1559 | goto out; |
1560 | } else if (num_map % EVENT_REMAP_CELLS) { | |
1561 | dev_err(sdma->dev, "the property %s must modulo %d\n", | |
1562 | propname, EVENT_REMAP_CELLS); | |
1563 | ret = -EINVAL; | |
1564 | goto out; | |
1565 | } | |
1566 | ||
1567 | gpr = syscon_node_to_regmap(gpr_np); | |
1568 | if (IS_ERR(gpr)) { | |
1569 | dev_err(sdma->dev, "failed to get gpr regmap\n"); | |
1570 | ret = PTR_ERR(gpr); | |
1571 | goto out; | |
1572 | } | |
1573 | ||
1574 | for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) { | |
1575 | ret = of_property_read_u32_index(np, propname, i, ®); | |
1576 | if (ret) { | |
1577 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1578 | propname, i); | |
1579 | goto out; | |
1580 | } | |
1581 | ||
1582 | ret = of_property_read_u32_index(np, propname, i + 1, &shift); | |
1583 | if (ret) { | |
1584 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1585 | propname, i + 1); | |
1586 | goto out; | |
1587 | } | |
1588 | ||
1589 | ret = of_property_read_u32_index(np, propname, i + 2, &val); | |
1590 | if (ret) { | |
1591 | dev_err(sdma->dev, "failed to read property %s index %d\n", | |
1592 | propname, i + 2); | |
1593 | goto out; | |
1594 | } | |
1595 | ||
1596 | regmap_update_bits(gpr, reg, BIT(shift), val << shift); | |
1597 | } | |
1598 | ||
1599 | out: | |
1600 | if (!IS_ERR(gpr_np)) | |
1601 | of_node_put(gpr_np); | |
1602 | ||
1603 | return ret; | |
1604 | } | |
1605 | ||
fe6cf289 | 1606 | static int sdma_get_firmware(struct sdma_engine *sdma, |
7b4b88e0 SH |
1607 | const char *fw_name) |
1608 | { | |
1609 | int ret; | |
1610 | ||
1611 | ret = request_firmware_nowait(THIS_MODULE, | |
1612 | FW_ACTION_HOTPLUG, fw_name, sdma->dev, | |
1613 | GFP_KERNEL, sdma, sdma_load_firmware); | |
5b28aa31 SH |
1614 | |
1615 | return ret; | |
1616 | } | |
1617 | ||
19bfc772 | 1618 | static int sdma_init(struct sdma_engine *sdma) |
1ec1e82f SH |
1619 | { |
1620 | int i, ret; | |
1621 | dma_addr_t ccb_phys; | |
1622 | ||
b93edcdd FE |
1623 | ret = clk_enable(sdma->clk_ipg); |
1624 | if (ret) | |
1625 | return ret; | |
1626 | ret = clk_enable(sdma->clk_ahb); | |
1627 | if (ret) | |
1628 | goto disable_clk_ipg; | |
1ec1e82f SH |
1629 | |
1630 | /* Be sure SDMA has not started yet */ | |
c4b56857 | 1631 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f SH |
1632 | |
1633 | sdma->channel_control = dma_alloc_coherent(NULL, | |
1634 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + | |
1635 | sizeof(struct sdma_context_data), | |
1636 | &ccb_phys, GFP_KERNEL); | |
1637 | ||
1638 | if (!sdma->channel_control) { | |
1639 | ret = -ENOMEM; | |
1640 | goto err_dma_alloc; | |
1641 | } | |
1642 | ||
1643 | sdma->context = (void *)sdma->channel_control + | |
1644 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1645 | sdma->context_phys = ccb_phys + | |
1646 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1647 | ||
1648 | /* Zero-out the CCB structures array just allocated */ | |
1649 | memset(sdma->channel_control, 0, | |
1650 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); | |
1651 | ||
1652 | /* disable all channels */ | |
17bba72f | 1653 | for (i = 0; i < sdma->drvdata->num_events; i++) |
c4b56857 | 1654 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
1ec1e82f SH |
1655 | |
1656 | /* All channels have priority 0 */ | |
1657 | for (i = 0; i < MAX_DMA_CHANNELS; i++) | |
c4b56857 | 1658 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
1ec1e82f SH |
1659 | |
1660 | ret = sdma_request_channel(&sdma->channel[0]); | |
1661 | if (ret) | |
1662 | goto err_dma_alloc; | |
1663 | ||
1664 | sdma_config_ownership(&sdma->channel[0], false, true, false); | |
1665 | ||
1666 | /* Set Command Channel (Channel Zero) */ | |
c4b56857 | 1667 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
1ec1e82f SH |
1668 | |
1669 | /* Set bits of CONFIG register but with static context switching */ | |
1670 | /* FIXME: Check whether to set ACR bit depending on clock ratios */ | |
c4b56857 | 1671 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f | 1672 | |
c4b56857 | 1673 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 1674 | |
1ec1e82f SH |
1675 | /* Initializes channel's priorities */ |
1676 | sdma_set_channel_priority(&sdma->channel[0], 7); | |
1677 | ||
7560e3f3 SH |
1678 | clk_disable(sdma->clk_ipg); |
1679 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1680 | |
1681 | return 0; | |
1682 | ||
1683 | err_dma_alloc: | |
7560e3f3 | 1684 | clk_disable(sdma->clk_ahb); |
b93edcdd FE |
1685 | disable_clk_ipg: |
1686 | clk_disable(sdma->clk_ipg); | |
1ec1e82f SH |
1687 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); |
1688 | return ret; | |
1689 | } | |
1690 | ||
9479e17c SG |
1691 | static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) |
1692 | { | |
0b351865 | 1693 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
9479e17c SG |
1694 | struct imx_dma_data *data = fn_param; |
1695 | ||
1696 | if (!imx_dma_is_general_purpose(chan)) | |
1697 | return false; | |
1698 | ||
0b351865 NC |
1699 | sdmac->data = *data; |
1700 | chan->private = &sdmac->data; | |
9479e17c SG |
1701 | |
1702 | return true; | |
1703 | } | |
1704 | ||
1705 | static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, | |
1706 | struct of_dma *ofdma) | |
1707 | { | |
1708 | struct sdma_engine *sdma = ofdma->of_dma_data; | |
1709 | dma_cap_mask_t mask = sdma->dma_device.cap_mask; | |
1710 | struct imx_dma_data data; | |
1711 | ||
1712 | if (dma_spec->args_count != 3) | |
1713 | return NULL; | |
1714 | ||
1715 | data.dma_request = dma_spec->args[0]; | |
1716 | data.peripheral_type = dma_spec->args[1]; | |
1717 | data.priority = dma_spec->args[2]; | |
8391ecf4 SW |
1718 | /* |
1719 | * init dma_request2 to zero, which is not used by the dts. | |
1720 | * For P2P, dma_request2 is init from dma_request_channel(), | |
1721 | * chan->private will point to the imx_dma_data, and in | |
1722 | * device_alloc_chan_resources(), imx_dma_data.dma_request2 will | |
1723 | * be set to sdmac->event_id1. | |
1724 | */ | |
1725 | data.dma_request2 = 0; | |
9479e17c SG |
1726 | |
1727 | return dma_request_channel(mask, sdma_filter_fn, &data); | |
1728 | } | |
1729 | ||
e34b731f | 1730 | static int sdma_probe(struct platform_device *pdev) |
1ec1e82f | 1731 | { |
580975d7 SG |
1732 | const struct of_device_id *of_id = |
1733 | of_match_device(sdma_dt_ids, &pdev->dev); | |
1734 | struct device_node *np = pdev->dev.of_node; | |
8391ecf4 | 1735 | struct device_node *spba_bus; |
580975d7 | 1736 | const char *fw_name; |
1ec1e82f | 1737 | int ret; |
1ec1e82f | 1738 | int irq; |
1ec1e82f | 1739 | struct resource *iores; |
8391ecf4 | 1740 | struct resource spba_res; |
d4adcc01 | 1741 | struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); |
1ec1e82f | 1742 | int i; |
1ec1e82f | 1743 | struct sdma_engine *sdma; |
36e2f21a | 1744 | s32 *saddr_arr; |
17bba72f SH |
1745 | const struct sdma_driver_data *drvdata = NULL; |
1746 | ||
1747 | if (of_id) | |
1748 | drvdata = of_id->data; | |
1749 | else if (pdev->id_entry) | |
1750 | drvdata = (void *)pdev->id_entry->driver_data; | |
1751 | ||
1752 | if (!drvdata) { | |
1753 | dev_err(&pdev->dev, "unable to find driver data\n"); | |
1754 | return -EINVAL; | |
1755 | } | |
1ec1e82f | 1756 | |
42536b9f PR |
1757 | ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
1758 | if (ret) | |
1759 | return ret; | |
1760 | ||
7f24e0ee | 1761 | sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); |
1ec1e82f SH |
1762 | if (!sdma) |
1763 | return -ENOMEM; | |
1764 | ||
2ccaef05 | 1765 | spin_lock_init(&sdma->channel_0_lock); |
73eab978 | 1766 | |
1ec1e82f | 1767 | sdma->dev = &pdev->dev; |
17bba72f | 1768 | sdma->drvdata = drvdata; |
1ec1e82f | 1769 | |
1ec1e82f | 1770 | irq = platform_get_irq(pdev, 0); |
7f24e0ee | 1771 | if (irq < 0) |
63c72e02 | 1772 | return irq; |
1ec1e82f | 1773 | |
7f24e0ee FE |
1774 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1775 | sdma->regs = devm_ioremap_resource(&pdev->dev, iores); | |
1776 | if (IS_ERR(sdma->regs)) | |
1777 | return PTR_ERR(sdma->regs); | |
1ec1e82f | 1778 | |
7560e3f3 | 1779 | sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
7f24e0ee FE |
1780 | if (IS_ERR(sdma->clk_ipg)) |
1781 | return PTR_ERR(sdma->clk_ipg); | |
1ec1e82f | 1782 | |
7560e3f3 | 1783 | sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
7f24e0ee FE |
1784 | if (IS_ERR(sdma->clk_ahb)) |
1785 | return PTR_ERR(sdma->clk_ahb); | |
7560e3f3 | 1786 | |
fb9caf37 AY |
1787 | ret = clk_prepare(sdma->clk_ipg); |
1788 | if (ret) | |
1789 | return ret; | |
1790 | ||
1791 | ret = clk_prepare(sdma->clk_ahb); | |
1792 | if (ret) | |
1793 | goto err_clk; | |
7560e3f3 | 1794 | |
7f24e0ee FE |
1795 | ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", |
1796 | sdma); | |
1ec1e82f | 1797 | if (ret) |
fb9caf37 | 1798 | goto err_irq; |
1ec1e82f | 1799 | |
5bb9dbb5 VK |
1800 | sdma->irq = irq; |
1801 | ||
5b28aa31 | 1802 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
fb9caf37 AY |
1803 | if (!sdma->script_addrs) { |
1804 | ret = -ENOMEM; | |
1805 | goto err_irq; | |
1806 | } | |
1ec1e82f | 1807 | |
36e2f21a SH |
1808 | /* initially no scripts available */ |
1809 | saddr_arr = (s32 *)sdma->script_addrs; | |
1810 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) | |
1811 | saddr_arr[i] = -EINVAL; | |
1812 | ||
7214a8b1 SH |
1813 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
1814 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); | |
1815 | ||
1ec1e82f SH |
1816 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
1817 | /* Initialize channel parameters */ | |
1818 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1819 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1820 | ||
1821 | sdmac->sdma = sdma; | |
1822 | spin_lock_init(&sdmac->lock); | |
1823 | ||
1ec1e82f | 1824 | sdmac->chan.device = &sdma->dma_device; |
8ac69546 | 1825 | dma_cookie_init(&sdmac->chan); |
1ec1e82f SH |
1826 | sdmac->channel = i; |
1827 | ||
15f30f51 | 1828 | tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal, |
abd9ccc8 | 1829 | (unsigned long) sdmac); |
23889c63 SH |
1830 | /* |
1831 | * Add the channel to the DMAC list. Do not add channel 0 though | |
1832 | * because we need it internally in the SDMA driver. This also means | |
1833 | * that channel 0 in dmaengine counting matches sdma channel 1. | |
1834 | */ | |
1835 | if (i) | |
1836 | list_add_tail(&sdmac->chan.device_node, | |
1837 | &sdma->dma_device.channels); | |
1ec1e82f SH |
1838 | } |
1839 | ||
5b28aa31 | 1840 | ret = sdma_init(sdma); |
1ec1e82f SH |
1841 | if (ret) |
1842 | goto err_init; | |
1843 | ||
d078cd1b ZW |
1844 | ret = sdma_event_remap(sdma); |
1845 | if (ret) | |
1846 | goto err_init; | |
1847 | ||
dcfec3c0 SH |
1848 | if (sdma->drvdata->script_addrs) |
1849 | sdma_add_scripts(sdma, sdma->drvdata->script_addrs); | |
580975d7 | 1850 | if (pdata && pdata->script_addrs) |
5b28aa31 SH |
1851 | sdma_add_scripts(sdma, pdata->script_addrs); |
1852 | ||
580975d7 | 1853 | if (pdata) { |
6d0d7e2d FE |
1854 | ret = sdma_get_firmware(sdma, pdata->fw_name); |
1855 | if (ret) | |
ad1122e5 | 1856 | dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); |
580975d7 SG |
1857 | } else { |
1858 | /* | |
1859 | * Because that device tree does not encode ROM script address, | |
1860 | * the RAM script in firmware is mandatory for device tree | |
1861 | * probe, otherwise it fails. | |
1862 | */ | |
1863 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", | |
1864 | &fw_name); | |
6602b0dd | 1865 | if (ret) |
ad1122e5 | 1866 | dev_warn(&pdev->dev, "failed to get firmware name\n"); |
6602b0dd FE |
1867 | else { |
1868 | ret = sdma_get_firmware(sdma, fw_name); | |
1869 | if (ret) | |
ad1122e5 | 1870 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); |
580975d7 SG |
1871 | } |
1872 | } | |
5b28aa31 | 1873 | |
1ec1e82f SH |
1874 | sdma->dma_device.dev = &pdev->dev; |
1875 | ||
1876 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; | |
1877 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; | |
1878 | sdma->dma_device.device_tx_status = sdma_tx_status; | |
1879 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; | |
1880 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; | |
7b350ab0 | 1881 | sdma->dma_device.device_config = sdma_config; |
7f3ff14b | 1882 | sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay; |
f9d4a398 NC |
1883 | sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; |
1884 | sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; | |
1885 | sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; | |
6f3125ce | 1886 | sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
1ec1e82f | 1887 | sdma->dma_device.device_issue_pending = sdma_issue_pending; |
b9b3f82f SH |
1888 | sdma->dma_device.dev->dma_parms = &sdma->dma_parms; |
1889 | dma_set_max_seg_size(sdma->dma_device.dev, 65535); | |
1ec1e82f | 1890 | |
23e11811 VR |
1891 | platform_set_drvdata(pdev, sdma); |
1892 | ||
1ec1e82f SH |
1893 | ret = dma_async_device_register(&sdma->dma_device); |
1894 | if (ret) { | |
1895 | dev_err(&pdev->dev, "unable to register\n"); | |
1896 | goto err_init; | |
1897 | } | |
1898 | ||
9479e17c SG |
1899 | if (np) { |
1900 | ret = of_dma_controller_register(np, sdma_xlate, sdma); | |
1901 | if (ret) { | |
1902 | dev_err(&pdev->dev, "failed to register controller\n"); | |
1903 | goto err_register; | |
1904 | } | |
8391ecf4 SW |
1905 | |
1906 | spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); | |
1907 | ret = of_address_to_resource(spba_bus, 0, &spba_res); | |
1908 | if (!ret) { | |
1909 | sdma->spba_start_addr = spba_res.start; | |
1910 | sdma->spba_end_addr = spba_res.end; | |
1911 | } | |
1912 | of_node_put(spba_bus); | |
9479e17c SG |
1913 | } |
1914 | ||
1ec1e82f SH |
1915 | return 0; |
1916 | ||
9479e17c SG |
1917 | err_register: |
1918 | dma_async_device_unregister(&sdma->dma_device); | |
1ec1e82f SH |
1919 | err_init: |
1920 | kfree(sdma->script_addrs); | |
fb9caf37 AY |
1921 | err_irq: |
1922 | clk_unprepare(sdma->clk_ahb); | |
1923 | err_clk: | |
1924 | clk_unprepare(sdma->clk_ipg); | |
939fd4f0 | 1925 | return ret; |
1ec1e82f SH |
1926 | } |
1927 | ||
1d1bbd30 | 1928 | static int sdma_remove(struct platform_device *pdev) |
1ec1e82f | 1929 | { |
23e11811 | 1930 | struct sdma_engine *sdma = platform_get_drvdata(pdev); |
c12fe497 | 1931 | int i; |
23e11811 | 1932 | |
5bb9dbb5 | 1933 | devm_free_irq(&pdev->dev, sdma->irq, sdma); |
23e11811 VR |
1934 | dma_async_device_unregister(&sdma->dma_device); |
1935 | kfree(sdma->script_addrs); | |
fb9caf37 AY |
1936 | clk_unprepare(sdma->clk_ahb); |
1937 | clk_unprepare(sdma->clk_ipg); | |
c12fe497 VR |
1938 | /* Kill the tasklet */ |
1939 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1940 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1941 | ||
1942 | tasklet_kill(&sdmac->tasklet); | |
1943 | } | |
23e11811 VR |
1944 | |
1945 | platform_set_drvdata(pdev, NULL); | |
23e11811 | 1946 | return 0; |
1ec1e82f SH |
1947 | } |
1948 | ||
1949 | static struct platform_driver sdma_driver = { | |
1950 | .driver = { | |
1951 | .name = "imx-sdma", | |
580975d7 | 1952 | .of_match_table = sdma_dt_ids, |
1ec1e82f | 1953 | }, |
62550cd7 | 1954 | .id_table = sdma_devtypes, |
1d1bbd30 | 1955 | .remove = sdma_remove, |
23e11811 | 1956 | .probe = sdma_probe, |
1ec1e82f SH |
1957 | }; |
1958 | ||
23e11811 | 1959 | module_platform_driver(sdma_driver); |
1ec1e82f SH |
1960 | |
1961 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1962 | MODULE_DESCRIPTION("i.MX SDMA driver"); | |
c0879342 NC |
1963 | #if IS_ENABLED(CONFIG_SOC_IMX6Q) |
1964 | MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin"); | |
1965 | #endif | |
1966 | #if IS_ENABLED(CONFIG_SOC_IMX7D) | |
1967 | MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin"); | |
1968 | #endif | |
1ec1e82f | 1969 | MODULE_LICENSE("GPL"); |