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dmaengine/ste_dma40: support pm in dma40
[mirror_ubuntu-artful-kernel.git] / drivers / dma / imx-sdma.c
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1ec1e82f
SH		 1/*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20#include <linux/init.h>
f8de8f4c 21#include <linux/module.h>
1ec1e82f
SH		 22#include <linux/types.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/clk.h>
26#include <linux/wait.h>
27#include <linux/sched.h>
28#include <linux/semaphore.h>
29#include <linux/spinlock.h>
30#include <linux/device.h>
31#include <linux/dma-mapping.h>
32#include <linux/firmware.h>
33#include <linux/slab.h>
34#include <linux/platform_device.h>
35#include <linux/dmaengine.h>
580975d7
SG		 36#include <linux/of.h>
37#include <linux/of_device.h>
5c45ad77 38#include <linux/module.h>
1ec1e82f
SH		 39
40#include <asm/irq.h>
41#include <mach/sdma.h>
42#include <mach/dma.h>
43#include <mach/hardware.h>
44
45/* SDMA registers */
46#define SDMA_H_C0PTR 0x000
47#define SDMA_H_INTR 0x004
48#define SDMA_H_STATSTOP 0x008
49#define SDMA_H_START 0x00c
50#define SDMA_H_EVTOVR 0x010
51#define SDMA_H_DSPOVR 0x014
52#define SDMA_H_HOSTOVR 0x018
53#define SDMA_H_EVTPEND 0x01c
54#define SDMA_H_DSPENBL 0x020
55#define SDMA_H_RESET 0x024
56#define SDMA_H_EVTERR 0x028
57#define SDMA_H_INTRMSK 0x02c
58#define SDMA_H_PSW 0x030
59#define SDMA_H_EVTERRDBG 0x034
60#define SDMA_H_CONFIG 0x038
61#define SDMA_ONCE_ENB 0x040
62#define SDMA_ONCE_DATA 0x044
63#define SDMA_ONCE_INSTR 0x048
64#define SDMA_ONCE_STAT 0x04c
65#define SDMA_ONCE_CMD 0x050
66#define SDMA_EVT_MIRROR 0x054
67#define SDMA_ILLINSTADDR 0x058
68#define SDMA_CHN0ADDR 0x05c
69#define SDMA_ONCE_RTB 0x060
70#define SDMA_XTRIG_CONF1 0x070
71#define SDMA_XTRIG_CONF2 0x074
62550cd7
SG		 72#define SDMA_CHNENBL0_IMX35 0x200
73#define SDMA_CHNENBL0_IMX31 0x080
1ec1e82f
SH		 74#define SDMA_CHNPRI_0 0x100
75
76/*
77 * Buffer descriptor status values.
78 */
79#define BD_DONE 0x01
80#define BD_WRAP 0x02
81#define BD_CONT 0x04
82#define BD_INTR 0x08
83#define BD_RROR 0x10
84#define BD_LAST 0x20
85#define BD_EXTD 0x80
86
87/*
88 * Data Node descriptor status values.
89 */
90#define DND_END_OF_FRAME 0x80
91#define DND_END_OF_XFER 0x40
92#define DND_DONE 0x20
93#define DND_UNUSED 0x01
94
95/*
96 * IPCV2 descriptor status values.
97 */
98#define BD_IPCV2_END_OF_FRAME 0x40
99
100#define IPCV2_MAX_NODES 50
101/*
102 * Error bit set in the CCB status field by the SDMA,
103 * in setbd routine, in case of a transfer error
104 */
105#define DATA_ERROR 0x10000000
106
107/*
108 * Buffer descriptor commands.
109 */
110#define C0_ADDR 0x01
111#define C0_LOAD 0x02
112#define C0_DUMP 0x03
113#define C0_SETCTX 0x07
114#define C0_GETCTX 0x03
115#define C0_SETDM 0x01
116#define C0_SETPM 0x04
117#define C0_GETDM 0x02
118#define C0_GETPM 0x08
119/*
120 * Change endianness indicator in the BD command field
121 */
122#define CHANGE_ENDIANNESS 0x80
123
124/*
125 * Mode/Count of data node descriptors - IPCv2
126 */
127struct sdma_mode_count {
128 u32 count : 16; /* size of the buffer pointed by this BD */
129 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
130 u32 command : 8; /* command mostlky used for channel 0 */
131};
132
133/*
134 * Buffer descriptor
135 */
136struct sdma_buffer_descriptor {
137 struct sdma_mode_count mode;
138 u32 buffer_addr; /* address of the buffer described */
139 u32 ext_buffer_addr; /* extended buffer address */
140} __attribute__ ((packed));
141
142/**
143 * struct sdma_channel_control - Channel control Block
144 *
145 * @current_bd_ptr current buffer descriptor processed
146 * @base_bd_ptr first element of buffer descriptor array
147 * @unused padding. The SDMA engine expects an array of 128 byte
148 * control blocks
149 */
150struct sdma_channel_control {
151 u32 current_bd_ptr;
152 u32 base_bd_ptr;
153 u32 unused[2];
154} __attribute__ ((packed));
155
156/**
157 * struct sdma_state_registers - SDMA context for a channel
158 *
159 * @pc: program counter
160 * @t: test bit: status of arithmetic & test instruction
161 * @rpc: return program counter
162 * @sf: source fault while loading data
163 * @spc: loop start program counter
164 * @df: destination fault while storing data
165 * @epc: loop end program counter
166 * @lm: loop mode
167 */
168struct sdma_state_registers {
169 u32 pc :14;
170 u32 unused1: 1;
171 u32 t : 1;
172 u32 rpc :14;
173 u32 unused0: 1;
174 u32 sf : 1;
175 u32 spc :14;
176 u32 unused2: 1;
177 u32 df : 1;
178 u32 epc :14;
179 u32 lm : 2;
180} __attribute__ ((packed));
181
182/**
183 * struct sdma_context_data - sdma context specific to a channel
184 *
185 * @channel_state: channel state bits
186 * @gReg: general registers
187 * @mda: burst dma destination address register
188 * @msa: burst dma source address register
189 * @ms: burst dma status register
190 * @md: burst dma data register
191 * @pda: peripheral dma destination address register
192 * @psa: peripheral dma source address register
193 * @ps: peripheral dma status register
194 * @pd: peripheral dma data register
195 * @ca: CRC polynomial register
196 * @cs: CRC accumulator register
197 * @dda: dedicated core destination address register
198 * @dsa: dedicated core source address register
199 * @ds: dedicated core status register
200 * @dd: dedicated core data register
201 */
202struct sdma_context_data {
203 struct sdma_state_registers channel_state;
204 u32 gReg[8];
205 u32 mda;
206 u32 msa;
207 u32 ms;
208 u32 md;
209 u32 pda;
210 u32 psa;
211 u32 ps;
212 u32 pd;
213 u32 ca;
214 u32 cs;
215 u32 dda;
216 u32 dsa;
217 u32 ds;
218 u32 dd;
219 u32 scratch0;
220 u32 scratch1;
221 u32 scratch2;
222 u32 scratch3;
223 u32 scratch4;
224 u32 scratch5;
225 u32 scratch6;
226 u32 scratch7;
227} __attribute__ ((packed));
228
229#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
230
231struct sdma_engine;
232
233/**
234 * struct sdma_channel - housekeeping for a SDMA channel
235 *
236 * @sdma pointer to the SDMA engine for this channel
23889c63 237 * @channel the channel number, matches dmaengine chan_id + 1
1ec1e82f
SH		 238 * @direction transfer type. Needed for setting SDMA script
239 * @peripheral_type Peripheral type. Needed for setting SDMA script
240 * @event_id0 aka dma request line
241 * @event_id1 for channels that use 2 events
242 * @word_size peripheral access size
243 * @buf_tail ID of the buffer that was processed
244 * @done channel completion
245 * @num_bd max NUM_BD. number of descriptors currently handling
246 */
247struct sdma_channel {
248 struct sdma_engine *sdma;
249 unsigned int channel;
db8196df 250 enum dma_transfer_direction direction;
1ec1e82f
SH		 251 enum sdma_peripheral_type peripheral_type;
252 unsigned int event_id0;
253 unsigned int event_id1;
254 enum dma_slave_buswidth word_size;
255 unsigned int buf_tail;
256 struct completion done;
257 unsigned int num_bd;
258 struct sdma_buffer_descriptor *bd;
259 dma_addr_t bd_phys;
260 unsigned int pc_from_device, pc_to_device;
261 unsigned long flags;
262 dma_addr_t per_address;
263 u32 event_mask0, event_mask1;
264 u32 watermark_level;
265 u32 shp_addr, per_addr;
266 struct dma_chan chan;
267 spinlock_t lock;
268 struct dma_async_tx_descriptor desc;
269 dma_cookie_t last_completed;
270 enum dma_status status;
271};
272
273#define IMX_DMA_SG_LOOP (1 << 0)
274
275#define MAX_DMA_CHANNELS 32
276#define MXC_SDMA_DEFAULT_PRIORITY 1
277#define MXC_SDMA_MIN_PRIORITY 1
278#define MXC_SDMA_MAX_PRIORITY 7
279
1ec1e82f
SH		 280#define SDMA_FIRMWARE_MAGIC 0x414d4453
281
282/**
283 * struct sdma_firmware_header - Layout of the firmware image
284 *
285 * @magic "SDMA"
286 * @version_major increased whenever layout of struct sdma_script_start_addrs
287 * changes.
288 * @version_minor firmware minor version (for binary compatible changes)
289 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
290 * @num_script_addrs Number of script addresses in this image
291 * @ram_code_start offset of SDMA ram image in this firmware image
292 * @ram_code_size size of SDMA ram image
293 * @script_addrs Stores the start address of the SDMA scripts
294 * (in SDMA memory space)
295 */
296struct sdma_firmware_header {
297 u32 magic;
298 u32 version_major;
299 u32 version_minor;
300 u32 script_addrs_start;
301 u32 num_script_addrs;
302 u32 ram_code_start;
303 u32 ram_code_size;
304};
305
62550cd7
SG		 306enum sdma_devtype {
307 IMX31_SDMA, /* runs on i.mx31 */
308 IMX35_SDMA, /* runs on i.mx35 and later */
309};
310
1ec1e82f
SH		 311struct sdma_engine {
312 struct device *dev;
b9b3f82f 313 struct device_dma_parameters dma_parms;
1ec1e82f
SH		 314 struct sdma_channel channel[MAX_DMA_CHANNELS];
315 struct sdma_channel_control *channel_control;
316 void __iomem *regs;
62550cd7 317 enum sdma_devtype devtype;
1ec1e82f
SH		 318 unsigned int num_events;
319 struct sdma_context_data *context;
320 dma_addr_t context_phys;
321 struct dma_device dma_device;
322 struct clk *clk;
73eab978 323 struct mutex channel_0_lock;
1ec1e82f
SH		 324 struct sdma_script_start_addrs *script_addrs;
325};
326
62550cd7
SG		 327static struct platform_device_id sdma_devtypes[] = {
328 {
329 .name = "imx31-sdma",
330 .driver_data = IMX31_SDMA,
331 }, {
332 .name = "imx35-sdma",
333 .driver_data = IMX35_SDMA,
334 }, {
335 /* sentinel */
336 }
337};
338MODULE_DEVICE_TABLE(platform, sdma_devtypes);
339
580975d7
SG		 340static const struct of_device_id sdma_dt_ids[] = {
341 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
342 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
343 { /* sentinel */ }
344};
345MODULE_DEVICE_TABLE(of, sdma_dt_ids);
346
1ec1e82f
SH		 347#define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
348#define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
349#define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
350#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
351
352static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
353{
62550cd7
SG		 354 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
355 SDMA_CHNENBL0_IMX35);
1ec1e82f
SH		 356 return chnenbl0 + event * 4;
357}
358
359static int sdma_config_ownership(struct sdma_channel *sdmac,
360 bool event_override, bool mcu_override, bool dsp_override)
361{
362 struct sdma_engine *sdma = sdmac->sdma;
363 int channel = sdmac->channel;
364 u32 evt, mcu, dsp;
365
366 if (event_override && mcu_override && dsp_override)
367 return -EINVAL;
368
369 evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
370 mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
371 dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
372
373 if (dsp_override)
374 dsp &= ~(1 << channel);
375 else
376 dsp |= (1 << channel);
377
378 if (event_override)
379 evt &= ~(1 << channel);
380 else
381 evt |= (1 << channel);
382
383 if (mcu_override)
384 mcu &= ~(1 << channel);
385 else
386 mcu |= (1 << channel);
387
388 __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
389 __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
390 __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
391
392 return 0;
393}
394
395/*
396 * sdma_run_channel - run a channel and wait till it's done
397 */
398static int sdma_run_channel(struct sdma_channel *sdmac)
399{
400 struct sdma_engine *sdma = sdmac->sdma;
401 int channel = sdmac->channel;
402 int ret;
403
404 init_completion(&sdmac->done);
405
406 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
407
408 ret = wait_for_completion_timeout(&sdmac->done, HZ);
409
410 return ret ? 0 : -ETIMEDOUT;
411}
412
413static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
414 u32 address)
415{
416 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
417 void *buf_virt;
418 dma_addr_t buf_phys;
419 int ret;
420
73eab978
SH		 421 mutex_lock(&sdma->channel_0_lock);
422
1ec1e82f
SH		 423 buf_virt = dma_alloc_coherent(NULL,
424 size,
425 &buf_phys, GFP_KERNEL);
73eab978
SH		 426 if (!buf_virt) {
427 ret = -ENOMEM;
428 goto err_out;
429 }
1ec1e82f
SH		 430
431 bd0->mode.command = C0_SETPM;
432 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
433 bd0->mode.count = size / 2;
434 bd0->buffer_addr = buf_phys;
435 bd0->ext_buffer_addr = address;
436
437 memcpy(buf_virt, buf, size);
438
439 ret = sdma_run_channel(&sdma->channel[0]);
440
441 dma_free_coherent(NULL, size, buf_virt, buf_phys);
442
73eab978
SH		 443err_out:
444 mutex_unlock(&sdma->channel_0_lock);
445
1ec1e82f
SH		 446 return ret;
447}
448
449static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
450{
451 struct sdma_engine *sdma = sdmac->sdma;
452 int channel = sdmac->channel;
453 u32 val;
454 u32 chnenbl = chnenbl_ofs(sdma, event);
455
456 val = __raw_readl(sdma->regs + chnenbl);
457 val |= (1 << channel);
458 __raw_writel(val, sdma->regs + chnenbl);
459}
460
461static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
462{
463 struct sdma_engine *sdma = sdmac->sdma;
464 int channel = sdmac->channel;
465 u32 chnenbl = chnenbl_ofs(sdma, event);
466 u32 val;
467
468 val = __raw_readl(sdma->regs + chnenbl);
469 val &= ~(1 << channel);
470 __raw_writel(val, sdma->regs + chnenbl);
471}
472
473static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
474{
475 struct sdma_buffer_descriptor *bd;
476
477 /*
478 * loop mode. Iterate over descriptors, re-setup them and
479 * call callback function.
480 */
481 while (1) {
482 bd = &sdmac->bd[sdmac->buf_tail];
483
484 if (bd->mode.status & BD_DONE)
485 break;
486
487 if (bd->mode.status & BD_RROR)
488 sdmac->status = DMA_ERROR;
489 else
1e9cebb4 490 sdmac->status = DMA_IN_PROGRESS;
1ec1e82f
SH		 491
492 bd->mode.status |= BD_DONE;
493 sdmac->buf_tail++;
494 sdmac->buf_tail %= sdmac->num_bd;
495
496 if (sdmac->desc.callback)
497 sdmac->desc.callback(sdmac->desc.callback_param);
498 }
499}
500
501static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
502{
503 struct sdma_buffer_descriptor *bd;
504 int i, error = 0;
505
506 /*
507 * non loop mode. Iterate over all descriptors, collect
508 * errors and call callback function
509 */
510 for (i = 0; i < sdmac->num_bd; i++) {
511 bd = &sdmac->bd[i];
512
513 if (bd->mode.status & (BD_DONE | BD_RROR))
514 error = -EIO;
515 }
516
517 if (error)
518 sdmac->status = DMA_ERROR;
519 else
520 sdmac->status = DMA_SUCCESS;
521
522 if (sdmac->desc.callback)
523 sdmac->desc.callback(sdmac->desc.callback_param);
524 sdmac->last_completed = sdmac->desc.cookie;
525}
526
527static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
528{
529 complete(&sdmac->done);
530
531 /* not interested in channel 0 interrupts */
532 if (sdmac->channel == 0)
533 return;
534
535 if (sdmac->flags & IMX_DMA_SG_LOOP)
536 sdma_handle_channel_loop(sdmac);
537 else
538 mxc_sdma_handle_channel_normal(sdmac);
539}
540
541static irqreturn_t sdma_int_handler(int irq, void *dev_id)
542{
543 struct sdma_engine *sdma = dev_id;
544 u32 stat;
545
546 stat = __raw_readl(sdma->regs + SDMA_H_INTR);
547 __raw_writel(stat, sdma->regs + SDMA_H_INTR);
548
549 while (stat) {
550 int channel = fls(stat) - 1;
551 struct sdma_channel *sdmac = &sdma->channel[channel];
552
553 mxc_sdma_handle_channel(sdmac);
554
555 stat &= ~(1 << channel);
556 }
557
558 return IRQ_HANDLED;
559}
560
561/*
562 * sets the pc of SDMA script according to the peripheral type
563 */
564static void sdma_get_pc(struct sdma_channel *sdmac,
565 enum sdma_peripheral_type peripheral_type)
566{
567 struct sdma_engine *sdma = sdmac->sdma;
568 int per_2_emi = 0, emi_2_per = 0;
569 /*
570 * These are needed once we start to support transfers between
571 * two peripherals or memory-to-memory transfers
572 */
573 int per_2_per = 0, emi_2_emi = 0;
574
575 sdmac->pc_from_device = 0;
576 sdmac->pc_to_device = 0;
577
578 switch (peripheral_type) {
579 case IMX_DMATYPE_MEMORY:
580 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
581 break;
582 case IMX_DMATYPE_DSP:
583 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
584 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
585 break;
586 case IMX_DMATYPE_FIRI:
587 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
588 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
589 break;
590 case IMX_DMATYPE_UART:
591 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
592 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
593 break;
594 case IMX_DMATYPE_UART_SP:
595 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
596 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
597 break;
598 case IMX_DMATYPE_ATA:
599 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
600 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
601 break;
602 case IMX_DMATYPE_CSPI:
603 case IMX_DMATYPE_EXT:
604 case IMX_DMATYPE_SSI:
605 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
606 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
607 break;
608 case IMX_DMATYPE_SSI_SP:
609 case IMX_DMATYPE_MMC:
610 case IMX_DMATYPE_SDHC:
611 case IMX_DMATYPE_CSPI_SP:
612 case IMX_DMATYPE_ESAI:
613 case IMX_DMATYPE_MSHC_SP:
614 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
615 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
616 break;
617 case IMX_DMATYPE_ASRC:
618 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
619 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
620 per_2_per = sdma->script_addrs->per_2_per_addr;
621 break;
622 case IMX_DMATYPE_MSHC:
623 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
624 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
625 break;
626 case IMX_DMATYPE_CCM:
627 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
628 break;
629 case IMX_DMATYPE_SPDIF:
630 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
631 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
632 break;
633 case IMX_DMATYPE_IPU_MEMORY:
634 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
635 break;
636 default:
637 break;
638 }
639
640 sdmac->pc_from_device = per_2_emi;
641 sdmac->pc_to_device = emi_2_per;
642}
643
644static int sdma_load_context(struct sdma_channel *sdmac)
645{
646 struct sdma_engine *sdma = sdmac->sdma;
647 int channel = sdmac->channel;
648 int load_address;
649 struct sdma_context_data *context = sdma->context;
650 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
651 int ret;
652
db8196df 653 if (sdmac->direction == DMA_DEV_TO_MEM) {
1ec1e82f
SH		 654 load_address = sdmac->pc_from_device;
655 } else {
656 load_address = sdmac->pc_to_device;
657 }
658
659 if (load_address < 0)
660 return load_address;
661
662 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
663 dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
664 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
665 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
666 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
667 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
668
73eab978
SH		 669 mutex_lock(&sdma->channel_0_lock);
670
1ec1e82f
SH		 671 memset(context, 0, sizeof(*context));
672 context->channel_state.pc = load_address;
673
674 /* Send by context the event mask,base address for peripheral
675 * and watermark level
676 */
677 context->gReg[0] = sdmac->event_mask1;
678 context->gReg[1] = sdmac->event_mask0;
679 context->gReg[2] = sdmac->per_addr;
680 context->gReg[6] = sdmac->shp_addr;
681 context->gReg[7] = sdmac->watermark_level;
682
683 bd0->mode.command = C0_SETDM;
684 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
685 bd0->mode.count = sizeof(*context) / 4;
686 bd0->buffer_addr = sdma->context_phys;
687 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
688
689 ret = sdma_run_channel(&sdma->channel[0]);
690
73eab978
SH		 691 mutex_unlock(&sdma->channel_0_lock);
692
1ec1e82f
SH		 693 return ret;
694}
695
696static void sdma_disable_channel(struct sdma_channel *sdmac)
697{
698 struct sdma_engine *sdma = sdmac->sdma;
699 int channel = sdmac->channel;
700
701 __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
702 sdmac->status = DMA_ERROR;
703}
704
705static int sdma_config_channel(struct sdma_channel *sdmac)
706{
707 int ret;
708
709 sdma_disable_channel(sdmac);
710
711 sdmac->event_mask0 = 0;
712 sdmac->event_mask1 = 0;
713 sdmac->shp_addr = 0;
714 sdmac->per_addr = 0;
715
716 if (sdmac->event_id0) {
717 if (sdmac->event_id0 > 32)
718 return -EINVAL;
719 sdma_event_enable(sdmac, sdmac->event_id0);
720 }
721
722 switch (sdmac->peripheral_type) {
723 case IMX_DMATYPE_DSP:
724 sdma_config_ownership(sdmac, false, true, true);
725 break;
726 case IMX_DMATYPE_MEMORY:
727 sdma_config_ownership(sdmac, false, true, false);
728 break;
729 default:
730 sdma_config_ownership(sdmac, true, true, false);
731 break;
732 }
733
734 sdma_get_pc(sdmac, sdmac->peripheral_type);
735
736 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
737 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
738 /* Handle multiple event channels differently */
739 if (sdmac->event_id1) {
740 sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
741 if (sdmac->event_id1 > 31)
742 sdmac->watermark_level |= 1 << 31;
743 sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
744 if (sdmac->event_id0 > 31)
745 sdmac->watermark_level |= 1 << 30;
746 } else {
747 sdmac->event_mask0 = 1 << sdmac->event_id0;
748 sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
749 }
750 /* Watermark Level */
751 sdmac->watermark_level |= sdmac->watermark_level;
752 /* Address */
753 sdmac->shp_addr = sdmac->per_address;
754 } else {
755 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
756 }
757
758 ret = sdma_load_context(sdmac);
759
760 return ret;
761}
762
763static int sdma_set_channel_priority(struct sdma_channel *sdmac,
764 unsigned int priority)
765{
766 struct sdma_engine *sdma = sdmac->sdma;
767 int channel = sdmac->channel;
768
769 if (priority < MXC_SDMA_MIN_PRIORITY
770 || priority > MXC_SDMA_MAX_PRIORITY) {
771 return -EINVAL;
772 }
773
774 __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
775
776 return 0;
777}
778
779static int sdma_request_channel(struct sdma_channel *sdmac)
780{
781 struct sdma_engine *sdma = sdmac->sdma;
782 int channel = sdmac->channel;
783 int ret = -EBUSY;
784
785 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
786 if (!sdmac->bd) {
787 ret = -ENOMEM;
788 goto out;
789 }
790
791 memset(sdmac->bd, 0, PAGE_SIZE);
792
793 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
794 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
795
796 clk_enable(sdma->clk);
797
798 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
799
800 init_completion(&sdmac->done);
801
802 sdmac->buf_tail = 0;
803
804 return 0;
805out:
806
807 return ret;
808}
809
810static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
811{
812 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
813}
814
d718f4eb 815static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
1ec1e82f 816{
d718f4eb 817 dma_cookie_t cookie = sdmac->chan.cookie;
1ec1e82f
SH		 818
819 if (++cookie < 0)
820 cookie = 1;
821
d718f4eb
SG		 822 sdmac->chan.cookie = cookie;
823 sdmac->desc.cookie = cookie;
1ec1e82f
SH		 824
825 return cookie;
826}
827
828static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
829{
830 return container_of(chan, struct sdma_channel, chan);
831}
832
833static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
834{
835 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
836 struct sdma_engine *sdma = sdmac->sdma;
837 dma_cookie_t cookie;
838
839 spin_lock_irq(&sdmac->lock);
840
841 cookie = sdma_assign_cookie(sdmac);
842
23889c63 843 sdma_enable_channel(sdma, sdmac->channel);
1ec1e82f
SH		 844
845 spin_unlock_irq(&sdmac->lock);
846
847 return cookie;
848}
849
850static int sdma_alloc_chan_resources(struct dma_chan *chan)
851{
852 struct sdma_channel *sdmac = to_sdma_chan(chan);
853 struct imx_dma_data *data = chan->private;
854 int prio, ret;
855
1ec1e82f
SH		 856 if (!data)
857 return -EINVAL;
858
859 switch (data->priority) {
860 case DMA_PRIO_HIGH:
861 prio = 3;
862 break;
863 case DMA_PRIO_MEDIUM:
864 prio = 2;
865 break;
866 case DMA_PRIO_LOW:
867 default:
868 prio = 1;
869 break;
870 }
871
872 sdmac->peripheral_type = data->peripheral_type;
873 sdmac->event_id0 = data->dma_request;
874 ret = sdma_set_channel_priority(sdmac, prio);
875 if (ret)
876 return ret;
877
878 ret = sdma_request_channel(sdmac);
879 if (ret)
880 return ret;
881
882 dma_async_tx_descriptor_init(&sdmac->desc, chan);
883 sdmac->desc.tx_submit = sdma_tx_submit;
884 /* txd.flags will be overwritten in prep funcs */
885 sdmac->desc.flags = DMA_CTRL_ACK;
886
887 return 0;
888}
889
890static void sdma_free_chan_resources(struct dma_chan *chan)
891{
892 struct sdma_channel *sdmac = to_sdma_chan(chan);
893 struct sdma_engine *sdma = sdmac->sdma;
894
895 sdma_disable_channel(sdmac);
896
897 if (sdmac->event_id0)
898 sdma_event_disable(sdmac, sdmac->event_id0);
899 if (sdmac->event_id1)
900 sdma_event_disable(sdmac, sdmac->event_id1);
901
902 sdmac->event_id0 = 0;
903 sdmac->event_id1 = 0;
904
905 sdma_set_channel_priority(sdmac, 0);
906
907 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
908
909 clk_disable(sdma->clk);
910}
911
912static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
913 struct dma_chan *chan, struct scatterlist *sgl,
db8196df 914 unsigned int sg_len, enum dma_transfer_direction direction,
1ec1e82f
SH		 915 unsigned long flags)
916{
917 struct sdma_channel *sdmac = to_sdma_chan(chan);
918 struct sdma_engine *sdma = sdmac->sdma;
919 int ret, i, count;
23889c63 920 int channel = sdmac->channel;
1ec1e82f
SH		 921 struct scatterlist *sg;
922
923 if (sdmac->status == DMA_IN_PROGRESS)
924 return NULL;
925 sdmac->status = DMA_IN_PROGRESS;
926
927 sdmac->flags = 0;
928
929 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
930 sg_len, channel);
931
932 sdmac->direction = direction;
933 ret = sdma_load_context(sdmac);
934 if (ret)
935 goto err_out;
936
937 if (sg_len > NUM_BD) {
938 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
939 channel, sg_len, NUM_BD);
940 ret = -EINVAL;
941 goto err_out;
942 }
943
944 for_each_sg(sgl, sg, sg_len, i) {
945 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
946 int param;
947
d2f5c276 948 bd->buffer_addr = sg->dma_address;
1ec1e82f
SH		 949
950 count = sg->length;
951
952 if (count > 0xffff) {
953 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
954 channel, count, 0xffff);
955 ret = -EINVAL;
956 goto err_out;
957 }
958
959 bd->mode.count = count;
960
961 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
962 ret = -EINVAL;
963 goto err_out;
964 }
1fa81c27
SH		 965
966 switch (sdmac->word_size) {
967 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1ec1e82f 968 bd->mode.command = 0;
1fa81c27
SH		 969 if (count & 3 || sg->dma_address & 3)
970 return NULL;
971 break;
972 case DMA_SLAVE_BUSWIDTH_2_BYTES:
973 bd->mode.command = 2;
974 if (count & 1 || sg->dma_address & 1)
975 return NULL;
976 break;
977 case DMA_SLAVE_BUSWIDTH_1_BYTE:
978 bd->mode.command = 1;
979 break;
980 default:
981 return NULL;
982 }
1ec1e82f
SH		 983
984 param = BD_DONE | BD_EXTD | BD_CONT;
985
341b9419 986 if (i + 1 == sg_len) {
1ec1e82f 987 param |= BD_INTR;
341b9419
SG		 988 param |= BD_LAST;
989 param &= ~BD_CONT;
1ec1e82f
SH		 990 }
991
1ec1e82f
SH		 992 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
993 i, count, sg->dma_address,
994 param & BD_WRAP ? "wrap" : "",
995 param & BD_INTR ? " intr" : "");
996
997 bd->mode.status = param;
998 }
999
1000 sdmac->num_bd = sg_len;
1001 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1002
1003 return &sdmac->desc;
1004err_out:
4b2ce9dd 1005 sdmac->status = DMA_ERROR;
1ec1e82f
SH		 1006 return NULL;
1007}
1008
1009static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1010 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
db8196df 1011 size_t period_len, enum dma_transfer_direction direction)
1ec1e82f
SH		 1012{
1013 struct sdma_channel *sdmac = to_sdma_chan(chan);
1014 struct sdma_engine *sdma = sdmac->sdma;
1015 int num_periods = buf_len / period_len;
23889c63 1016 int channel = sdmac->channel;
1ec1e82f
SH		 1017 int ret, i = 0, buf = 0;
1018
1019 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1020
1021 if (sdmac->status == DMA_IN_PROGRESS)
1022 return NULL;
1023
1024 sdmac->status = DMA_IN_PROGRESS;
1025
1026 sdmac->flags |= IMX_DMA_SG_LOOP;
1027 sdmac->direction = direction;
1028 ret = sdma_load_context(sdmac);
1029 if (ret)
1030 goto err_out;
1031
1032 if (num_periods > NUM_BD) {
1033 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1034 channel, num_periods, NUM_BD);
1035 goto err_out;
1036 }
1037
1038 if (period_len > 0xffff) {
1039 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1040 channel, period_len, 0xffff);
1041 goto err_out;
1042 }
1043
1044 while (buf < buf_len) {
1045 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1046 int param;
1047
1048 bd->buffer_addr = dma_addr;
1049
1050 bd->mode.count = period_len;
1051
1052 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1053 goto err_out;
1054 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1055 bd->mode.command = 0;
1056 else
1057 bd->mode.command = sdmac->word_size;
1058
1059 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1060 if (i + 1 == num_periods)
1061 param |= BD_WRAP;
1062
1063 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1064 i, period_len, dma_addr,
1065 param & BD_WRAP ? "wrap" : "",
1066 param & BD_INTR ? " intr" : "");
1067
1068 bd->mode.status = param;
1069
1070 dma_addr += period_len;
1071 buf += period_len;
1072
1073 i++;
1074 }
1075
1076 sdmac->num_bd = num_periods;
1077 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1078
1079 return &sdmac->desc;
1080err_out:
1081 sdmac->status = DMA_ERROR;
1082 return NULL;
1083}
1084
1085static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1086 unsigned long arg)
1087{
1088 struct sdma_channel *sdmac = to_sdma_chan(chan);
1089 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1090
1091 switch (cmd) {
1092 case DMA_TERMINATE_ALL:
1093 sdma_disable_channel(sdmac);
1094 return 0;
1095 case DMA_SLAVE_CONFIG:
db8196df 1096 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1ec1e82f
SH		 1097 sdmac->per_address = dmaengine_cfg->src_addr;
1098 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1099 sdmac->word_size = dmaengine_cfg->src_addr_width;
1100 } else {
1101 sdmac->per_address = dmaengine_cfg->dst_addr;
1102 sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1103 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1104 }
1105 return sdma_config_channel(sdmac);
1106 default:
1107 return -ENOSYS;
1108 }
1109
1110 return -EINVAL;
1111}
1112
1113static enum dma_status sdma_tx_status(struct dma_chan *chan,
1114 dma_cookie_t cookie,
1115 struct dma_tx_state *txstate)
1116{
1117 struct sdma_channel *sdmac = to_sdma_chan(chan);
1118 dma_cookie_t last_used;
1ec1e82f
SH		 1119
1120 last_used = chan->cookie;
1121
1ec1e82f
SH		 1122 dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1123
8a965911 1124 return sdmac->status;
1ec1e82f
SH		 1125}
1126
1127static void sdma_issue_pending(struct dma_chan *chan)
1128{
1129 /*
1130 * Nothing to do. We only have a single descriptor
1131 */
1132}
1133
5b28aa31
SH		 1134#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1135
1136static void sdma_add_scripts(struct sdma_engine *sdma,
1137 const struct sdma_script_start_addrs *addr)
1138{
1139 s32 *addr_arr = (u32 *)addr;
1140 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1141 int i;
1142
1143 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1144 if (addr_arr[i] > 0)
1145 saddr_arr[i] = addr_arr[i];
1146}
1147
7b4b88e0 1148static void sdma_load_firmware(const struct firmware *fw, void *context)
5b28aa31 1149{
7b4b88e0 1150 struct sdma_engine *sdma = context;
5b28aa31 1151 const struct sdma_firmware_header *header;
5b28aa31
SH		 1152 const struct sdma_script_start_addrs *addr;
1153 unsigned short *ram_code;
1154
7b4b88e0
SH		 1155 if (!fw) {
1156 dev_err(sdma->dev, "firmware not found\n");
1157 return;
1158 }
5b28aa31
SH		 1159
1160 if (fw->size < sizeof(*header))
1161 goto err_firmware;
1162
1163 header = (struct sdma_firmware_header *)fw->data;
1164
1165 if (header->magic != SDMA_FIRMWARE_MAGIC)
1166 goto err_firmware;
1167 if (header->ram_code_start + header->ram_code_size > fw->size)
1168 goto err_firmware;
1169
1170 addr = (void *)header + header->script_addrs_start;
1171 ram_code = (void *)header + header->ram_code_start;
1172
1173 clk_enable(sdma->clk);
1174 /* download the RAM image for SDMA */
1175 sdma_load_script(sdma, ram_code,
1176 header->ram_code_size,
6866fd3b 1177 addr->ram_code_start_addr);
5b28aa31
SH		 1178 clk_disable(sdma->clk);
1179
1180 sdma_add_scripts(sdma, addr);
1181
1182 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1183 header->version_major,
1184 header->version_minor);
1185
1186err_firmware:
1187 release_firmware(fw);
7b4b88e0
SH		 1188}
1189
1190static int __init sdma_get_firmware(struct sdma_engine *sdma,
1191 const char *fw_name)
1192{
1193 int ret;
1194
1195 ret = request_firmware_nowait(THIS_MODULE,
1196 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1197 GFP_KERNEL, sdma, sdma_load_firmware);
5b28aa31
SH		 1198
1199 return ret;
1200}
1201
1202static int __init sdma_init(struct sdma_engine *sdma)
1ec1e82f
SH		 1203{
1204 int i, ret;
1205 dma_addr_t ccb_phys;
1206
62550cd7
SG		 1207 switch (sdma->devtype) {
1208 case IMX31_SDMA:
1ec1e82f
SH		 1209 sdma->num_events = 32;
1210 break;
62550cd7 1211 case IMX35_SDMA:
1ec1e82f
SH		 1212 sdma->num_events = 48;
1213 break;
1214 default:
62550cd7
SG		 1215 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1216 sdma->devtype);
1ec1e82f
SH		 1217 return -ENODEV;
1218 }
1219
1220 clk_enable(sdma->clk);
1221
1222 /* Be sure SDMA has not started yet */
1223 __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1224
1225 sdma->channel_control = dma_alloc_coherent(NULL,
1226 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1227 sizeof(struct sdma_context_data),
1228 &ccb_phys, GFP_KERNEL);
1229
1230 if (!sdma->channel_control) {
1231 ret = -ENOMEM;
1232 goto err_dma_alloc;
1233 }
1234
1235 sdma->context = (void *)sdma->channel_control +
1236 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1237 sdma->context_phys = ccb_phys +
1238 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1239
1240 /* Zero-out the CCB structures array just allocated */
1241 memset(sdma->channel_control, 0,
1242 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1243
1244 /* disable all channels */
1245 for (i = 0; i < sdma->num_events; i++)
1246 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1247
1248 /* All channels have priority 0 */
1249 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1250 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1251
1252 ret = sdma_request_channel(&sdma->channel[0]);
1253 if (ret)
1254 goto err_dma_alloc;
1255
1256 sdma_config_ownership(&sdma->channel[0], false, true, false);
1257
1258 /* Set Command Channel (Channel Zero) */
1259 __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1260
1261 /* Set bits of CONFIG register but with static context switching */
1262 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1263 __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1264
1265 __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1266
1ec1e82f
SH		 1267 /* Set bits of CONFIG register with given context switching mode */
1268 __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1269
1270 /* Initializes channel's priorities */
1271 sdma_set_channel_priority(&sdma->channel[0], 7);
1272
1273 clk_disable(sdma->clk);
1274
1275 return 0;
1276
1277err_dma_alloc:
1278 clk_disable(sdma->clk);
1279 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1280 return ret;
1281}
1282
1283static int __init sdma_probe(struct platform_device *pdev)
1284{
580975d7
SG		 1285 const struct of_device_id *of_id =
1286 of_match_device(sdma_dt_ids, &pdev->dev);
1287 struct device_node *np = pdev->dev.of_node;
1288 const char *fw_name;
1ec1e82f 1289 int ret;
1ec1e82f 1290 int irq;
1ec1e82f
SH		 1291 struct resource *iores;
1292 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1ec1e82f 1293 int i;
1ec1e82f 1294 struct sdma_engine *sdma;
36e2f21a 1295 s32 *saddr_arr;
1ec1e82f
SH		 1296
1297 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1298 if (!sdma)
1299 return -ENOMEM;
1300
73eab978
SH		 1301 mutex_init(&sdma->channel_0_lock);
1302
1ec1e82f
SH		 1303 sdma->dev = &pdev->dev;
1304
1305 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 irq = platform_get_irq(pdev, 0);
580975d7 1307 if (!iores || irq < 0) {
1ec1e82f
SH		 1308 ret = -EINVAL;
1309 goto err_irq;
1310 }
1311
1312 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1313 ret = -EBUSY;
1314 goto err_request_region;
1315 }
1316
1317 sdma->clk = clk_get(&pdev->dev, NULL);
1318 if (IS_ERR(sdma->clk)) {
1319 ret = PTR_ERR(sdma->clk);
1320 goto err_clk;
1321 }
1322
1323 sdma->regs = ioremap(iores->start, resource_size(iores));
1324 if (!sdma->regs) {
1325 ret = -ENOMEM;
1326 goto err_ioremap;
1327 }
1328
1329 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1330 if (ret)
1331 goto err_request_irq;
1332
5b28aa31 1333 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1c1d9547
AL		 1334 if (!sdma->script_addrs) {
1335 ret = -ENOMEM;
5b28aa31 1336 goto err_alloc;
1c1d9547 1337 }
1ec1e82f 1338
36e2f21a
SH		 1339 /* initially no scripts available */
1340 saddr_arr = (s32 *)sdma->script_addrs;
1341 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1342 saddr_arr[i] = -EINVAL;
1343
580975d7
SG		 1344 if (of_id)
1345 pdev->id_entry = of_id->data;
62550cd7 1346 sdma->devtype = pdev->id_entry->driver_data;
1ec1e82f 1347
7214a8b1
SH		 1348 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1349 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1350
1ec1e82f
SH		 1351 INIT_LIST_HEAD(&sdma->dma_device.channels);
1352 /* Initialize channel parameters */
1353 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1354 struct sdma_channel *sdmac = &sdma->channel[i];
1355
1356 sdmac->sdma = sdma;
1357 spin_lock_init(&sdmac->lock);
1358
1ec1e82f 1359 sdmac->chan.device = &sdma->dma_device;
1ec1e82f
SH		 1360 sdmac->channel = i;
1361
23889c63
SH		 1362 /*
1363 * Add the channel to the DMAC list. Do not add channel 0 though
1364 * because we need it internally in the SDMA driver. This also means
1365 * that channel 0 in dmaengine counting matches sdma channel 1.
1366 */
1367 if (i)
1368 list_add_tail(&sdmac->chan.device_node,
1369 &sdma->dma_device.channels);
1ec1e82f
SH		 1370 }
1371
5b28aa31 1372 ret = sdma_init(sdma);
1ec1e82f
SH		 1373 if (ret)
1374 goto err_init;
1375
580975d7 1376 if (pdata && pdata->script_addrs)
5b28aa31
SH		 1377 sdma_add_scripts(sdma, pdata->script_addrs);
1378
580975d7
SG		 1379 if (pdata) {
1380 sdma_get_firmware(sdma, pdata->fw_name);
1381 } else {
1382 /*
1383 * Because that device tree does not encode ROM script address,
1384 * the RAM script in firmware is mandatory for device tree
1385 * probe, otherwise it fails.
1386 */
1387 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1388 &fw_name);
1389 if (ret) {
1390 dev_err(&pdev->dev, "failed to get firmware name\n");
1391 goto err_init;
1392 }
1393
1394 ret = sdma_get_firmware(sdma, fw_name);
1395 if (ret) {
1396 dev_err(&pdev->dev, "failed to get firmware\n");
1397 goto err_init;
1398 }
1399 }
5b28aa31 1400
1ec1e82f
SH		 1401 sdma->dma_device.dev = &pdev->dev;
1402
1403 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1404 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1405 sdma->dma_device.device_tx_status = sdma_tx_status;
1406 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1407 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1408 sdma->dma_device.device_control = sdma_control;
1409 sdma->dma_device.device_issue_pending = sdma_issue_pending;
b9b3f82f
SH		 1410 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1411 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1ec1e82f
SH		 1412
1413 ret = dma_async_device_register(&sdma->dma_device);
1414 if (ret) {
1415 dev_err(&pdev->dev, "unable to register\n");
1416 goto err_init;
1417 }
1418
5b28aa31 1419 dev_info(sdma->dev, "initialized\n");
1ec1e82f
SH		 1420
1421 return 0;
1422
1423err_init:
1424 kfree(sdma->script_addrs);
5b28aa31 1425err_alloc:
1ec1e82f
SH		 1426 free_irq(irq, sdma);
1427err_request_irq:
1428 iounmap(sdma->regs);
1429err_ioremap:
1430 clk_put(sdma->clk);
1431err_clk:
1432 release_mem_region(iores->start, resource_size(iores));
1433err_request_region:
1434err_irq:
1435 kfree(sdma);
939fd4f0 1436 return ret;
1ec1e82f
SH		 1437}
1438
1439static int __exit sdma_remove(struct platform_device *pdev)
1440{
1441 return -EBUSY;
1442}
1443
1444static struct platform_driver sdma_driver = {
1445 .driver = {
1446 .name = "imx-sdma",
580975d7 1447 .of_match_table = sdma_dt_ids,
1ec1e82f 1448 },
62550cd7 1449 .id_table = sdma_devtypes,
1ec1e82f
SH		 1450 .remove = __exit_p(sdma_remove),
1451};
1452
1453static int __init sdma_module_init(void)
1454{
1455 return platform_driver_probe(&sdma_driver, sdma_probe);
1456}
c989a7fc 1457module_init(sdma_module_init);
1ec1e82f
SH		 1458
1459MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1460MODULE_DESCRIPTION("i.MX SDMA driver");
1461MODULE_LICENSE("GPL");
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