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1ec1e82f SH |
1 | /* |
2 | * drivers/dma/imx-sdma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale Smart DMA engine | |
5 | * | |
6 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
7 | * | |
8 | * Based on code from Freescale: | |
9 | * | |
10 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
11 | * | |
12 | * The code contained herein is licensed under the GNU General Public | |
13 | * License. You may obtain a copy of the GNU General Public License | |
14 | * Version 2 or later at the following locations: | |
15 | * | |
16 | * http://www.opensource.org/licenses/gpl-license.html | |
17 | * http://www.gnu.org/copyleft/gpl.html | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
f8de8f4c | 21 | #include <linux/module.h> |
1ec1e82f | 22 | #include <linux/types.h> |
0bbc1413 | 23 | #include <linux/bitops.h> |
1ec1e82f SH |
24 | #include <linux/mm.h> |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/clk.h> | |
2ccaef05 | 27 | #include <linux/delay.h> |
1ec1e82f SH |
28 | #include <linux/sched.h> |
29 | #include <linux/semaphore.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/firmware.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/dmaengine.h> | |
580975d7 SG |
37 | #include <linux/of.h> |
38 | #include <linux/of_device.h> | |
9479e17c | 39 | #include <linux/of_dma.h> |
1ec1e82f SH |
40 | |
41 | #include <asm/irq.h> | |
82906b13 AB |
42 | #include <linux/platform_data/dma-imx-sdma.h> |
43 | #include <linux/platform_data/dma-imx.h> | |
1ec1e82f | 44 | |
d2ebfb33 RKAL |
45 | #include "dmaengine.h" |
46 | ||
1ec1e82f SH |
47 | /* SDMA registers */ |
48 | #define SDMA_H_C0PTR 0x000 | |
49 | #define SDMA_H_INTR 0x004 | |
50 | #define SDMA_H_STATSTOP 0x008 | |
51 | #define SDMA_H_START 0x00c | |
52 | #define SDMA_H_EVTOVR 0x010 | |
53 | #define SDMA_H_DSPOVR 0x014 | |
54 | #define SDMA_H_HOSTOVR 0x018 | |
55 | #define SDMA_H_EVTPEND 0x01c | |
56 | #define SDMA_H_DSPENBL 0x020 | |
57 | #define SDMA_H_RESET 0x024 | |
58 | #define SDMA_H_EVTERR 0x028 | |
59 | #define SDMA_H_INTRMSK 0x02c | |
60 | #define SDMA_H_PSW 0x030 | |
61 | #define SDMA_H_EVTERRDBG 0x034 | |
62 | #define SDMA_H_CONFIG 0x038 | |
63 | #define SDMA_ONCE_ENB 0x040 | |
64 | #define SDMA_ONCE_DATA 0x044 | |
65 | #define SDMA_ONCE_INSTR 0x048 | |
66 | #define SDMA_ONCE_STAT 0x04c | |
67 | #define SDMA_ONCE_CMD 0x050 | |
68 | #define SDMA_EVT_MIRROR 0x054 | |
69 | #define SDMA_ILLINSTADDR 0x058 | |
70 | #define SDMA_CHN0ADDR 0x05c | |
71 | #define SDMA_ONCE_RTB 0x060 | |
72 | #define SDMA_XTRIG_CONF1 0x070 | |
73 | #define SDMA_XTRIG_CONF2 0x074 | |
62550cd7 SG |
74 | #define SDMA_CHNENBL0_IMX35 0x200 |
75 | #define SDMA_CHNENBL0_IMX31 0x080 | |
1ec1e82f SH |
76 | #define SDMA_CHNPRI_0 0x100 |
77 | ||
78 | /* | |
79 | * Buffer descriptor status values. | |
80 | */ | |
81 | #define BD_DONE 0x01 | |
82 | #define BD_WRAP 0x02 | |
83 | #define BD_CONT 0x04 | |
84 | #define BD_INTR 0x08 | |
85 | #define BD_RROR 0x10 | |
86 | #define BD_LAST 0x20 | |
87 | #define BD_EXTD 0x80 | |
88 | ||
89 | /* | |
90 | * Data Node descriptor status values. | |
91 | */ | |
92 | #define DND_END_OF_FRAME 0x80 | |
93 | #define DND_END_OF_XFER 0x40 | |
94 | #define DND_DONE 0x20 | |
95 | #define DND_UNUSED 0x01 | |
96 | ||
97 | /* | |
98 | * IPCV2 descriptor status values. | |
99 | */ | |
100 | #define BD_IPCV2_END_OF_FRAME 0x40 | |
101 | ||
102 | #define IPCV2_MAX_NODES 50 | |
103 | /* | |
104 | * Error bit set in the CCB status field by the SDMA, | |
105 | * in setbd routine, in case of a transfer error | |
106 | */ | |
107 | #define DATA_ERROR 0x10000000 | |
108 | ||
109 | /* | |
110 | * Buffer descriptor commands. | |
111 | */ | |
112 | #define C0_ADDR 0x01 | |
113 | #define C0_LOAD 0x02 | |
114 | #define C0_DUMP 0x03 | |
115 | #define C0_SETCTX 0x07 | |
116 | #define C0_GETCTX 0x03 | |
117 | #define C0_SETDM 0x01 | |
118 | #define C0_SETPM 0x04 | |
119 | #define C0_GETDM 0x02 | |
120 | #define C0_GETPM 0x08 | |
121 | /* | |
122 | * Change endianness indicator in the BD command field | |
123 | */ | |
124 | #define CHANGE_ENDIANNESS 0x80 | |
125 | ||
126 | /* | |
127 | * Mode/Count of data node descriptors - IPCv2 | |
128 | */ | |
129 | struct sdma_mode_count { | |
130 | u32 count : 16; /* size of the buffer pointed by this BD */ | |
131 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ | |
132 | u32 command : 8; /* command mostlky used for channel 0 */ | |
133 | }; | |
134 | ||
135 | /* | |
136 | * Buffer descriptor | |
137 | */ | |
138 | struct sdma_buffer_descriptor { | |
139 | struct sdma_mode_count mode; | |
140 | u32 buffer_addr; /* address of the buffer described */ | |
141 | u32 ext_buffer_addr; /* extended buffer address */ | |
142 | } __attribute__ ((packed)); | |
143 | ||
144 | /** | |
145 | * struct sdma_channel_control - Channel control Block | |
146 | * | |
147 | * @current_bd_ptr current buffer descriptor processed | |
148 | * @base_bd_ptr first element of buffer descriptor array | |
149 | * @unused padding. The SDMA engine expects an array of 128 byte | |
150 | * control blocks | |
151 | */ | |
152 | struct sdma_channel_control { | |
153 | u32 current_bd_ptr; | |
154 | u32 base_bd_ptr; | |
155 | u32 unused[2]; | |
156 | } __attribute__ ((packed)); | |
157 | ||
158 | /** | |
159 | * struct sdma_state_registers - SDMA context for a channel | |
160 | * | |
161 | * @pc: program counter | |
162 | * @t: test bit: status of arithmetic & test instruction | |
163 | * @rpc: return program counter | |
164 | * @sf: source fault while loading data | |
165 | * @spc: loop start program counter | |
166 | * @df: destination fault while storing data | |
167 | * @epc: loop end program counter | |
168 | * @lm: loop mode | |
169 | */ | |
170 | struct sdma_state_registers { | |
171 | u32 pc :14; | |
172 | u32 unused1: 1; | |
173 | u32 t : 1; | |
174 | u32 rpc :14; | |
175 | u32 unused0: 1; | |
176 | u32 sf : 1; | |
177 | u32 spc :14; | |
178 | u32 unused2: 1; | |
179 | u32 df : 1; | |
180 | u32 epc :14; | |
181 | u32 lm : 2; | |
182 | } __attribute__ ((packed)); | |
183 | ||
184 | /** | |
185 | * struct sdma_context_data - sdma context specific to a channel | |
186 | * | |
187 | * @channel_state: channel state bits | |
188 | * @gReg: general registers | |
189 | * @mda: burst dma destination address register | |
190 | * @msa: burst dma source address register | |
191 | * @ms: burst dma status register | |
192 | * @md: burst dma data register | |
193 | * @pda: peripheral dma destination address register | |
194 | * @psa: peripheral dma source address register | |
195 | * @ps: peripheral dma status register | |
196 | * @pd: peripheral dma data register | |
197 | * @ca: CRC polynomial register | |
198 | * @cs: CRC accumulator register | |
199 | * @dda: dedicated core destination address register | |
200 | * @dsa: dedicated core source address register | |
201 | * @ds: dedicated core status register | |
202 | * @dd: dedicated core data register | |
203 | */ | |
204 | struct sdma_context_data { | |
205 | struct sdma_state_registers channel_state; | |
206 | u32 gReg[8]; | |
207 | u32 mda; | |
208 | u32 msa; | |
209 | u32 ms; | |
210 | u32 md; | |
211 | u32 pda; | |
212 | u32 psa; | |
213 | u32 ps; | |
214 | u32 pd; | |
215 | u32 ca; | |
216 | u32 cs; | |
217 | u32 dda; | |
218 | u32 dsa; | |
219 | u32 ds; | |
220 | u32 dd; | |
221 | u32 scratch0; | |
222 | u32 scratch1; | |
223 | u32 scratch2; | |
224 | u32 scratch3; | |
225 | u32 scratch4; | |
226 | u32 scratch5; | |
227 | u32 scratch6; | |
228 | u32 scratch7; | |
229 | } __attribute__ ((packed)); | |
230 | ||
231 | #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) | |
232 | ||
233 | struct sdma_engine; | |
234 | ||
235 | /** | |
236 | * struct sdma_channel - housekeeping for a SDMA channel | |
237 | * | |
238 | * @sdma pointer to the SDMA engine for this channel | |
23889c63 | 239 | * @channel the channel number, matches dmaengine chan_id + 1 |
1ec1e82f SH |
240 | * @direction transfer type. Needed for setting SDMA script |
241 | * @peripheral_type Peripheral type. Needed for setting SDMA script | |
242 | * @event_id0 aka dma request line | |
243 | * @event_id1 for channels that use 2 events | |
244 | * @word_size peripheral access size | |
245 | * @buf_tail ID of the buffer that was processed | |
1ec1e82f SH |
246 | * @num_bd max NUM_BD. number of descriptors currently handling |
247 | */ | |
248 | struct sdma_channel { | |
249 | struct sdma_engine *sdma; | |
250 | unsigned int channel; | |
db8196df | 251 | enum dma_transfer_direction direction; |
1ec1e82f SH |
252 | enum sdma_peripheral_type peripheral_type; |
253 | unsigned int event_id0; | |
254 | unsigned int event_id1; | |
255 | enum dma_slave_buswidth word_size; | |
256 | unsigned int buf_tail; | |
1ec1e82f | 257 | unsigned int num_bd; |
d1a792f3 | 258 | unsigned int period_len; |
1ec1e82f SH |
259 | struct sdma_buffer_descriptor *bd; |
260 | dma_addr_t bd_phys; | |
261 | unsigned int pc_from_device, pc_to_device; | |
262 | unsigned long flags; | |
263 | dma_addr_t per_address; | |
0bbc1413 RZ |
264 | unsigned long event_mask[2]; |
265 | unsigned long watermark_level; | |
1ec1e82f SH |
266 | u32 shp_addr, per_addr; |
267 | struct dma_chan chan; | |
268 | spinlock_t lock; | |
269 | struct dma_async_tx_descriptor desc; | |
1ec1e82f | 270 | enum dma_status status; |
ab59a510 HS |
271 | unsigned int chn_count; |
272 | unsigned int chn_real_count; | |
abd9ccc8 | 273 | struct tasklet_struct tasklet; |
1ec1e82f SH |
274 | }; |
275 | ||
0bbc1413 | 276 | #define IMX_DMA_SG_LOOP BIT(0) |
1ec1e82f SH |
277 | |
278 | #define MAX_DMA_CHANNELS 32 | |
279 | #define MXC_SDMA_DEFAULT_PRIORITY 1 | |
280 | #define MXC_SDMA_MIN_PRIORITY 1 | |
281 | #define MXC_SDMA_MAX_PRIORITY 7 | |
282 | ||
1ec1e82f SH |
283 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
284 | ||
285 | /** | |
286 | * struct sdma_firmware_header - Layout of the firmware image | |
287 | * | |
288 | * @magic "SDMA" | |
289 | * @version_major increased whenever layout of struct sdma_script_start_addrs | |
290 | * changes. | |
291 | * @version_minor firmware minor version (for binary compatible changes) | |
292 | * @script_addrs_start offset of struct sdma_script_start_addrs in this image | |
293 | * @num_script_addrs Number of script addresses in this image | |
294 | * @ram_code_start offset of SDMA ram image in this firmware image | |
295 | * @ram_code_size size of SDMA ram image | |
296 | * @script_addrs Stores the start address of the SDMA scripts | |
297 | * (in SDMA memory space) | |
298 | */ | |
299 | struct sdma_firmware_header { | |
300 | u32 magic; | |
301 | u32 version_major; | |
302 | u32 version_minor; | |
303 | u32 script_addrs_start; | |
304 | u32 num_script_addrs; | |
305 | u32 ram_code_start; | |
306 | u32 ram_code_size; | |
307 | }; | |
308 | ||
17bba72f SH |
309 | struct sdma_driver_data { |
310 | int chnenbl0; | |
311 | int num_events; | |
dcfec3c0 | 312 | struct sdma_script_start_addrs *script_addrs; |
62550cd7 SG |
313 | }; |
314 | ||
1ec1e82f SH |
315 | struct sdma_engine { |
316 | struct device *dev; | |
b9b3f82f | 317 | struct device_dma_parameters dma_parms; |
1ec1e82f SH |
318 | struct sdma_channel channel[MAX_DMA_CHANNELS]; |
319 | struct sdma_channel_control *channel_control; | |
320 | void __iomem *regs; | |
1ec1e82f SH |
321 | struct sdma_context_data *context; |
322 | dma_addr_t context_phys; | |
323 | struct dma_device dma_device; | |
7560e3f3 SH |
324 | struct clk *clk_ipg; |
325 | struct clk *clk_ahb; | |
2ccaef05 | 326 | spinlock_t channel_0_lock; |
cd72b846 | 327 | u32 script_number; |
1ec1e82f | 328 | struct sdma_script_start_addrs *script_addrs; |
17bba72f SH |
329 | const struct sdma_driver_data *drvdata; |
330 | }; | |
331 | ||
e9fd58de | 332 | static struct sdma_driver_data sdma_imx31 = { |
17bba72f SH |
333 | .chnenbl0 = SDMA_CHNENBL0_IMX31, |
334 | .num_events = 32, | |
335 | }; | |
336 | ||
dcfec3c0 SH |
337 | static struct sdma_script_start_addrs sdma_script_imx25 = { |
338 | .ap_2_ap_addr = 729, | |
339 | .uart_2_mcu_addr = 904, | |
340 | .per_2_app_addr = 1255, | |
341 | .mcu_2_app_addr = 834, | |
342 | .uartsh_2_mcu_addr = 1120, | |
343 | .per_2_shp_addr = 1329, | |
344 | .mcu_2_shp_addr = 1048, | |
345 | .ata_2_mcu_addr = 1560, | |
346 | .mcu_2_ata_addr = 1479, | |
347 | .app_2_per_addr = 1189, | |
348 | .app_2_mcu_addr = 770, | |
349 | .shp_2_per_addr = 1407, | |
350 | .shp_2_mcu_addr = 979, | |
351 | }; | |
352 | ||
e9fd58de | 353 | static struct sdma_driver_data sdma_imx25 = { |
dcfec3c0 SH |
354 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
355 | .num_events = 48, | |
356 | .script_addrs = &sdma_script_imx25, | |
357 | }; | |
358 | ||
e9fd58de | 359 | static struct sdma_driver_data sdma_imx35 = { |
17bba72f SH |
360 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
361 | .num_events = 48, | |
1ec1e82f SH |
362 | }; |
363 | ||
dcfec3c0 SH |
364 | static struct sdma_script_start_addrs sdma_script_imx51 = { |
365 | .ap_2_ap_addr = 642, | |
366 | .uart_2_mcu_addr = 817, | |
367 | .mcu_2_app_addr = 747, | |
368 | .mcu_2_shp_addr = 961, | |
369 | .ata_2_mcu_addr = 1473, | |
370 | .mcu_2_ata_addr = 1392, | |
371 | .app_2_per_addr = 1033, | |
372 | .app_2_mcu_addr = 683, | |
373 | .shp_2_per_addr = 1251, | |
374 | .shp_2_mcu_addr = 892, | |
375 | }; | |
376 | ||
e9fd58de | 377 | static struct sdma_driver_data sdma_imx51 = { |
dcfec3c0 SH |
378 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
379 | .num_events = 48, | |
380 | .script_addrs = &sdma_script_imx51, | |
381 | }; | |
382 | ||
383 | static struct sdma_script_start_addrs sdma_script_imx53 = { | |
384 | .ap_2_ap_addr = 642, | |
385 | .app_2_mcu_addr = 683, | |
386 | .mcu_2_app_addr = 747, | |
387 | .uart_2_mcu_addr = 817, | |
388 | .shp_2_mcu_addr = 891, | |
389 | .mcu_2_shp_addr = 960, | |
390 | .uartsh_2_mcu_addr = 1032, | |
391 | .spdif_2_mcu_addr = 1100, | |
392 | .mcu_2_spdif_addr = 1134, | |
393 | .firi_2_mcu_addr = 1193, | |
394 | .mcu_2_firi_addr = 1290, | |
395 | }; | |
396 | ||
e9fd58de | 397 | static struct sdma_driver_data sdma_imx53 = { |
dcfec3c0 SH |
398 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
399 | .num_events = 48, | |
400 | .script_addrs = &sdma_script_imx53, | |
401 | }; | |
402 | ||
403 | static struct sdma_script_start_addrs sdma_script_imx6q = { | |
404 | .ap_2_ap_addr = 642, | |
405 | .uart_2_mcu_addr = 817, | |
406 | .mcu_2_app_addr = 747, | |
407 | .per_2_per_addr = 6331, | |
408 | .uartsh_2_mcu_addr = 1032, | |
409 | .mcu_2_shp_addr = 960, | |
410 | .app_2_mcu_addr = 683, | |
411 | .shp_2_mcu_addr = 891, | |
412 | .spdif_2_mcu_addr = 1100, | |
413 | .mcu_2_spdif_addr = 1134, | |
414 | }; | |
415 | ||
e9fd58de | 416 | static struct sdma_driver_data sdma_imx6q = { |
dcfec3c0 SH |
417 | .chnenbl0 = SDMA_CHNENBL0_IMX35, |
418 | .num_events = 48, | |
419 | .script_addrs = &sdma_script_imx6q, | |
420 | }; | |
421 | ||
62550cd7 SG |
422 | static struct platform_device_id sdma_devtypes[] = { |
423 | { | |
dcfec3c0 SH |
424 | .name = "imx25-sdma", |
425 | .driver_data = (unsigned long)&sdma_imx25, | |
426 | }, { | |
62550cd7 | 427 | .name = "imx31-sdma", |
17bba72f | 428 | .driver_data = (unsigned long)&sdma_imx31, |
62550cd7 SG |
429 | }, { |
430 | .name = "imx35-sdma", | |
17bba72f | 431 | .driver_data = (unsigned long)&sdma_imx35, |
dcfec3c0 SH |
432 | }, { |
433 | .name = "imx51-sdma", | |
434 | .driver_data = (unsigned long)&sdma_imx51, | |
435 | }, { | |
436 | .name = "imx53-sdma", | |
437 | .driver_data = (unsigned long)&sdma_imx53, | |
438 | }, { | |
439 | .name = "imx6q-sdma", | |
440 | .driver_data = (unsigned long)&sdma_imx6q, | |
62550cd7 SG |
441 | }, { |
442 | /* sentinel */ | |
443 | } | |
444 | }; | |
445 | MODULE_DEVICE_TABLE(platform, sdma_devtypes); | |
446 | ||
580975d7 | 447 | static const struct of_device_id sdma_dt_ids[] = { |
dcfec3c0 SH |
448 | { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, }, |
449 | { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, }, | |
450 | { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, }, | |
17bba72f | 451 | { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, }, |
dcfec3c0 | 452 | { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, }, |
63edea16 | 453 | { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, }, |
580975d7 SG |
454 | { /* sentinel */ } |
455 | }; | |
456 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); | |
457 | ||
0bbc1413 RZ |
458 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
459 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ | |
460 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ | |
1ec1e82f SH |
461 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
462 | ||
463 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) | |
464 | { | |
17bba72f | 465 | u32 chnenbl0 = sdma->drvdata->chnenbl0; |
1ec1e82f SH |
466 | return chnenbl0 + event * 4; |
467 | } | |
468 | ||
469 | static int sdma_config_ownership(struct sdma_channel *sdmac, | |
470 | bool event_override, bool mcu_override, bool dsp_override) | |
471 | { | |
472 | struct sdma_engine *sdma = sdmac->sdma; | |
473 | int channel = sdmac->channel; | |
0bbc1413 | 474 | unsigned long evt, mcu, dsp; |
1ec1e82f SH |
475 | |
476 | if (event_override && mcu_override && dsp_override) | |
477 | return -EINVAL; | |
478 | ||
c4b56857 RZ |
479 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
480 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); | |
481 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
482 | |
483 | if (dsp_override) | |
0bbc1413 | 484 | __clear_bit(channel, &dsp); |
1ec1e82f | 485 | else |
0bbc1413 | 486 | __set_bit(channel, &dsp); |
1ec1e82f SH |
487 | |
488 | if (event_override) | |
0bbc1413 | 489 | __clear_bit(channel, &evt); |
1ec1e82f | 490 | else |
0bbc1413 | 491 | __set_bit(channel, &evt); |
1ec1e82f SH |
492 | |
493 | if (mcu_override) | |
0bbc1413 | 494 | __clear_bit(channel, &mcu); |
1ec1e82f | 495 | else |
0bbc1413 | 496 | __set_bit(channel, &mcu); |
1ec1e82f | 497 | |
c4b56857 RZ |
498 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
499 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); | |
500 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
b9a59166 RZ |
505 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
506 | { | |
0bbc1413 | 507 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
b9a59166 RZ |
508 | } |
509 | ||
1ec1e82f | 510 | /* |
2ccaef05 | 511 | * sdma_run_channel0 - run a channel and wait till it's done |
1ec1e82f | 512 | */ |
2ccaef05 | 513 | static int sdma_run_channel0(struct sdma_engine *sdma) |
1ec1e82f | 514 | { |
1ec1e82f | 515 | int ret; |
2ccaef05 | 516 | unsigned long timeout = 500; |
1ec1e82f | 517 | |
2ccaef05 | 518 | sdma_enable_channel(sdma, 0); |
1ec1e82f | 519 | |
2ccaef05 RZ |
520 | while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { |
521 | if (timeout-- <= 0) | |
522 | break; | |
523 | udelay(1); | |
524 | } | |
1ec1e82f | 525 | |
2ccaef05 RZ |
526 | if (ret) { |
527 | /* Clear the interrupt status */ | |
528 | writel_relaxed(ret, sdma->regs + SDMA_H_INTR); | |
529 | } else { | |
530 | dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); | |
531 | } | |
1ec1e82f SH |
532 | |
533 | return ret ? 0 : -ETIMEDOUT; | |
534 | } | |
535 | ||
536 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, | |
537 | u32 address) | |
538 | { | |
539 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
540 | void *buf_virt; | |
541 | dma_addr_t buf_phys; | |
542 | int ret; | |
2ccaef05 | 543 | unsigned long flags; |
73eab978 | 544 | |
1ec1e82f SH |
545 | buf_virt = dma_alloc_coherent(NULL, |
546 | size, | |
547 | &buf_phys, GFP_KERNEL); | |
73eab978 | 548 | if (!buf_virt) { |
2ccaef05 | 549 | return -ENOMEM; |
73eab978 | 550 | } |
1ec1e82f | 551 | |
2ccaef05 RZ |
552 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
553 | ||
1ec1e82f SH |
554 | bd0->mode.command = C0_SETPM; |
555 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
556 | bd0->mode.count = size / 2; | |
557 | bd0->buffer_addr = buf_phys; | |
558 | bd0->ext_buffer_addr = address; | |
559 | ||
560 | memcpy(buf_virt, buf, size); | |
561 | ||
2ccaef05 | 562 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 563 | |
2ccaef05 | 564 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
1ec1e82f | 565 | |
2ccaef05 | 566 | dma_free_coherent(NULL, size, buf_virt, buf_phys); |
73eab978 | 567 | |
1ec1e82f SH |
568 | return ret; |
569 | } | |
570 | ||
571 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) | |
572 | { | |
573 | struct sdma_engine *sdma = sdmac->sdma; | |
574 | int channel = sdmac->channel; | |
0bbc1413 | 575 | unsigned long val; |
1ec1e82f SH |
576 | u32 chnenbl = chnenbl_ofs(sdma, event); |
577 | ||
c4b56857 | 578 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 579 | __set_bit(channel, &val); |
c4b56857 | 580 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
581 | } |
582 | ||
583 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) | |
584 | { | |
585 | struct sdma_engine *sdma = sdmac->sdma; | |
586 | int channel = sdmac->channel; | |
587 | u32 chnenbl = chnenbl_ofs(sdma, event); | |
0bbc1413 | 588 | unsigned long val; |
1ec1e82f | 589 | |
c4b56857 | 590 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 591 | __clear_bit(channel, &val); |
c4b56857 | 592 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
593 | } |
594 | ||
595 | static void sdma_handle_channel_loop(struct sdma_channel *sdmac) | |
d1a792f3 RKAL |
596 | { |
597 | if (sdmac->desc.callback) | |
598 | sdmac->desc.callback(sdmac->desc.callback_param); | |
599 | } | |
600 | ||
601 | static void sdma_update_channel_loop(struct sdma_channel *sdmac) | |
1ec1e82f SH |
602 | { |
603 | struct sdma_buffer_descriptor *bd; | |
604 | ||
605 | /* | |
606 | * loop mode. Iterate over descriptors, re-setup them and | |
607 | * call callback function. | |
608 | */ | |
609 | while (1) { | |
610 | bd = &sdmac->bd[sdmac->buf_tail]; | |
611 | ||
612 | if (bd->mode.status & BD_DONE) | |
613 | break; | |
614 | ||
615 | if (bd->mode.status & BD_RROR) | |
616 | sdmac->status = DMA_ERROR; | |
1ec1e82f SH |
617 | |
618 | bd->mode.status |= BD_DONE; | |
619 | sdmac->buf_tail++; | |
620 | sdmac->buf_tail %= sdmac->num_bd; | |
1ec1e82f SH |
621 | } |
622 | } | |
623 | ||
624 | static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) | |
625 | { | |
626 | struct sdma_buffer_descriptor *bd; | |
627 | int i, error = 0; | |
628 | ||
ab59a510 | 629 | sdmac->chn_real_count = 0; |
1ec1e82f SH |
630 | /* |
631 | * non loop mode. Iterate over all descriptors, collect | |
632 | * errors and call callback function | |
633 | */ | |
634 | for (i = 0; i < sdmac->num_bd; i++) { | |
635 | bd = &sdmac->bd[i]; | |
636 | ||
637 | if (bd->mode.status & (BD_DONE | BD_RROR)) | |
638 | error = -EIO; | |
ab59a510 | 639 | sdmac->chn_real_count += bd->mode.count; |
1ec1e82f SH |
640 | } |
641 | ||
642 | if (error) | |
643 | sdmac->status = DMA_ERROR; | |
644 | else | |
409bff6a | 645 | sdmac->status = DMA_COMPLETE; |
1ec1e82f | 646 | |
f7fbce07 | 647 | dma_cookie_complete(&sdmac->desc); |
1ec1e82f SH |
648 | if (sdmac->desc.callback) |
649 | sdmac->desc.callback(sdmac->desc.callback_param); | |
1ec1e82f SH |
650 | } |
651 | ||
abd9ccc8 | 652 | static void sdma_tasklet(unsigned long data) |
1ec1e82f | 653 | { |
abd9ccc8 HS |
654 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
655 | ||
1ec1e82f SH |
656 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
657 | sdma_handle_channel_loop(sdmac); | |
658 | else | |
659 | mxc_sdma_handle_channel_normal(sdmac); | |
660 | } | |
661 | ||
662 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) | |
663 | { | |
664 | struct sdma_engine *sdma = dev_id; | |
0bbc1413 | 665 | unsigned long stat; |
1ec1e82f | 666 | |
c4b56857 | 667 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
2ccaef05 RZ |
668 | /* not interested in channel 0 interrupts */ |
669 | stat &= ~1; | |
c4b56857 | 670 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); |
1ec1e82f SH |
671 | |
672 | while (stat) { | |
673 | int channel = fls(stat) - 1; | |
674 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
675 | ||
d1a792f3 RKAL |
676 | if (sdmac->flags & IMX_DMA_SG_LOOP) |
677 | sdma_update_channel_loop(sdmac); | |
678 | ||
abd9ccc8 | 679 | tasklet_schedule(&sdmac->tasklet); |
1ec1e82f | 680 | |
0bbc1413 | 681 | __clear_bit(channel, &stat); |
1ec1e82f SH |
682 | } |
683 | ||
684 | return IRQ_HANDLED; | |
685 | } | |
686 | ||
687 | /* | |
688 | * sets the pc of SDMA script according to the peripheral type | |
689 | */ | |
690 | static void sdma_get_pc(struct sdma_channel *sdmac, | |
691 | enum sdma_peripheral_type peripheral_type) | |
692 | { | |
693 | struct sdma_engine *sdma = sdmac->sdma; | |
694 | int per_2_emi = 0, emi_2_per = 0; | |
695 | /* | |
696 | * These are needed once we start to support transfers between | |
697 | * two peripherals or memory-to-memory transfers | |
698 | */ | |
699 | int per_2_per = 0, emi_2_emi = 0; | |
700 | ||
701 | sdmac->pc_from_device = 0; | |
702 | sdmac->pc_to_device = 0; | |
703 | ||
704 | switch (peripheral_type) { | |
705 | case IMX_DMATYPE_MEMORY: | |
706 | emi_2_emi = sdma->script_addrs->ap_2_ap_addr; | |
707 | break; | |
708 | case IMX_DMATYPE_DSP: | |
709 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; | |
710 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; | |
711 | break; | |
712 | case IMX_DMATYPE_FIRI: | |
713 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; | |
714 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; | |
715 | break; | |
716 | case IMX_DMATYPE_UART: | |
717 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; | |
718 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
719 | break; | |
720 | case IMX_DMATYPE_UART_SP: | |
721 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; | |
722 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
723 | break; | |
724 | case IMX_DMATYPE_ATA: | |
725 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; | |
726 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; | |
727 | break; | |
728 | case IMX_DMATYPE_CSPI: | |
729 | case IMX_DMATYPE_EXT: | |
730 | case IMX_DMATYPE_SSI: | |
731 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; | |
732 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
733 | break; | |
1a895578 NC |
734 | case IMX_DMATYPE_SSI_DUAL: |
735 | per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; | |
736 | emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; | |
737 | break; | |
1ec1e82f SH |
738 | case IMX_DMATYPE_SSI_SP: |
739 | case IMX_DMATYPE_MMC: | |
740 | case IMX_DMATYPE_SDHC: | |
741 | case IMX_DMATYPE_CSPI_SP: | |
742 | case IMX_DMATYPE_ESAI: | |
743 | case IMX_DMATYPE_MSHC_SP: | |
744 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
745 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
746 | break; | |
747 | case IMX_DMATYPE_ASRC: | |
748 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; | |
749 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; | |
750 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
751 | break; | |
752 | case IMX_DMATYPE_MSHC: | |
753 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; | |
754 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; | |
755 | break; | |
756 | case IMX_DMATYPE_CCM: | |
757 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; | |
758 | break; | |
759 | case IMX_DMATYPE_SPDIF: | |
760 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; | |
761 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; | |
762 | break; | |
763 | case IMX_DMATYPE_IPU_MEMORY: | |
764 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; | |
765 | break; | |
766 | default: | |
767 | break; | |
768 | } | |
769 | ||
770 | sdmac->pc_from_device = per_2_emi; | |
771 | sdmac->pc_to_device = emi_2_per; | |
772 | } | |
773 | ||
774 | static int sdma_load_context(struct sdma_channel *sdmac) | |
775 | { | |
776 | struct sdma_engine *sdma = sdmac->sdma; | |
777 | int channel = sdmac->channel; | |
778 | int load_address; | |
779 | struct sdma_context_data *context = sdma->context; | |
780 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
781 | int ret; | |
2ccaef05 | 782 | unsigned long flags; |
1ec1e82f | 783 | |
db8196df | 784 | if (sdmac->direction == DMA_DEV_TO_MEM) { |
1ec1e82f SH |
785 | load_address = sdmac->pc_from_device; |
786 | } else { | |
787 | load_address = sdmac->pc_to_device; | |
788 | } | |
789 | ||
790 | if (load_address < 0) | |
791 | return load_address; | |
792 | ||
793 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); | |
0bbc1413 | 794 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
1ec1e82f SH |
795 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
796 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); | |
0bbc1413 RZ |
797 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
798 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); | |
1ec1e82f | 799 | |
2ccaef05 | 800 | spin_lock_irqsave(&sdma->channel_0_lock, flags); |
73eab978 | 801 | |
1ec1e82f SH |
802 | memset(context, 0, sizeof(*context)); |
803 | context->channel_state.pc = load_address; | |
804 | ||
805 | /* Send by context the event mask,base address for peripheral | |
806 | * and watermark level | |
807 | */ | |
0bbc1413 RZ |
808 | context->gReg[0] = sdmac->event_mask[1]; |
809 | context->gReg[1] = sdmac->event_mask[0]; | |
1ec1e82f SH |
810 | context->gReg[2] = sdmac->per_addr; |
811 | context->gReg[6] = sdmac->shp_addr; | |
812 | context->gReg[7] = sdmac->watermark_level; | |
813 | ||
814 | bd0->mode.command = C0_SETDM; | |
815 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
816 | bd0->mode.count = sizeof(*context) / 4; | |
817 | bd0->buffer_addr = sdma->context_phys; | |
818 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; | |
2ccaef05 | 819 | ret = sdma_run_channel0(sdma); |
1ec1e82f | 820 | |
2ccaef05 | 821 | spin_unlock_irqrestore(&sdma->channel_0_lock, flags); |
73eab978 | 822 | |
1ec1e82f SH |
823 | return ret; |
824 | } | |
825 | ||
826 | static void sdma_disable_channel(struct sdma_channel *sdmac) | |
827 | { | |
828 | struct sdma_engine *sdma = sdmac->sdma; | |
829 | int channel = sdmac->channel; | |
830 | ||
0bbc1413 | 831 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
1ec1e82f SH |
832 | sdmac->status = DMA_ERROR; |
833 | } | |
834 | ||
835 | static int sdma_config_channel(struct sdma_channel *sdmac) | |
836 | { | |
837 | int ret; | |
838 | ||
839 | sdma_disable_channel(sdmac); | |
840 | ||
0bbc1413 RZ |
841 | sdmac->event_mask[0] = 0; |
842 | sdmac->event_mask[1] = 0; | |
1ec1e82f SH |
843 | sdmac->shp_addr = 0; |
844 | sdmac->per_addr = 0; | |
845 | ||
846 | if (sdmac->event_id0) { | |
17bba72f | 847 | if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) |
1ec1e82f SH |
848 | return -EINVAL; |
849 | sdma_event_enable(sdmac, sdmac->event_id0); | |
850 | } | |
851 | ||
852 | switch (sdmac->peripheral_type) { | |
853 | case IMX_DMATYPE_DSP: | |
854 | sdma_config_ownership(sdmac, false, true, true); | |
855 | break; | |
856 | case IMX_DMATYPE_MEMORY: | |
857 | sdma_config_ownership(sdmac, false, true, false); | |
858 | break; | |
859 | default: | |
860 | sdma_config_ownership(sdmac, true, true, false); | |
861 | break; | |
862 | } | |
863 | ||
864 | sdma_get_pc(sdmac, sdmac->peripheral_type); | |
865 | ||
866 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && | |
867 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { | |
868 | /* Handle multiple event channels differently */ | |
869 | if (sdmac->event_id1) { | |
0bbc1413 | 870 | sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); |
1ec1e82f | 871 | if (sdmac->event_id1 > 31) |
0bbc1413 RZ |
872 | __set_bit(31, &sdmac->watermark_level); |
873 | sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); | |
1ec1e82f | 874 | if (sdmac->event_id0 > 31) |
0bbc1413 | 875 | __set_bit(30, &sdmac->watermark_level); |
1ec1e82f | 876 | } else { |
0bbc1413 | 877 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
1ec1e82f SH |
878 | } |
879 | /* Watermark Level */ | |
880 | sdmac->watermark_level |= sdmac->watermark_level; | |
881 | /* Address */ | |
882 | sdmac->shp_addr = sdmac->per_address; | |
883 | } else { | |
884 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ | |
885 | } | |
886 | ||
887 | ret = sdma_load_context(sdmac); | |
888 | ||
889 | return ret; | |
890 | } | |
891 | ||
892 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, | |
893 | unsigned int priority) | |
894 | { | |
895 | struct sdma_engine *sdma = sdmac->sdma; | |
896 | int channel = sdmac->channel; | |
897 | ||
898 | if (priority < MXC_SDMA_MIN_PRIORITY | |
899 | || priority > MXC_SDMA_MAX_PRIORITY) { | |
900 | return -EINVAL; | |
901 | } | |
902 | ||
c4b56857 | 903 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
1ec1e82f SH |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static int sdma_request_channel(struct sdma_channel *sdmac) | |
909 | { | |
910 | struct sdma_engine *sdma = sdmac->sdma; | |
911 | int channel = sdmac->channel; | |
912 | int ret = -EBUSY; | |
913 | ||
9f92d223 JP |
914 | sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, |
915 | GFP_KERNEL); | |
1ec1e82f SH |
916 | if (!sdmac->bd) { |
917 | ret = -ENOMEM; | |
918 | goto out; | |
919 | } | |
920 | ||
1ec1e82f SH |
921 | sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; |
922 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
923 | ||
1ec1e82f | 924 | sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); |
1ec1e82f SH |
925 | return 0; |
926 | out: | |
927 | ||
928 | return ret; | |
929 | } | |
930 | ||
1ec1e82f SH |
931 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
932 | { | |
933 | return container_of(chan, struct sdma_channel, chan); | |
934 | } | |
935 | ||
936 | static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
937 | { | |
f69f2e26 | 938 | unsigned long flags; |
1ec1e82f | 939 | struct sdma_channel *sdmac = to_sdma_chan(tx->chan); |
1ec1e82f SH |
940 | dma_cookie_t cookie; |
941 | ||
f69f2e26 | 942 | spin_lock_irqsave(&sdmac->lock, flags); |
1ec1e82f | 943 | |
884485e1 | 944 | cookie = dma_cookie_assign(tx); |
1ec1e82f | 945 | |
f69f2e26 | 946 | spin_unlock_irqrestore(&sdmac->lock, flags); |
1ec1e82f SH |
947 | |
948 | return cookie; | |
949 | } | |
950 | ||
951 | static int sdma_alloc_chan_resources(struct dma_chan *chan) | |
952 | { | |
953 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
954 | struct imx_dma_data *data = chan->private; | |
955 | int prio, ret; | |
956 | ||
1ec1e82f SH |
957 | if (!data) |
958 | return -EINVAL; | |
959 | ||
960 | switch (data->priority) { | |
961 | case DMA_PRIO_HIGH: | |
962 | prio = 3; | |
963 | break; | |
964 | case DMA_PRIO_MEDIUM: | |
965 | prio = 2; | |
966 | break; | |
967 | case DMA_PRIO_LOW: | |
968 | default: | |
969 | prio = 1; | |
970 | break; | |
971 | } | |
972 | ||
973 | sdmac->peripheral_type = data->peripheral_type; | |
974 | sdmac->event_id0 = data->dma_request; | |
c2c744d3 | 975 | |
7560e3f3 SH |
976 | clk_enable(sdmac->sdma->clk_ipg); |
977 | clk_enable(sdmac->sdma->clk_ahb); | |
c2c744d3 | 978 | |
3bb5e7ca | 979 | ret = sdma_request_channel(sdmac); |
1ec1e82f SH |
980 | if (ret) |
981 | return ret; | |
982 | ||
3bb5e7ca | 983 | ret = sdma_set_channel_priority(sdmac, prio); |
1ec1e82f SH |
984 | if (ret) |
985 | return ret; | |
986 | ||
987 | dma_async_tx_descriptor_init(&sdmac->desc, chan); | |
988 | sdmac->desc.tx_submit = sdma_tx_submit; | |
989 | /* txd.flags will be overwritten in prep funcs */ | |
990 | sdmac->desc.flags = DMA_CTRL_ACK; | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | static void sdma_free_chan_resources(struct dma_chan *chan) | |
996 | { | |
997 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
998 | struct sdma_engine *sdma = sdmac->sdma; | |
999 | ||
1000 | sdma_disable_channel(sdmac); | |
1001 | ||
1002 | if (sdmac->event_id0) | |
1003 | sdma_event_disable(sdmac, sdmac->event_id0); | |
1004 | if (sdmac->event_id1) | |
1005 | sdma_event_disable(sdmac, sdmac->event_id1); | |
1006 | ||
1007 | sdmac->event_id0 = 0; | |
1008 | sdmac->event_id1 = 0; | |
1009 | ||
1010 | sdma_set_channel_priority(sdmac, 0); | |
1011 | ||
1012 | dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); | |
1013 | ||
7560e3f3 SH |
1014 | clk_disable(sdma->clk_ipg); |
1015 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1016 | } |
1017 | ||
1018 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( | |
1019 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 1020 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 1021 | unsigned long flags, void *context) |
1ec1e82f SH |
1022 | { |
1023 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1024 | struct sdma_engine *sdma = sdmac->sdma; | |
1025 | int ret, i, count; | |
23889c63 | 1026 | int channel = sdmac->channel; |
1ec1e82f SH |
1027 | struct scatterlist *sg; |
1028 | ||
1029 | if (sdmac->status == DMA_IN_PROGRESS) | |
1030 | return NULL; | |
1031 | sdmac->status = DMA_IN_PROGRESS; | |
1032 | ||
1033 | sdmac->flags = 0; | |
1034 | ||
8e2e27c7 RZ |
1035 | sdmac->buf_tail = 0; |
1036 | ||
1ec1e82f SH |
1037 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", |
1038 | sg_len, channel); | |
1039 | ||
1040 | sdmac->direction = direction; | |
1041 | ret = sdma_load_context(sdmac); | |
1042 | if (ret) | |
1043 | goto err_out; | |
1044 | ||
1045 | if (sg_len > NUM_BD) { | |
1046 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1047 | channel, sg_len, NUM_BD); | |
1048 | ret = -EINVAL; | |
1049 | goto err_out; | |
1050 | } | |
1051 | ||
ab59a510 | 1052 | sdmac->chn_count = 0; |
1ec1e82f SH |
1053 | for_each_sg(sgl, sg, sg_len, i) { |
1054 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1055 | int param; | |
1056 | ||
d2f5c276 | 1057 | bd->buffer_addr = sg->dma_address; |
1ec1e82f | 1058 | |
fdaf9c4b | 1059 | count = sg_dma_len(sg); |
1ec1e82f SH |
1060 | |
1061 | if (count > 0xffff) { | |
1062 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", | |
1063 | channel, count, 0xffff); | |
1064 | ret = -EINVAL; | |
1065 | goto err_out; | |
1066 | } | |
1067 | ||
1068 | bd->mode.count = count; | |
ab59a510 | 1069 | sdmac->chn_count += count; |
1ec1e82f SH |
1070 | |
1071 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { | |
1072 | ret = -EINVAL; | |
1073 | goto err_out; | |
1074 | } | |
1fa81c27 SH |
1075 | |
1076 | switch (sdmac->word_size) { | |
1077 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1ec1e82f | 1078 | bd->mode.command = 0; |
1fa81c27 SH |
1079 | if (count & 3 || sg->dma_address & 3) |
1080 | return NULL; | |
1081 | break; | |
1082 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1083 | bd->mode.command = 2; | |
1084 | if (count & 1 || sg->dma_address & 1) | |
1085 | return NULL; | |
1086 | break; | |
1087 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1088 | bd->mode.command = 1; | |
1089 | break; | |
1090 | default: | |
1091 | return NULL; | |
1092 | } | |
1ec1e82f SH |
1093 | |
1094 | param = BD_DONE | BD_EXTD | BD_CONT; | |
1095 | ||
341b9419 | 1096 | if (i + 1 == sg_len) { |
1ec1e82f | 1097 | param |= BD_INTR; |
341b9419 SG |
1098 | param |= BD_LAST; |
1099 | param &= ~BD_CONT; | |
1ec1e82f SH |
1100 | } |
1101 | ||
c3cc74b2 OJ |
1102 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1103 | i, count, (u64)sg->dma_address, | |
1ec1e82f SH |
1104 | param & BD_WRAP ? "wrap" : "", |
1105 | param & BD_INTR ? " intr" : ""); | |
1106 | ||
1107 | bd->mode.status = param; | |
1108 | } | |
1109 | ||
1110 | sdmac->num_bd = sg_len; | |
1111 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1112 | ||
1113 | return &sdmac->desc; | |
1114 | err_out: | |
4b2ce9dd | 1115 | sdmac->status = DMA_ERROR; |
1ec1e82f SH |
1116 | return NULL; |
1117 | } | |
1118 | ||
1119 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( | |
1120 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f | 1121 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 1122 | unsigned long flags, void *context) |
1ec1e82f SH |
1123 | { |
1124 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1125 | struct sdma_engine *sdma = sdmac->sdma; | |
1126 | int num_periods = buf_len / period_len; | |
23889c63 | 1127 | int channel = sdmac->channel; |
1ec1e82f SH |
1128 | int ret, i = 0, buf = 0; |
1129 | ||
1130 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); | |
1131 | ||
1132 | if (sdmac->status == DMA_IN_PROGRESS) | |
1133 | return NULL; | |
1134 | ||
1135 | sdmac->status = DMA_IN_PROGRESS; | |
1136 | ||
8e2e27c7 | 1137 | sdmac->buf_tail = 0; |
d1a792f3 | 1138 | sdmac->period_len = period_len; |
8e2e27c7 | 1139 | |
1ec1e82f SH |
1140 | sdmac->flags |= IMX_DMA_SG_LOOP; |
1141 | sdmac->direction = direction; | |
1142 | ret = sdma_load_context(sdmac); | |
1143 | if (ret) | |
1144 | goto err_out; | |
1145 | ||
1146 | if (num_periods > NUM_BD) { | |
1147 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1148 | channel, num_periods, NUM_BD); | |
1149 | goto err_out; | |
1150 | } | |
1151 | ||
1152 | if (period_len > 0xffff) { | |
1153 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", | |
1154 | channel, period_len, 0xffff); | |
1155 | goto err_out; | |
1156 | } | |
1157 | ||
1158 | while (buf < buf_len) { | |
1159 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1160 | int param; | |
1161 | ||
1162 | bd->buffer_addr = dma_addr; | |
1163 | ||
1164 | bd->mode.count = period_len; | |
1165 | ||
1166 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1167 | goto err_out; | |
1168 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1169 | bd->mode.command = 0; | |
1170 | else | |
1171 | bd->mode.command = sdmac->word_size; | |
1172 | ||
1173 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; | |
1174 | if (i + 1 == num_periods) | |
1175 | param |= BD_WRAP; | |
1176 | ||
c3cc74b2 OJ |
1177 | dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", |
1178 | i, period_len, (u64)dma_addr, | |
1ec1e82f SH |
1179 | param & BD_WRAP ? "wrap" : "", |
1180 | param & BD_INTR ? " intr" : ""); | |
1181 | ||
1182 | bd->mode.status = param; | |
1183 | ||
1184 | dma_addr += period_len; | |
1185 | buf += period_len; | |
1186 | ||
1187 | i++; | |
1188 | } | |
1189 | ||
1190 | sdmac->num_bd = num_periods; | |
1191 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1192 | ||
1193 | return &sdmac->desc; | |
1194 | err_out: | |
1195 | sdmac->status = DMA_ERROR; | |
1196 | return NULL; | |
1197 | } | |
1198 | ||
1199 | static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1200 | unsigned long arg) | |
1201 | { | |
1202 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1203 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
1204 | ||
1205 | switch (cmd) { | |
1206 | case DMA_TERMINATE_ALL: | |
1207 | sdma_disable_channel(sdmac); | |
1208 | return 0; | |
1209 | case DMA_SLAVE_CONFIG: | |
db8196df | 1210 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1ec1e82f | 1211 | sdmac->per_address = dmaengine_cfg->src_addr; |
94ac27a5 PR |
1212 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * |
1213 | dmaengine_cfg->src_addr_width; | |
1ec1e82f SH |
1214 | sdmac->word_size = dmaengine_cfg->src_addr_width; |
1215 | } else { | |
1216 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
94ac27a5 PR |
1217 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * |
1218 | dmaengine_cfg->dst_addr_width; | |
1ec1e82f SH |
1219 | sdmac->word_size = dmaengine_cfg->dst_addr_width; |
1220 | } | |
e6966433 | 1221 | sdmac->direction = dmaengine_cfg->direction; |
1ec1e82f SH |
1222 | return sdma_config_channel(sdmac); |
1223 | default: | |
1224 | return -ENOSYS; | |
1225 | } | |
1226 | ||
1227 | return -EINVAL; | |
1228 | } | |
1229 | ||
1230 | static enum dma_status sdma_tx_status(struct dma_chan *chan, | |
e8e3a790 AS |
1231 | dma_cookie_t cookie, |
1232 | struct dma_tx_state *txstate) | |
1ec1e82f SH |
1233 | { |
1234 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
d1a792f3 RKAL |
1235 | u32 residue; |
1236 | ||
1237 | if (sdmac->flags & IMX_DMA_SG_LOOP) | |
1238 | residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len; | |
1239 | else | |
1240 | residue = sdmac->chn_count - sdmac->chn_real_count; | |
1ec1e82f | 1241 | |
e8e3a790 | 1242 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
d1a792f3 | 1243 | residue); |
1ec1e82f | 1244 | |
8a965911 | 1245 | return sdmac->status; |
1ec1e82f SH |
1246 | } |
1247 | ||
1248 | static void sdma_issue_pending(struct dma_chan *chan) | |
1249 | { | |
2b4f130e SH |
1250 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1251 | struct sdma_engine *sdma = sdmac->sdma; | |
1252 | ||
1253 | if (sdmac->status == DMA_IN_PROGRESS) | |
1254 | sdma_enable_channel(sdma, sdmac->channel); | |
1ec1e82f SH |
1255 | } |
1256 | ||
5b28aa31 | 1257 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
cd72b846 | 1258 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38 |
5b28aa31 SH |
1259 | |
1260 | static void sdma_add_scripts(struct sdma_engine *sdma, | |
1261 | const struct sdma_script_start_addrs *addr) | |
1262 | { | |
1263 | s32 *addr_arr = (u32 *)addr; | |
1264 | s32 *saddr_arr = (u32 *)sdma->script_addrs; | |
1265 | int i; | |
1266 | ||
70dabaed NC |
1267 | /* use the default firmware in ROM if missing external firmware */ |
1268 | if (!sdma->script_number) | |
1269 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1270 | ||
cd72b846 | 1271 | for (i = 0; i < sdma->script_number; i++) |
5b28aa31 SH |
1272 | if (addr_arr[i] > 0) |
1273 | saddr_arr[i] = addr_arr[i]; | |
1274 | } | |
1275 | ||
7b4b88e0 | 1276 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
5b28aa31 | 1277 | { |
7b4b88e0 | 1278 | struct sdma_engine *sdma = context; |
5b28aa31 | 1279 | const struct sdma_firmware_header *header; |
5b28aa31 SH |
1280 | const struct sdma_script_start_addrs *addr; |
1281 | unsigned short *ram_code; | |
1282 | ||
7b4b88e0 SH |
1283 | if (!fw) { |
1284 | dev_err(sdma->dev, "firmware not found\n"); | |
1285 | return; | |
1286 | } | |
5b28aa31 SH |
1287 | |
1288 | if (fw->size < sizeof(*header)) | |
1289 | goto err_firmware; | |
1290 | ||
1291 | header = (struct sdma_firmware_header *)fw->data; | |
1292 | ||
1293 | if (header->magic != SDMA_FIRMWARE_MAGIC) | |
1294 | goto err_firmware; | |
1295 | if (header->ram_code_start + header->ram_code_size > fw->size) | |
1296 | goto err_firmware; | |
cd72b846 NC |
1297 | switch (header->version_major) { |
1298 | case 1: | |
1299 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; | |
1300 | break; | |
1301 | case 2: | |
1302 | sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; | |
1303 | break; | |
1304 | default: | |
1305 | dev_err(sdma->dev, "unknown firmware version\n"); | |
1306 | goto err_firmware; | |
1307 | } | |
5b28aa31 SH |
1308 | |
1309 | addr = (void *)header + header->script_addrs_start; | |
1310 | ram_code = (void *)header + header->ram_code_start; | |
1311 | ||
7560e3f3 SH |
1312 | clk_enable(sdma->clk_ipg); |
1313 | clk_enable(sdma->clk_ahb); | |
5b28aa31 SH |
1314 | /* download the RAM image for SDMA */ |
1315 | sdma_load_script(sdma, ram_code, | |
1316 | header->ram_code_size, | |
6866fd3b | 1317 | addr->ram_code_start_addr); |
7560e3f3 SH |
1318 | clk_disable(sdma->clk_ipg); |
1319 | clk_disable(sdma->clk_ahb); | |
5b28aa31 SH |
1320 | |
1321 | sdma_add_scripts(sdma, addr); | |
1322 | ||
1323 | dev_info(sdma->dev, "loaded firmware %d.%d\n", | |
1324 | header->version_major, | |
1325 | header->version_minor); | |
1326 | ||
1327 | err_firmware: | |
1328 | release_firmware(fw); | |
7b4b88e0 SH |
1329 | } |
1330 | ||
1331 | static int __init sdma_get_firmware(struct sdma_engine *sdma, | |
1332 | const char *fw_name) | |
1333 | { | |
1334 | int ret; | |
1335 | ||
1336 | ret = request_firmware_nowait(THIS_MODULE, | |
1337 | FW_ACTION_HOTPLUG, fw_name, sdma->dev, | |
1338 | GFP_KERNEL, sdma, sdma_load_firmware); | |
5b28aa31 SH |
1339 | |
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | static int __init sdma_init(struct sdma_engine *sdma) | |
1ec1e82f SH |
1344 | { |
1345 | int i, ret; | |
1346 | dma_addr_t ccb_phys; | |
1347 | ||
7560e3f3 SH |
1348 | clk_enable(sdma->clk_ipg); |
1349 | clk_enable(sdma->clk_ahb); | |
1ec1e82f SH |
1350 | |
1351 | /* Be sure SDMA has not started yet */ | |
c4b56857 | 1352 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f SH |
1353 | |
1354 | sdma->channel_control = dma_alloc_coherent(NULL, | |
1355 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + | |
1356 | sizeof(struct sdma_context_data), | |
1357 | &ccb_phys, GFP_KERNEL); | |
1358 | ||
1359 | if (!sdma->channel_control) { | |
1360 | ret = -ENOMEM; | |
1361 | goto err_dma_alloc; | |
1362 | } | |
1363 | ||
1364 | sdma->context = (void *)sdma->channel_control + | |
1365 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1366 | sdma->context_phys = ccb_phys + | |
1367 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1368 | ||
1369 | /* Zero-out the CCB structures array just allocated */ | |
1370 | memset(sdma->channel_control, 0, | |
1371 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); | |
1372 | ||
1373 | /* disable all channels */ | |
17bba72f | 1374 | for (i = 0; i < sdma->drvdata->num_events; i++) |
c4b56857 | 1375 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
1ec1e82f SH |
1376 | |
1377 | /* All channels have priority 0 */ | |
1378 | for (i = 0; i < MAX_DMA_CHANNELS; i++) | |
c4b56857 | 1379 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
1ec1e82f SH |
1380 | |
1381 | ret = sdma_request_channel(&sdma->channel[0]); | |
1382 | if (ret) | |
1383 | goto err_dma_alloc; | |
1384 | ||
1385 | sdma_config_ownership(&sdma->channel[0], false, true, false); | |
1386 | ||
1387 | /* Set Command Channel (Channel Zero) */ | |
c4b56857 | 1388 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
1ec1e82f SH |
1389 | |
1390 | /* Set bits of CONFIG register but with static context switching */ | |
1391 | /* FIXME: Check whether to set ACR bit depending on clock ratios */ | |
c4b56857 | 1392 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f | 1393 | |
c4b56857 | 1394 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 1395 | |
1ec1e82f | 1396 | /* Set bits of CONFIG register with given context switching mode */ |
c4b56857 | 1397 | writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f SH |
1398 | |
1399 | /* Initializes channel's priorities */ | |
1400 | sdma_set_channel_priority(&sdma->channel[0], 7); | |
1401 | ||
7560e3f3 SH |
1402 | clk_disable(sdma->clk_ipg); |
1403 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1404 | |
1405 | return 0; | |
1406 | ||
1407 | err_dma_alloc: | |
7560e3f3 SH |
1408 | clk_disable(sdma->clk_ipg); |
1409 | clk_disable(sdma->clk_ahb); | |
1ec1e82f SH |
1410 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); |
1411 | return ret; | |
1412 | } | |
1413 | ||
9479e17c SG |
1414 | static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) |
1415 | { | |
1416 | struct imx_dma_data *data = fn_param; | |
1417 | ||
1418 | if (!imx_dma_is_general_purpose(chan)) | |
1419 | return false; | |
1420 | ||
1421 | chan->private = data; | |
1422 | ||
1423 | return true; | |
1424 | } | |
1425 | ||
1426 | static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec, | |
1427 | struct of_dma *ofdma) | |
1428 | { | |
1429 | struct sdma_engine *sdma = ofdma->of_dma_data; | |
1430 | dma_cap_mask_t mask = sdma->dma_device.cap_mask; | |
1431 | struct imx_dma_data data; | |
1432 | ||
1433 | if (dma_spec->args_count != 3) | |
1434 | return NULL; | |
1435 | ||
1436 | data.dma_request = dma_spec->args[0]; | |
1437 | data.peripheral_type = dma_spec->args[1]; | |
1438 | data.priority = dma_spec->args[2]; | |
1439 | ||
1440 | return dma_request_channel(mask, sdma_filter_fn, &data); | |
1441 | } | |
1442 | ||
1ec1e82f SH |
1443 | static int __init sdma_probe(struct platform_device *pdev) |
1444 | { | |
580975d7 SG |
1445 | const struct of_device_id *of_id = |
1446 | of_match_device(sdma_dt_ids, &pdev->dev); | |
1447 | struct device_node *np = pdev->dev.of_node; | |
1448 | const char *fw_name; | |
1ec1e82f | 1449 | int ret; |
1ec1e82f | 1450 | int irq; |
1ec1e82f | 1451 | struct resource *iores; |
d4adcc01 | 1452 | struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); |
1ec1e82f | 1453 | int i; |
1ec1e82f | 1454 | struct sdma_engine *sdma; |
36e2f21a | 1455 | s32 *saddr_arr; |
17bba72f SH |
1456 | const struct sdma_driver_data *drvdata = NULL; |
1457 | ||
1458 | if (of_id) | |
1459 | drvdata = of_id->data; | |
1460 | else if (pdev->id_entry) | |
1461 | drvdata = (void *)pdev->id_entry->driver_data; | |
1462 | ||
1463 | if (!drvdata) { | |
1464 | dev_err(&pdev->dev, "unable to find driver data\n"); | |
1465 | return -EINVAL; | |
1466 | } | |
1ec1e82f | 1467 | |
42536b9f PR |
1468 | ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
1469 | if (ret) | |
1470 | return ret; | |
1471 | ||
1ec1e82f SH |
1472 | sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); |
1473 | if (!sdma) | |
1474 | return -ENOMEM; | |
1475 | ||
2ccaef05 | 1476 | spin_lock_init(&sdma->channel_0_lock); |
73eab978 | 1477 | |
1ec1e82f | 1478 | sdma->dev = &pdev->dev; |
17bba72f | 1479 | sdma->drvdata = drvdata; |
1ec1e82f SH |
1480 | |
1481 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1482 | irq = platform_get_irq(pdev, 0); | |
580975d7 | 1483 | if (!iores || irq < 0) { |
1ec1e82f SH |
1484 | ret = -EINVAL; |
1485 | goto err_irq; | |
1486 | } | |
1487 | ||
1488 | if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { | |
1489 | ret = -EBUSY; | |
1490 | goto err_request_region; | |
1491 | } | |
1492 | ||
7560e3f3 SH |
1493 | sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1494 | if (IS_ERR(sdma->clk_ipg)) { | |
1495 | ret = PTR_ERR(sdma->clk_ipg); | |
1ec1e82f SH |
1496 | goto err_clk; |
1497 | } | |
1498 | ||
7560e3f3 SH |
1499 | sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
1500 | if (IS_ERR(sdma->clk_ahb)) { | |
1501 | ret = PTR_ERR(sdma->clk_ahb); | |
1502 | goto err_clk; | |
1503 | } | |
1504 | ||
1505 | clk_prepare(sdma->clk_ipg); | |
1506 | clk_prepare(sdma->clk_ahb); | |
1507 | ||
1ec1e82f SH |
1508 | sdma->regs = ioremap(iores->start, resource_size(iores)); |
1509 | if (!sdma->regs) { | |
1510 | ret = -ENOMEM; | |
1511 | goto err_ioremap; | |
1512 | } | |
1513 | ||
1514 | ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); | |
1515 | if (ret) | |
1516 | goto err_request_irq; | |
1517 | ||
5b28aa31 | 1518 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
1c1d9547 AL |
1519 | if (!sdma->script_addrs) { |
1520 | ret = -ENOMEM; | |
5b28aa31 | 1521 | goto err_alloc; |
1c1d9547 | 1522 | } |
1ec1e82f | 1523 | |
36e2f21a SH |
1524 | /* initially no scripts available */ |
1525 | saddr_arr = (s32 *)sdma->script_addrs; | |
1526 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) | |
1527 | saddr_arr[i] = -EINVAL; | |
1528 | ||
7214a8b1 SH |
1529 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
1530 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); | |
1531 | ||
1ec1e82f SH |
1532 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
1533 | /* Initialize channel parameters */ | |
1534 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1535 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1536 | ||
1537 | sdmac->sdma = sdma; | |
1538 | spin_lock_init(&sdmac->lock); | |
1539 | ||
1ec1e82f | 1540 | sdmac->chan.device = &sdma->dma_device; |
8ac69546 | 1541 | dma_cookie_init(&sdmac->chan); |
1ec1e82f SH |
1542 | sdmac->channel = i; |
1543 | ||
abd9ccc8 HS |
1544 | tasklet_init(&sdmac->tasklet, sdma_tasklet, |
1545 | (unsigned long) sdmac); | |
23889c63 SH |
1546 | /* |
1547 | * Add the channel to the DMAC list. Do not add channel 0 though | |
1548 | * because we need it internally in the SDMA driver. This also means | |
1549 | * that channel 0 in dmaengine counting matches sdma channel 1. | |
1550 | */ | |
1551 | if (i) | |
1552 | list_add_tail(&sdmac->chan.device_node, | |
1553 | &sdma->dma_device.channels); | |
1ec1e82f SH |
1554 | } |
1555 | ||
5b28aa31 | 1556 | ret = sdma_init(sdma); |
1ec1e82f SH |
1557 | if (ret) |
1558 | goto err_init; | |
1559 | ||
dcfec3c0 SH |
1560 | if (sdma->drvdata->script_addrs) |
1561 | sdma_add_scripts(sdma, sdma->drvdata->script_addrs); | |
580975d7 | 1562 | if (pdata && pdata->script_addrs) |
5b28aa31 SH |
1563 | sdma_add_scripts(sdma, pdata->script_addrs); |
1564 | ||
580975d7 | 1565 | if (pdata) { |
6d0d7e2d FE |
1566 | ret = sdma_get_firmware(sdma, pdata->fw_name); |
1567 | if (ret) | |
ad1122e5 | 1568 | dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); |
580975d7 SG |
1569 | } else { |
1570 | /* | |
1571 | * Because that device tree does not encode ROM script address, | |
1572 | * the RAM script in firmware is mandatory for device tree | |
1573 | * probe, otherwise it fails. | |
1574 | */ | |
1575 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", | |
1576 | &fw_name); | |
6602b0dd | 1577 | if (ret) |
ad1122e5 | 1578 | dev_warn(&pdev->dev, "failed to get firmware name\n"); |
6602b0dd FE |
1579 | else { |
1580 | ret = sdma_get_firmware(sdma, fw_name); | |
1581 | if (ret) | |
ad1122e5 | 1582 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); |
580975d7 SG |
1583 | } |
1584 | } | |
5b28aa31 | 1585 | |
1ec1e82f SH |
1586 | sdma->dma_device.dev = &pdev->dev; |
1587 | ||
1588 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; | |
1589 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; | |
1590 | sdma->dma_device.device_tx_status = sdma_tx_status; | |
1591 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; | |
1592 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; | |
1593 | sdma->dma_device.device_control = sdma_control; | |
1594 | sdma->dma_device.device_issue_pending = sdma_issue_pending; | |
b9b3f82f SH |
1595 | sdma->dma_device.dev->dma_parms = &sdma->dma_parms; |
1596 | dma_set_max_seg_size(sdma->dma_device.dev, 65535); | |
1ec1e82f SH |
1597 | |
1598 | ret = dma_async_device_register(&sdma->dma_device); | |
1599 | if (ret) { | |
1600 | dev_err(&pdev->dev, "unable to register\n"); | |
1601 | goto err_init; | |
1602 | } | |
1603 | ||
9479e17c SG |
1604 | if (np) { |
1605 | ret = of_dma_controller_register(np, sdma_xlate, sdma); | |
1606 | if (ret) { | |
1607 | dev_err(&pdev->dev, "failed to register controller\n"); | |
1608 | goto err_register; | |
1609 | } | |
1610 | } | |
1611 | ||
5b28aa31 | 1612 | dev_info(sdma->dev, "initialized\n"); |
1ec1e82f SH |
1613 | |
1614 | return 0; | |
1615 | ||
9479e17c SG |
1616 | err_register: |
1617 | dma_async_device_unregister(&sdma->dma_device); | |
1ec1e82f SH |
1618 | err_init: |
1619 | kfree(sdma->script_addrs); | |
5b28aa31 | 1620 | err_alloc: |
1ec1e82f SH |
1621 | free_irq(irq, sdma); |
1622 | err_request_irq: | |
1623 | iounmap(sdma->regs); | |
1624 | err_ioremap: | |
1ec1e82f SH |
1625 | err_clk: |
1626 | release_mem_region(iores->start, resource_size(iores)); | |
1627 | err_request_region: | |
1628 | err_irq: | |
1629 | kfree(sdma); | |
939fd4f0 | 1630 | return ret; |
1ec1e82f SH |
1631 | } |
1632 | ||
1d1bbd30 | 1633 | static int sdma_remove(struct platform_device *pdev) |
1ec1e82f SH |
1634 | { |
1635 | return -EBUSY; | |
1636 | } | |
1637 | ||
1638 | static struct platform_driver sdma_driver = { | |
1639 | .driver = { | |
1640 | .name = "imx-sdma", | |
580975d7 | 1641 | .of_match_table = sdma_dt_ids, |
1ec1e82f | 1642 | }, |
62550cd7 | 1643 | .id_table = sdma_devtypes, |
1d1bbd30 | 1644 | .remove = sdma_remove, |
1ec1e82f SH |
1645 | }; |
1646 | ||
1647 | static int __init sdma_module_init(void) | |
1648 | { | |
1649 | return platform_driver_probe(&sdma_driver, sdma_probe); | |
1650 | } | |
c989a7fc | 1651 | module_init(sdma_module_init); |
1ec1e82f SH |
1652 | |
1653 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1654 | MODULE_DESCRIPTION("i.MX SDMA driver"); | |
1655 | MODULE_LICENSE("GPL"); |