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1ec1e82f SH |
1 | /* |
2 | * drivers/dma/imx-sdma.c | |
3 | * | |
4 | * This file contains a driver for the Freescale Smart DMA engine | |
5 | * | |
6 | * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
7 | * | |
8 | * Based on code from Freescale: | |
9 | * | |
10 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
11 | * | |
12 | * The code contained herein is licensed under the GNU General Public | |
13 | * License. You may obtain a copy of the GNU General Public License | |
14 | * Version 2 or later at the following locations: | |
15 | * | |
16 | * http://www.opensource.org/licenses/gpl-license.html | |
17 | * http://www.gnu.org/copyleft/gpl.html | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
f8de8f4c | 21 | #include <linux/module.h> |
1ec1e82f | 22 | #include <linux/types.h> |
0bbc1413 | 23 | #include <linux/bitops.h> |
1ec1e82f SH |
24 | #include <linux/mm.h> |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/wait.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/semaphore.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/firmware.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/dmaengine.h> | |
580975d7 SG |
37 | #include <linux/of.h> |
38 | #include <linux/of_device.h> | |
1ec1e82f SH |
39 | |
40 | #include <asm/irq.h> | |
41 | #include <mach/sdma.h> | |
42 | #include <mach/dma.h> | |
43 | #include <mach/hardware.h> | |
44 | ||
d2ebfb33 RKAL |
45 | #include "dmaengine.h" |
46 | ||
1ec1e82f SH |
47 | /* SDMA registers */ |
48 | #define SDMA_H_C0PTR 0x000 | |
49 | #define SDMA_H_INTR 0x004 | |
50 | #define SDMA_H_STATSTOP 0x008 | |
51 | #define SDMA_H_START 0x00c | |
52 | #define SDMA_H_EVTOVR 0x010 | |
53 | #define SDMA_H_DSPOVR 0x014 | |
54 | #define SDMA_H_HOSTOVR 0x018 | |
55 | #define SDMA_H_EVTPEND 0x01c | |
56 | #define SDMA_H_DSPENBL 0x020 | |
57 | #define SDMA_H_RESET 0x024 | |
58 | #define SDMA_H_EVTERR 0x028 | |
59 | #define SDMA_H_INTRMSK 0x02c | |
60 | #define SDMA_H_PSW 0x030 | |
61 | #define SDMA_H_EVTERRDBG 0x034 | |
62 | #define SDMA_H_CONFIG 0x038 | |
63 | #define SDMA_ONCE_ENB 0x040 | |
64 | #define SDMA_ONCE_DATA 0x044 | |
65 | #define SDMA_ONCE_INSTR 0x048 | |
66 | #define SDMA_ONCE_STAT 0x04c | |
67 | #define SDMA_ONCE_CMD 0x050 | |
68 | #define SDMA_EVT_MIRROR 0x054 | |
69 | #define SDMA_ILLINSTADDR 0x058 | |
70 | #define SDMA_CHN0ADDR 0x05c | |
71 | #define SDMA_ONCE_RTB 0x060 | |
72 | #define SDMA_XTRIG_CONF1 0x070 | |
73 | #define SDMA_XTRIG_CONF2 0x074 | |
62550cd7 SG |
74 | #define SDMA_CHNENBL0_IMX35 0x200 |
75 | #define SDMA_CHNENBL0_IMX31 0x080 | |
1ec1e82f SH |
76 | #define SDMA_CHNPRI_0 0x100 |
77 | ||
78 | /* | |
79 | * Buffer descriptor status values. | |
80 | */ | |
81 | #define BD_DONE 0x01 | |
82 | #define BD_WRAP 0x02 | |
83 | #define BD_CONT 0x04 | |
84 | #define BD_INTR 0x08 | |
85 | #define BD_RROR 0x10 | |
86 | #define BD_LAST 0x20 | |
87 | #define BD_EXTD 0x80 | |
88 | ||
89 | /* | |
90 | * Data Node descriptor status values. | |
91 | */ | |
92 | #define DND_END_OF_FRAME 0x80 | |
93 | #define DND_END_OF_XFER 0x40 | |
94 | #define DND_DONE 0x20 | |
95 | #define DND_UNUSED 0x01 | |
96 | ||
97 | /* | |
98 | * IPCV2 descriptor status values. | |
99 | */ | |
100 | #define BD_IPCV2_END_OF_FRAME 0x40 | |
101 | ||
102 | #define IPCV2_MAX_NODES 50 | |
103 | /* | |
104 | * Error bit set in the CCB status field by the SDMA, | |
105 | * in setbd routine, in case of a transfer error | |
106 | */ | |
107 | #define DATA_ERROR 0x10000000 | |
108 | ||
109 | /* | |
110 | * Buffer descriptor commands. | |
111 | */ | |
112 | #define C0_ADDR 0x01 | |
113 | #define C0_LOAD 0x02 | |
114 | #define C0_DUMP 0x03 | |
115 | #define C0_SETCTX 0x07 | |
116 | #define C0_GETCTX 0x03 | |
117 | #define C0_SETDM 0x01 | |
118 | #define C0_SETPM 0x04 | |
119 | #define C0_GETDM 0x02 | |
120 | #define C0_GETPM 0x08 | |
121 | /* | |
122 | * Change endianness indicator in the BD command field | |
123 | */ | |
124 | #define CHANGE_ENDIANNESS 0x80 | |
125 | ||
126 | /* | |
127 | * Mode/Count of data node descriptors - IPCv2 | |
128 | */ | |
129 | struct sdma_mode_count { | |
130 | u32 count : 16; /* size of the buffer pointed by this BD */ | |
131 | u32 status : 8; /* E,R,I,C,W,D status bits stored here */ | |
132 | u32 command : 8; /* command mostlky used for channel 0 */ | |
133 | }; | |
134 | ||
135 | /* | |
136 | * Buffer descriptor | |
137 | */ | |
138 | struct sdma_buffer_descriptor { | |
139 | struct sdma_mode_count mode; | |
140 | u32 buffer_addr; /* address of the buffer described */ | |
141 | u32 ext_buffer_addr; /* extended buffer address */ | |
142 | } __attribute__ ((packed)); | |
143 | ||
144 | /** | |
145 | * struct sdma_channel_control - Channel control Block | |
146 | * | |
147 | * @current_bd_ptr current buffer descriptor processed | |
148 | * @base_bd_ptr first element of buffer descriptor array | |
149 | * @unused padding. The SDMA engine expects an array of 128 byte | |
150 | * control blocks | |
151 | */ | |
152 | struct sdma_channel_control { | |
153 | u32 current_bd_ptr; | |
154 | u32 base_bd_ptr; | |
155 | u32 unused[2]; | |
156 | } __attribute__ ((packed)); | |
157 | ||
158 | /** | |
159 | * struct sdma_state_registers - SDMA context for a channel | |
160 | * | |
161 | * @pc: program counter | |
162 | * @t: test bit: status of arithmetic & test instruction | |
163 | * @rpc: return program counter | |
164 | * @sf: source fault while loading data | |
165 | * @spc: loop start program counter | |
166 | * @df: destination fault while storing data | |
167 | * @epc: loop end program counter | |
168 | * @lm: loop mode | |
169 | */ | |
170 | struct sdma_state_registers { | |
171 | u32 pc :14; | |
172 | u32 unused1: 1; | |
173 | u32 t : 1; | |
174 | u32 rpc :14; | |
175 | u32 unused0: 1; | |
176 | u32 sf : 1; | |
177 | u32 spc :14; | |
178 | u32 unused2: 1; | |
179 | u32 df : 1; | |
180 | u32 epc :14; | |
181 | u32 lm : 2; | |
182 | } __attribute__ ((packed)); | |
183 | ||
184 | /** | |
185 | * struct sdma_context_data - sdma context specific to a channel | |
186 | * | |
187 | * @channel_state: channel state bits | |
188 | * @gReg: general registers | |
189 | * @mda: burst dma destination address register | |
190 | * @msa: burst dma source address register | |
191 | * @ms: burst dma status register | |
192 | * @md: burst dma data register | |
193 | * @pda: peripheral dma destination address register | |
194 | * @psa: peripheral dma source address register | |
195 | * @ps: peripheral dma status register | |
196 | * @pd: peripheral dma data register | |
197 | * @ca: CRC polynomial register | |
198 | * @cs: CRC accumulator register | |
199 | * @dda: dedicated core destination address register | |
200 | * @dsa: dedicated core source address register | |
201 | * @ds: dedicated core status register | |
202 | * @dd: dedicated core data register | |
203 | */ | |
204 | struct sdma_context_data { | |
205 | struct sdma_state_registers channel_state; | |
206 | u32 gReg[8]; | |
207 | u32 mda; | |
208 | u32 msa; | |
209 | u32 ms; | |
210 | u32 md; | |
211 | u32 pda; | |
212 | u32 psa; | |
213 | u32 ps; | |
214 | u32 pd; | |
215 | u32 ca; | |
216 | u32 cs; | |
217 | u32 dda; | |
218 | u32 dsa; | |
219 | u32 ds; | |
220 | u32 dd; | |
221 | u32 scratch0; | |
222 | u32 scratch1; | |
223 | u32 scratch2; | |
224 | u32 scratch3; | |
225 | u32 scratch4; | |
226 | u32 scratch5; | |
227 | u32 scratch6; | |
228 | u32 scratch7; | |
229 | } __attribute__ ((packed)); | |
230 | ||
231 | #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor)) | |
232 | ||
233 | struct sdma_engine; | |
234 | ||
235 | /** | |
236 | * struct sdma_channel - housekeeping for a SDMA channel | |
237 | * | |
238 | * @sdma pointer to the SDMA engine for this channel | |
23889c63 | 239 | * @channel the channel number, matches dmaengine chan_id + 1 |
1ec1e82f SH |
240 | * @direction transfer type. Needed for setting SDMA script |
241 | * @peripheral_type Peripheral type. Needed for setting SDMA script | |
242 | * @event_id0 aka dma request line | |
243 | * @event_id1 for channels that use 2 events | |
244 | * @word_size peripheral access size | |
245 | * @buf_tail ID of the buffer that was processed | |
246 | * @done channel completion | |
247 | * @num_bd max NUM_BD. number of descriptors currently handling | |
248 | */ | |
249 | struct sdma_channel { | |
250 | struct sdma_engine *sdma; | |
251 | unsigned int channel; | |
db8196df | 252 | enum dma_transfer_direction direction; |
1ec1e82f SH |
253 | enum sdma_peripheral_type peripheral_type; |
254 | unsigned int event_id0; | |
255 | unsigned int event_id1; | |
256 | enum dma_slave_buswidth word_size; | |
257 | unsigned int buf_tail; | |
258 | struct completion done; | |
259 | unsigned int num_bd; | |
260 | struct sdma_buffer_descriptor *bd; | |
261 | dma_addr_t bd_phys; | |
262 | unsigned int pc_from_device, pc_to_device; | |
263 | unsigned long flags; | |
264 | dma_addr_t per_address; | |
0bbc1413 RZ |
265 | unsigned long event_mask[2]; |
266 | unsigned long watermark_level; | |
1ec1e82f SH |
267 | u32 shp_addr, per_addr; |
268 | struct dma_chan chan; | |
269 | spinlock_t lock; | |
270 | struct dma_async_tx_descriptor desc; | |
1ec1e82f | 271 | enum dma_status status; |
ab59a510 HS |
272 | unsigned int chn_count; |
273 | unsigned int chn_real_count; | |
abd9ccc8 | 274 | struct tasklet_struct tasklet; |
1ec1e82f SH |
275 | }; |
276 | ||
0bbc1413 | 277 | #define IMX_DMA_SG_LOOP BIT(0) |
1ec1e82f SH |
278 | |
279 | #define MAX_DMA_CHANNELS 32 | |
280 | #define MXC_SDMA_DEFAULT_PRIORITY 1 | |
281 | #define MXC_SDMA_MIN_PRIORITY 1 | |
282 | #define MXC_SDMA_MAX_PRIORITY 7 | |
283 | ||
1ec1e82f SH |
284 | #define SDMA_FIRMWARE_MAGIC 0x414d4453 |
285 | ||
286 | /** | |
287 | * struct sdma_firmware_header - Layout of the firmware image | |
288 | * | |
289 | * @magic "SDMA" | |
290 | * @version_major increased whenever layout of struct sdma_script_start_addrs | |
291 | * changes. | |
292 | * @version_minor firmware minor version (for binary compatible changes) | |
293 | * @script_addrs_start offset of struct sdma_script_start_addrs in this image | |
294 | * @num_script_addrs Number of script addresses in this image | |
295 | * @ram_code_start offset of SDMA ram image in this firmware image | |
296 | * @ram_code_size size of SDMA ram image | |
297 | * @script_addrs Stores the start address of the SDMA scripts | |
298 | * (in SDMA memory space) | |
299 | */ | |
300 | struct sdma_firmware_header { | |
301 | u32 magic; | |
302 | u32 version_major; | |
303 | u32 version_minor; | |
304 | u32 script_addrs_start; | |
305 | u32 num_script_addrs; | |
306 | u32 ram_code_start; | |
307 | u32 ram_code_size; | |
308 | }; | |
309 | ||
62550cd7 SG |
310 | enum sdma_devtype { |
311 | IMX31_SDMA, /* runs on i.mx31 */ | |
312 | IMX35_SDMA, /* runs on i.mx35 and later */ | |
313 | }; | |
314 | ||
1ec1e82f SH |
315 | struct sdma_engine { |
316 | struct device *dev; | |
b9b3f82f | 317 | struct device_dma_parameters dma_parms; |
1ec1e82f SH |
318 | struct sdma_channel channel[MAX_DMA_CHANNELS]; |
319 | struct sdma_channel_control *channel_control; | |
320 | void __iomem *regs; | |
62550cd7 | 321 | enum sdma_devtype devtype; |
1ec1e82f SH |
322 | unsigned int num_events; |
323 | struct sdma_context_data *context; | |
324 | dma_addr_t context_phys; | |
325 | struct dma_device dma_device; | |
326 | struct clk *clk; | |
73eab978 | 327 | struct mutex channel_0_lock; |
1ec1e82f SH |
328 | struct sdma_script_start_addrs *script_addrs; |
329 | }; | |
330 | ||
62550cd7 SG |
331 | static struct platform_device_id sdma_devtypes[] = { |
332 | { | |
333 | .name = "imx31-sdma", | |
334 | .driver_data = IMX31_SDMA, | |
335 | }, { | |
336 | .name = "imx35-sdma", | |
337 | .driver_data = IMX35_SDMA, | |
338 | }, { | |
339 | /* sentinel */ | |
340 | } | |
341 | }; | |
342 | MODULE_DEVICE_TABLE(platform, sdma_devtypes); | |
343 | ||
580975d7 SG |
344 | static const struct of_device_id sdma_dt_ids[] = { |
345 | { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], }, | |
346 | { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], }, | |
347 | { /* sentinel */ } | |
348 | }; | |
349 | MODULE_DEVICE_TABLE(of, sdma_dt_ids); | |
350 | ||
0bbc1413 RZ |
351 | #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */ |
352 | #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */ | |
353 | #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */ | |
1ec1e82f SH |
354 | #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/ |
355 | ||
356 | static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) | |
357 | { | |
62550cd7 SG |
358 | u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 : |
359 | SDMA_CHNENBL0_IMX35); | |
1ec1e82f SH |
360 | return chnenbl0 + event * 4; |
361 | } | |
362 | ||
363 | static int sdma_config_ownership(struct sdma_channel *sdmac, | |
364 | bool event_override, bool mcu_override, bool dsp_override) | |
365 | { | |
366 | struct sdma_engine *sdma = sdmac->sdma; | |
367 | int channel = sdmac->channel; | |
0bbc1413 | 368 | unsigned long evt, mcu, dsp; |
1ec1e82f SH |
369 | |
370 | if (event_override && mcu_override && dsp_override) | |
371 | return -EINVAL; | |
372 | ||
c4b56857 RZ |
373 | evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); |
374 | mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); | |
375 | dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
376 | |
377 | if (dsp_override) | |
0bbc1413 | 378 | __clear_bit(channel, &dsp); |
1ec1e82f | 379 | else |
0bbc1413 | 380 | __set_bit(channel, &dsp); |
1ec1e82f SH |
381 | |
382 | if (event_override) | |
0bbc1413 | 383 | __clear_bit(channel, &evt); |
1ec1e82f | 384 | else |
0bbc1413 | 385 | __set_bit(channel, &evt); |
1ec1e82f SH |
386 | |
387 | if (mcu_override) | |
0bbc1413 | 388 | __clear_bit(channel, &mcu); |
1ec1e82f | 389 | else |
0bbc1413 | 390 | __set_bit(channel, &mcu); |
1ec1e82f | 391 | |
c4b56857 RZ |
392 | writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); |
393 | writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); | |
394 | writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); | |
1ec1e82f SH |
395 | |
396 | return 0; | |
397 | } | |
398 | ||
b9a59166 RZ |
399 | static void sdma_enable_channel(struct sdma_engine *sdma, int channel) |
400 | { | |
0bbc1413 | 401 | writel(BIT(channel), sdma->regs + SDMA_H_START); |
b9a59166 RZ |
402 | } |
403 | ||
1ec1e82f SH |
404 | /* |
405 | * sdma_run_channel - run a channel and wait till it's done | |
406 | */ | |
407 | static int sdma_run_channel(struct sdma_channel *sdmac) | |
408 | { | |
409 | struct sdma_engine *sdma = sdmac->sdma; | |
410 | int channel = sdmac->channel; | |
411 | int ret; | |
412 | ||
413 | init_completion(&sdmac->done); | |
414 | ||
b9a59166 | 415 | sdma_enable_channel(sdma, channel); |
1ec1e82f SH |
416 | |
417 | ret = wait_for_completion_timeout(&sdmac->done, HZ); | |
418 | ||
419 | return ret ? 0 : -ETIMEDOUT; | |
420 | } | |
421 | ||
422 | static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, | |
423 | u32 address) | |
424 | { | |
425 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
426 | void *buf_virt; | |
427 | dma_addr_t buf_phys; | |
428 | int ret; | |
429 | ||
73eab978 SH |
430 | mutex_lock(&sdma->channel_0_lock); |
431 | ||
1ec1e82f SH |
432 | buf_virt = dma_alloc_coherent(NULL, |
433 | size, | |
434 | &buf_phys, GFP_KERNEL); | |
73eab978 SH |
435 | if (!buf_virt) { |
436 | ret = -ENOMEM; | |
437 | goto err_out; | |
438 | } | |
1ec1e82f SH |
439 | |
440 | bd0->mode.command = C0_SETPM; | |
441 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
442 | bd0->mode.count = size / 2; | |
443 | bd0->buffer_addr = buf_phys; | |
444 | bd0->ext_buffer_addr = address; | |
445 | ||
446 | memcpy(buf_virt, buf, size); | |
447 | ||
448 | ret = sdma_run_channel(&sdma->channel[0]); | |
449 | ||
450 | dma_free_coherent(NULL, size, buf_virt, buf_phys); | |
451 | ||
73eab978 SH |
452 | err_out: |
453 | mutex_unlock(&sdma->channel_0_lock); | |
454 | ||
1ec1e82f SH |
455 | return ret; |
456 | } | |
457 | ||
458 | static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) | |
459 | { | |
460 | struct sdma_engine *sdma = sdmac->sdma; | |
461 | int channel = sdmac->channel; | |
0bbc1413 | 462 | unsigned long val; |
1ec1e82f SH |
463 | u32 chnenbl = chnenbl_ofs(sdma, event); |
464 | ||
c4b56857 | 465 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 466 | __set_bit(channel, &val); |
c4b56857 | 467 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
468 | } |
469 | ||
470 | static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) | |
471 | { | |
472 | struct sdma_engine *sdma = sdmac->sdma; | |
473 | int channel = sdmac->channel; | |
474 | u32 chnenbl = chnenbl_ofs(sdma, event); | |
0bbc1413 | 475 | unsigned long val; |
1ec1e82f | 476 | |
c4b56857 | 477 | val = readl_relaxed(sdma->regs + chnenbl); |
0bbc1413 | 478 | __clear_bit(channel, &val); |
c4b56857 | 479 | writel_relaxed(val, sdma->regs + chnenbl); |
1ec1e82f SH |
480 | } |
481 | ||
482 | static void sdma_handle_channel_loop(struct sdma_channel *sdmac) | |
483 | { | |
484 | struct sdma_buffer_descriptor *bd; | |
485 | ||
486 | /* | |
487 | * loop mode. Iterate over descriptors, re-setup them and | |
488 | * call callback function. | |
489 | */ | |
490 | while (1) { | |
491 | bd = &sdmac->bd[sdmac->buf_tail]; | |
492 | ||
493 | if (bd->mode.status & BD_DONE) | |
494 | break; | |
495 | ||
496 | if (bd->mode.status & BD_RROR) | |
497 | sdmac->status = DMA_ERROR; | |
498 | else | |
1e9cebb4 | 499 | sdmac->status = DMA_IN_PROGRESS; |
1ec1e82f SH |
500 | |
501 | bd->mode.status |= BD_DONE; | |
502 | sdmac->buf_tail++; | |
503 | sdmac->buf_tail %= sdmac->num_bd; | |
504 | ||
505 | if (sdmac->desc.callback) | |
506 | sdmac->desc.callback(sdmac->desc.callback_param); | |
507 | } | |
508 | } | |
509 | ||
510 | static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac) | |
511 | { | |
512 | struct sdma_buffer_descriptor *bd; | |
513 | int i, error = 0; | |
514 | ||
ab59a510 | 515 | sdmac->chn_real_count = 0; |
1ec1e82f SH |
516 | /* |
517 | * non loop mode. Iterate over all descriptors, collect | |
518 | * errors and call callback function | |
519 | */ | |
520 | for (i = 0; i < sdmac->num_bd; i++) { | |
521 | bd = &sdmac->bd[i]; | |
522 | ||
523 | if (bd->mode.status & (BD_DONE | BD_RROR)) | |
524 | error = -EIO; | |
ab59a510 | 525 | sdmac->chn_real_count += bd->mode.count; |
1ec1e82f SH |
526 | } |
527 | ||
528 | if (error) | |
529 | sdmac->status = DMA_ERROR; | |
530 | else | |
531 | sdmac->status = DMA_SUCCESS; | |
532 | ||
f7fbce07 | 533 | dma_cookie_complete(&sdmac->desc); |
1ec1e82f SH |
534 | if (sdmac->desc.callback) |
535 | sdmac->desc.callback(sdmac->desc.callback_param); | |
1ec1e82f SH |
536 | } |
537 | ||
abd9ccc8 | 538 | static void sdma_tasklet(unsigned long data) |
1ec1e82f | 539 | { |
abd9ccc8 HS |
540 | struct sdma_channel *sdmac = (struct sdma_channel *) data; |
541 | ||
1ec1e82f SH |
542 | complete(&sdmac->done); |
543 | ||
544 | /* not interested in channel 0 interrupts */ | |
545 | if (sdmac->channel == 0) | |
546 | return; | |
547 | ||
548 | if (sdmac->flags & IMX_DMA_SG_LOOP) | |
549 | sdma_handle_channel_loop(sdmac); | |
550 | else | |
551 | mxc_sdma_handle_channel_normal(sdmac); | |
552 | } | |
553 | ||
554 | static irqreturn_t sdma_int_handler(int irq, void *dev_id) | |
555 | { | |
556 | struct sdma_engine *sdma = dev_id; | |
0bbc1413 | 557 | unsigned long stat; |
1ec1e82f | 558 | |
c4b56857 RZ |
559 | stat = readl_relaxed(sdma->regs + SDMA_H_INTR); |
560 | writel_relaxed(stat, sdma->regs + SDMA_H_INTR); | |
1ec1e82f SH |
561 | |
562 | while (stat) { | |
563 | int channel = fls(stat) - 1; | |
564 | struct sdma_channel *sdmac = &sdma->channel[channel]; | |
565 | ||
abd9ccc8 | 566 | tasklet_schedule(&sdmac->tasklet); |
1ec1e82f | 567 | |
0bbc1413 | 568 | __clear_bit(channel, &stat); |
1ec1e82f SH |
569 | } |
570 | ||
571 | return IRQ_HANDLED; | |
572 | } | |
573 | ||
574 | /* | |
575 | * sets the pc of SDMA script according to the peripheral type | |
576 | */ | |
577 | static void sdma_get_pc(struct sdma_channel *sdmac, | |
578 | enum sdma_peripheral_type peripheral_type) | |
579 | { | |
580 | struct sdma_engine *sdma = sdmac->sdma; | |
581 | int per_2_emi = 0, emi_2_per = 0; | |
582 | /* | |
583 | * These are needed once we start to support transfers between | |
584 | * two peripherals or memory-to-memory transfers | |
585 | */ | |
586 | int per_2_per = 0, emi_2_emi = 0; | |
587 | ||
588 | sdmac->pc_from_device = 0; | |
589 | sdmac->pc_to_device = 0; | |
590 | ||
591 | switch (peripheral_type) { | |
592 | case IMX_DMATYPE_MEMORY: | |
593 | emi_2_emi = sdma->script_addrs->ap_2_ap_addr; | |
594 | break; | |
595 | case IMX_DMATYPE_DSP: | |
596 | emi_2_per = sdma->script_addrs->bp_2_ap_addr; | |
597 | per_2_emi = sdma->script_addrs->ap_2_bp_addr; | |
598 | break; | |
599 | case IMX_DMATYPE_FIRI: | |
600 | per_2_emi = sdma->script_addrs->firi_2_mcu_addr; | |
601 | emi_2_per = sdma->script_addrs->mcu_2_firi_addr; | |
602 | break; | |
603 | case IMX_DMATYPE_UART: | |
604 | per_2_emi = sdma->script_addrs->uart_2_mcu_addr; | |
605 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
606 | break; | |
607 | case IMX_DMATYPE_UART_SP: | |
608 | per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; | |
609 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
610 | break; | |
611 | case IMX_DMATYPE_ATA: | |
612 | per_2_emi = sdma->script_addrs->ata_2_mcu_addr; | |
613 | emi_2_per = sdma->script_addrs->mcu_2_ata_addr; | |
614 | break; | |
615 | case IMX_DMATYPE_CSPI: | |
616 | case IMX_DMATYPE_EXT: | |
617 | case IMX_DMATYPE_SSI: | |
618 | per_2_emi = sdma->script_addrs->app_2_mcu_addr; | |
619 | emi_2_per = sdma->script_addrs->mcu_2_app_addr; | |
620 | break; | |
621 | case IMX_DMATYPE_SSI_SP: | |
622 | case IMX_DMATYPE_MMC: | |
623 | case IMX_DMATYPE_SDHC: | |
624 | case IMX_DMATYPE_CSPI_SP: | |
625 | case IMX_DMATYPE_ESAI: | |
626 | case IMX_DMATYPE_MSHC_SP: | |
627 | per_2_emi = sdma->script_addrs->shp_2_mcu_addr; | |
628 | emi_2_per = sdma->script_addrs->mcu_2_shp_addr; | |
629 | break; | |
630 | case IMX_DMATYPE_ASRC: | |
631 | per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; | |
632 | emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; | |
633 | per_2_per = sdma->script_addrs->per_2_per_addr; | |
634 | break; | |
635 | case IMX_DMATYPE_MSHC: | |
636 | per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; | |
637 | emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; | |
638 | break; | |
639 | case IMX_DMATYPE_CCM: | |
640 | per_2_emi = sdma->script_addrs->dptc_dvfs_addr; | |
641 | break; | |
642 | case IMX_DMATYPE_SPDIF: | |
643 | per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; | |
644 | emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; | |
645 | break; | |
646 | case IMX_DMATYPE_IPU_MEMORY: | |
647 | emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; | |
648 | break; | |
649 | default: | |
650 | break; | |
651 | } | |
652 | ||
653 | sdmac->pc_from_device = per_2_emi; | |
654 | sdmac->pc_to_device = emi_2_per; | |
655 | } | |
656 | ||
657 | static int sdma_load_context(struct sdma_channel *sdmac) | |
658 | { | |
659 | struct sdma_engine *sdma = sdmac->sdma; | |
660 | int channel = sdmac->channel; | |
661 | int load_address; | |
662 | struct sdma_context_data *context = sdma->context; | |
663 | struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; | |
664 | int ret; | |
665 | ||
db8196df | 666 | if (sdmac->direction == DMA_DEV_TO_MEM) { |
1ec1e82f SH |
667 | load_address = sdmac->pc_from_device; |
668 | } else { | |
669 | load_address = sdmac->pc_to_device; | |
670 | } | |
671 | ||
672 | if (load_address < 0) | |
673 | return load_address; | |
674 | ||
675 | dev_dbg(sdma->dev, "load_address = %d\n", load_address); | |
0bbc1413 | 676 | dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); |
1ec1e82f SH |
677 | dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); |
678 | dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); | |
0bbc1413 RZ |
679 | dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); |
680 | dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); | |
1ec1e82f | 681 | |
73eab978 SH |
682 | mutex_lock(&sdma->channel_0_lock); |
683 | ||
1ec1e82f SH |
684 | memset(context, 0, sizeof(*context)); |
685 | context->channel_state.pc = load_address; | |
686 | ||
687 | /* Send by context the event mask,base address for peripheral | |
688 | * and watermark level | |
689 | */ | |
0bbc1413 RZ |
690 | context->gReg[0] = sdmac->event_mask[1]; |
691 | context->gReg[1] = sdmac->event_mask[0]; | |
1ec1e82f SH |
692 | context->gReg[2] = sdmac->per_addr; |
693 | context->gReg[6] = sdmac->shp_addr; | |
694 | context->gReg[7] = sdmac->watermark_level; | |
695 | ||
696 | bd0->mode.command = C0_SETDM; | |
697 | bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; | |
698 | bd0->mode.count = sizeof(*context) / 4; | |
699 | bd0->buffer_addr = sdma->context_phys; | |
700 | bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; | |
701 | ||
702 | ret = sdma_run_channel(&sdma->channel[0]); | |
703 | ||
73eab978 SH |
704 | mutex_unlock(&sdma->channel_0_lock); |
705 | ||
1ec1e82f SH |
706 | return ret; |
707 | } | |
708 | ||
709 | static void sdma_disable_channel(struct sdma_channel *sdmac) | |
710 | { | |
711 | struct sdma_engine *sdma = sdmac->sdma; | |
712 | int channel = sdmac->channel; | |
713 | ||
0bbc1413 | 714 | writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); |
1ec1e82f SH |
715 | sdmac->status = DMA_ERROR; |
716 | } | |
717 | ||
718 | static int sdma_config_channel(struct sdma_channel *sdmac) | |
719 | { | |
720 | int ret; | |
721 | ||
722 | sdma_disable_channel(sdmac); | |
723 | ||
0bbc1413 RZ |
724 | sdmac->event_mask[0] = 0; |
725 | sdmac->event_mask[1] = 0; | |
1ec1e82f SH |
726 | sdmac->shp_addr = 0; |
727 | sdmac->per_addr = 0; | |
728 | ||
729 | if (sdmac->event_id0) { | |
b78bd91f | 730 | if (sdmac->event_id0 >= sdmac->sdma->num_events) |
1ec1e82f SH |
731 | return -EINVAL; |
732 | sdma_event_enable(sdmac, sdmac->event_id0); | |
733 | } | |
734 | ||
735 | switch (sdmac->peripheral_type) { | |
736 | case IMX_DMATYPE_DSP: | |
737 | sdma_config_ownership(sdmac, false, true, true); | |
738 | break; | |
739 | case IMX_DMATYPE_MEMORY: | |
740 | sdma_config_ownership(sdmac, false, true, false); | |
741 | break; | |
742 | default: | |
743 | sdma_config_ownership(sdmac, true, true, false); | |
744 | break; | |
745 | } | |
746 | ||
747 | sdma_get_pc(sdmac, sdmac->peripheral_type); | |
748 | ||
749 | if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && | |
750 | (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { | |
751 | /* Handle multiple event channels differently */ | |
752 | if (sdmac->event_id1) { | |
0bbc1413 | 753 | sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); |
1ec1e82f | 754 | if (sdmac->event_id1 > 31) |
0bbc1413 RZ |
755 | __set_bit(31, &sdmac->watermark_level); |
756 | sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); | |
1ec1e82f | 757 | if (sdmac->event_id0 > 31) |
0bbc1413 | 758 | __set_bit(30, &sdmac->watermark_level); |
1ec1e82f | 759 | } else { |
0bbc1413 | 760 | __set_bit(sdmac->event_id0, sdmac->event_mask); |
1ec1e82f SH |
761 | } |
762 | /* Watermark Level */ | |
763 | sdmac->watermark_level |= sdmac->watermark_level; | |
764 | /* Address */ | |
765 | sdmac->shp_addr = sdmac->per_address; | |
766 | } else { | |
767 | sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ | |
768 | } | |
769 | ||
770 | ret = sdma_load_context(sdmac); | |
771 | ||
772 | return ret; | |
773 | } | |
774 | ||
775 | static int sdma_set_channel_priority(struct sdma_channel *sdmac, | |
776 | unsigned int priority) | |
777 | { | |
778 | struct sdma_engine *sdma = sdmac->sdma; | |
779 | int channel = sdmac->channel; | |
780 | ||
781 | if (priority < MXC_SDMA_MIN_PRIORITY | |
782 | || priority > MXC_SDMA_MAX_PRIORITY) { | |
783 | return -EINVAL; | |
784 | } | |
785 | ||
c4b56857 | 786 | writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); |
1ec1e82f SH |
787 | |
788 | return 0; | |
789 | } | |
790 | ||
791 | static int sdma_request_channel(struct sdma_channel *sdmac) | |
792 | { | |
793 | struct sdma_engine *sdma = sdmac->sdma; | |
794 | int channel = sdmac->channel; | |
795 | int ret = -EBUSY; | |
796 | ||
797 | sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); | |
798 | if (!sdmac->bd) { | |
799 | ret = -ENOMEM; | |
800 | goto out; | |
801 | } | |
802 | ||
803 | memset(sdmac->bd, 0, PAGE_SIZE); | |
804 | ||
805 | sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; | |
806 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
807 | ||
1ec1e82f SH |
808 | sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY); |
809 | ||
810 | init_completion(&sdmac->done); | |
811 | ||
812 | sdmac->buf_tail = 0; | |
813 | ||
814 | return 0; | |
815 | out: | |
816 | ||
817 | return ret; | |
818 | } | |
819 | ||
1ec1e82f SH |
820 | static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) |
821 | { | |
822 | return container_of(chan, struct sdma_channel, chan); | |
823 | } | |
824 | ||
825 | static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
826 | { | |
f69f2e26 | 827 | unsigned long flags; |
1ec1e82f | 828 | struct sdma_channel *sdmac = to_sdma_chan(tx->chan); |
1ec1e82f SH |
829 | dma_cookie_t cookie; |
830 | ||
f69f2e26 | 831 | spin_lock_irqsave(&sdmac->lock, flags); |
1ec1e82f | 832 | |
884485e1 | 833 | cookie = dma_cookie_assign(tx); |
1ec1e82f | 834 | |
f69f2e26 | 835 | spin_unlock_irqrestore(&sdmac->lock, flags); |
1ec1e82f SH |
836 | |
837 | return cookie; | |
838 | } | |
839 | ||
840 | static int sdma_alloc_chan_resources(struct dma_chan *chan) | |
841 | { | |
842 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
843 | struct imx_dma_data *data = chan->private; | |
844 | int prio, ret; | |
845 | ||
1ec1e82f SH |
846 | if (!data) |
847 | return -EINVAL; | |
848 | ||
849 | switch (data->priority) { | |
850 | case DMA_PRIO_HIGH: | |
851 | prio = 3; | |
852 | break; | |
853 | case DMA_PRIO_MEDIUM: | |
854 | prio = 2; | |
855 | break; | |
856 | case DMA_PRIO_LOW: | |
857 | default: | |
858 | prio = 1; | |
859 | break; | |
860 | } | |
861 | ||
862 | sdmac->peripheral_type = data->peripheral_type; | |
863 | sdmac->event_id0 = data->dma_request; | |
c2c744d3 RZ |
864 | |
865 | clk_enable(sdmac->sdma->clk); | |
866 | ||
3bb5e7ca | 867 | ret = sdma_request_channel(sdmac); |
1ec1e82f SH |
868 | if (ret) |
869 | return ret; | |
870 | ||
3bb5e7ca | 871 | ret = sdma_set_channel_priority(sdmac, prio); |
1ec1e82f SH |
872 | if (ret) |
873 | return ret; | |
874 | ||
875 | dma_async_tx_descriptor_init(&sdmac->desc, chan); | |
876 | sdmac->desc.tx_submit = sdma_tx_submit; | |
877 | /* txd.flags will be overwritten in prep funcs */ | |
878 | sdmac->desc.flags = DMA_CTRL_ACK; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
883 | static void sdma_free_chan_resources(struct dma_chan *chan) | |
884 | { | |
885 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
886 | struct sdma_engine *sdma = sdmac->sdma; | |
887 | ||
888 | sdma_disable_channel(sdmac); | |
889 | ||
890 | if (sdmac->event_id0) | |
891 | sdma_event_disable(sdmac, sdmac->event_id0); | |
892 | if (sdmac->event_id1) | |
893 | sdma_event_disable(sdmac, sdmac->event_id1); | |
894 | ||
895 | sdmac->event_id0 = 0; | |
896 | sdmac->event_id1 = 0; | |
897 | ||
898 | sdma_set_channel_priority(sdmac, 0); | |
899 | ||
900 | dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); | |
901 | ||
902 | clk_disable(sdma->clk); | |
903 | } | |
904 | ||
905 | static struct dma_async_tx_descriptor *sdma_prep_slave_sg( | |
906 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 907 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 908 | unsigned long flags, void *context) |
1ec1e82f SH |
909 | { |
910 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
911 | struct sdma_engine *sdma = sdmac->sdma; | |
912 | int ret, i, count; | |
23889c63 | 913 | int channel = sdmac->channel; |
1ec1e82f SH |
914 | struct scatterlist *sg; |
915 | ||
916 | if (sdmac->status == DMA_IN_PROGRESS) | |
917 | return NULL; | |
918 | sdmac->status = DMA_IN_PROGRESS; | |
919 | ||
920 | sdmac->flags = 0; | |
921 | ||
922 | dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", | |
923 | sg_len, channel); | |
924 | ||
925 | sdmac->direction = direction; | |
926 | ret = sdma_load_context(sdmac); | |
927 | if (ret) | |
928 | goto err_out; | |
929 | ||
930 | if (sg_len > NUM_BD) { | |
931 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
932 | channel, sg_len, NUM_BD); | |
933 | ret = -EINVAL; | |
934 | goto err_out; | |
935 | } | |
936 | ||
ab59a510 | 937 | sdmac->chn_count = 0; |
1ec1e82f SH |
938 | for_each_sg(sgl, sg, sg_len, i) { |
939 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
940 | int param; | |
941 | ||
d2f5c276 | 942 | bd->buffer_addr = sg->dma_address; |
1ec1e82f SH |
943 | |
944 | count = sg->length; | |
945 | ||
946 | if (count > 0xffff) { | |
947 | dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", | |
948 | channel, count, 0xffff); | |
949 | ret = -EINVAL; | |
950 | goto err_out; | |
951 | } | |
952 | ||
953 | bd->mode.count = count; | |
ab59a510 | 954 | sdmac->chn_count += count; |
1ec1e82f SH |
955 | |
956 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) { | |
957 | ret = -EINVAL; | |
958 | goto err_out; | |
959 | } | |
1fa81c27 SH |
960 | |
961 | switch (sdmac->word_size) { | |
962 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1ec1e82f | 963 | bd->mode.command = 0; |
1fa81c27 SH |
964 | if (count & 3 || sg->dma_address & 3) |
965 | return NULL; | |
966 | break; | |
967 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
968 | bd->mode.command = 2; | |
969 | if (count & 1 || sg->dma_address & 1) | |
970 | return NULL; | |
971 | break; | |
972 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
973 | bd->mode.command = 1; | |
974 | break; | |
975 | default: | |
976 | return NULL; | |
977 | } | |
1ec1e82f SH |
978 | |
979 | param = BD_DONE | BD_EXTD | BD_CONT; | |
980 | ||
341b9419 | 981 | if (i + 1 == sg_len) { |
1ec1e82f | 982 | param |= BD_INTR; |
341b9419 SG |
983 | param |= BD_LAST; |
984 | param &= ~BD_CONT; | |
1ec1e82f SH |
985 | } |
986 | ||
1ec1e82f SH |
987 | dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n", |
988 | i, count, sg->dma_address, | |
989 | param & BD_WRAP ? "wrap" : "", | |
990 | param & BD_INTR ? " intr" : ""); | |
991 | ||
992 | bd->mode.status = param; | |
993 | } | |
994 | ||
995 | sdmac->num_bd = sg_len; | |
996 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
997 | ||
998 | return &sdmac->desc; | |
999 | err_out: | |
4b2ce9dd | 1000 | sdmac->status = DMA_ERROR; |
1ec1e82f SH |
1001 | return NULL; |
1002 | } | |
1003 | ||
1004 | static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( | |
1005 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
185ecb5f AB |
1006 | size_t period_len, enum dma_transfer_direction direction, |
1007 | void *context) | |
1ec1e82f SH |
1008 | { |
1009 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1010 | struct sdma_engine *sdma = sdmac->sdma; | |
1011 | int num_periods = buf_len / period_len; | |
23889c63 | 1012 | int channel = sdmac->channel; |
1ec1e82f SH |
1013 | int ret, i = 0, buf = 0; |
1014 | ||
1015 | dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); | |
1016 | ||
1017 | if (sdmac->status == DMA_IN_PROGRESS) | |
1018 | return NULL; | |
1019 | ||
1020 | sdmac->status = DMA_IN_PROGRESS; | |
1021 | ||
1022 | sdmac->flags |= IMX_DMA_SG_LOOP; | |
1023 | sdmac->direction = direction; | |
1024 | ret = sdma_load_context(sdmac); | |
1025 | if (ret) | |
1026 | goto err_out; | |
1027 | ||
1028 | if (num_periods > NUM_BD) { | |
1029 | dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", | |
1030 | channel, num_periods, NUM_BD); | |
1031 | goto err_out; | |
1032 | } | |
1033 | ||
1034 | if (period_len > 0xffff) { | |
1035 | dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n", | |
1036 | channel, period_len, 0xffff); | |
1037 | goto err_out; | |
1038 | } | |
1039 | ||
1040 | while (buf < buf_len) { | |
1041 | struct sdma_buffer_descriptor *bd = &sdmac->bd[i]; | |
1042 | int param; | |
1043 | ||
1044 | bd->buffer_addr = dma_addr; | |
1045 | ||
1046 | bd->mode.count = period_len; | |
1047 | ||
1048 | if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1049 | goto err_out; | |
1050 | if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) | |
1051 | bd->mode.command = 0; | |
1052 | else | |
1053 | bd->mode.command = sdmac->word_size; | |
1054 | ||
1055 | param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR; | |
1056 | if (i + 1 == num_periods) | |
1057 | param |= BD_WRAP; | |
1058 | ||
1059 | dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n", | |
1060 | i, period_len, dma_addr, | |
1061 | param & BD_WRAP ? "wrap" : "", | |
1062 | param & BD_INTR ? " intr" : ""); | |
1063 | ||
1064 | bd->mode.status = param; | |
1065 | ||
1066 | dma_addr += period_len; | |
1067 | buf += period_len; | |
1068 | ||
1069 | i++; | |
1070 | } | |
1071 | ||
1072 | sdmac->num_bd = num_periods; | |
1073 | sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; | |
1074 | ||
1075 | return &sdmac->desc; | |
1076 | err_out: | |
1077 | sdmac->status = DMA_ERROR; | |
1078 | return NULL; | |
1079 | } | |
1080 | ||
1081 | static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1082 | unsigned long arg) | |
1083 | { | |
1084 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1085 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
1086 | ||
1087 | switch (cmd) { | |
1088 | case DMA_TERMINATE_ALL: | |
1089 | sdma_disable_channel(sdmac); | |
1090 | return 0; | |
1091 | case DMA_SLAVE_CONFIG: | |
db8196df | 1092 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { |
1ec1e82f | 1093 | sdmac->per_address = dmaengine_cfg->src_addr; |
94ac27a5 PR |
1094 | sdmac->watermark_level = dmaengine_cfg->src_maxburst * |
1095 | dmaengine_cfg->src_addr_width; | |
1ec1e82f SH |
1096 | sdmac->word_size = dmaengine_cfg->src_addr_width; |
1097 | } else { | |
1098 | sdmac->per_address = dmaengine_cfg->dst_addr; | |
94ac27a5 PR |
1099 | sdmac->watermark_level = dmaengine_cfg->dst_maxburst * |
1100 | dmaengine_cfg->dst_addr_width; | |
1ec1e82f SH |
1101 | sdmac->word_size = dmaengine_cfg->dst_addr_width; |
1102 | } | |
e6966433 | 1103 | sdmac->direction = dmaengine_cfg->direction; |
1ec1e82f SH |
1104 | return sdma_config_channel(sdmac); |
1105 | default: | |
1106 | return -ENOSYS; | |
1107 | } | |
1108 | ||
1109 | return -EINVAL; | |
1110 | } | |
1111 | ||
1112 | static enum dma_status sdma_tx_status(struct dma_chan *chan, | |
1113 | dma_cookie_t cookie, | |
1114 | struct dma_tx_state *txstate) | |
1115 | { | |
1116 | struct sdma_channel *sdmac = to_sdma_chan(chan); | |
1117 | dma_cookie_t last_used; | |
1ec1e82f SH |
1118 | |
1119 | last_used = chan->cookie; | |
1120 | ||
4d4e58de | 1121 | dma_set_tx_state(txstate, chan->completed_cookie, last_used, |
ab59a510 | 1122 | sdmac->chn_count - sdmac->chn_real_count); |
1ec1e82f | 1123 | |
8a965911 | 1124 | return sdmac->status; |
1ec1e82f SH |
1125 | } |
1126 | ||
1127 | static void sdma_issue_pending(struct dma_chan *chan) | |
1128 | { | |
2b4f130e SH |
1129 | struct sdma_channel *sdmac = to_sdma_chan(chan); |
1130 | struct sdma_engine *sdma = sdmac->sdma; | |
1131 | ||
1132 | if (sdmac->status == DMA_IN_PROGRESS) | |
1133 | sdma_enable_channel(sdma, sdmac->channel); | |
1ec1e82f SH |
1134 | } |
1135 | ||
5b28aa31 SH |
1136 | #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34 |
1137 | ||
1138 | static void sdma_add_scripts(struct sdma_engine *sdma, | |
1139 | const struct sdma_script_start_addrs *addr) | |
1140 | { | |
1141 | s32 *addr_arr = (u32 *)addr; | |
1142 | s32 *saddr_arr = (u32 *)sdma->script_addrs; | |
1143 | int i; | |
1144 | ||
1145 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) | |
1146 | if (addr_arr[i] > 0) | |
1147 | saddr_arr[i] = addr_arr[i]; | |
1148 | } | |
1149 | ||
7b4b88e0 | 1150 | static void sdma_load_firmware(const struct firmware *fw, void *context) |
5b28aa31 | 1151 | { |
7b4b88e0 | 1152 | struct sdma_engine *sdma = context; |
5b28aa31 | 1153 | const struct sdma_firmware_header *header; |
5b28aa31 SH |
1154 | const struct sdma_script_start_addrs *addr; |
1155 | unsigned short *ram_code; | |
1156 | ||
7b4b88e0 SH |
1157 | if (!fw) { |
1158 | dev_err(sdma->dev, "firmware not found\n"); | |
1159 | return; | |
1160 | } | |
5b28aa31 SH |
1161 | |
1162 | if (fw->size < sizeof(*header)) | |
1163 | goto err_firmware; | |
1164 | ||
1165 | header = (struct sdma_firmware_header *)fw->data; | |
1166 | ||
1167 | if (header->magic != SDMA_FIRMWARE_MAGIC) | |
1168 | goto err_firmware; | |
1169 | if (header->ram_code_start + header->ram_code_size > fw->size) | |
1170 | goto err_firmware; | |
1171 | ||
1172 | addr = (void *)header + header->script_addrs_start; | |
1173 | ram_code = (void *)header + header->ram_code_start; | |
1174 | ||
1175 | clk_enable(sdma->clk); | |
1176 | /* download the RAM image for SDMA */ | |
1177 | sdma_load_script(sdma, ram_code, | |
1178 | header->ram_code_size, | |
6866fd3b | 1179 | addr->ram_code_start_addr); |
5b28aa31 SH |
1180 | clk_disable(sdma->clk); |
1181 | ||
1182 | sdma_add_scripts(sdma, addr); | |
1183 | ||
1184 | dev_info(sdma->dev, "loaded firmware %d.%d\n", | |
1185 | header->version_major, | |
1186 | header->version_minor); | |
1187 | ||
1188 | err_firmware: | |
1189 | release_firmware(fw); | |
7b4b88e0 SH |
1190 | } |
1191 | ||
1192 | static int __init sdma_get_firmware(struct sdma_engine *sdma, | |
1193 | const char *fw_name) | |
1194 | { | |
1195 | int ret; | |
1196 | ||
1197 | ret = request_firmware_nowait(THIS_MODULE, | |
1198 | FW_ACTION_HOTPLUG, fw_name, sdma->dev, | |
1199 | GFP_KERNEL, sdma, sdma_load_firmware); | |
5b28aa31 SH |
1200 | |
1201 | return ret; | |
1202 | } | |
1203 | ||
1204 | static int __init sdma_init(struct sdma_engine *sdma) | |
1ec1e82f SH |
1205 | { |
1206 | int i, ret; | |
1207 | dma_addr_t ccb_phys; | |
1208 | ||
62550cd7 SG |
1209 | switch (sdma->devtype) { |
1210 | case IMX31_SDMA: | |
1ec1e82f SH |
1211 | sdma->num_events = 32; |
1212 | break; | |
62550cd7 | 1213 | case IMX35_SDMA: |
1ec1e82f SH |
1214 | sdma->num_events = 48; |
1215 | break; | |
1216 | default: | |
62550cd7 SG |
1217 | dev_err(sdma->dev, "Unknown sdma type %d. aborting\n", |
1218 | sdma->devtype); | |
1ec1e82f SH |
1219 | return -ENODEV; |
1220 | } | |
1221 | ||
1222 | clk_enable(sdma->clk); | |
1223 | ||
1224 | /* Be sure SDMA has not started yet */ | |
c4b56857 | 1225 | writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f SH |
1226 | |
1227 | sdma->channel_control = dma_alloc_coherent(NULL, | |
1228 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + | |
1229 | sizeof(struct sdma_context_data), | |
1230 | &ccb_phys, GFP_KERNEL); | |
1231 | ||
1232 | if (!sdma->channel_control) { | |
1233 | ret = -ENOMEM; | |
1234 | goto err_dma_alloc; | |
1235 | } | |
1236 | ||
1237 | sdma->context = (void *)sdma->channel_control + | |
1238 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1239 | sdma->context_phys = ccb_phys + | |
1240 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control); | |
1241 | ||
1242 | /* Zero-out the CCB structures array just allocated */ | |
1243 | memset(sdma->channel_control, 0, | |
1244 | MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)); | |
1245 | ||
1246 | /* disable all channels */ | |
1247 | for (i = 0; i < sdma->num_events; i++) | |
c4b56857 | 1248 | writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); |
1ec1e82f SH |
1249 | |
1250 | /* All channels have priority 0 */ | |
1251 | for (i = 0; i < MAX_DMA_CHANNELS; i++) | |
c4b56857 | 1252 | writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); |
1ec1e82f SH |
1253 | |
1254 | ret = sdma_request_channel(&sdma->channel[0]); | |
1255 | if (ret) | |
1256 | goto err_dma_alloc; | |
1257 | ||
1258 | sdma_config_ownership(&sdma->channel[0], false, true, false); | |
1259 | ||
1260 | /* Set Command Channel (Channel Zero) */ | |
c4b56857 | 1261 | writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); |
1ec1e82f SH |
1262 | |
1263 | /* Set bits of CONFIG register but with static context switching */ | |
1264 | /* FIXME: Check whether to set ACR bit depending on clock ratios */ | |
c4b56857 | 1265 | writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f | 1266 | |
c4b56857 | 1267 | writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); |
1ec1e82f | 1268 | |
1ec1e82f | 1269 | /* Set bits of CONFIG register with given context switching mode */ |
c4b56857 | 1270 | writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); |
1ec1e82f SH |
1271 | |
1272 | /* Initializes channel's priorities */ | |
1273 | sdma_set_channel_priority(&sdma->channel[0], 7); | |
1274 | ||
1275 | clk_disable(sdma->clk); | |
1276 | ||
1277 | return 0; | |
1278 | ||
1279 | err_dma_alloc: | |
1280 | clk_disable(sdma->clk); | |
1281 | dev_err(sdma->dev, "initialisation failed with %d\n", ret); | |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | static int __init sdma_probe(struct platform_device *pdev) | |
1286 | { | |
580975d7 SG |
1287 | const struct of_device_id *of_id = |
1288 | of_match_device(sdma_dt_ids, &pdev->dev); | |
1289 | struct device_node *np = pdev->dev.of_node; | |
1290 | const char *fw_name; | |
1ec1e82f | 1291 | int ret; |
1ec1e82f | 1292 | int irq; |
1ec1e82f SH |
1293 | struct resource *iores; |
1294 | struct sdma_platform_data *pdata = pdev->dev.platform_data; | |
1ec1e82f | 1295 | int i; |
1ec1e82f | 1296 | struct sdma_engine *sdma; |
36e2f21a | 1297 | s32 *saddr_arr; |
1ec1e82f SH |
1298 | |
1299 | sdma = kzalloc(sizeof(*sdma), GFP_KERNEL); | |
1300 | if (!sdma) | |
1301 | return -ENOMEM; | |
1302 | ||
73eab978 SH |
1303 | mutex_init(&sdma->channel_0_lock); |
1304 | ||
1ec1e82f SH |
1305 | sdma->dev = &pdev->dev; |
1306 | ||
1307 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1308 | irq = platform_get_irq(pdev, 0); | |
580975d7 | 1309 | if (!iores || irq < 0) { |
1ec1e82f SH |
1310 | ret = -EINVAL; |
1311 | goto err_irq; | |
1312 | } | |
1313 | ||
1314 | if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) { | |
1315 | ret = -EBUSY; | |
1316 | goto err_request_region; | |
1317 | } | |
1318 | ||
1319 | sdma->clk = clk_get(&pdev->dev, NULL); | |
1320 | if (IS_ERR(sdma->clk)) { | |
1321 | ret = PTR_ERR(sdma->clk); | |
1322 | goto err_clk; | |
1323 | } | |
1324 | ||
1325 | sdma->regs = ioremap(iores->start, resource_size(iores)); | |
1326 | if (!sdma->regs) { | |
1327 | ret = -ENOMEM; | |
1328 | goto err_ioremap; | |
1329 | } | |
1330 | ||
1331 | ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma); | |
1332 | if (ret) | |
1333 | goto err_request_irq; | |
1334 | ||
5b28aa31 | 1335 | sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); |
1c1d9547 AL |
1336 | if (!sdma->script_addrs) { |
1337 | ret = -ENOMEM; | |
5b28aa31 | 1338 | goto err_alloc; |
1c1d9547 | 1339 | } |
1ec1e82f | 1340 | |
36e2f21a SH |
1341 | /* initially no scripts available */ |
1342 | saddr_arr = (s32 *)sdma->script_addrs; | |
1343 | for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++) | |
1344 | saddr_arr[i] = -EINVAL; | |
1345 | ||
580975d7 SG |
1346 | if (of_id) |
1347 | pdev->id_entry = of_id->data; | |
62550cd7 | 1348 | sdma->devtype = pdev->id_entry->driver_data; |
1ec1e82f | 1349 | |
7214a8b1 SH |
1350 | dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); |
1351 | dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); | |
1352 | ||
1ec1e82f SH |
1353 | INIT_LIST_HEAD(&sdma->dma_device.channels); |
1354 | /* Initialize channel parameters */ | |
1355 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { | |
1356 | struct sdma_channel *sdmac = &sdma->channel[i]; | |
1357 | ||
1358 | sdmac->sdma = sdma; | |
1359 | spin_lock_init(&sdmac->lock); | |
1360 | ||
1ec1e82f | 1361 | sdmac->chan.device = &sdma->dma_device; |
8ac69546 | 1362 | dma_cookie_init(&sdmac->chan); |
1ec1e82f SH |
1363 | sdmac->channel = i; |
1364 | ||
abd9ccc8 HS |
1365 | tasklet_init(&sdmac->tasklet, sdma_tasklet, |
1366 | (unsigned long) sdmac); | |
23889c63 SH |
1367 | /* |
1368 | * Add the channel to the DMAC list. Do not add channel 0 though | |
1369 | * because we need it internally in the SDMA driver. This also means | |
1370 | * that channel 0 in dmaengine counting matches sdma channel 1. | |
1371 | */ | |
1372 | if (i) | |
1373 | list_add_tail(&sdmac->chan.device_node, | |
1374 | &sdma->dma_device.channels); | |
1ec1e82f SH |
1375 | } |
1376 | ||
5b28aa31 | 1377 | ret = sdma_init(sdma); |
1ec1e82f SH |
1378 | if (ret) |
1379 | goto err_init; | |
1380 | ||
580975d7 | 1381 | if (pdata && pdata->script_addrs) |
5b28aa31 SH |
1382 | sdma_add_scripts(sdma, pdata->script_addrs); |
1383 | ||
580975d7 | 1384 | if (pdata) { |
6d0d7e2d FE |
1385 | ret = sdma_get_firmware(sdma, pdata->fw_name); |
1386 | if (ret) | |
ad1122e5 | 1387 | dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); |
580975d7 SG |
1388 | } else { |
1389 | /* | |
1390 | * Because that device tree does not encode ROM script address, | |
1391 | * the RAM script in firmware is mandatory for device tree | |
1392 | * probe, otherwise it fails. | |
1393 | */ | |
1394 | ret = of_property_read_string(np, "fsl,sdma-ram-script-name", | |
1395 | &fw_name); | |
6602b0dd | 1396 | if (ret) |
ad1122e5 | 1397 | dev_warn(&pdev->dev, "failed to get firmware name\n"); |
6602b0dd FE |
1398 | else { |
1399 | ret = sdma_get_firmware(sdma, fw_name); | |
1400 | if (ret) | |
ad1122e5 | 1401 | dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); |
580975d7 SG |
1402 | } |
1403 | } | |
5b28aa31 | 1404 | |
1ec1e82f SH |
1405 | sdma->dma_device.dev = &pdev->dev; |
1406 | ||
1407 | sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; | |
1408 | sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; | |
1409 | sdma->dma_device.device_tx_status = sdma_tx_status; | |
1410 | sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; | |
1411 | sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; | |
1412 | sdma->dma_device.device_control = sdma_control; | |
1413 | sdma->dma_device.device_issue_pending = sdma_issue_pending; | |
b9b3f82f SH |
1414 | sdma->dma_device.dev->dma_parms = &sdma->dma_parms; |
1415 | dma_set_max_seg_size(sdma->dma_device.dev, 65535); | |
1ec1e82f SH |
1416 | |
1417 | ret = dma_async_device_register(&sdma->dma_device); | |
1418 | if (ret) { | |
1419 | dev_err(&pdev->dev, "unable to register\n"); | |
1420 | goto err_init; | |
1421 | } | |
1422 | ||
5b28aa31 | 1423 | dev_info(sdma->dev, "initialized\n"); |
1ec1e82f SH |
1424 | |
1425 | return 0; | |
1426 | ||
1427 | err_init: | |
1428 | kfree(sdma->script_addrs); | |
5b28aa31 | 1429 | err_alloc: |
1ec1e82f SH |
1430 | free_irq(irq, sdma); |
1431 | err_request_irq: | |
1432 | iounmap(sdma->regs); | |
1433 | err_ioremap: | |
1434 | clk_put(sdma->clk); | |
1435 | err_clk: | |
1436 | release_mem_region(iores->start, resource_size(iores)); | |
1437 | err_request_region: | |
1438 | err_irq: | |
1439 | kfree(sdma); | |
939fd4f0 | 1440 | return ret; |
1ec1e82f SH |
1441 | } |
1442 | ||
1443 | static int __exit sdma_remove(struct platform_device *pdev) | |
1444 | { | |
1445 | return -EBUSY; | |
1446 | } | |
1447 | ||
1448 | static struct platform_driver sdma_driver = { | |
1449 | .driver = { | |
1450 | .name = "imx-sdma", | |
580975d7 | 1451 | .of_match_table = sdma_dt_ids, |
1ec1e82f | 1452 | }, |
62550cd7 | 1453 | .id_table = sdma_devtypes, |
1ec1e82f SH |
1454 | .remove = __exit_p(sdma_remove), |
1455 | }; | |
1456 | ||
1457 | static int __init sdma_module_init(void) | |
1458 | { | |
1459 | return platform_driver_probe(&sdma_driver, sdma_probe); | |
1460 | } | |
c989a7fc | 1461 | module_init(sdma_module_init); |
1ec1e82f SH |
1462 | |
1463 | MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>"); | |
1464 | MODULE_DESCRIPTION("i.MX SDMA driver"); | |
1465 | MODULE_LICENSE("GPL"); |