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b3c567e4 VK |
1 | /* |
2 | * intel_mid_dma.c - Intel Langwell DMA Drivers | |
3 | * | |
4 | * Copyright (C) 2008-10 Intel Corp | |
5 | * Author: Vinod Koul <vinod.koul@intel.com> | |
6 | * The driver design is based on dw_dmac driver | |
7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
21 | * | |
22 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
23 | * | |
24 | * | |
25 | */ | |
26 | #include <linux/pci.h> | |
27 | #include <linux/interrupt.h> | |
53a61bad | 28 | #include <linux/pm_runtime.h> |
b3c567e4 | 29 | #include <linux/intel_mid_dma.h> |
7c52d551 | 30 | #include <linux/module.h> |
b3c567e4 | 31 | |
d2ebfb33 RKAL |
32 | #include "dmaengine.h" |
33 | ||
b3c567e4 VK |
34 | #define MAX_CHAN 4 /*max ch across controllers*/ |
35 | #include "intel_mid_dma_regs.h" | |
36 | ||
37 | #define INTEL_MID_DMAC1_ID 0x0814 | |
38 | #define INTEL_MID_DMAC2_ID 0x0813 | |
39 | #define INTEL_MID_GP_DMAC2_ID 0x0827 | |
40 | #define INTEL_MFLD_DMAC1_ID 0x0830 | |
41 | #define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008 | |
42 | #define LNW_PERIPHRAL_MASK_SIZE 0x10 | |
43 | #define LNW_PERIPHRAL_STATUS 0x0 | |
44 | #define LNW_PERIPHRAL_MASK 0x8 | |
45 | ||
46 | struct intel_mid_dma_probe_info { | |
47 | u8 max_chan; | |
48 | u8 ch_base; | |
49 | u16 block_size; | |
50 | u32 pimr_mask; | |
51 | }; | |
52 | ||
53 | #define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \ | |
54 | ((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \ | |
55 | .max_chan = (_max_chan), \ | |
56 | .ch_base = (_ch_base), \ | |
57 | .block_size = (_block_size), \ | |
58 | .pimr_mask = (_pimr_mask), \ | |
59 | }) | |
60 | ||
61 | /***************************************************************************** | |
62 | Utility Functions*/ | |
63 | /** | |
64 | * get_ch_index - convert status to channel | |
65 | * @status: status mask | |
66 | * @base: dma ch base value | |
67 | * | |
68 | * Modify the status mask and return the channel index needing | |
69 | * attention (or -1 if neither) | |
70 | */ | |
71 | static int get_ch_index(int *status, unsigned int base) | |
72 | { | |
73 | int i; | |
74 | for (i = 0; i < MAX_CHAN; i++) { | |
75 | if (*status & (1 << (i + base))) { | |
76 | *status = *status & ~(1 << (i + base)); | |
77 | pr_debug("MDMA: index %d New status %x\n", i, *status); | |
78 | return i; | |
79 | } | |
80 | } | |
81 | return -1; | |
82 | } | |
83 | ||
84 | /** | |
85 | * get_block_ts - calculates dma transaction length | |
86 | * @len: dma transfer length | |
87 | * @tx_width: dma transfer src width | |
88 | * @block_size: dma controller max block size | |
89 | * | |
90 | * Based on src width calculate the DMA trsaction length in data items | |
91 | * return data items or FFFF if exceeds max length for block | |
92 | */ | |
93 | static int get_block_ts(int len, int tx_width, int block_size) | |
94 | { | |
95 | int byte_width = 0, block_ts = 0; | |
96 | ||
97 | switch (tx_width) { | |
20dd6390 | 98 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
b3c567e4 VK |
99 | byte_width = 1; |
100 | break; | |
20dd6390 | 101 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
b3c567e4 VK |
102 | byte_width = 2; |
103 | break; | |
20dd6390 | 104 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
b3c567e4 VK |
105 | default: |
106 | byte_width = 4; | |
107 | break; | |
108 | } | |
109 | ||
110 | block_ts = len/byte_width; | |
111 | if (block_ts > block_size) | |
112 | block_ts = 0xFFFF; | |
113 | return block_ts; | |
114 | } | |
115 | ||
116 | /***************************************************************************** | |
117 | DMAC1 interrupt Functions*/ | |
118 | ||
119 | /** | |
120 | * dmac1_mask_periphral_intr - mask the periphral interrupt | |
4598fc2c | 121 | * @mid: dma device for which masking is required |
b3c567e4 VK |
122 | * |
123 | * Masks the DMA periphral interrupt | |
124 | * this is valid for DMAC1 family controllers only | |
125 | * This controller should have periphral mask registers already mapped | |
126 | */ | |
4598fc2c | 127 | static void dmac1_mask_periphral_intr(struct middma_device *mid) |
b3c567e4 VK |
128 | { |
129 | u32 pimr; | |
b3c567e4 VK |
130 | |
131 | if (mid->pimr_mask) { | |
132 | pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK); | |
133 | pimr |= mid->pimr_mask; | |
134 | writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK); | |
135 | } | |
136 | return; | |
137 | } | |
138 | ||
139 | /** | |
140 | * dmac1_unmask_periphral_intr - unmask the periphral interrupt | |
141 | * @midc: dma channel for which masking is required | |
142 | * | |
143 | * UnMasks the DMA periphral interrupt, | |
144 | * this is valid for DMAC1 family controllers only | |
145 | * This controller should have periphral mask registers already mapped | |
146 | */ | |
147 | static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan *midc) | |
148 | { | |
149 | u32 pimr; | |
150 | struct middma_device *mid = to_middma_device(midc->chan.device); | |
151 | ||
152 | if (mid->pimr_mask) { | |
153 | pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK); | |
154 | pimr &= ~mid->pimr_mask; | |
155 | writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK); | |
156 | } | |
157 | return; | |
158 | } | |
159 | ||
160 | /** | |
161 | * enable_dma_interrupt - enable the periphral interrupt | |
162 | * @midc: dma channel for which enable interrupt is required | |
163 | * | |
164 | * Enable the DMA periphral interrupt, | |
165 | * this is valid for DMAC1 family controllers only | |
166 | * This controller should have periphral mask registers already mapped | |
167 | */ | |
168 | static void enable_dma_interrupt(struct intel_mid_dma_chan *midc) | |
169 | { | |
170 | dmac1_unmask_periphral_intr(midc); | |
171 | ||
172 | /*en ch interrupts*/ | |
173 | iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR); | |
174 | iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR); | |
175 | return; | |
176 | } | |
177 | ||
178 | /** | |
179 | * disable_dma_interrupt - disable the periphral interrupt | |
180 | * @midc: dma channel for which disable interrupt is required | |
181 | * | |
182 | * Disable the DMA periphral interrupt, | |
183 | * this is valid for DMAC1 family controllers only | |
184 | * This controller should have periphral mask registers already mapped | |
185 | */ | |
186 | static void disable_dma_interrupt(struct intel_mid_dma_chan *midc) | |
187 | { | |
188 | /*Check LPE PISR, make sure fwd is disabled*/ | |
b3c567e4 VK |
189 | iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK); |
190 | iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR); | |
191 | iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR); | |
192 | return; | |
193 | } | |
194 | ||
195 | /***************************************************************************** | |
196 | DMA channel helper Functions*/ | |
197 | /** | |
198 | * mid_desc_get - get a descriptor | |
199 | * @midc: dma channel for which descriptor is required | |
200 | * | |
201 | * Obtain a descriptor for the channel. Returns NULL if none are free. | |
202 | * Once the descriptor is returned it is private until put on another | |
203 | * list or freed | |
204 | */ | |
205 | static struct intel_mid_dma_desc *midc_desc_get(struct intel_mid_dma_chan *midc) | |
206 | { | |
207 | struct intel_mid_dma_desc *desc, *_desc; | |
208 | struct intel_mid_dma_desc *ret = NULL; | |
209 | ||
210 | spin_lock_bh(&midc->lock); | |
211 | list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) { | |
212 | if (async_tx_test_ack(&desc->txd)) { | |
213 | list_del(&desc->desc_node); | |
214 | ret = desc; | |
215 | break; | |
216 | } | |
217 | } | |
218 | spin_unlock_bh(&midc->lock); | |
219 | return ret; | |
220 | } | |
221 | ||
222 | /** | |
223 | * mid_desc_put - put a descriptor | |
224 | * @midc: dma channel for which descriptor is required | |
225 | * @desc: descriptor to put | |
226 | * | |
227 | * Return a descriptor from lwn_desc_get back to the free pool | |
228 | */ | |
229 | static void midc_desc_put(struct intel_mid_dma_chan *midc, | |
230 | struct intel_mid_dma_desc *desc) | |
231 | { | |
232 | if (desc) { | |
233 | spin_lock_bh(&midc->lock); | |
234 | list_add_tail(&desc->desc_node, &midc->free_list); | |
235 | spin_unlock_bh(&midc->lock); | |
236 | } | |
237 | } | |
238 | /** | |
239 | * midc_dostart - begin a DMA transaction | |
240 | * @midc: channel for which txn is to be started | |
241 | * @first: first descriptor of series | |
242 | * | |
243 | * Load a transaction into the engine. This must be called with midc->lock | |
244 | * held and bh disabled. | |
245 | */ | |
246 | static void midc_dostart(struct intel_mid_dma_chan *midc, | |
247 | struct intel_mid_dma_desc *first) | |
248 | { | |
249 | struct middma_device *mid = to_middma_device(midc->chan.device); | |
250 | ||
251 | /* channel is idle */ | |
53a61bad | 252 | if (midc->busy && test_ch_en(midc->dma_base, midc->ch_id)) { |
b3c567e4 VK |
253 | /*error*/ |
254 | pr_err("ERR_MDMA: channel is busy in start\n"); | |
255 | /* The tasklet will hopefully advance the queue... */ | |
256 | return; | |
257 | } | |
53a61bad | 258 | midc->busy = true; |
b3c567e4 VK |
259 | /*write registers and en*/ |
260 | iowrite32(first->sar, midc->ch_regs + SAR); | |
261 | iowrite32(first->dar, midc->ch_regs + DAR); | |
576e3c39 | 262 | iowrite32(first->lli_phys, midc->ch_regs + LLP); |
b3c567e4 VK |
263 | iowrite32(first->cfg_hi, midc->ch_regs + CFG_HIGH); |
264 | iowrite32(first->cfg_lo, midc->ch_regs + CFG_LOW); | |
265 | iowrite32(first->ctl_lo, midc->ch_regs + CTL_LOW); | |
266 | iowrite32(first->ctl_hi, midc->ch_regs + CTL_HIGH); | |
267 | pr_debug("MDMA:TX SAR %x,DAR %x,CFGL %x,CFGH %x,CTLH %x, CTLL %x\n", | |
268 | (int)first->sar, (int)first->dar, first->cfg_hi, | |
269 | first->cfg_lo, first->ctl_hi, first->ctl_lo); | |
576e3c39 | 270 | first->status = DMA_IN_PROGRESS; |
b3c567e4 VK |
271 | |
272 | iowrite32(ENABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN); | |
b3c567e4 VK |
273 | } |
274 | ||
275 | /** | |
276 | * midc_descriptor_complete - process completed descriptor | |
277 | * @midc: channel owning the descriptor | |
278 | * @desc: the descriptor itself | |
279 | * | |
280 | * Process a completed descriptor and perform any callbacks upon | |
281 | * the completion. The completion handling drops the lock during the | |
282 | * callbacks but must be called with the lock held. | |
283 | */ | |
284 | static void midc_descriptor_complete(struct intel_mid_dma_chan *midc, | |
1fded075 AH |
285 | struct intel_mid_dma_desc *desc) |
286 | __releases(&midc->lock) __acquires(&midc->lock) | |
b3c567e4 VK |
287 | { |
288 | struct dma_async_tx_descriptor *txd = &desc->txd; | |
289 | dma_async_tx_callback callback_txd = NULL; | |
576e3c39 | 290 | struct intel_mid_dma_lli *llitem; |
b3c567e4 VK |
291 | void *param_txd = NULL; |
292 | ||
f7fbce07 | 293 | dma_cookie_complete(txd); |
b3c567e4 VK |
294 | callback_txd = txd->callback; |
295 | param_txd = txd->callback_param; | |
296 | ||
576e3c39 RB |
297 | if (desc->lli != NULL) { |
298 | /*clear the DONE bit of completed LLI in memory*/ | |
299 | llitem = desc->lli + desc->current_lli; | |
300 | llitem->ctl_hi &= CLEAR_DONE; | |
301 | if (desc->current_lli < desc->lli_length-1) | |
302 | (desc->current_lli)++; | |
303 | else | |
304 | desc->current_lli = 0; | |
305 | } | |
b3c567e4 VK |
306 | spin_unlock_bh(&midc->lock); |
307 | if (callback_txd) { | |
308 | pr_debug("MDMA: TXD callback set ... calling\n"); | |
309 | callback_txd(param_txd); | |
576e3c39 RB |
310 | } |
311 | if (midc->raw_tfr) { | |
312 | desc->status = DMA_SUCCESS; | |
313 | if (desc->lli != NULL) { | |
314 | pci_pool_free(desc->lli_pool, desc->lli, | |
315 | desc->lli_phys); | |
316 | pci_pool_destroy(desc->lli_pool); | |
1fded075 | 317 | desc->lli = NULL; |
576e3c39 RB |
318 | } |
319 | list_move(&desc->desc_node, &midc->free_list); | |
320 | midc->busy = false; | |
b3c567e4 VK |
321 | } |
322 | spin_lock_bh(&midc->lock); | |
323 | ||
324 | } | |
325 | /** | |
326 | * midc_scan_descriptors - check the descriptors in channel | |
327 | * mark completed when tx is completete | |
328 | * @mid: device | |
329 | * @midc: channel to scan | |
330 | * | |
331 | * Walk the descriptor chain for the device and process any entries | |
332 | * that are complete. | |
333 | */ | |
334 | static void midc_scan_descriptors(struct middma_device *mid, | |
335 | struct intel_mid_dma_chan *midc) | |
336 | { | |
337 | struct intel_mid_dma_desc *desc = NULL, *_desc = NULL; | |
338 | ||
339 | /*tx is complete*/ | |
340 | list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) { | |
576e3c39 | 341 | if (desc->status == DMA_IN_PROGRESS) |
b3c567e4 | 342 | midc_descriptor_complete(midc, desc); |
b3c567e4 VK |
343 | } |
344 | return; | |
576e3c39 RB |
345 | } |
346 | /** | |
347 | * midc_lli_fill_sg - Helper function to convert | |
348 | * SG list to Linked List Items. | |
349 | *@midc: Channel | |
350 | *@desc: DMA descriptor | |
351 | *@sglist: Pointer to SG list | |
352 | *@sglen: SG list length | |
353 | *@flags: DMA transaction flags | |
354 | * | |
355 | * Walk through the SG list and convert the SG list into Linked | |
356 | * List Items (LLI). | |
357 | */ | |
358 | static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc, | |
359 | struct intel_mid_dma_desc *desc, | |
360 | struct scatterlist *sglist, | |
361 | unsigned int sglen, | |
362 | unsigned int flags) | |
363 | { | |
364 | struct intel_mid_dma_slave *mids; | |
365 | struct scatterlist *sg; | |
366 | dma_addr_t lli_next, sg_phy_addr; | |
367 | struct intel_mid_dma_lli *lli_bloc_desc; | |
368 | union intel_mid_dma_ctl_lo ctl_lo; | |
369 | union intel_mid_dma_ctl_hi ctl_hi; | |
370 | int i; | |
371 | ||
372 | pr_debug("MDMA: Entered midc_lli_fill_sg\n"); | |
20dd6390 | 373 | mids = midc->mid_slave; |
576e3c39 RB |
374 | |
375 | lli_bloc_desc = desc->lli; | |
376 | lli_next = desc->lli_phys; | |
b3c567e4 | 377 | |
576e3c39 RB |
378 | ctl_lo.ctl_lo = desc->ctl_lo; |
379 | ctl_hi.ctl_hi = desc->ctl_hi; | |
380 | for_each_sg(sglist, sg, sglen, i) { | |
381 | /*Populate CTL_LOW and LLI values*/ | |
382 | if (i != sglen - 1) { | |
383 | lli_next = lli_next + | |
384 | sizeof(struct intel_mid_dma_lli); | |
385 | } else { | |
386 | /*Check for circular list, otherwise terminate LLI to ZERO*/ | |
387 | if (flags & DMA_PREP_CIRCULAR_LIST) { | |
388 | pr_debug("MDMA: LLI is configured in circular mode\n"); | |
389 | lli_next = desc->lli_phys; | |
390 | } else { | |
391 | lli_next = 0; | |
392 | ctl_lo.ctlx.llp_dst_en = 0; | |
393 | ctl_lo.ctlx.llp_src_en = 0; | |
394 | } | |
395 | } | |
396 | /*Populate CTL_HI values*/ | |
397 | ctl_hi.ctlx.block_ts = get_block_ts(sg->length, | |
398 | desc->width, | |
399 | midc->dma->block_size); | |
400 | /*Populate SAR and DAR values*/ | |
401 | sg_phy_addr = sg_phys(sg); | |
db8196df | 402 | if (desc->dirn == DMA_MEM_TO_DEV) { |
576e3c39 | 403 | lli_bloc_desc->sar = sg_phy_addr; |
20dd6390 | 404 | lli_bloc_desc->dar = mids->dma_slave.dst_addr; |
db8196df | 405 | } else if (desc->dirn == DMA_DEV_TO_MEM) { |
20dd6390 | 406 | lli_bloc_desc->sar = mids->dma_slave.src_addr; |
576e3c39 RB |
407 | lli_bloc_desc->dar = sg_phy_addr; |
408 | } | |
409 | /*Copy values into block descriptor in system memroy*/ | |
410 | lli_bloc_desc->llp = lli_next; | |
411 | lli_bloc_desc->ctl_lo = ctl_lo.ctl_lo; | |
412 | lli_bloc_desc->ctl_hi = ctl_hi.ctl_hi; | |
413 | ||
414 | lli_bloc_desc++; | |
415 | } | |
416 | /*Copy very first LLI values to descriptor*/ | |
417 | desc->ctl_lo = desc->lli->ctl_lo; | |
418 | desc->ctl_hi = desc->lli->ctl_hi; | |
419 | desc->sar = desc->lli->sar; | |
420 | desc->dar = desc->lli->dar; | |
421 | ||
422 | return 0; | |
423 | } | |
b3c567e4 VK |
424 | /***************************************************************************** |
425 | DMA engine callback Functions*/ | |
426 | /** | |
427 | * intel_mid_dma_tx_submit - callback to submit DMA transaction | |
428 | * @tx: dma engine descriptor | |
429 | * | |
430 | * Submit the DMA trasaction for this descriptor, start if ch idle | |
431 | */ | |
432 | static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx) | |
433 | { | |
434 | struct intel_mid_dma_desc *desc = to_intel_mid_dma_desc(tx); | |
435 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(tx->chan); | |
436 | dma_cookie_t cookie; | |
437 | ||
438 | spin_lock_bh(&midc->lock); | |
884485e1 | 439 | cookie = dma_cookie_assign(tx); |
b3c567e4 | 440 | |
576e3c39 | 441 | if (list_empty(&midc->active_list)) |
b3c567e4 | 442 | list_add_tail(&desc->desc_node, &midc->active_list); |
576e3c39 | 443 | else |
b3c567e4 | 444 | list_add_tail(&desc->desc_node, &midc->queue); |
576e3c39 RB |
445 | |
446 | midc_dostart(midc, desc); | |
b3c567e4 VK |
447 | spin_unlock_bh(&midc->lock); |
448 | ||
449 | return cookie; | |
450 | } | |
451 | ||
452 | /** | |
453 | * intel_mid_dma_issue_pending - callback to issue pending txn | |
454 | * @chan: chan where pending trascation needs to be checked and submitted | |
455 | * | |
456 | * Call for scan to issue pending descriptors | |
457 | */ | |
458 | static void intel_mid_dma_issue_pending(struct dma_chan *chan) | |
459 | { | |
460 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan); | |
461 | ||
462 | spin_lock_bh(&midc->lock); | |
463 | if (!list_empty(&midc->queue)) | |
464 | midc_scan_descriptors(to_middma_device(chan->device), midc); | |
465 | spin_unlock_bh(&midc->lock); | |
466 | } | |
467 | ||
468 | /** | |
469 | * intel_mid_dma_tx_status - Return status of txn | |
470 | * @chan: chan for where status needs to be checked | |
471 | * @cookie: cookie for txn | |
472 | * @txstate: DMA txn state | |
473 | * | |
474 | * Return status of DMA txn | |
475 | */ | |
476 | static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan, | |
477 | dma_cookie_t cookie, | |
478 | struct dma_tx_state *txstate) | |
479 | { | |
96a2af41 | 480 | enum dma_status ret; |
b3c567e4 | 481 | |
96a2af41 | 482 | ret = dma_cookie_status(chan, cookie, txstate); |
b3c567e4 | 483 | if (ret != DMA_SUCCESS) { |
1fded075 | 484 | spin_lock_bh(&midc->lock); |
b3c567e4 | 485 | midc_scan_descriptors(to_middma_device(chan->device), midc); |
1fded075 | 486 | spin_unlock_bh(&midc->lock); |
b3c567e4 | 487 | |
96a2af41 | 488 | ret = dma_cookie_status(chan, cookie, txstate); |
b3c567e4 VK |
489 | } |
490 | ||
b3c567e4 VK |
491 | return ret; |
492 | } | |
493 | ||
20dd6390 KV |
494 | static int dma_slave_control(struct dma_chan *chan, unsigned long arg) |
495 | { | |
496 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan); | |
497 | struct dma_slave_config *slave = (struct dma_slave_config *)arg; | |
498 | struct intel_mid_dma_slave *mid_slave; | |
499 | ||
500 | BUG_ON(!midc); | |
501 | BUG_ON(!slave); | |
502 | pr_debug("MDMA: slave control called\n"); | |
503 | ||
504 | mid_slave = to_intel_mid_dma_slave(slave); | |
505 | ||
506 | BUG_ON(!mid_slave); | |
507 | ||
508 | midc->mid_slave = mid_slave; | |
509 | return 0; | |
510 | } | |
b3c567e4 VK |
511 | /** |
512 | * intel_mid_dma_device_control - DMA device control | |
513 | * @chan: chan for DMA control | |
514 | * @cmd: control cmd | |
515 | * @arg: cmd arg value | |
516 | * | |
517 | * Perform DMA control command | |
518 | */ | |
519 | static int intel_mid_dma_device_control(struct dma_chan *chan, | |
520 | enum dma_ctrl_cmd cmd, unsigned long arg) | |
521 | { | |
522 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan); | |
523 | struct middma_device *mid = to_middma_device(chan->device); | |
524 | struct intel_mid_dma_desc *desc, *_desc; | |
576e3c39 | 525 | union intel_mid_dma_cfg_lo cfg_lo; |
b3c567e4 | 526 | |
20dd6390 KV |
527 | if (cmd == DMA_SLAVE_CONFIG) |
528 | return dma_slave_control(chan, arg); | |
529 | ||
b3c567e4 VK |
530 | if (cmd != DMA_TERMINATE_ALL) |
531 | return -ENXIO; | |
532 | ||
533 | spin_lock_bh(&midc->lock); | |
53a61bad | 534 | if (midc->busy == false) { |
b3c567e4 VK |
535 | spin_unlock_bh(&midc->lock); |
536 | return 0; | |
537 | } | |
576e3c39 RB |
538 | /*Suspend and disable the channel*/ |
539 | cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW); | |
540 | cfg_lo.cfgx.ch_susp = 1; | |
541 | iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW); | |
542 | iowrite32(DISABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN); | |
543 | midc->busy = false; | |
b3c567e4 VK |
544 | /* Disable interrupts */ |
545 | disable_dma_interrupt(midc); | |
576e3c39 | 546 | midc->descs_allocated = 0; |
b3c567e4 VK |
547 | |
548 | spin_unlock_bh(&midc->lock); | |
576e3c39 RB |
549 | list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) { |
550 | if (desc->lli != NULL) { | |
551 | pci_pool_free(desc->lli_pool, desc->lli, | |
552 | desc->lli_phys); | |
553 | pci_pool_destroy(desc->lli_pool); | |
1fded075 | 554 | desc->lli = NULL; |
576e3c39 RB |
555 | } |
556 | list_move(&desc->desc_node, &midc->free_list); | |
b3c567e4 VK |
557 | } |
558 | return 0; | |
559 | } | |
560 | ||
b3c567e4 VK |
561 | |
562 | /** | |
563 | * intel_mid_dma_prep_memcpy - Prep memcpy txn | |
564 | * @chan: chan for DMA transfer | |
565 | * @dest: destn address | |
566 | * @src: src address | |
567 | * @len: DMA transfer len | |
568 | * @flags: DMA flags | |
569 | * | |
570 | * Perform a DMA memcpy. Note we support slave periphral DMA transfers only | |
571 | * The periphral txn details should be filled in slave structure properly | |
572 | * Returns the descriptor for this txn | |
573 | */ | |
574 | static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy( | |
575 | struct dma_chan *chan, dma_addr_t dest, | |
576 | dma_addr_t src, size_t len, unsigned long flags) | |
577 | { | |
578 | struct intel_mid_dma_chan *midc; | |
579 | struct intel_mid_dma_desc *desc = NULL; | |
580 | struct intel_mid_dma_slave *mids; | |
581 | union intel_mid_dma_ctl_lo ctl_lo; | |
582 | union intel_mid_dma_ctl_hi ctl_hi; | |
583 | union intel_mid_dma_cfg_lo cfg_lo; | |
584 | union intel_mid_dma_cfg_hi cfg_hi; | |
20dd6390 | 585 | enum dma_slave_buswidth width; |
b3c567e4 VK |
586 | |
587 | pr_debug("MDMA: Prep for memcpy\n"); | |
8b649223 | 588 | BUG_ON(!chan); |
b3c567e4 VK |
589 | if (!len) |
590 | return NULL; | |
591 | ||
b3c567e4 | 592 | midc = to_intel_mid_dma_chan(chan); |
8b649223 | 593 | BUG_ON(!midc); |
b3c567e4 | 594 | |
20dd6390 KV |
595 | mids = midc->mid_slave; |
596 | BUG_ON(!mids); | |
597 | ||
b3c567e4 VK |
598 | pr_debug("MDMA:called for DMA %x CH %d Length %zu\n", |
599 | midc->dma->pci_id, midc->ch_id, len); | |
600 | pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n", | |
20dd6390 KV |
601 | mids->cfg_mode, mids->dma_slave.direction, |
602 | mids->hs_mode, mids->dma_slave.src_addr_width); | |
b3c567e4 VK |
603 | |
604 | /*calculate CFG_LO*/ | |
605 | if (mids->hs_mode == LNW_DMA_SW_HS) { | |
606 | cfg_lo.cfg_lo = 0; | |
607 | cfg_lo.cfgx.hs_sel_dst = 1; | |
608 | cfg_lo.cfgx.hs_sel_src = 1; | |
609 | } else if (mids->hs_mode == LNW_DMA_HW_HS) | |
610 | cfg_lo.cfg_lo = 0x00000; | |
611 | ||
612 | /*calculate CFG_HI*/ | |
613 | if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) { | |
614 | /*SW HS only*/ | |
615 | cfg_hi.cfg_hi = 0; | |
616 | } else { | |
617 | cfg_hi.cfg_hi = 0; | |
618 | if (midc->dma->pimr_mask) { | |
619 | cfg_hi.cfgx.protctl = 0x0; /*default value*/ | |
620 | cfg_hi.cfgx.fifo_mode = 1; | |
db8196df | 621 | if (mids->dma_slave.direction == DMA_MEM_TO_DEV) { |
b3c567e4 VK |
622 | cfg_hi.cfgx.src_per = 0; |
623 | if (mids->device_instance == 0) | |
624 | cfg_hi.cfgx.dst_per = 3; | |
625 | if (mids->device_instance == 1) | |
626 | cfg_hi.cfgx.dst_per = 1; | |
db8196df | 627 | } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) { |
b3c567e4 VK |
628 | if (mids->device_instance == 0) |
629 | cfg_hi.cfgx.src_per = 2; | |
630 | if (mids->device_instance == 1) | |
631 | cfg_hi.cfgx.src_per = 0; | |
632 | cfg_hi.cfgx.dst_per = 0; | |
633 | } | |
634 | } else { | |
635 | cfg_hi.cfgx.protctl = 0x1; /*default value*/ | |
636 | cfg_hi.cfgx.src_per = cfg_hi.cfgx.dst_per = | |
637 | midc->ch_id - midc->dma->chan_base; | |
638 | } | |
639 | } | |
640 | ||
641 | /*calculate CTL_HI*/ | |
642 | ctl_hi.ctlx.reser = 0; | |
576e3c39 | 643 | ctl_hi.ctlx.done = 0; |
20dd6390 | 644 | width = mids->dma_slave.src_addr_width; |
b3c567e4 VK |
645 | |
646 | ctl_hi.ctlx.block_ts = get_block_ts(len, width, midc->dma->block_size); | |
647 | pr_debug("MDMA:calc len %d for block size %d\n", | |
648 | ctl_hi.ctlx.block_ts, midc->dma->block_size); | |
649 | /*calculate CTL_LO*/ | |
650 | ctl_lo.ctl_lo = 0; | |
651 | ctl_lo.ctlx.int_en = 1; | |
20dd6390 KV |
652 | ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst; |
653 | ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst; | |
b3c567e4 | 654 | |
0be035f3 FT |
655 | /* |
656 | * Here we need some translation from "enum dma_slave_buswidth" | |
657 | * to the format for our dma controller | |
658 | * standard intel_mid_dmac's format | |
659 | * 1 Byte 0b000 | |
660 | * 2 Bytes 0b001 | |
661 | * 4 Bytes 0b010 | |
662 | */ | |
663 | ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2; | |
664 | ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2; | |
665 | ||
b3c567e4 VK |
666 | if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) { |
667 | ctl_lo.ctlx.tt_fc = 0; | |
668 | ctl_lo.ctlx.sinc = 0; | |
669 | ctl_lo.ctlx.dinc = 0; | |
670 | } else { | |
db8196df | 671 | if (mids->dma_slave.direction == DMA_MEM_TO_DEV) { |
b3c567e4 VK |
672 | ctl_lo.ctlx.sinc = 0; |
673 | ctl_lo.ctlx.dinc = 2; | |
674 | ctl_lo.ctlx.tt_fc = 1; | |
db8196df | 675 | } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) { |
b3c567e4 VK |
676 | ctl_lo.ctlx.sinc = 2; |
677 | ctl_lo.ctlx.dinc = 0; | |
678 | ctl_lo.ctlx.tt_fc = 2; | |
679 | } | |
680 | } | |
681 | ||
682 | pr_debug("MDMA:Calc CTL LO %x, CTL HI %x, CFG LO %x, CFG HI %x\n", | |
683 | ctl_lo.ctl_lo, ctl_hi.ctl_hi, cfg_lo.cfg_lo, cfg_hi.cfg_hi); | |
684 | ||
685 | enable_dma_interrupt(midc); | |
686 | ||
687 | desc = midc_desc_get(midc); | |
688 | if (desc == NULL) | |
689 | goto err_desc_get; | |
690 | desc->sar = src; | |
691 | desc->dar = dest ; | |
692 | desc->len = len; | |
693 | desc->cfg_hi = cfg_hi.cfg_hi; | |
694 | desc->cfg_lo = cfg_lo.cfg_lo; | |
695 | desc->ctl_lo = ctl_lo.ctl_lo; | |
696 | desc->ctl_hi = ctl_hi.ctl_hi; | |
697 | desc->width = width; | |
20dd6390 | 698 | desc->dirn = mids->dma_slave.direction; |
576e3c39 RB |
699 | desc->lli_phys = 0; |
700 | desc->lli = NULL; | |
701 | desc->lli_pool = NULL; | |
b3c567e4 VK |
702 | return &desc->txd; |
703 | ||
704 | err_desc_get: | |
705 | pr_err("ERR_MDMA: Failed to get desc\n"); | |
706 | midc_desc_put(midc, desc); | |
707 | return NULL; | |
708 | } | |
576e3c39 RB |
709 | /** |
710 | * intel_mid_dma_prep_slave_sg - Prep slave sg txn | |
711 | * @chan: chan for DMA transfer | |
712 | * @sgl: scatter gather list | |
713 | * @sg_len: length of sg txn | |
714 | * @direction: DMA transfer dirtn | |
715 | * @flags: DMA flags | |
716 | * | |
717 | * Prepares LLI based periphral transfer | |
718 | */ | |
719 | static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg( | |
720 | struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 721 | unsigned int sg_len, enum dma_transfer_direction direction, |
576e3c39 RB |
722 | unsigned long flags) |
723 | { | |
724 | struct intel_mid_dma_chan *midc = NULL; | |
725 | struct intel_mid_dma_slave *mids = NULL; | |
726 | struct intel_mid_dma_desc *desc = NULL; | |
727 | struct dma_async_tx_descriptor *txd = NULL; | |
728 | union intel_mid_dma_ctl_lo ctl_lo; | |
729 | ||
730 | pr_debug("MDMA: Prep for slave SG\n"); | |
731 | ||
732 | if (!sg_len) { | |
733 | pr_err("MDMA: Invalid SG length\n"); | |
734 | return NULL; | |
735 | } | |
736 | midc = to_intel_mid_dma_chan(chan); | |
737 | BUG_ON(!midc); | |
738 | ||
20dd6390 | 739 | mids = midc->mid_slave; |
576e3c39 RB |
740 | BUG_ON(!mids); |
741 | ||
742 | if (!midc->dma->pimr_mask) { | |
0be035f3 FT |
743 | /* We can still handle sg list with only one item */ |
744 | if (sg_len == 1) { | |
745 | txd = intel_mid_dma_prep_memcpy(chan, | |
746 | mids->dma_slave.dst_addr, | |
747 | mids->dma_slave.src_addr, | |
748 | sgl->length, | |
749 | flags); | |
750 | return txd; | |
751 | } else { | |
752 | pr_warn("MDMA: SG list is not supported by this controller\n"); | |
753 | return NULL; | |
754 | } | |
576e3c39 RB |
755 | } |
756 | ||
757 | pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n", | |
758 | sg_len, direction, flags); | |
759 | ||
760 | txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags); | |
761 | if (NULL == txd) { | |
762 | pr_err("MDMA: Prep memcpy failed\n"); | |
763 | return NULL; | |
764 | } | |
0be035f3 | 765 | |
576e3c39 RB |
766 | desc = to_intel_mid_dma_desc(txd); |
767 | desc->dirn = direction; | |
768 | ctl_lo.ctl_lo = desc->ctl_lo; | |
769 | ctl_lo.ctlx.llp_dst_en = 1; | |
770 | ctl_lo.ctlx.llp_src_en = 1; | |
771 | desc->ctl_lo = ctl_lo.ctl_lo; | |
772 | desc->lli_length = sg_len; | |
773 | desc->current_lli = 0; | |
774 | /* DMA coherent memory pool for LLI descriptors*/ | |
775 | desc->lli_pool = pci_pool_create("intel_mid_dma_lli_pool", | |
776 | midc->dma->pdev, | |
777 | (sizeof(struct intel_mid_dma_lli)*sg_len), | |
778 | 32, 0); | |
779 | if (NULL == desc->lli_pool) { | |
780 | pr_err("MID_DMA:LLI pool create failed\n"); | |
781 | return NULL; | |
782 | } | |
783 | ||
784 | desc->lli = pci_pool_alloc(desc->lli_pool, GFP_KERNEL, &desc->lli_phys); | |
785 | if (!desc->lli) { | |
786 | pr_err("MID_DMA: LLI alloc failed\n"); | |
787 | pci_pool_destroy(desc->lli_pool); | |
788 | return NULL; | |
789 | } | |
790 | ||
791 | midc_lli_fill_sg(midc, desc, sgl, sg_len, flags); | |
792 | if (flags & DMA_PREP_INTERRUPT) { | |
793 | iowrite32(UNMASK_INTR_REG(midc->ch_id), | |
794 | midc->dma_base + MASK_BLOCK); | |
795 | pr_debug("MDMA:Enabled Block interrupt\n"); | |
796 | } | |
797 | return &desc->txd; | |
798 | } | |
b3c567e4 VK |
799 | |
800 | /** | |
801 | * intel_mid_dma_free_chan_resources - Frees dma resources | |
802 | * @chan: chan requiring attention | |
803 | * | |
804 | * Frees the allocated resources on this DMA chan | |
805 | */ | |
806 | static void intel_mid_dma_free_chan_resources(struct dma_chan *chan) | |
807 | { | |
808 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan); | |
809 | struct middma_device *mid = to_middma_device(chan->device); | |
810 | struct intel_mid_dma_desc *desc, *_desc; | |
811 | ||
53a61bad | 812 | if (true == midc->busy) { |
b3c567e4 VK |
813 | /*trying to free ch in use!!!!!*/ |
814 | pr_err("ERR_MDMA: trying to free ch in use\n"); | |
815 | } | |
b3c567e4 VK |
816 | spin_lock_bh(&midc->lock); |
817 | midc->descs_allocated = 0; | |
818 | list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) { | |
819 | list_del(&desc->desc_node); | |
820 | pci_pool_free(mid->dma_pool, desc, desc->txd.phys); | |
821 | } | |
822 | list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) { | |
823 | list_del(&desc->desc_node); | |
824 | pci_pool_free(mid->dma_pool, desc, desc->txd.phys); | |
825 | } | |
826 | list_for_each_entry_safe(desc, _desc, &midc->queue, desc_node) { | |
827 | list_del(&desc->desc_node); | |
828 | pci_pool_free(mid->dma_pool, desc, desc->txd.phys); | |
829 | } | |
830 | spin_unlock_bh(&midc->lock); | |
831 | midc->in_use = false; | |
53a61bad | 832 | midc->busy = false; |
b3c567e4 VK |
833 | /* Disable CH interrupts */ |
834 | iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK); | |
835 | iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR); | |
91c1c9e3 | 836 | pm_runtime_put(&mid->pdev->dev); |
b3c567e4 VK |
837 | } |
838 | ||
839 | /** | |
840 | * intel_mid_dma_alloc_chan_resources - Allocate dma resources | |
841 | * @chan: chan requiring attention | |
842 | * | |
843 | * Allocates DMA resources on this chan | |
844 | * Return the descriptors allocated | |
845 | */ | |
846 | static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan) | |
847 | { | |
848 | struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan); | |
849 | struct middma_device *mid = to_middma_device(chan->device); | |
850 | struct intel_mid_dma_desc *desc; | |
851 | dma_addr_t phys; | |
852 | int i = 0; | |
853 | ||
53a61bad KV |
854 | pm_runtime_get_sync(&mid->pdev->dev); |
855 | ||
856 | if (mid->state == SUSPENDED) { | |
8730790b | 857 | if (dma_resume(&mid->pdev->dev)) { |
53a61bad KV |
858 | pr_err("ERR_MDMA: resume failed"); |
859 | return -EFAULT; | |
860 | } | |
861 | } | |
b3c567e4 VK |
862 | |
863 | /* ASSERT: channel is idle */ | |
864 | if (test_ch_en(mid->dma_base, midc->ch_id)) { | |
865 | /*ch is not idle*/ | |
866 | pr_err("ERR_MDMA: ch not idle\n"); | |
53a61bad | 867 | pm_runtime_put(&mid->pdev->dev); |
b3c567e4 VK |
868 | return -EIO; |
869 | } | |
4d4e58de | 870 | chan->completed_cookie = chan->cookie = 1; |
b3c567e4 VK |
871 | |
872 | spin_lock_bh(&midc->lock); | |
873 | while (midc->descs_allocated < DESCS_PER_CHANNEL) { | |
874 | spin_unlock_bh(&midc->lock); | |
875 | desc = pci_pool_alloc(mid->dma_pool, GFP_KERNEL, &phys); | |
876 | if (!desc) { | |
877 | pr_err("ERR_MDMA: desc failed\n"); | |
53a61bad | 878 | pm_runtime_put(&mid->pdev->dev); |
b3c567e4 VK |
879 | return -ENOMEM; |
880 | /*check*/ | |
881 | } | |
882 | dma_async_tx_descriptor_init(&desc->txd, chan); | |
883 | desc->txd.tx_submit = intel_mid_dma_tx_submit; | |
884 | desc->txd.flags = DMA_CTRL_ACK; | |
885 | desc->txd.phys = phys; | |
886 | spin_lock_bh(&midc->lock); | |
887 | i = ++midc->descs_allocated; | |
888 | list_add_tail(&desc->desc_node, &midc->free_list); | |
889 | } | |
890 | spin_unlock_bh(&midc->lock); | |
53a61bad KV |
891 | midc->in_use = true; |
892 | midc->busy = false; | |
b3c567e4 VK |
893 | pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i); |
894 | return i; | |
895 | } | |
896 | ||
897 | /** | |
898 | * midc_handle_error - Handle DMA txn error | |
25985edc LDM |
899 | * @mid: controller where error occurred |
900 | * @midc: chan where error occurred | |
b3c567e4 VK |
901 | * |
902 | * Scan the descriptor for error | |
903 | */ | |
904 | static void midc_handle_error(struct middma_device *mid, | |
905 | struct intel_mid_dma_chan *midc) | |
906 | { | |
907 | midc_scan_descriptors(mid, midc); | |
908 | } | |
909 | ||
910 | /** | |
911 | * dma_tasklet - DMA interrupt tasklet | |
912 | * @data: tasklet arg (the controller structure) | |
913 | * | |
914 | * Scan the controller for interrupts for completion/error | |
915 | * Clear the interrupt and call for handling completion/error | |
916 | */ | |
917 | static void dma_tasklet(unsigned long data) | |
918 | { | |
919 | struct middma_device *mid = NULL; | |
920 | struct intel_mid_dma_chan *midc = NULL; | |
576e3c39 | 921 | u32 status, raw_tfr, raw_block; |
b3c567e4 VK |
922 | int i; |
923 | ||
924 | mid = (struct middma_device *)data; | |
925 | if (mid == NULL) { | |
926 | pr_err("ERR_MDMA: tasklet Null param\n"); | |
927 | return; | |
928 | } | |
929 | pr_debug("MDMA: in tasklet for device %x\n", mid->pci_id); | |
576e3c39 RB |
930 | raw_tfr = ioread32(mid->dma_base + RAW_TFR); |
931 | raw_block = ioread32(mid->dma_base + RAW_BLOCK); | |
932 | status = raw_tfr | raw_block; | |
b3c567e4 VK |
933 | status &= mid->intr_mask; |
934 | while (status) { | |
935 | /*txn interrupt*/ | |
936 | i = get_ch_index(&status, mid->chan_base); | |
937 | if (i < 0) { | |
938 | pr_err("ERR_MDMA:Invalid ch index %x\n", i); | |
939 | return; | |
940 | } | |
941 | midc = &mid->ch[i]; | |
942 | if (midc == NULL) { | |
943 | pr_err("ERR_MDMA:Null param midc\n"); | |
944 | return; | |
945 | } | |
946 | pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n", | |
947 | status, midc->ch_id, i); | |
576e3c39 RB |
948 | midc->raw_tfr = raw_tfr; |
949 | midc->raw_block = raw_block; | |
950 | spin_lock_bh(&midc->lock); | |
b3c567e4 VK |
951 | /*clearing this interrupts first*/ |
952 | iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_TFR); | |
576e3c39 RB |
953 | if (raw_block) { |
954 | iowrite32((1 << midc->ch_id), | |
955 | mid->dma_base + CLEAR_BLOCK); | |
956 | } | |
b3c567e4 VK |
957 | midc_scan_descriptors(mid, midc); |
958 | pr_debug("MDMA:Scan of desc... complete, unmasking\n"); | |
959 | iowrite32(UNMASK_INTR_REG(midc->ch_id), | |
960 | mid->dma_base + MASK_TFR); | |
576e3c39 RB |
961 | if (raw_block) { |
962 | iowrite32(UNMASK_INTR_REG(midc->ch_id), | |
963 | mid->dma_base + MASK_BLOCK); | |
964 | } | |
b3c567e4 VK |
965 | spin_unlock_bh(&midc->lock); |
966 | } | |
967 | ||
968 | status = ioread32(mid->dma_base + RAW_ERR); | |
969 | status &= mid->intr_mask; | |
970 | while (status) { | |
971 | /*err interrupt*/ | |
972 | i = get_ch_index(&status, mid->chan_base); | |
973 | if (i < 0) { | |
974 | pr_err("ERR_MDMA:Invalid ch index %x\n", i); | |
975 | return; | |
976 | } | |
977 | midc = &mid->ch[i]; | |
978 | if (midc == NULL) { | |
979 | pr_err("ERR_MDMA:Null param midc\n"); | |
980 | return; | |
981 | } | |
982 | pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n", | |
983 | status, midc->ch_id, i); | |
984 | ||
985 | iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_ERR); | |
986 | spin_lock_bh(&midc->lock); | |
987 | midc_handle_error(mid, midc); | |
988 | iowrite32(UNMASK_INTR_REG(midc->ch_id), | |
989 | mid->dma_base + MASK_ERR); | |
990 | spin_unlock_bh(&midc->lock); | |
991 | } | |
992 | pr_debug("MDMA:Exiting takslet...\n"); | |
993 | return; | |
994 | } | |
995 | ||
996 | static void dma_tasklet1(unsigned long data) | |
997 | { | |
998 | pr_debug("MDMA:in takslet1...\n"); | |
999 | return dma_tasklet(data); | |
1000 | } | |
1001 | ||
1002 | static void dma_tasklet2(unsigned long data) | |
1003 | { | |
1004 | pr_debug("MDMA:in takslet2...\n"); | |
1005 | return dma_tasklet(data); | |
1006 | } | |
1007 | ||
1008 | /** | |
1009 | * intel_mid_dma_interrupt - DMA ISR | |
1010 | * @irq: IRQ where interrupt occurred | |
1011 | * @data: ISR cllback data (the controller structure) | |
1012 | * | |
1013 | * See if this is our interrupt if so then schedule the tasklet | |
1014 | * otherwise ignore | |
1015 | */ | |
1016 | static irqreturn_t intel_mid_dma_interrupt(int irq, void *data) | |
1017 | { | |
1018 | struct middma_device *mid = data; | |
b306df5e | 1019 | u32 tfr_status, err_status; |
b3c567e4 VK |
1020 | int call_tasklet = 0; |
1021 | ||
b306df5e YW |
1022 | tfr_status = ioread32(mid->dma_base + RAW_TFR); |
1023 | err_status = ioread32(mid->dma_base + RAW_ERR); | |
1024 | if (!tfr_status && !err_status) | |
1025 | return IRQ_NONE; | |
1026 | ||
b3c567e4 VK |
1027 | /*DMA Interrupt*/ |
1028 | pr_debug("MDMA:Got an interrupt on irq %d\n", irq); | |
b306df5e YW |
1029 | pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask); |
1030 | tfr_status &= mid->intr_mask; | |
1031 | if (tfr_status) { | |
b3c567e4 | 1032 | /*need to disable intr*/ |
576e3c39 RB |
1033 | iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_TFR); |
1034 | iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_BLOCK); | |
b306df5e | 1035 | pr_debug("MDMA: Calling tasklet %x\n", tfr_status); |
b3c567e4 VK |
1036 | call_tasklet = 1; |
1037 | } | |
b306df5e YW |
1038 | err_status &= mid->intr_mask; |
1039 | if (err_status) { | |
7f99a421 AH |
1040 | iowrite32((err_status << INT_MASK_WE), |
1041 | mid->dma_base + MASK_ERR); | |
b3c567e4 VK |
1042 | call_tasklet = 1; |
1043 | } | |
1044 | if (call_tasklet) | |
1045 | tasklet_schedule(&mid->tasklet); | |
1046 | ||
1047 | return IRQ_HANDLED; | |
1048 | } | |
1049 | ||
1050 | static irqreturn_t intel_mid_dma_interrupt1(int irq, void *data) | |
1051 | { | |
1052 | return intel_mid_dma_interrupt(irq, data); | |
1053 | } | |
1054 | ||
1055 | static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data) | |
1056 | { | |
1057 | return intel_mid_dma_interrupt(irq, data); | |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * mid_setup_dma - Setup the DMA controller | |
1062 | * @pdev: Controller PCI device structure | |
1063 | * | |
b595076a UKK |
1064 | * Initialize the DMA controller, channels, registers with DMA engine, |
1065 | * ISR. Initialize DMA controller channels. | |
b3c567e4 VK |
1066 | */ |
1067 | static int mid_setup_dma(struct pci_dev *pdev) | |
1068 | { | |
1069 | struct middma_device *dma = pci_get_drvdata(pdev); | |
1070 | int err, i; | |
b3c567e4 VK |
1071 | |
1072 | /* DMA coherent memory pool for DMA descriptor allocations */ | |
1073 | dma->dma_pool = pci_pool_create("intel_mid_dma_desc_pool", pdev, | |
1074 | sizeof(struct intel_mid_dma_desc), | |
1075 | 32, 0); | |
1076 | if (NULL == dma->dma_pool) { | |
1077 | pr_err("ERR_MDMA:pci_pool_create failed\n"); | |
1078 | err = -ENOMEM; | |
b3c567e4 VK |
1079 | goto err_dma_pool; |
1080 | } | |
1081 | ||
1082 | INIT_LIST_HEAD(&dma->common.channels); | |
1083 | dma->pci_id = pdev->device; | |
1084 | if (dma->pimr_mask) { | |
1085 | dma->mask_reg = ioremap(LNW_PERIPHRAL_MASK_BASE, | |
1086 | LNW_PERIPHRAL_MASK_SIZE); | |
1087 | if (dma->mask_reg == NULL) { | |
25985edc | 1088 | pr_err("ERR_MDMA:Can't map periphral intr space !!\n"); |
2a0ff7a6 AH |
1089 | err = -ENOMEM; |
1090 | goto err_ioremap; | |
b3c567e4 VK |
1091 | } |
1092 | } else | |
1093 | dma->mask_reg = NULL; | |
1094 | ||
1095 | pr_debug("MDMA:Adding %d channel for this controller\n", dma->max_chan); | |
1096 | /*init CH structures*/ | |
1097 | dma->intr_mask = 0; | |
53a61bad | 1098 | dma->state = RUNNING; |
b3c567e4 VK |
1099 | for (i = 0; i < dma->max_chan; i++) { |
1100 | struct intel_mid_dma_chan *midch = &dma->ch[i]; | |
1101 | ||
1102 | midch->chan.device = &dma->common; | |
1103 | midch->chan.cookie = 1; | |
b3c567e4 VK |
1104 | midch->ch_id = dma->chan_base + i; |
1105 | pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id); | |
1106 | ||
1107 | midch->dma_base = dma->dma_base; | |
1108 | midch->ch_regs = dma->dma_base + DMA_CH_SIZE * midch->ch_id; | |
1109 | midch->dma = dma; | |
1110 | dma->intr_mask |= 1 << (dma->chan_base + i); | |
1111 | spin_lock_init(&midch->lock); | |
1112 | ||
1113 | INIT_LIST_HEAD(&midch->active_list); | |
1114 | INIT_LIST_HEAD(&midch->queue); | |
1115 | INIT_LIST_HEAD(&midch->free_list); | |
1116 | /*mask interrupts*/ | |
1117 | iowrite32(MASK_INTR_REG(midch->ch_id), | |
1118 | dma->dma_base + MASK_BLOCK); | |
1119 | iowrite32(MASK_INTR_REG(midch->ch_id), | |
1120 | dma->dma_base + MASK_SRC_TRAN); | |
1121 | iowrite32(MASK_INTR_REG(midch->ch_id), | |
1122 | dma->dma_base + MASK_DST_TRAN); | |
1123 | iowrite32(MASK_INTR_REG(midch->ch_id), | |
1124 | dma->dma_base + MASK_ERR); | |
1125 | iowrite32(MASK_INTR_REG(midch->ch_id), | |
1126 | dma->dma_base + MASK_TFR); | |
1127 | ||
1128 | disable_dma_interrupt(midch); | |
1129 | list_add_tail(&midch->chan.device_node, &dma->common.channels); | |
1130 | } | |
1131 | pr_debug("MDMA: Calc Mask as %x for this controller\n", dma->intr_mask); | |
1132 | ||
1133 | /*init dma structure*/ | |
1134 | dma_cap_zero(dma->common.cap_mask); | |
1135 | dma_cap_set(DMA_MEMCPY, dma->common.cap_mask); | |
1136 | dma_cap_set(DMA_SLAVE, dma->common.cap_mask); | |
1137 | dma_cap_set(DMA_PRIVATE, dma->common.cap_mask); | |
1138 | dma->common.dev = &pdev->dev; | |
b3c567e4 VK |
1139 | |
1140 | dma->common.device_alloc_chan_resources = | |
1141 | intel_mid_dma_alloc_chan_resources; | |
1142 | dma->common.device_free_chan_resources = | |
1143 | intel_mid_dma_free_chan_resources; | |
1144 | ||
1145 | dma->common.device_tx_status = intel_mid_dma_tx_status; | |
1146 | dma->common.device_prep_dma_memcpy = intel_mid_dma_prep_memcpy; | |
1147 | dma->common.device_issue_pending = intel_mid_dma_issue_pending; | |
1148 | dma->common.device_prep_slave_sg = intel_mid_dma_prep_slave_sg; | |
1149 | dma->common.device_control = intel_mid_dma_device_control; | |
1150 | ||
1151 | /*enable dma cntrl*/ | |
1152 | iowrite32(REG_BIT0, dma->dma_base + DMA_CFG); | |
1153 | ||
1154 | /*register irq */ | |
1155 | if (dma->pimr_mask) { | |
b3c567e4 VK |
1156 | pr_debug("MDMA:Requesting irq shared for DMAC1\n"); |
1157 | err = request_irq(pdev->irq, intel_mid_dma_interrupt1, | |
1158 | IRQF_SHARED, "INTEL_MID_DMAC1", dma); | |
1159 | if (0 != err) | |
1160 | goto err_irq; | |
1161 | } else { | |
1162 | dma->intr_mask = 0x03; | |
b3c567e4 VK |
1163 | pr_debug("MDMA:Requesting irq for DMAC2\n"); |
1164 | err = request_irq(pdev->irq, intel_mid_dma_interrupt2, | |
03b96dca | 1165 | IRQF_SHARED, "INTEL_MID_DMAC2", dma); |
b3c567e4 VK |
1166 | if (0 != err) |
1167 | goto err_irq; | |
1168 | } | |
1169 | /*register device w/ engine*/ | |
1170 | err = dma_async_device_register(&dma->common); | |
1171 | if (0 != err) { | |
1172 | pr_err("ERR_MDMA:device_register failed: %d\n", err); | |
1173 | goto err_engine; | |
1174 | } | |
1175 | if (dma->pimr_mask) { | |
1176 | pr_debug("setting up tasklet1 for DMAC1\n"); | |
1177 | tasklet_init(&dma->tasklet, dma_tasklet1, (unsigned long)dma); | |
1178 | } else { | |
1179 | pr_debug("setting up tasklet2 for DMAC2\n"); | |
1180 | tasklet_init(&dma->tasklet, dma_tasklet2, (unsigned long)dma); | |
1181 | } | |
1182 | return 0; | |
1183 | ||
1184 | err_engine: | |
1185 | free_irq(pdev->irq, dma); | |
1186 | err_irq: | |
2a0ff7a6 AH |
1187 | if (dma->mask_reg) |
1188 | iounmap(dma->mask_reg); | |
1189 | err_ioremap: | |
b3c567e4 | 1190 | pci_pool_destroy(dma->dma_pool); |
b3c567e4 VK |
1191 | err_dma_pool: |
1192 | pr_err("ERR_MDMA:setup_dma failed: %d\n", err); | |
1193 | return err; | |
1194 | ||
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * middma_shutdown - Shutdown the DMA controller | |
1199 | * @pdev: Controller PCI device structure | |
1200 | * | |
1201 | * Called by remove | |
1202 | * Unregister DMa controller, clear all structures and free interrupt | |
1203 | */ | |
1204 | static void middma_shutdown(struct pci_dev *pdev) | |
1205 | { | |
1206 | struct middma_device *device = pci_get_drvdata(pdev); | |
1207 | ||
1208 | dma_async_device_unregister(&device->common); | |
1209 | pci_pool_destroy(device->dma_pool); | |
1210 | if (device->mask_reg) | |
1211 | iounmap(device->mask_reg); | |
1212 | if (device->dma_base) | |
1213 | iounmap(device->dma_base); | |
1214 | free_irq(pdev->irq, device); | |
1215 | return; | |
1216 | } | |
1217 | ||
1218 | /** | |
1219 | * intel_mid_dma_probe - PCI Probe | |
1220 | * @pdev: Controller PCI device structure | |
1221 | * @id: pci device id structure | |
1222 | * | |
b595076a | 1223 | * Initialize the PCI device, map BARs, query driver data. |
b3c567e4 VK |
1224 | * Call setup_dma to complete contoller and chan initilzation |
1225 | */ | |
1226 | static int __devinit intel_mid_dma_probe(struct pci_dev *pdev, | |
1227 | const struct pci_device_id *id) | |
1228 | { | |
1229 | struct middma_device *device; | |
1230 | u32 base_addr, bar_size; | |
1231 | struct intel_mid_dma_probe_info *info; | |
1232 | int err; | |
1233 | ||
1234 | pr_debug("MDMA: probe for %x\n", pdev->device); | |
1235 | info = (void *)id->driver_data; | |
1236 | pr_debug("MDMA: CH %d, base %d, block len %d, Periphral mask %x\n", | |
1237 | info->max_chan, info->ch_base, | |
1238 | info->block_size, info->pimr_mask); | |
1239 | ||
1240 | err = pci_enable_device(pdev); | |
1241 | if (err) | |
1242 | goto err_enable_device; | |
1243 | ||
1244 | err = pci_request_regions(pdev, "intel_mid_dmac"); | |
1245 | if (err) | |
1246 | goto err_request_regions; | |
1247 | ||
1248 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1249 | if (err) | |
1250 | goto err_set_dma_mask; | |
1251 | ||
1252 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
1253 | if (err) | |
1254 | goto err_set_dma_mask; | |
1255 | ||
1256 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
1257 | if (!device) { | |
1258 | pr_err("ERR_MDMA:kzalloc failed probe\n"); | |
1259 | err = -ENOMEM; | |
1260 | goto err_kzalloc; | |
1261 | } | |
1262 | device->pdev = pci_dev_get(pdev); | |
1263 | ||
1264 | base_addr = pci_resource_start(pdev, 0); | |
1265 | bar_size = pci_resource_len(pdev, 0); | |
1266 | device->dma_base = ioremap_nocache(base_addr, DMA_REG_SIZE); | |
1267 | if (!device->dma_base) { | |
1268 | pr_err("ERR_MDMA:ioremap failed\n"); | |
1269 | err = -ENOMEM; | |
1270 | goto err_ioremap; | |
1271 | } | |
1272 | pci_set_drvdata(pdev, device); | |
1273 | pci_set_master(pdev); | |
1274 | device->max_chan = info->max_chan; | |
1275 | device->chan_base = info->ch_base; | |
1276 | device->block_size = info->block_size; | |
1277 | device->pimr_mask = info->pimr_mask; | |
1278 | ||
1279 | err = mid_setup_dma(pdev); | |
1280 | if (err) | |
1281 | goto err_dma; | |
1282 | ||
e2142df7 | 1283 | pm_runtime_put_noidle(&pdev->dev); |
53a61bad | 1284 | pm_runtime_allow(&pdev->dev); |
b3c567e4 VK |
1285 | return 0; |
1286 | ||
1287 | err_dma: | |
1288 | iounmap(device->dma_base); | |
1289 | err_ioremap: | |
1290 | pci_dev_put(pdev); | |
1291 | kfree(device); | |
1292 | err_kzalloc: | |
1293 | err_set_dma_mask: | |
1294 | pci_release_regions(pdev); | |
1295 | pci_disable_device(pdev); | |
1296 | err_request_regions: | |
1297 | err_enable_device: | |
1298 | pr_err("ERR_MDMA:Probe failed %d\n", err); | |
1299 | return err; | |
1300 | } | |
1301 | ||
1302 | /** | |
1303 | * intel_mid_dma_remove - PCI remove | |
1304 | * @pdev: Controller PCI device structure | |
1305 | * | |
1306 | * Free up all resources and data | |
1307 | * Call shutdown_dma to complete contoller and chan cleanup | |
1308 | */ | |
1309 | static void __devexit intel_mid_dma_remove(struct pci_dev *pdev) | |
1310 | { | |
1311 | struct middma_device *device = pci_get_drvdata(pdev); | |
e2142df7 KCA |
1312 | |
1313 | pm_runtime_get_noresume(&pdev->dev); | |
1314 | pm_runtime_forbid(&pdev->dev); | |
b3c567e4 VK |
1315 | middma_shutdown(pdev); |
1316 | pci_dev_put(pdev); | |
1317 | kfree(device); | |
1318 | pci_release_regions(pdev); | |
1319 | pci_disable_device(pdev); | |
1320 | } | |
1321 | ||
53a61bad KV |
1322 | /* Power Management */ |
1323 | /* | |
1324 | * dma_suspend - PCI suspend function | |
1325 | * | |
1326 | * @pci: PCI device structure | |
1327 | * @state: PM message | |
1328 | * | |
1329 | * This function is called by OS when a power event occurs | |
1330 | */ | |
8730790b | 1331 | static int dma_suspend(struct device *dev) |
53a61bad | 1332 | { |
8730790b | 1333 | struct pci_dev *pci = to_pci_dev(dev); |
53a61bad KV |
1334 | int i; |
1335 | struct middma_device *device = pci_get_drvdata(pci); | |
1336 | pr_debug("MDMA: dma_suspend called\n"); | |
1337 | ||
1338 | for (i = 0; i < device->max_chan; i++) { | |
1339 | if (device->ch[i].in_use) | |
1340 | return -EAGAIN; | |
1341 | } | |
4598fc2c | 1342 | dmac1_mask_periphral_intr(device); |
53a61bad | 1343 | device->state = SUSPENDED; |
53a61bad KV |
1344 | pci_save_state(pci); |
1345 | pci_disable_device(pci); | |
1346 | pci_set_power_state(pci, PCI_D3hot); | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | /** | |
1351 | * dma_resume - PCI resume function | |
1352 | * | |
1353 | * @pci: PCI device structure | |
1354 | * | |
1355 | * This function is called by OS when a power event occurs | |
1356 | */ | |
8730790b | 1357 | int dma_resume(struct device *dev) |
53a61bad | 1358 | { |
8730790b | 1359 | struct pci_dev *pci = to_pci_dev(dev); |
53a61bad KV |
1360 | int ret; |
1361 | struct middma_device *device = pci_get_drvdata(pci); | |
1362 | ||
1363 | pr_debug("MDMA: dma_resume called\n"); | |
1364 | pci_set_power_state(pci, PCI_D0); | |
1365 | pci_restore_state(pci); | |
1366 | ret = pci_enable_device(pci); | |
1367 | if (ret) { | |
25985edc | 1368 | pr_err("MDMA: device can't be enabled for %x\n", pci->device); |
53a61bad KV |
1369 | return ret; |
1370 | } | |
1371 | device->state = RUNNING; | |
1372 | iowrite32(REG_BIT0, device->dma_base + DMA_CFG); | |
53a61bad KV |
1373 | return 0; |
1374 | } | |
1375 | ||
1376 | static int dma_runtime_suspend(struct device *dev) | |
1377 | { | |
1378 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
e2142df7 KCA |
1379 | struct middma_device *device = pci_get_drvdata(pci_dev); |
1380 | ||
1381 | device->state = SUSPENDED; | |
1382 | return 0; | |
53a61bad KV |
1383 | } |
1384 | ||
1385 | static int dma_runtime_resume(struct device *dev) | |
1386 | { | |
1387 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
e2142df7 KCA |
1388 | struct middma_device *device = pci_get_drvdata(pci_dev); |
1389 | ||
1390 | device->state = RUNNING; | |
1391 | iowrite32(REG_BIT0, device->dma_base + DMA_CFG); | |
1392 | return 0; | |
53a61bad KV |
1393 | } |
1394 | ||
1395 | static int dma_runtime_idle(struct device *dev) | |
1396 | { | |
1397 | struct pci_dev *pdev = to_pci_dev(dev); | |
1398 | struct middma_device *device = pci_get_drvdata(pdev); | |
1399 | int i; | |
1400 | ||
1401 | for (i = 0; i < device->max_chan; i++) { | |
1402 | if (device->ch[i].in_use) | |
1403 | return -EAGAIN; | |
1404 | } | |
1405 | ||
1406 | return pm_schedule_suspend(dev, 0); | |
1407 | } | |
1408 | ||
b3c567e4 VK |
1409 | /****************************************************************************** |
1410 | * PCI stuff | |
1411 | */ | |
1412 | static struct pci_device_id intel_mid_dma_ids[] = { | |
1413 | { PCI_VDEVICE(INTEL, INTEL_MID_DMAC1_ID), INFO(2, 6, 4095, 0x200020)}, | |
1414 | { PCI_VDEVICE(INTEL, INTEL_MID_DMAC2_ID), INFO(2, 0, 2047, 0)}, | |
1415 | { PCI_VDEVICE(INTEL, INTEL_MID_GP_DMAC2_ID), INFO(2, 0, 2047, 0)}, | |
1416 | { PCI_VDEVICE(INTEL, INTEL_MFLD_DMAC1_ID), INFO(4, 0, 4095, 0x400040)}, | |
1417 | { 0, } | |
1418 | }; | |
1419 | MODULE_DEVICE_TABLE(pci, intel_mid_dma_ids); | |
1420 | ||
53a61bad KV |
1421 | static const struct dev_pm_ops intel_mid_dma_pm = { |
1422 | .runtime_suspend = dma_runtime_suspend, | |
1423 | .runtime_resume = dma_runtime_resume, | |
1424 | .runtime_idle = dma_runtime_idle, | |
8730790b KCA |
1425 | .suspend = dma_suspend, |
1426 | .resume = dma_resume, | |
53a61bad KV |
1427 | }; |
1428 | ||
cf2f9c59 | 1429 | static struct pci_driver intel_mid_dma_pci_driver = { |
b3c567e4 VK |
1430 | .name = "Intel MID DMA", |
1431 | .id_table = intel_mid_dma_ids, | |
1432 | .probe = intel_mid_dma_probe, | |
1433 | .remove = __devexit_p(intel_mid_dma_remove), | |
53a61bad | 1434 | #ifdef CONFIG_PM |
53a61bad KV |
1435 | .driver = { |
1436 | .pm = &intel_mid_dma_pm, | |
1437 | }, | |
1438 | #endif | |
b3c567e4 VK |
1439 | }; |
1440 | ||
1441 | static int __init intel_mid_dma_init(void) | |
1442 | { | |
1443 | pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n", | |
1444 | INTEL_MID_DMA_DRIVER_VERSION); | |
cf2f9c59 | 1445 | return pci_register_driver(&intel_mid_dma_pci_driver); |
b3c567e4 VK |
1446 | } |
1447 | fs_initcall(intel_mid_dma_init); | |
1448 | ||
1449 | static void __exit intel_mid_dma_exit(void) | |
1450 | { | |
cf2f9c59 | 1451 | pci_unregister_driver(&intel_mid_dma_pci_driver); |
b3c567e4 VK |
1452 | } |
1453 | module_exit(intel_mid_dma_exit); | |
1454 | ||
1455 | MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>"); | |
1456 | MODULE_DESCRIPTION("Intel (R) MID DMAC Driver"); | |
1457 | MODULE_LICENSE("GPL v2"); | |
1458 | MODULE_VERSION(INTEL_MID_DMA_DRIVER_VERSION); |