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Commit | Line | Data |
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0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
85596a19 | 3 | * Copyright(c) 2004 - 2015 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
43d6e369 SN |
14 | * The full GNU General Public License is included in this distribution in |
15 | * the file called "COPYING". | |
0bbd5f4e | 16 | * |
0bbd5f4e CL |
17 | */ |
18 | ||
19 | /* | |
20 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
21 | * copy operations. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
0bbd5f4e CL |
27 | #include <linux/pci.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/dmaengine.h> | |
30 | #include <linux/delay.h> | |
6b00c92c | 31 | #include <linux/dma-mapping.h> |
09177e85 | 32 | #include <linux/workqueue.h> |
70c71606 | 33 | #include <linux/prefetch.h> |
dd4645eb | 34 | #include <linux/sizes.h> |
584ec227 DW |
35 | #include "dma.h" |
36 | #include "registers.h" | |
37 | #include "hw.h" | |
0bbd5f4e | 38 | |
d2ebfb33 RKAL |
39 | #include "../dmaengine.h" |
40 | ||
aed681d1 | 41 | static char *chanerr_str[] = { |
d46dc995 | 42 | "DMA Transfer Source Address Error", |
aed681d1 DJ |
43 | "DMA Transfer Destination Address Error", |
44 | "Next Descriptor Address Error", | |
45 | "Descriptor Error", | |
46 | "Chan Address Value Error", | |
47 | "CHANCMD Error", | |
48 | "Chipset Uncorrectable Data Integrity Error", | |
49 | "DMA Uncorrectable Data Integrity Error", | |
50 | "Read Data Error", | |
51 | "Write Data Error", | |
52 | "Descriptor Control Error", | |
53 | "Descriptor Transfer Size Error", | |
54 | "Completion Address Error", | |
55 | "Interrupt Configuration Error", | |
56 | "Super extended descriptor Address Error", | |
57 | "Unaffiliated Error", | |
58 | "CRC or XOR P Error", | |
59 | "XOR Q Error", | |
60 | "Descriptor Count Error", | |
61 | "DIF All F detect Error", | |
62 | "Guard Tag verification Error", | |
63 | "Application Tag verification Error", | |
64 | "Reference Tag verification Error", | |
65 | "Bundle Bit Error", | |
66 | "Result DIF All F detect Error", | |
67 | "Result Guard Tag verification Error", | |
68 | "Result Application Tag verification Error", | |
69 | "Result Reference Tag verification Error", | |
aed681d1 DJ |
70 | }; |
71 | ||
3372de58 DJ |
72 | static void ioat_eh(struct ioatdma_chan *ioat_chan); |
73 | ||
aed681d1 DJ |
74 | static void ioat_print_chanerrs(struct ioatdma_chan *ioat_chan, u32 chanerr) |
75 | { | |
76 | int i; | |
77 | ||
1b779416 | 78 | for (i = 0; i < ARRAY_SIZE(chanerr_str); i++) { |
aed681d1 | 79 | if ((chanerr >> i) & 1) { |
1b779416 CIK |
80 | dev_err(to_dev(ioat_chan), "Err(%d): %s\n", |
81 | i, chanerr_str[i]); | |
aed681d1 DJ |
82 | } |
83 | } | |
84 | } | |
85 | ||
3e037454 SN |
86 | /** |
87 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
88 | * @irq: interrupt id | |
89 | * @data: interrupt data | |
90 | */ | |
c0f28ce6 | 91 | irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
3e037454 SN |
92 | { |
93 | struct ioatdma_device *instance = data; | |
5a976888 | 94 | struct ioatdma_chan *ioat_chan; |
3e037454 SN |
95 | unsigned long attnstatus; |
96 | int bit; | |
97 | u8 intrctrl; | |
98 | ||
99 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
100 | ||
101 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
102 | return IRQ_NONE; | |
103 | ||
104 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
105 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
106 | return IRQ_NONE; | |
107 | } | |
108 | ||
109 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
984b3f57 | 110 | for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { |
5a976888 DJ |
111 | ioat_chan = ioat_chan_by_index(instance, bit); |
112 | if (test_bit(IOAT_RUN, &ioat_chan->state)) | |
113 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
114 | } |
115 | ||
116 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
117 | return IRQ_HANDLED; | |
118 | } | |
119 | ||
120 | /** | |
121 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
122 | * @irq: interrupt id | |
123 | * @data: interrupt data | |
124 | */ | |
c0f28ce6 | 125 | irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
3e037454 | 126 | { |
5a976888 | 127 | struct ioatdma_chan *ioat_chan = data; |
3e037454 | 128 | |
5a976888 DJ |
129 | if (test_bit(IOAT_RUN, &ioat_chan->state)) |
130 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
131 | |
132 | return IRQ_HANDLED; | |
133 | } | |
134 | ||
5a976888 | 135 | void ioat_stop(struct ioatdma_chan *ioat_chan) |
da87ca4d | 136 | { |
55f878ec DJ |
137 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
138 | struct pci_dev *pdev = ioat_dma->pdev; | |
5a976888 | 139 | int chan_id = chan_num(ioat_chan); |
da87ca4d DW |
140 | struct msix_entry *msix; |
141 | ||
142 | /* 1/ stop irq from firing tasklets | |
143 | * 2/ stop the tasklet from re-arming irqs | |
144 | */ | |
5a976888 | 145 | clear_bit(IOAT_RUN, &ioat_chan->state); |
da87ca4d DW |
146 | |
147 | /* flush inflight interrupts */ | |
55f878ec | 148 | switch (ioat_dma->irq_mode) { |
da87ca4d | 149 | case IOAT_MSIX: |
55f878ec | 150 | msix = &ioat_dma->msix_entries[chan_id]; |
da87ca4d DW |
151 | synchronize_irq(msix->vector); |
152 | break; | |
153 | case IOAT_MSI: | |
154 | case IOAT_INTX: | |
155 | synchronize_irq(pdev->irq); | |
156 | break; | |
157 | default: | |
158 | break; | |
159 | } | |
160 | ||
161 | /* flush inflight timers */ | |
5a976888 | 162 | del_timer_sync(&ioat_chan->timer); |
da87ca4d DW |
163 | |
164 | /* flush inflight tasklet runs */ | |
5a976888 | 165 | tasklet_kill(&ioat_chan->cleanup_task); |
da87ca4d DW |
166 | |
167 | /* final cleanup now that everything is quiesced and can't re-arm */ | |
ef97bd0f | 168 | ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan); |
da87ca4d DW |
169 | } |
170 | ||
3372de58 | 171 | static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
172 | { |
173 | ioat_chan->dmacount += ioat_ring_pending(ioat_chan); | |
174 | ioat_chan->issued = ioat_chan->head; | |
175 | writew(ioat_chan->dmacount, | |
176 | ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); | |
177 | dev_dbg(to_dev(ioat_chan), | |
178 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
179 | __func__, ioat_chan->head, ioat_chan->tail, | |
180 | ioat_chan->issued, ioat_chan->dmacount); | |
181 | } | |
182 | ||
183 | void ioat_issue_pending(struct dma_chan *c) | |
184 | { | |
185 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
186 | ||
187 | if (ioat_ring_pending(ioat_chan)) { | |
188 | spin_lock_bh(&ioat_chan->prep_lock); | |
189 | __ioat_issue_pending(ioat_chan); | |
190 | spin_unlock_bh(&ioat_chan->prep_lock); | |
191 | } | |
192 | } | |
193 | ||
194 | /** | |
195 | * ioat_update_pending - log pending descriptors | |
196 | * @ioat: ioat+ channel | |
197 | * | |
198 | * Check if the number of unsubmitted descriptors has exceeded the | |
199 | * watermark. Called with prep_lock held | |
200 | */ | |
201 | static void ioat_update_pending(struct ioatdma_chan *ioat_chan) | |
202 | { | |
203 | if (ioat_ring_pending(ioat_chan) > ioat_pending_level) | |
204 | __ioat_issue_pending(ioat_chan); | |
205 | } | |
206 | ||
207 | static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan) | |
208 | { | |
209 | struct ioat_ring_ent *desc; | |
210 | struct ioat_dma_descriptor *hw; | |
211 | ||
212 | if (ioat_ring_space(ioat_chan) < 1) { | |
213 | dev_err(to_dev(ioat_chan), | |
214 | "Unable to start null desc - ring full\n"); | |
215 | return; | |
216 | } | |
217 | ||
218 | dev_dbg(to_dev(ioat_chan), | |
219 | "%s: head: %#x tail: %#x issued: %#x\n", | |
220 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
221 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); | |
222 | ||
223 | hw = desc->hw; | |
224 | hw->ctl = 0; | |
225 | hw->ctl_f.null = 1; | |
226 | hw->ctl_f.int_en = 1; | |
227 | hw->ctl_f.compl_write = 1; | |
228 | /* set size to non-zero value (channel returns error when size is 0) */ | |
229 | hw->size = NULL_DESC_BUFFER_SIZE; | |
230 | hw->src_addr = 0; | |
231 | hw->dst_addr = 0; | |
232 | async_tx_ack(&desc->txd); | |
233 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
234 | dump_desc_dbg(ioat_chan, desc); | |
235 | /* make sure descriptors are written before we submit */ | |
236 | wmb(); | |
237 | ioat_chan->head += 1; | |
238 | __ioat_issue_pending(ioat_chan); | |
239 | } | |
240 | ||
c0f28ce6 | 241 | void ioat_start_null_desc(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
242 | { |
243 | spin_lock_bh(&ioat_chan->prep_lock); | |
ad4a7b50 DJ |
244 | if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
245 | __ioat_start_null_desc(ioat_chan); | |
885b2010 DJ |
246 | spin_unlock_bh(&ioat_chan->prep_lock); |
247 | } | |
248 | ||
3372de58 | 249 | static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
250 | { |
251 | /* set the tail to be re-issued */ | |
252 | ioat_chan->issued = ioat_chan->tail; | |
253 | ioat_chan->dmacount = 0; | |
885b2010 DJ |
254 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
255 | ||
256 | dev_dbg(to_dev(ioat_chan), | |
257 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
258 | __func__, ioat_chan->head, ioat_chan->tail, | |
259 | ioat_chan->issued, ioat_chan->dmacount); | |
260 | ||
261 | if (ioat_ring_pending(ioat_chan)) { | |
262 | struct ioat_ring_ent *desc; | |
263 | ||
264 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
265 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
266 | __ioat_issue_pending(ioat_chan); | |
267 | } else | |
268 | __ioat_start_null_desc(ioat_chan); | |
269 | } | |
270 | ||
3372de58 | 271 | static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
272 | { |
273 | unsigned long end = jiffies + tmo; | |
274 | int err = 0; | |
275 | u32 status; | |
276 | ||
277 | status = ioat_chansts(ioat_chan); | |
278 | if (is_ioat_active(status) || is_ioat_idle(status)) | |
279 | ioat_suspend(ioat_chan); | |
280 | while (is_ioat_active(status) || is_ioat_idle(status)) { | |
281 | if (tmo && time_after(jiffies, end)) { | |
282 | err = -ETIMEDOUT; | |
283 | break; | |
284 | } | |
285 | status = ioat_chansts(ioat_chan); | |
286 | cpu_relax(); | |
287 | } | |
288 | ||
289 | return err; | |
290 | } | |
291 | ||
3372de58 | 292 | static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
293 | { |
294 | unsigned long end = jiffies + tmo; | |
295 | int err = 0; | |
296 | ||
297 | ioat_reset(ioat_chan); | |
298 | while (ioat_reset_pending(ioat_chan)) { | |
299 | if (end && time_after(jiffies, end)) { | |
300 | err = -ETIMEDOUT; | |
301 | break; | |
302 | } | |
303 | cpu_relax(); | |
304 | } | |
305 | ||
306 | return err; | |
307 | } | |
308 | ||
885b2010 | 309 | static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx) |
5c65cb93 | 310 | __releases(&ioat_chan->prep_lock) |
885b2010 DJ |
311 | { |
312 | struct dma_chan *c = tx->chan; | |
313 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
314 | dma_cookie_t cookie; | |
315 | ||
316 | cookie = dma_cookie_assign(tx); | |
317 | dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie); | |
318 | ||
319 | if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
320 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
321 | ||
322 | /* make descriptor updates visible before advancing ioat->head, | |
323 | * this is purposefully not smp_wmb() since we are also | |
324 | * publishing the descriptor updates to a dma device | |
325 | */ | |
326 | wmb(); | |
327 | ||
328 | ioat_chan->head += ioat_chan->produce; | |
329 | ||
330 | ioat_update_pending(ioat_chan); | |
331 | spin_unlock_bh(&ioat_chan->prep_lock); | |
332 | ||
333 | return cookie; | |
334 | } | |
335 | ||
336 | static struct ioat_ring_ent * | |
dd4645eb | 337 | ioat_alloc_ring_ent(struct dma_chan *chan, int idx, gfp_t flags) |
885b2010 DJ |
338 | { |
339 | struct ioat_dma_descriptor *hw; | |
340 | struct ioat_ring_ent *desc; | |
dd4645eb DJ |
341 | struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
342 | int chunk; | |
885b2010 | 343 | dma_addr_t phys; |
dd4645eb DJ |
344 | u8 *pos; |
345 | off_t offs; | |
885b2010 | 346 | |
dd4645eb DJ |
347 | chunk = idx / IOAT_DESCS_PER_2M; |
348 | idx &= (IOAT_DESCS_PER_2M - 1); | |
349 | offs = idx * IOAT_DESC_SZ; | |
350 | pos = (u8 *)ioat_chan->descs[chunk].virt + offs; | |
351 | phys = ioat_chan->descs[chunk].hw + offs; | |
352 | hw = (struct ioat_dma_descriptor *)pos; | |
885b2010 DJ |
353 | memset(hw, 0, sizeof(*hw)); |
354 | ||
355 | desc = kmem_cache_zalloc(ioat_cache, flags); | |
dd4645eb | 356 | if (!desc) |
885b2010 | 357 | return NULL; |
885b2010 DJ |
358 | |
359 | dma_async_tx_descriptor_init(&desc->txd, chan); | |
360 | desc->txd.tx_submit = ioat_tx_submit_unlock; | |
361 | desc->hw = hw; | |
362 | desc->txd.phys = phys; | |
363 | return desc; | |
364 | } | |
365 | ||
c0f28ce6 | 366 | void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) |
885b2010 | 367 | { |
885b2010 DJ |
368 | kmem_cache_free(ioat_cache, desc); |
369 | } | |
370 | ||
c0f28ce6 | 371 | struct ioat_ring_ent ** |
885b2010 DJ |
372 | ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags) |
373 | { | |
dd4645eb | 374 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
885b2010 | 375 | struct ioat_ring_ent **ring; |
dd4645eb DJ |
376 | int total_descs = 1 << order; |
377 | int i, chunks; | |
885b2010 DJ |
378 | |
379 | /* allocate the array to hold the software ring */ | |
dd4645eb | 380 | ring = kcalloc(total_descs, sizeof(*ring), flags); |
885b2010 DJ |
381 | if (!ring) |
382 | return NULL; | |
dd4645eb DJ |
383 | |
384 | ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M; | |
385 | ||
386 | for (i = 0; i < chunks; i++) { | |
387 | struct ioat_descs *descs = &ioat_chan->descs[i]; | |
388 | ||
389 | descs->virt = dma_alloc_coherent(to_dev(ioat_chan), | |
390 | SZ_2M, &descs->hw, flags); | |
391 | if (!descs->virt && (i > 0)) { | |
392 | int idx; | |
393 | ||
394 | for (idx = 0; idx < i; idx++) { | |
395 | dma_free_coherent(to_dev(ioat_chan), SZ_2M, | |
396 | descs->virt, descs->hw); | |
397 | descs->virt = NULL; | |
398 | descs->hw = 0; | |
399 | } | |
400 | ||
401 | ioat_chan->desc_chunks = 0; | |
402 | kfree(ring); | |
403 | return NULL; | |
404 | } | |
405 | } | |
406 | ||
407 | for (i = 0; i < total_descs; i++) { | |
408 | ring[i] = ioat_alloc_ring_ent(c, i, flags); | |
885b2010 | 409 | if (!ring[i]) { |
dd4645eb DJ |
410 | int idx; |
411 | ||
885b2010 DJ |
412 | while (i--) |
413 | ioat_free_ring_ent(ring[i], c); | |
dd4645eb DJ |
414 | |
415 | for (idx = 0; idx < ioat_chan->desc_chunks; idx++) { | |
416 | dma_free_coherent(to_dev(ioat_chan), | |
417 | SZ_2M, | |
418 | ioat_chan->descs[idx].virt, | |
419 | ioat_chan->descs[idx].hw); | |
420 | ioat_chan->descs[idx].virt = NULL; | |
421 | ioat_chan->descs[idx].hw = 0; | |
422 | } | |
423 | ||
424 | ioat_chan->desc_chunks = 0; | |
885b2010 DJ |
425 | kfree(ring); |
426 | return NULL; | |
427 | } | |
428 | set_desc_id(ring[i], i); | |
429 | } | |
430 | ||
431 | /* link descs */ | |
dd4645eb | 432 | for (i = 0; i < total_descs-1; i++) { |
885b2010 DJ |
433 | struct ioat_ring_ent *next = ring[i+1]; |
434 | struct ioat_dma_descriptor *hw = ring[i]->hw; | |
435 | ||
436 | hw->next = next->txd.phys; | |
437 | } | |
438 | ring[i]->hw->next = ring[0]->txd.phys; | |
439 | ||
440 | return ring; | |
441 | } | |
442 | ||
885b2010 DJ |
443 | /** |
444 | * ioat_check_space_lock - verify space and grab ring producer lock | |
445 | * @ioat: ioat,3 channel (ring) to operate on | |
446 | * @num_descs: allocation length | |
447 | */ | |
448 | int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs) | |
5c65cb93 | 449 | __acquires(&ioat_chan->prep_lock) |
885b2010 | 450 | { |
885b2010 DJ |
451 | spin_lock_bh(&ioat_chan->prep_lock); |
452 | /* never allow the last descriptor to be consumed, we need at | |
453 | * least one free at all times to allow for on-the-fly ring | |
454 | * resizing. | |
455 | */ | |
456 | if (likely(ioat_ring_space(ioat_chan) > num_descs)) { | |
457 | dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n", | |
458 | __func__, num_descs, ioat_chan->head, | |
459 | ioat_chan->tail, ioat_chan->issued); | |
460 | ioat_chan->produce = num_descs; | |
461 | return 0; /* with ioat->prep_lock held */ | |
462 | } | |
885b2010 DJ |
463 | spin_unlock_bh(&ioat_chan->prep_lock); |
464 | ||
885b2010 DJ |
465 | dev_dbg_ratelimited(to_dev(ioat_chan), |
466 | "%s: ring full! num_descs: %d (%x:%x:%x)\n", | |
467 | __func__, num_descs, ioat_chan->head, | |
468 | ioat_chan->tail, ioat_chan->issued); | |
469 | ||
470 | /* progress reclaim in the allocation failure case we may be | |
471 | * called under bh_disabled so we need to trigger the timer | |
472 | * event directly | |
473 | */ | |
474 | if (time_is_before_jiffies(ioat_chan->timer.expires) | |
475 | && timer_pending(&ioat_chan->timer)) { | |
885b2010 | 476 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
ef97bd0f | 477 | ioat_timer_event((unsigned long)ioat_chan); |
885b2010 DJ |
478 | } |
479 | ||
480 | return -ENOMEM; | |
481 | } | |
3372de58 DJ |
482 | |
483 | static bool desc_has_ext(struct ioat_ring_ent *desc) | |
484 | { | |
485 | struct ioat_dma_descriptor *hw = desc->hw; | |
486 | ||
487 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
488 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
489 | struct ioat_xor_descriptor *xor = desc->xor; | |
490 | ||
491 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) | |
492 | return true; | |
493 | } else if (hw->ctl_f.op == IOAT_OP_PQ || | |
494 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
495 | struct ioat_pq_descriptor *pq = desc->pq; | |
496 | ||
497 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
498 | return true; | |
499 | } | |
500 | ||
501 | return false; | |
502 | } | |
503 | ||
504 | static void | |
505 | ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed) | |
506 | { | |
507 | if (!sed) | |
508 | return; | |
509 | ||
510 | dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
511 | kmem_cache_free(ioat_sed_cache, sed); | |
512 | } | |
513 | ||
514 | static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan) | |
515 | { | |
516 | u64 phys_complete; | |
517 | u64 completion; | |
518 | ||
519 | completion = *ioat_chan->completion; | |
520 | phys_complete = ioat_chansts_to_addr(completion); | |
521 | ||
522 | dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__, | |
523 | (unsigned long long) phys_complete); | |
524 | ||
525 | return phys_complete; | |
526 | } | |
527 | ||
528 | static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, | |
529 | u64 *phys_complete) | |
530 | { | |
531 | *phys_complete = ioat_get_current_completion(ioat_chan); | |
532 | if (*phys_complete == ioat_chan->last_completion) | |
533 | return false; | |
534 | ||
535 | clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); | |
536 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
537 | ||
538 | return true; | |
539 | } | |
540 | ||
541 | static void | |
542 | desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc) | |
543 | { | |
544 | struct ioat_dma_descriptor *hw = desc->hw; | |
545 | ||
546 | switch (hw->ctl_f.op) { | |
547 | case IOAT_OP_PQ_VAL: | |
548 | case IOAT_OP_PQ_VAL_16S: | |
549 | { | |
550 | struct ioat_pq_descriptor *pq = desc->pq; | |
551 | ||
552 | /* check if there's error written */ | |
553 | if (!pq->dwbes_f.wbes) | |
554 | return; | |
555 | ||
556 | /* need to set a chanerr var for checking to clear later */ | |
557 | ||
558 | if (pq->dwbes_f.p_val_err) | |
559 | *desc->result |= SUM_CHECK_P_RESULT; | |
560 | ||
561 | if (pq->dwbes_f.q_val_err) | |
562 | *desc->result |= SUM_CHECK_Q_RESULT; | |
563 | ||
564 | return; | |
565 | } | |
566 | default: | |
567 | return; | |
568 | } | |
569 | } | |
570 | ||
571 | /** | |
572 | * __cleanup - reclaim used descriptors | |
573 | * @ioat: channel (ring) to clean | |
574 | */ | |
575 | static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete) | |
576 | { | |
577 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
578 | struct ioat_ring_ent *desc; | |
579 | bool seen_current = false; | |
580 | int idx = ioat_chan->tail, i; | |
581 | u16 active; | |
582 | ||
583 | dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
584 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
585 | ||
586 | /* | |
587 | * At restart of the channel, the completion address and the | |
588 | * channel status will be 0 due to starting a new chain. Since | |
589 | * it's new chain and the first descriptor "fails", there is | |
590 | * nothing to clean up. We do not want to reap the entire submitted | |
591 | * chain due to this 0 address value and then BUG. | |
592 | */ | |
593 | if (!phys_complete) | |
594 | return; | |
595 | ||
596 | active = ioat_ring_active(ioat_chan); | |
597 | for (i = 0; i < active && !seen_current; i++) { | |
598 | struct dma_async_tx_descriptor *tx; | |
599 | ||
600 | smp_read_barrier_depends(); | |
601 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); | |
602 | desc = ioat_get_ring_ent(ioat_chan, idx + i); | |
603 | dump_desc_dbg(ioat_chan, desc); | |
604 | ||
605 | /* set err stat if we are using dwbes */ | |
606 | if (ioat_dma->cap & IOAT_CAP_DWBES) | |
607 | desc_get_errstat(ioat_chan, desc); | |
608 | ||
609 | tx = &desc->txd; | |
610 | if (tx->cookie) { | |
611 | dma_cookie_complete(tx); | |
612 | dma_descriptor_unmap(tx); | |
63992864 DJ |
613 | dmaengine_desc_get_callback_invoke(tx, NULL); |
614 | tx->callback = NULL; | |
9546d4cd | 615 | tx->callback_result = NULL; |
3372de58 DJ |
616 | } |
617 | ||
618 | if (tx->phys == phys_complete) | |
619 | seen_current = true; | |
620 | ||
621 | /* skip extended descriptors */ | |
622 | if (desc_has_ext(desc)) { | |
623 | BUG_ON(i + 1 >= active); | |
624 | i++; | |
625 | } | |
626 | ||
627 | /* cleanup super extended descriptors */ | |
628 | if (desc->sed) { | |
629 | ioat_free_sed(ioat_dma, desc->sed); | |
630 | desc->sed = NULL; | |
631 | } | |
632 | } | |
633 | ||
634 | /* finish all descriptor reads before incrementing tail */ | |
635 | smp_mb(); | |
636 | ioat_chan->tail = idx + i; | |
637 | /* no active descs have written a completion? */ | |
638 | BUG_ON(active && !seen_current); | |
639 | ioat_chan->last_completion = phys_complete; | |
640 | ||
641 | if (active - i == 0) { | |
642 | dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n", | |
643 | __func__); | |
3372de58 DJ |
644 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
645 | } | |
646 | ||
647 | /* 5 microsecond delay per pending descriptor */ | |
648 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), | |
649 | ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET); | |
650 | } | |
651 | ||
652 | static void ioat_cleanup(struct ioatdma_chan *ioat_chan) | |
653 | { | |
654 | u64 phys_complete; | |
655 | ||
656 | spin_lock_bh(&ioat_chan->cleanup_lock); | |
657 | ||
658 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
659 | __cleanup(ioat_chan, phys_complete); | |
660 | ||
661 | if (is_ioat_halted(*ioat_chan->completion)) { | |
662 | u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
663 | ||
9546d4cd DJ |
664 | if (chanerr & |
665 | (IOAT_CHANERR_HANDLE_MASK | IOAT_CHANERR_RECOVER_MASK)) { | |
3372de58 DJ |
666 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
667 | ioat_eh(ioat_chan); | |
668 | } | |
669 | } | |
670 | ||
671 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
672 | } | |
673 | ||
674 | void ioat_cleanup_event(unsigned long data) | |
675 | { | |
676 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
677 | ||
678 | ioat_cleanup(ioat_chan); | |
679 | if (!test_bit(IOAT_RUN, &ioat_chan->state)) | |
680 | return; | |
681 | writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); | |
682 | } | |
683 | ||
684 | static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) | |
685 | { | |
686 | u64 phys_complete; | |
687 | ||
688 | ioat_quiesce(ioat_chan, 0); | |
689 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
690 | __cleanup(ioat_chan, phys_complete); | |
691 | ||
692 | __ioat_restart_chan(ioat_chan); | |
693 | } | |
694 | ||
9546d4cd DJ |
695 | |
696 | static void ioat_abort_descs(struct ioatdma_chan *ioat_chan) | |
697 | { | |
698 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
699 | struct ioat_ring_ent *desc; | |
700 | u16 active; | |
701 | int idx = ioat_chan->tail, i; | |
702 | ||
703 | /* | |
704 | * We assume that the failed descriptor has been processed. | |
705 | * Now we are just returning all the remaining submitted | |
706 | * descriptors to abort. | |
707 | */ | |
708 | active = ioat_ring_active(ioat_chan); | |
709 | ||
710 | /* we skip the failed descriptor that tail points to */ | |
711 | for (i = 1; i < active; i++) { | |
712 | struct dma_async_tx_descriptor *tx; | |
713 | ||
714 | smp_read_barrier_depends(); | |
715 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); | |
716 | desc = ioat_get_ring_ent(ioat_chan, idx + i); | |
717 | ||
718 | tx = &desc->txd; | |
719 | if (tx->cookie) { | |
720 | struct dmaengine_result res; | |
721 | ||
722 | dma_cookie_complete(tx); | |
723 | dma_descriptor_unmap(tx); | |
724 | res.result = DMA_TRANS_ABORTED; | |
725 | dmaengine_desc_get_callback_invoke(tx, &res); | |
726 | tx->callback = NULL; | |
727 | tx->callback_result = NULL; | |
728 | } | |
729 | ||
730 | /* skip extended descriptors */ | |
731 | if (desc_has_ext(desc)) { | |
732 | WARN_ON(i + 1 >= active); | |
733 | i++; | |
734 | } | |
735 | ||
736 | /* cleanup super extended descriptors */ | |
737 | if (desc->sed) { | |
738 | ioat_free_sed(ioat_dma, desc->sed); | |
739 | desc->sed = NULL; | |
740 | } | |
741 | } | |
742 | ||
743 | smp_mb(); /* finish all descriptor reads before incrementing tail */ | |
744 | ioat_chan->tail = idx + active; | |
745 | ||
746 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
747 | ioat_chan->last_completion = *ioat_chan->completion = desc->txd.phys; | |
748 | } | |
749 | ||
3372de58 DJ |
750 | static void ioat_eh(struct ioatdma_chan *ioat_chan) |
751 | { | |
752 | struct pci_dev *pdev = to_pdev(ioat_chan); | |
753 | struct ioat_dma_descriptor *hw; | |
754 | struct dma_async_tx_descriptor *tx; | |
755 | u64 phys_complete; | |
756 | struct ioat_ring_ent *desc; | |
757 | u32 err_handled = 0; | |
758 | u32 chanerr_int; | |
759 | u32 chanerr; | |
9546d4cd DJ |
760 | bool abort = false; |
761 | struct dmaengine_result res; | |
3372de58 DJ |
762 | |
763 | /* cleanup so tail points to descriptor that caused the error */ | |
764 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
765 | __cleanup(ioat_chan, phys_complete); | |
766 | ||
767 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
768 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
769 | ||
770 | dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n", | |
771 | __func__, chanerr, chanerr_int); | |
772 | ||
773 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
774 | hw = desc->hw; | |
775 | dump_desc_dbg(ioat_chan, desc); | |
776 | ||
777 | switch (hw->ctl_f.op) { | |
778 | case IOAT_OP_XOR_VAL: | |
779 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
780 | *desc->result |= SUM_CHECK_P_RESULT; | |
781 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
782 | } | |
783 | break; | |
784 | case IOAT_OP_PQ_VAL: | |
785 | case IOAT_OP_PQ_VAL_16S: | |
786 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
787 | *desc->result |= SUM_CHECK_P_RESULT; | |
788 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
789 | } | |
790 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
791 | *desc->result |= SUM_CHECK_Q_RESULT; | |
792 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
793 | } | |
794 | break; | |
795 | } | |
796 | ||
9546d4cd DJ |
797 | if (chanerr & IOAT_CHANERR_RECOVER_MASK) { |
798 | if (chanerr & IOAT_CHANERR_READ_DATA_ERR) { | |
799 | res.result = DMA_TRANS_READ_FAILED; | |
800 | err_handled |= IOAT_CHANERR_READ_DATA_ERR; | |
801 | } else if (chanerr & IOAT_CHANERR_WRITE_DATA_ERR) { | |
802 | res.result = DMA_TRANS_WRITE_FAILED; | |
803 | err_handled |= IOAT_CHANERR_WRITE_DATA_ERR; | |
804 | } | |
805 | ||
806 | abort = true; | |
807 | } else | |
808 | res.result = DMA_TRANS_NOERROR; | |
809 | ||
3372de58 DJ |
810 | /* fault on unhandled error or spurious halt */ |
811 | if (chanerr ^ err_handled || chanerr == 0) { | |
812 | dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n", | |
813 | __func__, chanerr, err_handled); | |
aed681d1 DJ |
814 | dev_err(to_dev(ioat_chan), "Errors handled:\n"); |
815 | ioat_print_chanerrs(ioat_chan, err_handled); | |
816 | dev_err(to_dev(ioat_chan), "Errors not handled:\n"); | |
817 | ioat_print_chanerrs(ioat_chan, (chanerr & ~err_handled)); | |
818 | ||
3372de58 | 819 | BUG(); |
3372de58 DJ |
820 | } |
821 | ||
9546d4cd DJ |
822 | /* cleanup the faulty descriptor since we are continuing */ |
823 | tx = &desc->txd; | |
824 | if (tx->cookie) { | |
825 | dma_cookie_complete(tx); | |
826 | dma_descriptor_unmap(tx); | |
827 | dmaengine_desc_get_callback_invoke(tx, &res); | |
828 | tx->callback = NULL; | |
829 | tx->callback_result = NULL; | |
830 | } | |
3372de58 DJ |
831 | |
832 | /* mark faulting descriptor as complete */ | |
833 | *ioat_chan->completion = desc->txd.phys; | |
834 | ||
835 | spin_lock_bh(&ioat_chan->prep_lock); | |
9546d4cd DJ |
836 | /* we need abort all descriptors */ |
837 | if (abort) { | |
838 | ioat_abort_descs(ioat_chan); | |
839 | /* clean up the channel, we could be in weird state */ | |
840 | ioat_reset_hw(ioat_chan); | |
841 | } | |
842 | ||
843 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
844 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
845 | ||
3372de58 DJ |
846 | ioat_restart_channel(ioat_chan); |
847 | spin_unlock_bh(&ioat_chan->prep_lock); | |
848 | } | |
849 | ||
850 | static void check_active(struct ioatdma_chan *ioat_chan) | |
851 | { | |
852 | if (ioat_ring_active(ioat_chan)) { | |
853 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
854 | return; | |
855 | } | |
856 | ||
857 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
858 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); | |
3372de58 DJ |
859 | } |
860 | ||
861 | void ioat_timer_event(unsigned long data) | |
862 | { | |
863 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
864 | dma_addr_t phys_complete; | |
865 | u64 status; | |
866 | ||
867 | status = ioat_chansts(ioat_chan); | |
868 | ||
869 | /* when halted due to errors check for channel | |
870 | * programming errors before advancing the completion state | |
871 | */ | |
872 | if (is_ioat_halted(status)) { | |
873 | u32 chanerr; | |
874 | ||
875 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
876 | dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n", | |
877 | __func__, chanerr); | |
aed681d1 DJ |
878 | dev_err(to_dev(ioat_chan), "Errors:\n"); |
879 | ioat_print_chanerrs(ioat_chan, chanerr); | |
880 | ||
9546d4cd DJ |
881 | if (test_bit(IOAT_RUN, &ioat_chan->state)) { |
882 | spin_lock_bh(&ioat_chan->cleanup_lock); | |
883 | spin_lock_bh(&ioat_chan->prep_lock); | |
884 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
885 | spin_unlock_bh(&ioat_chan->prep_lock); | |
886 | ||
887 | ioat_abort_descs(ioat_chan); | |
888 | dev_warn(to_dev(ioat_chan), "Reset channel...\n"); | |
889 | ioat_reset_hw(ioat_chan); | |
890 | dev_warn(to_dev(ioat_chan), "Restart channel...\n"); | |
891 | ioat_restart_channel(ioat_chan); | |
892 | ||
893 | spin_lock_bh(&ioat_chan->prep_lock); | |
894 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
895 | spin_unlock_bh(&ioat_chan->prep_lock); | |
896 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
897 | } | |
898 | ||
899 | return; | |
3372de58 DJ |
900 | } |
901 | ||
8a695db0 DJ |
902 | spin_lock_bh(&ioat_chan->cleanup_lock); |
903 | ||
904 | /* handle the no-actives case */ | |
905 | if (!ioat_ring_active(ioat_chan)) { | |
906 | spin_lock_bh(&ioat_chan->prep_lock); | |
907 | check_active(ioat_chan); | |
908 | spin_unlock_bh(&ioat_chan->prep_lock); | |
909 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
910 | return; | |
911 | } | |
912 | ||
3372de58 DJ |
913 | /* if we haven't made progress and we have already |
914 | * acknowledged a pending completion once, then be more | |
915 | * forceful with a restart | |
916 | */ | |
3372de58 DJ |
917 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
918 | __cleanup(ioat_chan, phys_complete); | |
919 | else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) { | |
8a695db0 DJ |
920 | u32 chanerr; |
921 | ||
922 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
aed681d1 DJ |
923 | dev_err(to_dev(ioat_chan), "CHANSTS: %#Lx CHANERR: %#x\n", |
924 | status, chanerr); | |
925 | dev_err(to_dev(ioat_chan), "Errors:\n"); | |
926 | ioat_print_chanerrs(ioat_chan, chanerr); | |
927 | ||
928 | dev_dbg(to_dev(ioat_chan), "Active descriptors: %d\n", | |
929 | ioat_ring_active(ioat_chan)); | |
8a695db0 | 930 | |
3372de58 | 931 | spin_lock_bh(&ioat_chan->prep_lock); |
9546d4cd DJ |
932 | set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); |
933 | spin_unlock_bh(&ioat_chan->prep_lock); | |
934 | ||
935 | ioat_abort_descs(ioat_chan); | |
936 | dev_warn(to_dev(ioat_chan), "Resetting channel...\n"); | |
937 | ioat_reset_hw(ioat_chan); | |
938 | dev_warn(to_dev(ioat_chan), "Restarting channel...\n"); | |
3372de58 | 939 | ioat_restart_channel(ioat_chan); |
9546d4cd DJ |
940 | |
941 | spin_lock_bh(&ioat_chan->prep_lock); | |
942 | clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); | |
3372de58 DJ |
943 | spin_unlock_bh(&ioat_chan->prep_lock); |
944 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
945 | return; | |
8a695db0 | 946 | } else |
3372de58 | 947 | set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); |
3372de58 | 948 | |
8a695db0 | 949 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
3372de58 DJ |
950 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
951 | } | |
952 | ||
953 | enum dma_status | |
954 | ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, | |
955 | struct dma_tx_state *txstate) | |
956 | { | |
957 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
958 | enum dma_status ret; | |
959 | ||
960 | ret = dma_cookie_status(c, cookie, txstate); | |
961 | if (ret == DMA_COMPLETE) | |
962 | return ret; | |
963 | ||
964 | ioat_cleanup(ioat_chan); | |
965 | ||
966 | return dma_cookie_status(c, cookie, txstate); | |
967 | } | |
968 | ||
3372de58 DJ |
969 | int ioat_reset_hw(struct ioatdma_chan *ioat_chan) |
970 | { | |
971 | /* throw away whatever the channel was doing and get it | |
972 | * initialized, with ioat3 specific workarounds | |
973 | */ | |
974 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
975 | struct pci_dev *pdev = ioat_dma->pdev; | |
976 | u32 chanerr; | |
977 | u16 dev_id; | |
978 | int err; | |
979 | ||
980 | ioat_quiesce(ioat_chan, msecs_to_jiffies(100)); | |
981 | ||
982 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
983 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
984 | ||
985 | if (ioat_dma->version < IOAT_VER_3_3) { | |
986 | /* clear any pending errors */ | |
987 | err = pci_read_config_dword(pdev, | |
988 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
989 | if (err) { | |
990 | dev_err(&pdev->dev, | |
991 | "channel error register unreachable\n"); | |
992 | return err; | |
993 | } | |
994 | pci_write_config_dword(pdev, | |
995 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
996 | ||
997 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
998 | * (workaround for spurious config parity error after restart) | |
999 | */ | |
1000 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1001 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
1002 | pci_write_config_dword(pdev, | |
1003 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
1004 | 0x10); | |
1005 | } | |
1006 | } | |
1007 | ||
c997e30e DJ |
1008 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { |
1009 | ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000); | |
1010 | ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008); | |
1011 | ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800); | |
1012 | } | |
1013 | ||
1014 | ||
3372de58 | 1015 | err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200)); |
c997e30e DJ |
1016 | if (!err) { |
1017 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { | |
1018 | writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000); | |
1019 | writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008); | |
1020 | writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800); | |
1021 | } | |
1022 | } | |
3372de58 DJ |
1023 | |
1024 | if (err) | |
1025 | dev_err(&pdev->dev, "Failed to reset: %d\n", err); | |
1026 | ||
1027 | return err; | |
1028 | } |