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c2110923 DW |
1 | /* |
2 | * offload engine driver for the Intel Xscale series of i/o processors | |
3 | * Copyright © 2006, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * This driver supports the asynchrounous DMA copy and RAID engines available | |
22 | * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x) | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
c2110923 DW |
27 | #include <linux/delay.h> |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/memory.h> | |
33 | #include <linux/ioport.h> | |
f6dbf651 | 34 | #include <linux/raid/pq.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
c2110923 | 36 | |
a09e64fb | 37 | #include <mach/adma.h> |
c2110923 | 38 | |
d2ebfb33 RKAL |
39 | #include "dmaengine.h" |
40 | ||
c2110923 DW |
41 | #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) |
42 | #define to_iop_adma_device(dev) \ | |
43 | container_of(dev, struct iop_adma_device, common) | |
44 | #define tx_to_iop_adma_slot(tx) \ | |
45 | container_of(tx, struct iop_adma_desc_slot, async_tx) | |
46 | ||
47 | /** | |
48 | * iop_adma_free_slots - flags descriptor slots for reuse | |
49 | * @slot: Slot to free | |
50 | * Caller must hold &iop_chan->lock while calling this function | |
51 | */ | |
52 | static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) | |
53 | { | |
54 | int stride = slot->slots_per_op; | |
55 | ||
56 | while (stride--) { | |
57 | slot->slots_per_op = 0; | |
58 | slot = list_entry(slot->slot_node.next, | |
59 | struct iop_adma_desc_slot, | |
60 | slot_node); | |
61 | } | |
62 | } | |
63 | ||
7bf649ae DW |
64 | static void |
65 | iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) | |
66 | { | |
67 | struct dma_async_tx_descriptor *tx = &desc->async_tx; | |
68 | struct iop_adma_desc_slot *unmap = desc->group_head; | |
69 | struct device *dev = &iop_chan->device->pdev->dev; | |
70 | u32 len = unmap->unmap_len; | |
71 | enum dma_ctrl_flags flags = tx->flags; | |
72 | u32 src_cnt; | |
73 | dma_addr_t addr; | |
74 | dma_addr_t dest; | |
75 | ||
76 | src_cnt = unmap->unmap_src_cnt; | |
77 | dest = iop_desc_get_dest_addr(unmap, iop_chan); | |
78 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
79 | enum dma_data_direction dir; | |
80 | ||
81 | if (src_cnt > 1) /* is xor? */ | |
82 | dir = DMA_BIDIRECTIONAL; | |
83 | else | |
84 | dir = DMA_FROM_DEVICE; | |
85 | ||
86 | dma_unmap_page(dev, dest, len, dir); | |
87 | } | |
88 | ||
89 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
90 | while (src_cnt--) { | |
91 | addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt); | |
92 | if (addr == dest) | |
93 | continue; | |
94 | dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); | |
95 | } | |
96 | } | |
97 | desc->group_head = NULL; | |
98 | } | |
99 | ||
100 | static void | |
101 | iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc) | |
102 | { | |
103 | struct dma_async_tx_descriptor *tx = &desc->async_tx; | |
104 | struct iop_adma_desc_slot *unmap = desc->group_head; | |
105 | struct device *dev = &iop_chan->device->pdev->dev; | |
106 | u32 len = unmap->unmap_len; | |
107 | enum dma_ctrl_flags flags = tx->flags; | |
108 | u32 src_cnt = unmap->unmap_src_cnt; | |
109 | dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan); | |
110 | dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan); | |
111 | int i; | |
112 | ||
113 | if (tx->flags & DMA_PREP_CONTINUE) | |
114 | src_cnt -= 3; | |
115 | ||
116 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) { | |
117 | dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL); | |
118 | dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL); | |
119 | } | |
120 | ||
121 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
122 | dma_addr_t addr; | |
123 | ||
124 | for (i = 0; i < src_cnt; i++) { | |
125 | addr = iop_desc_get_src_addr(unmap, iop_chan, i); | |
126 | dma_unmap_page(dev, addr, len, DMA_TO_DEVICE); | |
127 | } | |
128 | if (desc->pq_check_result) { | |
129 | dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE); | |
130 | dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE); | |
131 | } | |
132 | } | |
133 | ||
134 | desc->group_head = NULL; | |
135 | } | |
136 | ||
137 | ||
c2110923 DW |
138 | static dma_cookie_t |
139 | iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, | |
140 | struct iop_adma_chan *iop_chan, dma_cookie_t cookie) | |
141 | { | |
507fbec4 DW |
142 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
143 | ||
144 | BUG_ON(tx->cookie < 0); | |
145 | if (tx->cookie > 0) { | |
146 | cookie = tx->cookie; | |
147 | tx->cookie = 0; | |
c2110923 DW |
148 | |
149 | /* call the callback (must not sleep or submit new | |
150 | * operations to this channel) | |
151 | */ | |
507fbec4 DW |
152 | if (tx->callback) |
153 | tx->callback(tx->callback_param); | |
c2110923 | 154 | |
d38a8c62 | 155 | dma_descriptor_unmap(tx); |
c2110923 DW |
156 | /* unmap dma addresses |
157 | * (unmap_single vs unmap_page?) | |
158 | */ | |
159 | if (desc->group_head && desc->unmap_len) { | |
7bf649ae DW |
160 | if (iop_desc_is_pq(desc)) |
161 | iop_desc_unmap_pq(iop_chan, desc); | |
162 | else | |
163 | iop_desc_unmap(iop_chan, desc); | |
c2110923 DW |
164 | } |
165 | } | |
166 | ||
167 | /* run dependent operations */ | |
507fbec4 | 168 | dma_run_dependencies(tx); |
c2110923 DW |
169 | |
170 | return cookie; | |
171 | } | |
172 | ||
173 | static int | |
174 | iop_adma_clean_slot(struct iop_adma_desc_slot *desc, | |
175 | struct iop_adma_chan *iop_chan) | |
176 | { | |
177 | /* the client is allowed to attach dependent operations | |
178 | * until 'ack' is set | |
179 | */ | |
636bdeaa | 180 | if (!async_tx_test_ack(&desc->async_tx)) |
c2110923 DW |
181 | return 0; |
182 | ||
183 | /* leave the last descriptor in the chain | |
184 | * so we can append to it | |
185 | */ | |
186 | if (desc->chain_node.next == &iop_chan->chain) | |
187 | return 1; | |
188 | ||
189 | dev_dbg(iop_chan->device->common.dev, | |
190 | "\tfree slot: %d slots_per_op: %d\n", | |
191 | desc->idx, desc->slots_per_op); | |
192 | ||
193 | list_del(&desc->chain_node); | |
194 | iop_adma_free_slots(desc); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
200 | { | |
201 | struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL; | |
202 | dma_cookie_t cookie = 0; | |
203 | u32 current_desc = iop_chan_get_current_descriptor(iop_chan); | |
204 | int busy = iop_chan_is_busy(iop_chan); | |
205 | int seen_current = 0, slot_cnt = 0, slots_per_op = 0; | |
206 | ||
3d9b525b | 207 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
208 | /* free completed slots from the chain starting with |
209 | * the oldest descriptor | |
210 | */ | |
211 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
212 | chain_node) { | |
213 | pr_debug("\tcookie: %d slot: %d busy: %d " | |
214 | "this_desc: %#x next_desc: %#x ack: %d\n", | |
215 | iter->async_tx.cookie, iter->idx, busy, | |
216 | iter->async_tx.phys, iop_desc_get_next_desc(iter), | |
636bdeaa | 217 | async_tx_test_ack(&iter->async_tx)); |
c2110923 DW |
218 | prefetch(_iter); |
219 | prefetch(&_iter->async_tx); | |
220 | ||
221 | /* do not advance past the current descriptor loaded into the | |
222 | * hardware channel, subsequent descriptors are either in | |
223 | * process or have not been submitted | |
224 | */ | |
225 | if (seen_current) | |
226 | break; | |
227 | ||
228 | /* stop the search if we reach the current descriptor and the | |
229 | * channel is busy, or if it appears that the current descriptor | |
230 | * needs to be re-read (i.e. has been appended to) | |
231 | */ | |
232 | if (iter->async_tx.phys == current_desc) { | |
233 | BUG_ON(seen_current++); | |
234 | if (busy || iop_desc_get_next_desc(iter)) | |
235 | break; | |
236 | } | |
237 | ||
238 | /* detect the start of a group transaction */ | |
239 | if (!slot_cnt && !slots_per_op) { | |
240 | slot_cnt = iter->slot_cnt; | |
241 | slots_per_op = iter->slots_per_op; | |
242 | if (slot_cnt <= slots_per_op) { | |
243 | slot_cnt = 0; | |
244 | slots_per_op = 0; | |
245 | } | |
246 | } | |
247 | ||
248 | if (slot_cnt) { | |
249 | pr_debug("\tgroup++\n"); | |
250 | if (!grp_start) | |
251 | grp_start = iter; | |
252 | slot_cnt -= slots_per_op; | |
253 | } | |
254 | ||
255 | /* all the members of a group are complete */ | |
256 | if (slots_per_op != 0 && slot_cnt == 0) { | |
257 | struct iop_adma_desc_slot *grp_iter, *_grp_iter; | |
258 | int end_of_chain = 0; | |
259 | pr_debug("\tgroup end\n"); | |
260 | ||
261 | /* collect the total results */ | |
262 | if (grp_start->xor_check_result) { | |
263 | u32 zero_sum_result = 0; | |
264 | slot_cnt = grp_start->slot_cnt; | |
265 | grp_iter = grp_start; | |
266 | ||
267 | list_for_each_entry_from(grp_iter, | |
268 | &iop_chan->chain, chain_node) { | |
269 | zero_sum_result |= | |
270 | iop_desc_get_zero_result(grp_iter); | |
271 | pr_debug("\titer%d result: %d\n", | |
272 | grp_iter->idx, zero_sum_result); | |
273 | slot_cnt -= slots_per_op; | |
274 | if (slot_cnt == 0) | |
275 | break; | |
276 | } | |
277 | pr_debug("\tgrp_start->xor_check_result: %p\n", | |
278 | grp_start->xor_check_result); | |
279 | *grp_start->xor_check_result = zero_sum_result; | |
280 | } | |
281 | ||
282 | /* clean up the group */ | |
283 | slot_cnt = grp_start->slot_cnt; | |
284 | grp_iter = grp_start; | |
285 | list_for_each_entry_safe_from(grp_iter, _grp_iter, | |
286 | &iop_chan->chain, chain_node) { | |
287 | cookie = iop_adma_run_tx_complete_actions( | |
288 | grp_iter, iop_chan, cookie); | |
289 | ||
290 | slot_cnt -= slots_per_op; | |
291 | end_of_chain = iop_adma_clean_slot(grp_iter, | |
292 | iop_chan); | |
293 | ||
294 | if (slot_cnt == 0 || end_of_chain) | |
295 | break; | |
296 | } | |
297 | ||
298 | /* the group should be complete at this point */ | |
299 | BUG_ON(slot_cnt); | |
300 | ||
301 | slots_per_op = 0; | |
302 | grp_start = NULL; | |
303 | if (end_of_chain) | |
304 | break; | |
305 | else | |
306 | continue; | |
307 | } else if (slots_per_op) /* wait for group completion */ | |
308 | continue; | |
309 | ||
310 | /* write back zero sum results (single descriptor case) */ | |
311 | if (iter->xor_check_result && iter->async_tx.cookie) | |
312 | *iter->xor_check_result = | |
313 | iop_desc_get_zero_result(iter); | |
314 | ||
315 | cookie = iop_adma_run_tx_complete_actions( | |
316 | iter, iop_chan, cookie); | |
317 | ||
318 | if (iop_adma_clean_slot(iter, iop_chan)) | |
319 | break; | |
320 | } | |
321 | ||
c2110923 | 322 | if (cookie > 0) { |
4d4e58de | 323 | iop_chan->common.completed_cookie = cookie; |
c2110923 DW |
324 | pr_debug("\tcompleted cookie %d\n", cookie); |
325 | } | |
326 | } | |
327 | ||
328 | static void | |
329 | iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
330 | { | |
331 | spin_lock_bh(&iop_chan->lock); | |
332 | __iop_adma_slot_cleanup(iop_chan); | |
333 | spin_unlock_bh(&iop_chan->lock); | |
334 | } | |
335 | ||
336 | static void iop_adma_tasklet(unsigned long data) | |
337 | { | |
19242d72 DW |
338 | struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data; |
339 | ||
72be12f0 DW |
340 | /* lockdep will flag depedency submissions as potentially |
341 | * recursive locking, this is not the case as a dependency | |
342 | * submission will never recurse a channels submit routine. | |
343 | * There are checks in async_tx.c to prevent this. | |
344 | */ | |
345 | spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING); | |
19242d72 DW |
346 | __iop_adma_slot_cleanup(iop_chan); |
347 | spin_unlock(&iop_chan->lock); | |
c2110923 DW |
348 | } |
349 | ||
350 | static struct iop_adma_desc_slot * | |
351 | iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots, | |
352 | int slots_per_op) | |
353 | { | |
354 | struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL; | |
e73ef9ac | 355 | LIST_HEAD(chain); |
c2110923 DW |
356 | int slots_found, retry = 0; |
357 | ||
358 | /* start search from the last allocated descrtiptor | |
359 | * if a contiguous allocation can not be found start searching | |
360 | * from the beginning of the list | |
361 | */ | |
362 | retry: | |
363 | slots_found = 0; | |
364 | if (retry == 0) | |
365 | iter = iop_chan->last_used; | |
366 | else | |
367 | iter = list_entry(&iop_chan->all_slots, | |
368 | struct iop_adma_desc_slot, | |
369 | slot_node); | |
370 | ||
371 | list_for_each_entry_safe_continue( | |
372 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
373 | prefetch(_iter); | |
374 | prefetch(&_iter->async_tx); | |
375 | if (iter->slots_per_op) { | |
376 | /* give up after finding the first busy slot | |
377 | * on the second pass through the list | |
378 | */ | |
379 | if (retry) | |
380 | break; | |
381 | ||
382 | slots_found = 0; | |
383 | continue; | |
384 | } | |
385 | ||
386 | /* start the allocation if the slot is correctly aligned */ | |
387 | if (!slots_found++) { | |
388 | if (iop_desc_is_aligned(iter, slots_per_op)) | |
389 | alloc_start = iter; | |
390 | else { | |
391 | slots_found = 0; | |
392 | continue; | |
393 | } | |
394 | } | |
395 | ||
396 | if (slots_found == num_slots) { | |
397 | struct iop_adma_desc_slot *alloc_tail = NULL; | |
398 | struct iop_adma_desc_slot *last_used = NULL; | |
399 | iter = alloc_start; | |
400 | while (num_slots) { | |
401 | int i; | |
402 | dev_dbg(iop_chan->device->common.dev, | |
403 | "allocated slot: %d " | |
404 | "(desc %p phys: %#x) slots_per_op %d\n", | |
405 | iter->idx, iter->hw_desc, | |
406 | iter->async_tx.phys, slots_per_op); | |
407 | ||
408 | /* pre-ack all but the last descriptor */ | |
409 | if (num_slots != slots_per_op) | |
636bdeaa | 410 | async_tx_ack(&iter->async_tx); |
c2110923 DW |
411 | |
412 | list_add_tail(&iter->chain_node, &chain); | |
413 | alloc_tail = iter; | |
414 | iter->async_tx.cookie = 0; | |
415 | iter->slot_cnt = num_slots; | |
416 | iter->xor_check_result = NULL; | |
417 | for (i = 0; i < slots_per_op; i++) { | |
418 | iter->slots_per_op = slots_per_op - i; | |
419 | last_used = iter; | |
420 | iter = list_entry(iter->slot_node.next, | |
421 | struct iop_adma_desc_slot, | |
422 | slot_node); | |
423 | } | |
424 | num_slots -= slots_per_op; | |
425 | } | |
426 | alloc_tail->group_head = alloc_start; | |
427 | alloc_tail->async_tx.cookie = -EBUSY; | |
308136d1 | 428 | list_splice(&chain, &alloc_tail->tx_list); |
c2110923 DW |
429 | iop_chan->last_used = last_used; |
430 | iop_desc_clear_next_desc(alloc_start); | |
431 | iop_desc_clear_next_desc(alloc_tail); | |
432 | return alloc_tail; | |
433 | } | |
434 | } | |
435 | if (!retry++) | |
436 | goto retry; | |
437 | ||
c7141d00 DW |
438 | /* perform direct reclaim if the allocation fails */ |
439 | __iop_adma_slot_cleanup(iop_chan); | |
c2110923 DW |
440 | |
441 | return NULL; | |
442 | } | |
443 | ||
c2110923 DW |
444 | static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan) |
445 | { | |
446 | dev_dbg(iop_chan->device->common.dev, "pending: %d\n", | |
447 | iop_chan->pending); | |
448 | ||
449 | if (iop_chan->pending >= IOP_ADMA_THRESHOLD) { | |
450 | iop_chan->pending = 0; | |
451 | iop_chan_append(iop_chan); | |
452 | } | |
453 | } | |
454 | ||
455 | static dma_cookie_t | |
456 | iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) | |
457 | { | |
458 | struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx); | |
459 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); | |
460 | struct iop_adma_desc_slot *grp_start, *old_chain_tail; | |
461 | int slot_cnt; | |
462 | int slots_per_op; | |
463 | dma_cookie_t cookie; | |
137cb55c | 464 | dma_addr_t next_dma; |
c2110923 DW |
465 | |
466 | grp_start = sw_desc->group_head; | |
467 | slot_cnt = grp_start->slot_cnt; | |
468 | slots_per_op = grp_start->slots_per_op; | |
469 | ||
470 | spin_lock_bh(&iop_chan->lock); | |
884485e1 | 471 | cookie = dma_cookie_assign(tx); |
c2110923 DW |
472 | |
473 | old_chain_tail = list_entry(iop_chan->chain.prev, | |
474 | struct iop_adma_desc_slot, chain_node); | |
308136d1 | 475 | list_splice_init(&sw_desc->tx_list, |
c2110923 DW |
476 | &old_chain_tail->chain_node); |
477 | ||
478 | /* fix up the hardware chain */ | |
137cb55c DW |
479 | next_dma = grp_start->async_tx.phys; |
480 | iop_desc_set_next_desc(old_chain_tail, next_dma); | |
481 | BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ | |
c2110923 | 482 | |
137cb55c | 483 | /* check for pre-chained descriptors */ |
65e50381 | 484 | iop_paranoia(iop_desc_get_next_desc(sw_desc)); |
c2110923 DW |
485 | |
486 | /* increment the pending count by the number of slots | |
487 | * memcpy operations have a 1:1 (slot:operation) relation | |
488 | * other operations are heavier and will pop the threshold | |
489 | * more often. | |
490 | */ | |
491 | iop_chan->pending += slot_cnt; | |
492 | iop_adma_check_threshold(iop_chan); | |
493 | spin_unlock_bh(&iop_chan->lock); | |
494 | ||
495 | dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n", | |
3d9b525b | 496 | __func__, sw_desc->async_tx.cookie, sw_desc->idx); |
c2110923 DW |
497 | |
498 | return cookie; | |
499 | } | |
500 | ||
c2110923 DW |
501 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan); |
502 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan); | |
503 | ||
5eb907aa DW |
504 | /** |
505 | * iop_adma_alloc_chan_resources - returns the number of allocated descriptors | |
506 | * @chan - allocate descriptor resources for this channel | |
507 | * @client - current client requesting the channel be ready for requests | |
508 | * | |
509 | * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To | |
510 | * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be | |
511 | * greater than 2x the number slots needed to satisfy a device->max_xor | |
512 | * request. | |
513 | * */ | |
aa1e6f1a | 514 | static int iop_adma_alloc_chan_resources(struct dma_chan *chan) |
c2110923 DW |
515 | { |
516 | char *hw_desc; | |
517 | int idx; | |
518 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
519 | struct iop_adma_desc_slot *slot = NULL; | |
520 | int init = iop_chan->slots_allocated ? 0 : 1; | |
521 | struct iop_adma_platform_data *plat_data = | |
d4adcc01 | 522 | dev_get_platdata(&iop_chan->device->pdev->dev); |
c2110923 DW |
523 | int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE; |
524 | ||
525 | /* Allocate descriptor slots */ | |
526 | do { | |
527 | idx = iop_chan->slots_allocated; | |
528 | if (idx == num_descs_in_pool) | |
529 | break; | |
530 | ||
531 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
532 | if (!slot) { | |
533 | printk(KERN_INFO "IOP ADMA Channel only initialized" | |
534 | " %d descriptor slots", idx); | |
535 | break; | |
536 | } | |
537 | hw_desc = (char *) iop_chan->device->dma_desc_pool_virt; | |
538 | slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; | |
539 | ||
540 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
541 | slot->async_tx.tx_submit = iop_adma_tx_submit; | |
308136d1 | 542 | INIT_LIST_HEAD(&slot->tx_list); |
c2110923 DW |
543 | INIT_LIST_HEAD(&slot->chain_node); |
544 | INIT_LIST_HEAD(&slot->slot_node); | |
c2110923 DW |
545 | hw_desc = (char *) iop_chan->device->dma_desc_pool; |
546 | slot->async_tx.phys = | |
547 | (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; | |
548 | slot->idx = idx; | |
549 | ||
550 | spin_lock_bh(&iop_chan->lock); | |
551 | iop_chan->slots_allocated++; | |
552 | list_add_tail(&slot->slot_node, &iop_chan->all_slots); | |
553 | spin_unlock_bh(&iop_chan->lock); | |
554 | } while (iop_chan->slots_allocated < num_descs_in_pool); | |
555 | ||
556 | if (idx && !iop_chan->last_used) | |
557 | iop_chan->last_used = list_entry(iop_chan->all_slots.next, | |
558 | struct iop_adma_desc_slot, | |
559 | slot_node); | |
560 | ||
561 | dev_dbg(iop_chan->device->common.dev, | |
562 | "allocated %d descriptor slots last_used: %p\n", | |
563 | iop_chan->slots_allocated, iop_chan->last_used); | |
564 | ||
565 | /* initialize the channel and the chain with a null operation */ | |
566 | if (init) { | |
567 | if (dma_has_cap(DMA_MEMCPY, | |
568 | iop_chan->device->common.cap_mask)) | |
569 | iop_chan_start_null_memcpy(iop_chan); | |
570 | else if (dma_has_cap(DMA_XOR, | |
571 | iop_chan->device->common.cap_mask)) | |
572 | iop_chan_start_null_xor(iop_chan); | |
573 | else | |
574 | BUG(); | |
575 | } | |
576 | ||
577 | return (idx > 0) ? idx : -ENOMEM; | |
578 | } | |
579 | ||
580 | static struct dma_async_tx_descriptor * | |
636bdeaa | 581 | iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
c2110923 DW |
582 | { |
583 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
584 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
585 | int slot_cnt, slots_per_op; | |
586 | ||
3d9b525b | 587 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
588 | |
589 | spin_lock_bh(&iop_chan->lock); | |
590 | slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan); | |
591 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
592 | if (sw_desc) { | |
593 | grp_start = sw_desc->group_head; | |
594 | iop_desc_init_interrupt(grp_start, iop_chan); | |
595 | grp_start->unmap_len = 0; | |
636bdeaa | 596 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
597 | } |
598 | spin_unlock_bh(&iop_chan->lock); | |
599 | ||
600 | return sw_desc ? &sw_desc->async_tx : NULL; | |
601 | } | |
602 | ||
c2110923 | 603 | static struct dma_async_tx_descriptor * |
0036731c | 604 | iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, |
d4c56f97 | 605 | dma_addr_t dma_src, size_t len, unsigned long flags) |
c2110923 DW |
606 | { |
607 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
608 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
609 | int slot_cnt, slots_per_op; | |
610 | ||
611 | if (unlikely(!len)) | |
612 | return NULL; | |
e2ec771a | 613 | BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT); |
c2110923 DW |
614 | |
615 | dev_dbg(iop_chan->device->common.dev, "%s len: %u\n", | |
3d9b525b | 616 | __func__, len); |
c2110923 DW |
617 | |
618 | spin_lock_bh(&iop_chan->lock); | |
619 | slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op); | |
620 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
621 | if (sw_desc) { | |
622 | grp_start = sw_desc->group_head; | |
d4c56f97 | 623 | iop_desc_init_memcpy(grp_start, flags); |
c2110923 | 624 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c DW |
625 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
626 | iop_desc_set_memcpy_src_addr(grp_start, dma_src); | |
c2110923 DW |
627 | sw_desc->unmap_src_cnt = 1; |
628 | sw_desc->unmap_len = len; | |
636bdeaa | 629 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
630 | } |
631 | spin_unlock_bh(&iop_chan->lock); | |
632 | ||
633 | return sw_desc ? &sw_desc->async_tx : NULL; | |
634 | } | |
635 | ||
c2110923 | 636 | static struct dma_async_tx_descriptor * |
0036731c DW |
637 | iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, |
638 | dma_addr_t *dma_src, unsigned int src_cnt, size_t len, | |
d4c56f97 | 639 | unsigned long flags) |
c2110923 DW |
640 | { |
641 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
642 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
643 | int slot_cnt, slots_per_op; | |
644 | ||
645 | if (unlikely(!len)) | |
646 | return NULL; | |
e2ec771a | 647 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); |
c2110923 DW |
648 | |
649 | dev_dbg(iop_chan->device->common.dev, | |
d4c56f97 | 650 | "%s src_cnt: %d len: %u flags: %lx\n", |
3d9b525b | 651 | __func__, src_cnt, len, flags); |
c2110923 DW |
652 | |
653 | spin_lock_bh(&iop_chan->lock); | |
654 | slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op); | |
655 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
656 | if (sw_desc) { | |
657 | grp_start = sw_desc->group_head; | |
d4c56f97 | 658 | iop_desc_init_xor(grp_start, src_cnt, flags); |
c2110923 | 659 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c | 660 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
c2110923 DW |
661 | sw_desc->unmap_src_cnt = src_cnt; |
662 | sw_desc->unmap_len = len; | |
636bdeaa | 663 | sw_desc->async_tx.flags = flags; |
0036731c DW |
664 | while (src_cnt--) |
665 | iop_desc_set_xor_src_addr(grp_start, src_cnt, | |
666 | dma_src[src_cnt]); | |
c2110923 DW |
667 | } |
668 | spin_unlock_bh(&iop_chan->lock); | |
669 | ||
670 | return sw_desc ? &sw_desc->async_tx : NULL; | |
671 | } | |
672 | ||
c2110923 | 673 | static struct dma_async_tx_descriptor * |
099f53cb DW |
674 | iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, |
675 | unsigned int src_cnt, size_t len, u32 *result, | |
676 | unsigned long flags) | |
c2110923 DW |
677 | { |
678 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
679 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
680 | int slot_cnt, slots_per_op; | |
681 | ||
682 | if (unlikely(!len)) | |
683 | return NULL; | |
684 | ||
685 | dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", | |
3d9b525b | 686 | __func__, src_cnt, len); |
c2110923 DW |
687 | |
688 | spin_lock_bh(&iop_chan->lock); | |
689 | slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op); | |
690 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
691 | if (sw_desc) { | |
692 | grp_start = sw_desc->group_head; | |
d4c56f97 | 693 | iop_desc_init_zero_sum(grp_start, src_cnt, flags); |
c2110923 DW |
694 | iop_desc_set_zero_sum_byte_count(grp_start, len); |
695 | grp_start->xor_check_result = result; | |
696 | pr_debug("\t%s: grp_start->xor_check_result: %p\n", | |
3d9b525b | 697 | __func__, grp_start->xor_check_result); |
c2110923 DW |
698 | sw_desc->unmap_src_cnt = src_cnt; |
699 | sw_desc->unmap_len = len; | |
636bdeaa | 700 | sw_desc->async_tx.flags = flags; |
0036731c DW |
701 | while (src_cnt--) |
702 | iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, | |
703 | dma_src[src_cnt]); | |
c2110923 DW |
704 | } |
705 | spin_unlock_bh(&iop_chan->lock); | |
706 | ||
707 | return sw_desc ? &sw_desc->async_tx : NULL; | |
708 | } | |
709 | ||
7bf649ae DW |
710 | static struct dma_async_tx_descriptor * |
711 | iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
712 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
713 | unsigned long flags) | |
714 | { | |
715 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
716 | struct iop_adma_desc_slot *sw_desc, *g; | |
717 | int slot_cnt, slots_per_op; | |
718 | int continue_srcs; | |
719 | ||
720 | if (unlikely(!len)) | |
721 | return NULL; | |
722 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); | |
723 | ||
724 | dev_dbg(iop_chan->device->common.dev, | |
725 | "%s src_cnt: %d len: %u flags: %lx\n", | |
726 | __func__, src_cnt, len, flags); | |
727 | ||
728 | if (dmaf_p_disabled_continue(flags)) | |
729 | continue_srcs = 1+src_cnt; | |
730 | else if (dmaf_continue(flags)) | |
731 | continue_srcs = 3+src_cnt; | |
732 | else | |
733 | continue_srcs = 0+src_cnt; | |
734 | ||
735 | spin_lock_bh(&iop_chan->lock); | |
736 | slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op); | |
737 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
738 | if (sw_desc) { | |
739 | int i; | |
740 | ||
741 | g = sw_desc->group_head; | |
742 | iop_desc_set_byte_count(g, iop_chan, len); | |
743 | ||
744 | /* even if P is disabled its destination address (bits | |
745 | * [3:0]) must match Q. It is ok if P points to an | |
746 | * invalid address, it won't be written. | |
747 | */ | |
748 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
749 | dst[0] = dst[1] & 0x7; | |
750 | ||
751 | iop_desc_set_pq_addr(g, dst); | |
752 | sw_desc->unmap_src_cnt = src_cnt; | |
753 | sw_desc->unmap_len = len; | |
754 | sw_desc->async_tx.flags = flags; | |
755 | for (i = 0; i < src_cnt; i++) | |
756 | iop_desc_set_pq_src_addr(g, i, src[i], scf[i]); | |
757 | ||
758 | /* if we are continuing a previous operation factor in | |
759 | * the old p and q values, see the comment for dma_maxpq | |
760 | * in include/linux/dmaengine.h | |
761 | */ | |
762 | if (dmaf_p_disabled_continue(flags)) | |
763 | iop_desc_set_pq_src_addr(g, i++, dst[1], 1); | |
764 | else if (dmaf_continue(flags)) { | |
765 | iop_desc_set_pq_src_addr(g, i++, dst[0], 0); | |
766 | iop_desc_set_pq_src_addr(g, i++, dst[1], 1); | |
767 | iop_desc_set_pq_src_addr(g, i++, dst[1], 0); | |
768 | } | |
769 | iop_desc_init_pq(g, i, flags); | |
770 | } | |
771 | spin_unlock_bh(&iop_chan->lock); | |
772 | ||
773 | return sw_desc ? &sw_desc->async_tx : NULL; | |
774 | } | |
775 | ||
776 | static struct dma_async_tx_descriptor * | |
777 | iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
778 | unsigned int src_cnt, const unsigned char *scf, | |
779 | size_t len, enum sum_check_flags *pqres, | |
780 | unsigned long flags) | |
781 | { | |
782 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
783 | struct iop_adma_desc_slot *sw_desc, *g; | |
784 | int slot_cnt, slots_per_op; | |
785 | ||
786 | if (unlikely(!len)) | |
787 | return NULL; | |
788 | BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); | |
789 | ||
790 | dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", | |
791 | __func__, src_cnt, len); | |
792 | ||
793 | spin_lock_bh(&iop_chan->lock); | |
794 | slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op); | |
795 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
796 | if (sw_desc) { | |
797 | /* for validate operations p and q are tagged onto the | |
798 | * end of the source list | |
799 | */ | |
800 | int pq_idx = src_cnt; | |
801 | ||
802 | g = sw_desc->group_head; | |
803 | iop_desc_init_pq_zero_sum(g, src_cnt+2, flags); | |
804 | iop_desc_set_pq_zero_sum_byte_count(g, len); | |
805 | g->pq_check_result = pqres; | |
806 | pr_debug("\t%s: g->pq_check_result: %p\n", | |
807 | __func__, g->pq_check_result); | |
808 | sw_desc->unmap_src_cnt = src_cnt+2; | |
809 | sw_desc->unmap_len = len; | |
810 | sw_desc->async_tx.flags = flags; | |
811 | while (src_cnt--) | |
812 | iop_desc_set_pq_zero_sum_src_addr(g, src_cnt, | |
813 | src[src_cnt], | |
814 | scf[src_cnt]); | |
815 | iop_desc_set_pq_zero_sum_addr(g, pq_idx, src); | |
816 | } | |
817 | spin_unlock_bh(&iop_chan->lock); | |
818 | ||
819 | return sw_desc ? &sw_desc->async_tx : NULL; | |
820 | } | |
821 | ||
c2110923 DW |
822 | static void iop_adma_free_chan_resources(struct dma_chan *chan) |
823 | { | |
824 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
825 | struct iop_adma_desc_slot *iter, *_iter; | |
826 | int in_use_descs = 0; | |
827 | ||
828 | iop_adma_slot_cleanup(iop_chan); | |
829 | ||
830 | spin_lock_bh(&iop_chan->lock); | |
831 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
832 | chain_node) { | |
833 | in_use_descs++; | |
834 | list_del(&iter->chain_node); | |
835 | } | |
836 | list_for_each_entry_safe_reverse( | |
837 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
838 | list_del(&iter->slot_node); | |
839 | kfree(iter); | |
840 | iop_chan->slots_allocated--; | |
841 | } | |
842 | iop_chan->last_used = NULL; | |
843 | ||
844 | dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n", | |
3d9b525b | 845 | __func__, iop_chan->slots_allocated); |
c2110923 DW |
846 | spin_unlock_bh(&iop_chan->lock); |
847 | ||
848 | /* one is ok since we left it on there on purpose */ | |
849 | if (in_use_descs > 1) | |
850 | printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n", | |
851 | in_use_descs - 1); | |
852 | } | |
853 | ||
854 | /** | |
07934481 | 855 | * iop_adma_status - poll the status of an ADMA transaction |
c2110923 DW |
856 | * @chan: ADMA channel handle |
857 | * @cookie: ADMA transaction identifier | |
07934481 | 858 | * @txstate: a holder for the current state of the channel or NULL |
c2110923 | 859 | */ |
07934481 | 860 | static enum dma_status iop_adma_status(struct dma_chan *chan, |
c2110923 | 861 | dma_cookie_t cookie, |
07934481 | 862 | struct dma_tx_state *txstate) |
c2110923 DW |
863 | { |
864 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
949ff5b8 | 865 | int ret; |
96a2af41 RKAL |
866 | |
867 | ret = dma_cookie_status(chan, cookie, txstate); | |
c2110923 DW |
868 | if (ret == DMA_SUCCESS) |
869 | return ret; | |
870 | ||
871 | iop_adma_slot_cleanup(iop_chan); | |
872 | ||
96a2af41 | 873 | return dma_cookie_status(chan, cookie, txstate); |
c2110923 DW |
874 | } |
875 | ||
876 | static irqreturn_t iop_adma_eot_handler(int irq, void *data) | |
877 | { | |
878 | struct iop_adma_chan *chan = data; | |
879 | ||
3d9b525b | 880 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
881 | |
882 | tasklet_schedule(&chan->irq_tasklet); | |
883 | ||
884 | iop_adma_device_clear_eot_status(chan); | |
885 | ||
886 | return IRQ_HANDLED; | |
887 | } | |
888 | ||
889 | static irqreturn_t iop_adma_eoc_handler(int irq, void *data) | |
890 | { | |
891 | struct iop_adma_chan *chan = data; | |
892 | ||
3d9b525b | 893 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
894 | |
895 | tasklet_schedule(&chan->irq_tasklet); | |
896 | ||
897 | iop_adma_device_clear_eoc_status(chan); | |
898 | ||
899 | return IRQ_HANDLED; | |
900 | } | |
901 | ||
902 | static irqreturn_t iop_adma_err_handler(int irq, void *data) | |
903 | { | |
904 | struct iop_adma_chan *chan = data; | |
905 | unsigned long status = iop_chan_get_status(chan); | |
906 | ||
1ba151cd | 907 | dev_err(chan->device->common.dev, |
c2110923 DW |
908 | "error ( %s%s%s%s%s%s%s)\n", |
909 | iop_is_err_int_parity(status, chan) ? "int_parity " : "", | |
910 | iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "", | |
911 | iop_is_err_int_tabort(status, chan) ? "int_tabort " : "", | |
912 | iop_is_err_int_mabort(status, chan) ? "int_mabort " : "", | |
913 | iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "", | |
914 | iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "", | |
915 | iop_is_err_split_tx(status, chan) ? "split_tx " : ""); | |
916 | ||
917 | iop_adma_device_clear_err_status(chan); | |
918 | ||
919 | BUG(); | |
920 | ||
921 | return IRQ_HANDLED; | |
922 | } | |
923 | ||
924 | static void iop_adma_issue_pending(struct dma_chan *chan) | |
925 | { | |
926 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
927 | ||
928 | if (iop_chan->pending) { | |
929 | iop_chan->pending = 0; | |
930 | iop_chan_append(iop_chan); | |
931 | } | |
932 | } | |
933 | ||
934 | /* | |
935 | * Perform a transaction to verify the HW works. | |
936 | */ | |
937 | #define IOP_ADMA_TEST_SIZE 2000 | |
938 | ||
463a1f8b | 939 | static int iop_adma_memcpy_self_test(struct iop_adma_device *device) |
c2110923 DW |
940 | { |
941 | int i; | |
942 | void *src, *dest; | |
943 | dma_addr_t src_dma, dest_dma; | |
944 | struct dma_chan *dma_chan; | |
945 | dma_cookie_t cookie; | |
946 | struct dma_async_tx_descriptor *tx; | |
947 | int err = 0; | |
948 | struct iop_adma_chan *iop_chan; | |
949 | ||
3d9b525b | 950 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 | 951 | |
eccf2144 | 952 | src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
953 | if (!src) |
954 | return -ENOMEM; | |
eccf2144 | 955 | dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
956 | if (!dest) { |
957 | kfree(src); | |
958 | return -ENOMEM; | |
959 | } | |
960 | ||
961 | /* Fill in src buffer */ | |
962 | for (i = 0; i < IOP_ADMA_TEST_SIZE; i++) | |
963 | ((u8 *) src)[i] = (u8)i; | |
964 | ||
c2110923 DW |
965 | /* Start copy, using first DMA channel */ |
966 | dma_chan = container_of(device->common.channels.next, | |
967 | struct dma_chan, | |
968 | device_node); | |
aa1e6f1a | 969 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c2110923 DW |
970 | err = -ENODEV; |
971 | goto out; | |
972 | } | |
973 | ||
c2110923 DW |
974 | dest_dma = dma_map_single(dma_chan->device->dev, dest, |
975 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
c2110923 DW |
976 | src_dma = dma_map_single(dma_chan->device->dev, src, |
977 | IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); | |
0036731c | 978 | tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
636bdeaa DW |
979 | IOP_ADMA_TEST_SIZE, |
980 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
981 | |
982 | cookie = iop_adma_tx_submit(tx); | |
983 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
984 | msleep(1); |
985 | ||
07934481 | 986 | if (iop_adma_status(dma_chan, cookie, NULL) != |
c2110923 | 987 | DMA_SUCCESS) { |
1ba151cd | 988 | dev_err(dma_chan->device->dev, |
c2110923 DW |
989 | "Self-test copy timed out, disabling\n"); |
990 | err = -ENODEV; | |
991 | goto free_resources; | |
992 | } | |
993 | ||
994 | iop_chan = to_iop_adma_chan(dma_chan); | |
995 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
996 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
997 | if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) { | |
1ba151cd | 998 | dev_err(dma_chan->device->dev, |
c2110923 DW |
999 | "Self-test copy failed compare, disabling\n"); |
1000 | err = -ENODEV; | |
1001 | goto free_resources; | |
1002 | } | |
1003 | ||
1004 | free_resources: | |
1005 | iop_adma_free_chan_resources(dma_chan); | |
1006 | out: | |
1007 | kfree(src); | |
1008 | kfree(dest); | |
1009 | return err; | |
1010 | } | |
1011 | ||
1012 | #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 1013 | static int |
099f53cb | 1014 | iop_adma_xor_val_self_test(struct iop_adma_device *device) |
c2110923 DW |
1015 | { |
1016 | int i, src_idx; | |
1017 | struct page *dest; | |
1018 | struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST]; | |
1019 | struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; | |
0036731c | 1020 | dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; |
f9f0a7d0 | 1021 | dma_addr_t dest_dma; |
c2110923 DW |
1022 | struct dma_async_tx_descriptor *tx; |
1023 | struct dma_chan *dma_chan; | |
1024 | dma_cookie_t cookie; | |
1025 | u8 cmp_byte = 0; | |
1026 | u32 cmp_word; | |
1027 | u32 zero_sum_result; | |
1028 | int err = 0; | |
1029 | struct iop_adma_chan *iop_chan; | |
1030 | ||
3d9b525b | 1031 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 DW |
1032 | |
1033 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
1034 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
1035 | if (!xor_srcs[src_idx]) { |
1036 | while (src_idx--) | |
c2110923 | 1037 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
1038 | return -ENOMEM; |
1039 | } | |
c2110923 DW |
1040 | } |
1041 | ||
1042 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
1043 | if (!dest) { |
1044 | while (src_idx--) | |
c2110923 | 1045 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
1046 | return -ENOMEM; |
1047 | } | |
c2110923 DW |
1048 | |
1049 | /* Fill in src buffers */ | |
1050 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
1051 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
1052 | for (i = 0; i < PAGE_SIZE; i++) | |
1053 | ptr[i] = (1 << src_idx); | |
1054 | } | |
1055 | ||
1056 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) | |
1057 | cmp_byte ^= (u8) (1 << src_idx); | |
1058 | ||
1059 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
1060 | (cmp_byte << 8) | cmp_byte; | |
1061 | ||
1062 | memset(page_address(dest), 0, PAGE_SIZE); | |
1063 | ||
1064 | dma_chan = container_of(device->common.channels.next, | |
1065 | struct dma_chan, | |
1066 | device_node); | |
aa1e6f1a | 1067 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { |
c2110923 DW |
1068 | err = -ENODEV; |
1069 | goto out; | |
1070 | } | |
1071 | ||
1072 | /* test xor */ | |
c2110923 DW |
1073 | dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, |
1074 | PAGE_SIZE, DMA_FROM_DEVICE); | |
0036731c DW |
1075 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) |
1076 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
1077 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
1078 | tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
636bdeaa DW |
1079 | IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, |
1080 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1081 | |
1082 | cookie = iop_adma_tx_submit(tx); | |
1083 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1084 | msleep(8); |
1085 | ||
07934481 | 1086 | if (iop_adma_status(dma_chan, cookie, NULL) != |
c2110923 | 1087 | DMA_SUCCESS) { |
1ba151cd | 1088 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1089 | "Self-test xor timed out, disabling\n"); |
1090 | err = -ENODEV; | |
1091 | goto free_resources; | |
1092 | } | |
1093 | ||
1094 | iop_chan = to_iop_adma_chan(dma_chan); | |
1095 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
1096 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1097 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
1098 | u32 *ptr = page_address(dest); | |
1099 | if (ptr[i] != cmp_word) { | |
1ba151cd | 1100 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1101 | "Self-test xor failed compare, disabling\n"); |
1102 | err = -ENODEV; | |
1103 | goto free_resources; | |
1104 | } | |
1105 | } | |
1106 | dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma, | |
1107 | PAGE_SIZE, DMA_TO_DEVICE); | |
1108 | ||
1109 | /* skip zero sum if the capability is not present */ | |
099f53cb | 1110 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) |
c2110923 DW |
1111 | goto free_resources; |
1112 | ||
1113 | /* zero sum the sources with the destintation page */ | |
1114 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) | |
1115 | zero_sum_srcs[i] = xor_srcs[i]; | |
1116 | zero_sum_srcs[i] = dest; | |
1117 | ||
1118 | zero_sum_result = 1; | |
1119 | ||
0036731c DW |
1120 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1121 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1122 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1123 | DMA_TO_DEVICE); | |
099f53cb DW |
1124 | tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, |
1125 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1126 | &zero_sum_result, | |
1127 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1128 | |
1129 | cookie = iop_adma_tx_submit(tx); | |
1130 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1131 | msleep(8); |
1132 | ||
07934481 | 1133 | if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
1ba151cd | 1134 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1135 | "Self-test zero sum timed out, disabling\n"); |
1136 | err = -ENODEV; | |
1137 | goto free_resources; | |
1138 | } | |
1139 | ||
1140 | if (zero_sum_result != 0) { | |
1ba151cd | 1141 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1142 | "Self-test zero sum failed compare, disabling\n"); |
1143 | err = -ENODEV; | |
1144 | goto free_resources; | |
1145 | } | |
1146 | ||
c2110923 DW |
1147 | /* test for non-zero parity sum */ |
1148 | zero_sum_result = 0; | |
0036731c DW |
1149 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1150 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1151 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1152 | DMA_TO_DEVICE); | |
099f53cb DW |
1153 | tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, |
1154 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1155 | &zero_sum_result, | |
1156 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1157 | |
1158 | cookie = iop_adma_tx_submit(tx); | |
1159 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1160 | msleep(8); |
1161 | ||
07934481 | 1162 | if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) { |
1ba151cd | 1163 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1164 | "Self-test non-zero sum timed out, disabling\n"); |
1165 | err = -ENODEV; | |
1166 | goto free_resources; | |
1167 | } | |
1168 | ||
1169 | if (zero_sum_result != 1) { | |
1ba151cd | 1170 | dev_err(dma_chan->device->dev, |
c2110923 DW |
1171 | "Self-test non-zero sum failed compare, disabling\n"); |
1172 | err = -ENODEV; | |
1173 | goto free_resources; | |
1174 | } | |
1175 | ||
1176 | free_resources: | |
1177 | iop_adma_free_chan_resources(dma_chan); | |
1178 | out: | |
1179 | src_idx = IOP_ADMA_NUM_SRC_TEST; | |
1180 | while (src_idx--) | |
1181 | __free_page(xor_srcs[src_idx]); | |
1182 | __free_page(dest); | |
1183 | return err; | |
1184 | } | |
1185 | ||
0261f741 | 1186 | #ifdef CONFIG_RAID6_PQ |
463a1f8b | 1187 | static int |
f6dbf651 DW |
1188 | iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device) |
1189 | { | |
1190 | /* combined sources, software pq results, and extra hw pq results */ | |
1191 | struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2]; | |
1192 | /* ptr to the extra hw pq buffers defined above */ | |
1193 | struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2]; | |
1194 | /* address conversion buffers (dma_map / page_address) */ | |
1195 | void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2]; | |
3d9ea9e3 DM |
1196 | dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2]; |
1197 | dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST]; | |
f6dbf651 DW |
1198 | |
1199 | int i; | |
1200 | struct dma_async_tx_descriptor *tx; | |
1201 | struct dma_chan *dma_chan; | |
1202 | dma_cookie_t cookie; | |
1203 | u32 zero_sum_result; | |
1204 | int err = 0; | |
1205 | struct device *dev; | |
1206 | ||
1207 | dev_dbg(device->common.dev, "%s\n", __func__); | |
1208 | ||
1209 | for (i = 0; i < ARRAY_SIZE(pq); i++) { | |
1210 | pq[i] = alloc_page(GFP_KERNEL); | |
1211 | if (!pq[i]) { | |
1212 | while (i--) | |
1213 | __free_page(pq[i]); | |
1214 | return -ENOMEM; | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | /* Fill in src buffers */ | |
1219 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) { | |
1220 | pq_sw[i] = page_address(pq[i]); | |
1221 | memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE); | |
1222 | } | |
1223 | pq_sw[i] = page_address(pq[i]); | |
1224 | pq_sw[i+1] = page_address(pq[i+1]); | |
1225 | ||
1226 | dma_chan = container_of(device->common.channels.next, | |
1227 | struct dma_chan, | |
1228 | device_node); | |
1229 | if (iop_adma_alloc_chan_resources(dma_chan) < 1) { | |
1230 | err = -ENODEV; | |
1231 | goto out; | |
1232 | } | |
1233 | ||
1234 | dev = dma_chan->device->dev; | |
1235 | ||
1236 | /* initialize the dests */ | |
1237 | memset(page_address(pq_hw[0]), 0 , PAGE_SIZE); | |
1238 | memset(page_address(pq_hw[1]), 0 , PAGE_SIZE); | |
1239 | ||
1240 | /* test pq */ | |
1241 | pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
1242 | pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
1243 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) | |
1244 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1245 | DMA_TO_DEVICE); | |
1246 | ||
1247 | tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src, | |
1248 | IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp, | |
1249 | PAGE_SIZE, | |
1250 | DMA_PREP_INTERRUPT | | |
1251 | DMA_CTRL_ACK); | |
1252 | ||
1253 | cookie = iop_adma_tx_submit(tx); | |
1254 | iop_adma_issue_pending(dma_chan); | |
1255 | msleep(8); | |
1256 | ||
07934481 | 1257 | if (iop_adma_status(dma_chan, cookie, NULL) != |
f6dbf651 DW |
1258 | DMA_SUCCESS) { |
1259 | dev_err(dev, "Self-test pq timed out, disabling\n"); | |
1260 | err = -ENODEV; | |
1261 | goto free_resources; | |
1262 | } | |
1263 | ||
1264 | raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw); | |
1265 | ||
1266 | if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST], | |
1267 | page_address(pq_hw[0]), PAGE_SIZE) != 0) { | |
1268 | dev_err(dev, "Self-test p failed compare, disabling\n"); | |
1269 | err = -ENODEV; | |
1270 | goto free_resources; | |
1271 | } | |
1272 | if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1], | |
1273 | page_address(pq_hw[1]), PAGE_SIZE) != 0) { | |
1274 | dev_err(dev, "Self-test q failed compare, disabling\n"); | |
1275 | err = -ENODEV; | |
1276 | goto free_resources; | |
1277 | } | |
1278 | ||
1279 | /* test correct zero sum using the software generated pq values */ | |
1280 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) | |
1281 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1282 | DMA_TO_DEVICE); | |
1283 | ||
1284 | zero_sum_result = ~0; | |
1285 | tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], | |
1286 | pq_src, IOP_ADMA_NUM_SRC_TEST, | |
1287 | raid6_gfexp, PAGE_SIZE, &zero_sum_result, | |
1288 | DMA_PREP_INTERRUPT|DMA_CTRL_ACK); | |
1289 | ||
1290 | cookie = iop_adma_tx_submit(tx); | |
1291 | iop_adma_issue_pending(dma_chan); | |
1292 | msleep(8); | |
1293 | ||
07934481 | 1294 | if (iop_adma_status(dma_chan, cookie, NULL) != |
f6dbf651 DW |
1295 | DMA_SUCCESS) { |
1296 | dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n"); | |
1297 | err = -ENODEV; | |
1298 | goto free_resources; | |
1299 | } | |
1300 | ||
1301 | if (zero_sum_result != 0) { | |
1302 | dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n", | |
1303 | zero_sum_result); | |
1304 | err = -ENODEV; | |
1305 | goto free_resources; | |
1306 | } | |
1307 | ||
1308 | /* test incorrect zero sum */ | |
1309 | i = IOP_ADMA_NUM_SRC_TEST; | |
1310 | memset(pq_sw[i] + 100, 0, 100); | |
1311 | memset(pq_sw[i+1] + 200, 0, 200); | |
1312 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) | |
1313 | pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, | |
1314 | DMA_TO_DEVICE); | |
1315 | ||
1316 | zero_sum_result = 0; | |
1317 | tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], | |
1318 | pq_src, IOP_ADMA_NUM_SRC_TEST, | |
1319 | raid6_gfexp, PAGE_SIZE, &zero_sum_result, | |
1320 | DMA_PREP_INTERRUPT|DMA_CTRL_ACK); | |
1321 | ||
1322 | cookie = iop_adma_tx_submit(tx); | |
1323 | iop_adma_issue_pending(dma_chan); | |
1324 | msleep(8); | |
1325 | ||
07934481 | 1326 | if (iop_adma_status(dma_chan, cookie, NULL) != |
f6dbf651 DW |
1327 | DMA_SUCCESS) { |
1328 | dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n"); | |
1329 | err = -ENODEV; | |
1330 | goto free_resources; | |
1331 | } | |
1332 | ||
1333 | if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) { | |
1334 | dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n", | |
1335 | zero_sum_result); | |
1336 | err = -ENODEV; | |
1337 | goto free_resources; | |
1338 | } | |
1339 | ||
1340 | free_resources: | |
1341 | iop_adma_free_chan_resources(dma_chan); | |
1342 | out: | |
1343 | i = ARRAY_SIZE(pq); | |
1344 | while (i--) | |
1345 | __free_page(pq[i]); | |
1346 | return err; | |
1347 | } | |
1348 | #endif | |
1349 | ||
4bf27b8b | 1350 | static int iop_adma_remove(struct platform_device *dev) |
c2110923 DW |
1351 | { |
1352 | struct iop_adma_device *device = platform_get_drvdata(dev); | |
1353 | struct dma_chan *chan, *_chan; | |
1354 | struct iop_adma_chan *iop_chan; | |
d4adcc01 | 1355 | struct iop_adma_platform_data *plat_data = dev_get_platdata(&dev->dev); |
c2110923 DW |
1356 | |
1357 | dma_async_device_unregister(&device->common); | |
1358 | ||
c2110923 DW |
1359 | dma_free_coherent(&dev->dev, plat_data->pool_size, |
1360 | device->dma_desc_pool_virt, device->dma_desc_pool); | |
1361 | ||
c2110923 DW |
1362 | list_for_each_entry_safe(chan, _chan, &device->common.channels, |
1363 | device_node) { | |
1364 | iop_chan = to_iop_adma_chan(chan); | |
1365 | list_del(&chan->device_node); | |
1366 | kfree(iop_chan); | |
1367 | } | |
1368 | kfree(device); | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
463a1f8b | 1373 | static int iop_adma_probe(struct platform_device *pdev) |
c2110923 DW |
1374 | { |
1375 | struct resource *res; | |
1376 | int ret = 0, i; | |
1377 | struct iop_adma_device *adev; | |
1378 | struct iop_adma_chan *iop_chan; | |
1379 | struct dma_device *dma_dev; | |
d4adcc01 | 1380 | struct iop_adma_platform_data *plat_data = dev_get_platdata(&pdev->dev); |
c2110923 DW |
1381 | |
1382 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1383 | if (!res) | |
1384 | return -ENODEV; | |
1385 | ||
1386 | if (!devm_request_mem_region(&pdev->dev, res->start, | |
2e032b62 | 1387 | resource_size(res), pdev->name)) |
c2110923 DW |
1388 | return -EBUSY; |
1389 | ||
1390 | adev = kzalloc(sizeof(*adev), GFP_KERNEL); | |
1391 | if (!adev) | |
1392 | return -ENOMEM; | |
1393 | dma_dev = &adev->common; | |
1394 | ||
1395 | /* allocate coherent memory for hardware descriptors | |
1396 | * note: writecombine gives slightly better performance, but | |
1397 | * requires that we explicitly flush the writes | |
1398 | */ | |
1399 | if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev, | |
1400 | plat_data->pool_size, | |
1401 | &adev->dma_desc_pool, | |
1402 | GFP_KERNEL)) == NULL) { | |
1403 | ret = -ENOMEM; | |
1404 | goto err_free_adev; | |
1405 | } | |
1406 | ||
b6695e41 | 1407 | dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %p\n", |
3d9b525b | 1408 | __func__, adev->dma_desc_pool_virt, |
c2110923 DW |
1409 | (void *) adev->dma_desc_pool); |
1410 | ||
1411 | adev->id = plat_data->hw_id; | |
1412 | ||
1413 | /* discover transaction capabilites from the platform data */ | |
1414 | dma_dev->cap_mask = plat_data->cap_mask; | |
1415 | ||
1416 | adev->pdev = pdev; | |
1417 | platform_set_drvdata(pdev, adev); | |
1418 | ||
1419 | INIT_LIST_HEAD(&dma_dev->channels); | |
1420 | ||
1421 | /* set base routines */ | |
1422 | dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources; | |
1423 | dma_dev->device_free_chan_resources = iop_adma_free_chan_resources; | |
07934481 | 1424 | dma_dev->device_tx_status = iop_adma_status; |
c2110923 | 1425 | dma_dev->device_issue_pending = iop_adma_issue_pending; |
c2110923 DW |
1426 | dma_dev->dev = &pdev->dev; |
1427 | ||
1428 | /* set prep routines based on capability */ | |
1429 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
1430 | dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy; | |
c2110923 DW |
1431 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
1432 | dma_dev->max_xor = iop_adma_get_max_xor(); | |
1433 | dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; | |
1434 | } | |
099f53cb DW |
1435 | if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) |
1436 | dma_dev->device_prep_dma_xor_val = | |
1437 | iop_adma_prep_dma_xor_val; | |
7bf649ae DW |
1438 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
1439 | dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0); | |
1440 | dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq; | |
1441 | } | |
1442 | if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) | |
1443 | dma_dev->device_prep_dma_pq_val = | |
1444 | iop_adma_prep_dma_pq_val; | |
c2110923 DW |
1445 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
1446 | dma_dev->device_prep_dma_interrupt = | |
1447 | iop_adma_prep_dma_interrupt; | |
1448 | ||
1449 | iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL); | |
1450 | if (!iop_chan) { | |
1451 | ret = -ENOMEM; | |
1452 | goto err_free_dma; | |
1453 | } | |
1454 | iop_chan->device = adev; | |
1455 | ||
1456 | iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, | |
2e032b62 | 1457 | resource_size(res)); |
c2110923 DW |
1458 | if (!iop_chan->mmr_base) { |
1459 | ret = -ENOMEM; | |
1460 | goto err_free_iop_chan; | |
1461 | } | |
1462 | tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long) | |
1463 | iop_chan); | |
1464 | ||
1465 | /* clear errors before enabling interrupts */ | |
1466 | iop_adma_device_clear_err_status(iop_chan); | |
1467 | ||
1468 | for (i = 0; i < 3; i++) { | |
1469 | irq_handler_t handler[] = { iop_adma_eot_handler, | |
1470 | iop_adma_eoc_handler, | |
1471 | iop_adma_err_handler }; | |
1472 | int irq = platform_get_irq(pdev, i); | |
1473 | if (irq < 0) { | |
1474 | ret = -ENXIO; | |
1475 | goto err_free_iop_chan; | |
1476 | } else { | |
1477 | ret = devm_request_irq(&pdev->dev, irq, | |
1478 | handler[i], 0, pdev->name, iop_chan); | |
1479 | if (ret) | |
1480 | goto err_free_iop_chan; | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | spin_lock_init(&iop_chan->lock); | |
c2110923 DW |
1485 | INIT_LIST_HEAD(&iop_chan->chain); |
1486 | INIT_LIST_HEAD(&iop_chan->all_slots); | |
c2110923 | 1487 | iop_chan->common.device = dma_dev; |
8ac69546 | 1488 | dma_cookie_init(&iop_chan->common); |
c2110923 DW |
1489 | list_add_tail(&iop_chan->common.device_node, &dma_dev->channels); |
1490 | ||
1491 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
1492 | ret = iop_adma_memcpy_self_test(adev); | |
1493 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); | |
1494 | if (ret) | |
1495 | goto err_free_iop_chan; | |
1496 | } | |
1497 | ||
48a9db46 | 1498 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
099f53cb | 1499 | ret = iop_adma_xor_val_self_test(adev); |
c2110923 DW |
1500 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1501 | if (ret) | |
1502 | goto err_free_iop_chan; | |
1503 | } | |
1504 | ||
f6dbf651 DW |
1505 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) && |
1506 | dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) { | |
0261f741 | 1507 | #ifdef CONFIG_RAID6_PQ |
f6dbf651 DW |
1508 | ret = iop_adma_pq_zero_sum_self_test(adev); |
1509 | dev_dbg(&pdev->dev, "pq self test returned %d\n", ret); | |
1510 | #else | |
1511 | /* can not test raid6, so do not publish capability */ | |
1512 | dma_cap_clear(DMA_PQ, dma_dev->cap_mask); | |
1513 | dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask); | |
1514 | ret = 0; | |
1515 | #endif | |
1516 | if (ret) | |
1517 | goto err_free_iop_chan; | |
1518 | } | |
1519 | ||
f9f0a7d0 | 1520 | dev_info(&pdev->dev, "Intel(R) IOP: ( %s%s%s%s%s%s)\n", |
1ba151cd JP |
1521 | dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", |
1522 | dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", | |
1523 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", | |
1524 | dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", | |
1ba151cd JP |
1525 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1526 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
c2110923 DW |
1527 | |
1528 | dma_async_device_register(dma_dev); | |
1529 | goto out; | |
1530 | ||
1531 | err_free_iop_chan: | |
1532 | kfree(iop_chan); | |
1533 | err_free_dma: | |
1534 | dma_free_coherent(&adev->pdev->dev, plat_data->pool_size, | |
1535 | adev->dma_desc_pool_virt, adev->dma_desc_pool); | |
1536 | err_free_adev: | |
1537 | kfree(adev); | |
1538 | out: | |
1539 | return ret; | |
1540 | } | |
1541 | ||
1542 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) | |
1543 | { | |
1544 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1545 | dma_cookie_t cookie; | |
1546 | int slot_cnt, slots_per_op; | |
1547 | ||
3d9b525b | 1548 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1549 | |
1550 | spin_lock_bh(&iop_chan->lock); | |
1551 | slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op); | |
1552 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1553 | if (sw_desc) { | |
1554 | grp_start = sw_desc->group_head; | |
1555 | ||
308136d1 | 1556 | list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa | 1557 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1558 | iop_desc_init_memcpy(grp_start, 0); |
1559 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1560 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1561 | iop_desc_set_memcpy_src_addr(grp_start, 0); | |
1562 | ||
2a926e46 | 1563 | cookie = dma_cookie_assign(&sw_desc->async_tx); |
c2110923 DW |
1564 | |
1565 | /* initialize the completed cookie to be less than | |
1566 | * the most recently used cookie | |
1567 | */ | |
4d4e58de | 1568 | iop_chan->common.completed_cookie = cookie - 1; |
c2110923 DW |
1569 | |
1570 | /* channel should not be busy */ | |
1571 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1572 | ||
1573 | /* clear any prior error-status bits */ | |
1574 | iop_adma_device_clear_err_status(iop_chan); | |
1575 | ||
1576 | /* disable operation */ | |
1577 | iop_chan_disable(iop_chan); | |
1578 | ||
1579 | /* set the descriptor address */ | |
1580 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1581 | ||
1582 | /* 1/ don't add pre-chained descriptors | |
1583 | * 2/ dummy read to flush next_desc write | |
1584 | */ | |
1585 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1586 | ||
1587 | /* run the descriptor */ | |
1588 | iop_chan_enable(iop_chan); | |
1589 | } else | |
1ba151cd JP |
1590 | dev_err(iop_chan->device->common.dev, |
1591 | "failed to allocate null descriptor\n"); | |
c2110923 DW |
1592 | spin_unlock_bh(&iop_chan->lock); |
1593 | } | |
1594 | ||
1595 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) | |
1596 | { | |
1597 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1598 | dma_cookie_t cookie; | |
1599 | int slot_cnt, slots_per_op; | |
1600 | ||
3d9b525b | 1601 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1602 | |
1603 | spin_lock_bh(&iop_chan->lock); | |
1604 | slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op); | |
1605 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1606 | if (sw_desc) { | |
1607 | grp_start = sw_desc->group_head; | |
308136d1 | 1608 | list_splice_init(&sw_desc->tx_list, &iop_chan->chain); |
636bdeaa | 1609 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1610 | iop_desc_init_null_xor(grp_start, 2, 0); |
1611 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1612 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1613 | iop_desc_set_xor_src_addr(grp_start, 0, 0); | |
1614 | iop_desc_set_xor_src_addr(grp_start, 1, 0); | |
1615 | ||
2a926e46 | 1616 | cookie = dma_cookie_assign(&sw_desc->async_tx); |
c2110923 DW |
1617 | |
1618 | /* initialize the completed cookie to be less than | |
1619 | * the most recently used cookie | |
1620 | */ | |
4d4e58de | 1621 | iop_chan->common.completed_cookie = cookie - 1; |
c2110923 DW |
1622 | |
1623 | /* channel should not be busy */ | |
1624 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1625 | ||
1626 | /* clear any prior error-status bits */ | |
1627 | iop_adma_device_clear_err_status(iop_chan); | |
1628 | ||
1629 | /* disable operation */ | |
1630 | iop_chan_disable(iop_chan); | |
1631 | ||
1632 | /* set the descriptor address */ | |
1633 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1634 | ||
1635 | /* 1/ don't add pre-chained descriptors | |
1636 | * 2/ dummy read to flush next_desc write | |
1637 | */ | |
1638 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1639 | ||
1640 | /* run the descriptor */ | |
1641 | iop_chan_enable(iop_chan); | |
1642 | } else | |
1ba151cd | 1643 | dev_err(iop_chan->device->common.dev, |
c2110923 DW |
1644 | "failed to allocate null descriptor\n"); |
1645 | spin_unlock_bh(&iop_chan->lock); | |
1646 | } | |
1647 | ||
1648 | static struct platform_driver iop_adma_driver = { | |
1649 | .probe = iop_adma_probe, | |
a7d6e3ec | 1650 | .remove = iop_adma_remove, |
c2110923 DW |
1651 | .driver = { |
1652 | .owner = THIS_MODULE, | |
1653 | .name = "iop-adma", | |
1654 | }, | |
1655 | }; | |
1656 | ||
c94e9105 | 1657 | module_platform_driver(iop_adma_driver); |
c2110923 DW |
1658 | |
1659 | MODULE_AUTHOR("Intel Corporation"); | |
1660 | MODULE_DESCRIPTION("IOP ADMA Engine Driver"); | |
1661 | MODULE_LICENSE("GPL"); | |
c94e9105 | 1662 | MODULE_ALIAS("platform:iop-adma"); |