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dma: improve section assignment in i.MX31 IPU DMA driver
[mirror_ubuntu-artful-kernel.git] / drivers / dma / ipu / ipu_idmac.c
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5296b56d
GL		 1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/err.h>
15#include <linux/spinlock.h>
16#include <linux/delay.h>
17#include <linux/list.h>
18#include <linux/clk.h>
19#include <linux/vmalloc.h>
20#include <linux/string.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23
24#include <mach/ipu.h>
25
26#include "ipu_intern.h"
27
28#define FS_VF_IN_VALID 0x00000002
29#define FS_ENC_IN_VALID 0x00000001
30
31/*
32 * There can be only one, we could allocate it dynamically, but then we'd have
33 * to add an extra parameter to some functions, and use something as ugly as
34 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
35 * in the ISR
36 */
37static struct ipu ipu_data;
38
39#define to_ipu(id) container_of(id, struct ipu, idmac)
40
41static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
42{
43 return __raw_readl(ipu->reg_ic + reg);
44}
45
46#define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
47
48static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
49{
50 __raw_writel(value, ipu->reg_ic + reg);
51}
52
53#define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
54
55static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
56{
57 return __raw_readl(ipu->reg_ipu + reg);
58}
59
60static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
61{
62 __raw_writel(value, ipu->reg_ipu + reg);
63}
64
65/*****************************************************************************
66 * IPU / IC common functions
67 */
68static void dump_idmac_reg(struct ipu *ipu)
69{
70 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
71 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
72 idmac_read_icreg(ipu, IDMAC_CONF),
73 idmac_read_icreg(ipu, IC_CONF),
74 idmac_read_icreg(ipu, IDMAC_CHA_EN),
75 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
76 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
77 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
78 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
79 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
80 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
81 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
82 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
83 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
84}
85
86static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
87{
88 switch (fmt) {
89 case IPU_PIX_FMT_GENERIC: /* generic data */
90 case IPU_PIX_FMT_RGB332:
91 case IPU_PIX_FMT_YUV420P:
92 case IPU_PIX_FMT_YUV422P:
93 default:
94 return 1;
95 case IPU_PIX_FMT_RGB565:
96 case IPU_PIX_FMT_YUYV:
97 case IPU_PIX_FMT_UYVY:
98 return 2;
99 case IPU_PIX_FMT_BGR24:
100 case IPU_PIX_FMT_RGB24:
101 return 3;
102 case IPU_PIX_FMT_GENERIC_32: /* generic data */
103 case IPU_PIX_FMT_BGR32:
104 case IPU_PIX_FMT_RGB32:
105 case IPU_PIX_FMT_ABGR32:
106 return 4;
107 }
108}
109
0149f7d5 110/* Enable direct write to memory by the Camera Sensor Interface */
5296b56d
GL		 111static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
112{
113 uint32_t ic_conf, mask;
114
115 switch (channel) {
116 case IDMAC_IC_0:
117 mask = IC_CONF_PRPENC_EN;
118 break;
119 case IDMAC_IC_7:
120 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
121 break;
122 default:
123 return;
124 }
125 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
126 idmac_write_icreg(ipu, ic_conf, IC_CONF);
127}
128
0149f7d5 129/* Called under spin_lock_irqsave(&ipu_data.lock) */
5296b56d
GL		 130static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
131{
132 uint32_t ic_conf, mask;
133
134 switch (channel) {
135 case IDMAC_IC_0:
136 mask = IC_CONF_PRPENC_EN;
137 break;
138 case IDMAC_IC_7:
139 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
140 break;
141 default:
142 return;
143 }
144 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
145 idmac_write_icreg(ipu, ic_conf, IC_CONF);
146}
147
148static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
149{
150 uint32_t stat = TASK_STAT_IDLE;
151 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
152
153 switch (channel) {
154 case IDMAC_IC_7:
155 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
156 TSTAT_CSI2MEM_OFFSET;
157 break;
158 case IDMAC_IC_0:
159 case IDMAC_SDC_0:
160 case IDMAC_SDC_1:
161 default:
162 break;
163 }
164 return stat;
165}
166
167struct chan_param_mem_planar {
168 /* Word 0 */
169 u32 xv:10;
170 u32 yv:10;
171 u32 xb:12;
172
173 u32 yb:12;
174 u32 res1:2;
175 u32 nsb:1;
176 u32 lnpb:6;
177 u32 ubo_l:11;
178
179 u32 ubo_h:15;
180 u32 vbo_l:17;
181
182 u32 vbo_h:9;
183 u32 res2:3;
184 u32 fw:12;
185 u32 fh_l:8;
186
187 u32 fh_h:4;
188 u32 res3:28;
189
190 /* Word 1 */
191 u32 eba0;
192
193 u32 eba1;
194
195 u32 bpp:3;
196 u32 sl:14;
197 u32 pfs:3;
198 u32 bam:3;
199 u32 res4:2;
200 u32 npb:6;
201 u32 res5:1;
202
203 u32 sat:2;
204 u32 res6:30;
205} __attribute__ ((packed));
206
207struct chan_param_mem_interleaved {
208 /* Word 0 */
209 u32 xv:10;
210 u32 yv:10;
211 u32 xb:12;
212
213 u32 yb:12;
214 u32 sce:1;
215 u32 res1:1;
216 u32 nsb:1;
217 u32 lnpb:6;
218 u32 sx:10;
219 u32 sy_l:1;
220
221 u32 sy_h:9;
222 u32 ns:10;
223 u32 sm:10;
224 u32 sdx_l:3;
225
226 u32 sdx_h:2;
227 u32 sdy:5;
228 u32 sdrx:1;
229 u32 sdry:1;
230 u32 sdr1:1;
231 u32 res2:2;
232 u32 fw:12;
233 u32 fh_l:8;
234
235 u32 fh_h:4;
236 u32 res3:28;
237
238 /* Word 1 */
239 u32 eba0;
240
241 u32 eba1;
242
243 u32 bpp:3;
244 u32 sl:14;
245 u32 pfs:3;
246 u32 bam:3;
247 u32 res4:2;
248 u32 npb:6;
249 u32 res5:1;
250
251 u32 sat:2;
252 u32 scc:1;
253 u32 ofs0:5;
254 u32 ofs1:5;
255 u32 ofs2:5;
256 u32 ofs3:5;
257 u32 wid0:3;
258 u32 wid1:3;
259 u32 wid2:3;
260
261 u32 wid3:3;
262 u32 dec_sel:1;
263 u32 res6:28;
264} __attribute__ ((packed));
265
266union chan_param_mem {
267 struct chan_param_mem_planar pp;
268 struct chan_param_mem_interleaved ip;
269};
270
271static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
272 u32 u_offset, u32 v_offset)
273{
274 params->pp.ubo_l = u_offset & 0x7ff;
275 params->pp.ubo_h = u_offset >> 11;
276 params->pp.vbo_l = v_offset & 0x1ffff;
277 params->pp.vbo_h = v_offset >> 17;
278}
279
280static void ipu_ch_param_set_size(union chan_param_mem *params,
281 uint32_t pixel_fmt, uint16_t width,
282 uint16_t height, uint16_t stride)
283{
284 u32 u_offset;
285 u32 v_offset;
286
287 params->pp.fw = width - 1;
288 params->pp.fh_l = height - 1;
289 params->pp.fh_h = (height - 1) >> 8;
290 params->pp.sl = stride - 1;
291
292 switch (pixel_fmt) {
293 case IPU_PIX_FMT_GENERIC:
294 /*Represents 8-bit Generic data */
295 params->pp.bpp = 3;
296 params->pp.pfs = 7;
297 params->pp.npb = 31;
298 params->pp.sat = 2; /* SAT = use 32-bit access */
299 break;
300 case IPU_PIX_FMT_GENERIC_32:
301 /*Represents 32-bit Generic data */
302 params->pp.bpp = 0;
303 params->pp.pfs = 7;
304 params->pp.npb = 7;
305 params->pp.sat = 2; /* SAT = use 32-bit access */
306 break;
307 case IPU_PIX_FMT_RGB565:
308 params->ip.bpp = 2;
309 params->ip.pfs = 4;
310 params->ip.npb = 7;
311 params->ip.sat = 2; /* SAT = 32-bit access */
312 params->ip.ofs0 = 0; /* Red bit offset */
313 params->ip.ofs1 = 5; /* Green bit offset */
314 params->ip.ofs2 = 11; /* Blue bit offset */
315 params->ip.ofs3 = 16; /* Alpha bit offset */
316 params->ip.wid0 = 4; /* Red bit width - 1 */
317 params->ip.wid1 = 5; /* Green bit width - 1 */
318 params->ip.wid2 = 4; /* Blue bit width - 1 */
319 break;
320 case IPU_PIX_FMT_BGR24:
321 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
322 params->ip.pfs = 4;
323 params->ip.npb = 7;
324 params->ip.sat = 2; /* SAT = 32-bit access */
325 params->ip.ofs0 = 0; /* Red bit offset */
326 params->ip.ofs1 = 8; /* Green bit offset */
327 params->ip.ofs2 = 16; /* Blue bit offset */
328 params->ip.ofs3 = 24; /* Alpha bit offset */
329 params->ip.wid0 = 7; /* Red bit width - 1 */
330 params->ip.wid1 = 7; /* Green bit width - 1 */
331 params->ip.wid2 = 7; /* Blue bit width - 1 */
332 break;
333 case IPU_PIX_FMT_RGB24:
334 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
335 params->ip.pfs = 4;
336 params->ip.npb = 7;
337 params->ip.sat = 2; /* SAT = 32-bit access */
338 params->ip.ofs0 = 16; /* Red bit offset */
339 params->ip.ofs1 = 8; /* Green bit offset */
340 params->ip.ofs2 = 0; /* Blue bit offset */
341 params->ip.ofs3 = 24; /* Alpha bit offset */
342 params->ip.wid0 = 7; /* Red bit width - 1 */
343 params->ip.wid1 = 7; /* Green bit width - 1 */
344 params->ip.wid2 = 7; /* Blue bit width - 1 */
345 break;
346 case IPU_PIX_FMT_BGRA32:
347 case IPU_PIX_FMT_BGR32:
348 params->ip.bpp = 0;
349 params->ip.pfs = 4;
350 params->ip.npb = 7;
351 params->ip.sat = 2; /* SAT = 32-bit access */
352 params->ip.ofs0 = 8; /* Red bit offset */
353 params->ip.ofs1 = 16; /* Green bit offset */
354 params->ip.ofs2 = 24; /* Blue bit offset */
355 params->ip.ofs3 = 0; /* Alpha bit offset */
356 params->ip.wid0 = 7; /* Red bit width - 1 */
357 params->ip.wid1 = 7; /* Green bit width - 1 */
358 params->ip.wid2 = 7; /* Blue bit width - 1 */
359 params->ip.wid3 = 7; /* Alpha bit width - 1 */
360 break;
361 case IPU_PIX_FMT_RGBA32:
362 case IPU_PIX_FMT_RGB32:
363 params->ip.bpp = 0;
364 params->ip.pfs = 4;
365 params->ip.npb = 7;
366 params->ip.sat = 2; /* SAT = 32-bit access */
367 params->ip.ofs0 = 24; /* Red bit offset */
368 params->ip.ofs1 = 16; /* Green bit offset */
369 params->ip.ofs2 = 8; /* Blue bit offset */
370 params->ip.ofs3 = 0; /* Alpha bit offset */
371 params->ip.wid0 = 7; /* Red bit width - 1 */
372 params->ip.wid1 = 7; /* Green bit width - 1 */
373 params->ip.wid2 = 7; /* Blue bit width - 1 */
374 params->ip.wid3 = 7; /* Alpha bit width - 1 */
375 break;
376 case IPU_PIX_FMT_ABGR32:
377 params->ip.bpp = 0;
378 params->ip.pfs = 4;
379 params->ip.npb = 7;
380 params->ip.sat = 2; /* SAT = 32-bit access */
381 params->ip.ofs0 = 8; /* Red bit offset */
382 params->ip.ofs1 = 16; /* Green bit offset */
383 params->ip.ofs2 = 24; /* Blue bit offset */
384 params->ip.ofs3 = 0; /* Alpha bit offset */
385 params->ip.wid0 = 7; /* Red bit width - 1 */
386 params->ip.wid1 = 7; /* Green bit width - 1 */
387 params->ip.wid2 = 7; /* Blue bit width - 1 */
388 params->ip.wid3 = 7; /* Alpha bit width - 1 */
389 break;
390 case IPU_PIX_FMT_UYVY:
391 params->ip.bpp = 2;
392 params->ip.pfs = 6;
393 params->ip.npb = 7;
394 params->ip.sat = 2; /* SAT = 32-bit access */
395 break;
396 case IPU_PIX_FMT_YUV420P2:
397 case IPU_PIX_FMT_YUV420P:
398 params->ip.bpp = 3;
399 params->ip.pfs = 3;
400 params->ip.npb = 7;
401 params->ip.sat = 2; /* SAT = 32-bit access */
402 u_offset = stride * height;
403 v_offset = u_offset + u_offset / 4;
404 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
405 break;
406 case IPU_PIX_FMT_YVU422P:
407 params->ip.bpp = 3;
408 params->ip.pfs = 2;
409 params->ip.npb = 7;
410 params->ip.sat = 2; /* SAT = 32-bit access */
411 v_offset = stride * height;
412 u_offset = v_offset + v_offset / 2;
413 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
414 break;
415 case IPU_PIX_FMT_YUV422P:
416 params->ip.bpp = 3;
417 params->ip.pfs = 2;
418 params->ip.npb = 7;
419 params->ip.sat = 2; /* SAT = 32-bit access */
420 u_offset = stride * height;
421 v_offset = u_offset + u_offset / 2;
422 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
423 break;
424 default:
425 dev_err(ipu_data.dev,
0149f7d5 426 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
5296b56d
GL		 427 break;
428 }
429
430 params->pp.nsb = 1;
431}
432
433static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
434 uint16_t burst_pixels)
435{
436 params->pp.npb = burst_pixels - 1;
0149f7d5 437}
5296b56d
GL		 438
439static void ipu_ch_param_set_buffer(union chan_param_mem *params,
440 dma_addr_t buf0, dma_addr_t buf1)
441{
442 params->pp.eba0 = buf0;
443 params->pp.eba1 = buf1;
0149f7d5 444}
5296b56d
GL		 445
446static void ipu_ch_param_set_rotation(union chan_param_mem *params,
447 enum ipu_rotate_mode rotate)
448{
449 params->pp.bam = rotate;
0149f7d5 450}
5296b56d
GL		 451
452static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
453 uint32_t num_words)
454{
455 for (; num_words > 0; num_words--) {
456 dev_dbg(ipu_data.dev,
457 "write param mem - addr = 0x%08X, data = 0x%08X\n",
458 addr, *data);
459 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
460 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
461 addr++;
462 if ((addr & 0x7) == 5) {
463 addr &= ~0x7; /* set to word 0 */
464 addr += 8; /* increment to next row */
465 }
466 }
467}
468
469static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
470 uint32_t *resize_coeff,
471 uint32_t *downsize_coeff)
472{
473 uint32_t temp_size;
474 uint32_t temp_downsize;
475
476 *resize_coeff = 1 << 13;
477 *downsize_coeff = 1 << 13;
478
479 /* Cannot downsize more than 8:1 */
480 if (out_size << 3 < in_size)
481 return -EINVAL;
482
483 /* compute downsizing coefficient */
484 temp_downsize = 0;
485 temp_size = in_size;
486 while (temp_size >= out_size * 2 && temp_downsize < 2) {
487 temp_size >>= 1;
488 temp_downsize++;
489 }
490 *downsize_coeff = temp_downsize;
491
492 /*
493 * compute resizing coefficient using the following formula:
494 * resize_coeff = M*(SI -1)/(SO - 1)
495 * where M = 2^13, SI - input size, SO - output size
496 */
497 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
498 if (*resize_coeff >= 16384L) {
499 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
500 *resize_coeff = 0x3FFF;
501 }
502
503 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
504 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
505 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
506 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
507
508 return 0;
509}
510
511static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
512{
513 switch (fmt) {
514 case IPU_PIX_FMT_RGB565:
515 case IPU_PIX_FMT_BGR24:
516 case IPU_PIX_FMT_RGB24:
517 case IPU_PIX_FMT_BGR32:
518 case IPU_PIX_FMT_RGB32:
519 return IPU_COLORSPACE_RGB;
520 default:
521 return IPU_COLORSPACE_YCBCR;
522 }
523}
524
525static int ipu_ic_init_prpenc(struct ipu *ipu,
526 union ipu_channel_param *params, bool src_is_csi)
527{
528 uint32_t reg, ic_conf;
529 uint32_t downsize_coeff, resize_coeff;
530 enum ipu_color_space in_fmt, out_fmt;
531
532 /* Setup vertical resizing */
533 calc_resize_coeffs(params->video.in_height,
534 params->video.out_height,
535 &resize_coeff, &downsize_coeff);
536 reg = (downsize_coeff << 30) | (resize_coeff << 16);
537
538 /* Setup horizontal resizing */
539 calc_resize_coeffs(params->video.in_width,
540 params->video.out_width,
541 &resize_coeff, &downsize_coeff);
542 reg |= (downsize_coeff << 14) | resize_coeff;
543
544 /* Setup color space conversion */
545 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
546 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
547
548 /*
549 * Colourspace conversion unsupported yet - see _init_csc() in
550 * Freescale sources
551 */
552 if (in_fmt != out_fmt) {
553 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
554 return -EOPNOTSUPP;
555 }
556
557 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
558
559 ic_conf = idmac_read_icreg(ipu, IC_CONF);
560
561 if (src_is_csi)
562 ic_conf &= ~IC_CONF_RWS_EN;
563 else
564 ic_conf |= IC_CONF_RWS_EN;
565
566 idmac_write_icreg(ipu, ic_conf, IC_CONF);
567
568 return 0;
569}
570
571static uint32_t dma_param_addr(uint32_t dma_ch)
572{
573 /* Channel Parameter Memory */
574 return 0x10000 | (dma_ch << 4);
0149f7d5 575}
5296b56d
GL		 576
577static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
578 bool prio)
579{
580 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
581
582 if (prio)
583 reg |= 1UL << channel;
584 else
585 reg &= ~(1UL << channel);
586
587 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
588
589 dump_idmac_reg(ipu);
590}
591
592static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
593{
594 uint32_t mask;
595
596 switch (channel) {
597 case IDMAC_IC_0:
598 case IDMAC_IC_7:
599 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
600 break;
601 case IDMAC_SDC_0:
602 case IDMAC_SDC_1:
603 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
604 break;
605 default:
606 mask = 0;
607 break;
608 }
609
610 return mask;
611}
612
613/**
614 * ipu_enable_channel() - enable an IPU channel.
0149f7d5
GL		 615 * @idmac: IPU DMAC context.
616 * @ichan: IDMAC channel.
5296b56d
GL		 617 * @return: 0 on success or negative error code on failure.
618 */
619static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
620{
621 struct ipu *ipu = to_ipu(idmac);
622 enum ipu_channel channel = ichan->dma_chan.chan_id;
623 uint32_t reg;
624 unsigned long flags;
625
626 spin_lock_irqsave(&ipu->lock, flags);
627
628 /* Reset to buffer 0 */
629 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
630 ichan->active_buffer = 0;
631 ichan->status = IPU_CHANNEL_ENABLED;
632
633 switch (channel) {
634 case IDMAC_SDC_0:
635 case IDMAC_SDC_1:
636 case IDMAC_IC_7:
637 ipu_channel_set_priority(ipu, channel, true);
638 default:
639 break;
640 }
641
642 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
643
644 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
645
646 ipu_ic_enable_task(ipu, channel);
647
648 spin_unlock_irqrestore(&ipu->lock, flags);
649 return 0;
650}
651
652/**
653 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
0149f7d5 654 * @ichan: IDMAC channel.
5296b56d
GL		 655 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
656 * @width: width of buffer in pixels.
657 * @height: height of buffer in pixels.
658 * @stride: stride length of buffer in pixels.
659 * @rot_mode: rotation mode of buffer. A rotation setting other than
660 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
661 * rotation channels.
662 * @phyaddr_0: buffer 0 physical address.
663 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
664 * NULL enables double buffering mode.
665 * @return: 0 on success or negative error code on failure.
666 */
667static int ipu_init_channel_buffer(struct idmac_channel *ichan,
668 enum pixel_fmt pixel_fmt,
669 uint16_t width, uint16_t height,
670 uint32_t stride,
671 enum ipu_rotate_mode rot_mode,
672 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
673{
674 enum ipu_channel channel = ichan->dma_chan.chan_id;
675 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
676 struct ipu *ipu = to_ipu(idmac);
677 union chan_param_mem params = {};
678 unsigned long flags;
679 uint32_t reg;
680 uint32_t stride_bytes;
681
682 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
683
684 if (stride_bytes % 4) {
685 dev_err(ipu->dev,
686 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
687 stride, stride_bytes);
688 return -EINVAL;
689 }
690
691 /* IC channel's stride must be a multiple of 8 pixels */
0149f7d5 692 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
5296b56d
GL		 693 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
694 return -EINVAL;
695 }
696
697 /* Build parameter memory data for DMA channel */
698 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
699 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
700 ipu_ch_param_set_rotation(&params, rot_mode);
701 /* Some channels (rotation) have restriction on burst length */
702 switch (channel) {
703 case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
704 invalid - Table 44-30 */
705/*
706 ipu_ch_param_set_burst_size(&params, 8);
707 */
708 break;
709 case IDMAC_SDC_0:
710 case IDMAC_SDC_1:
711 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
712 ipu_ch_param_set_burst_size(&params, 16);
713 break;
714 case IDMAC_IC_0:
715 default:
716 break;
717 }
718
719 spin_lock_irqsave(&ipu->lock, flags);
720
721 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
722
723 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
724
725 if (phyaddr_1)
726 reg |= 1UL << channel;
727 else
728 reg &= ~(1UL << channel);
729
730 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
731
732 ichan->status = IPU_CHANNEL_READY;
733
c74ef1f8 734 spin_unlock_irqrestore(&ipu->lock, flags);
5296b56d
GL		 735
736 return 0;
737}
738
739/**
740 * ipu_select_buffer() - mark a channel's buffer as ready.
741 * @channel: channel ID.
742 * @buffer_n: buffer number to mark ready.
743 */
744static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
745{
746 /* No locking - this is a write-one-to-set register, cleared by IPU */
747 if (buffer_n == 0)
748 /* Mark buffer 0 as ready. */
749 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
750 else
751 /* Mark buffer 1 as ready. */
752 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
753}
754
755/**
756 * ipu_update_channel_buffer() - update physical address of a channel buffer.
0149f7d5 757 * @ichan: IDMAC channel.
5296b56d
GL		 758 * @buffer_n: buffer number to update.
759 * 0 or 1 are the only valid values.
760 * @phyaddr: buffer physical address.
761 * @return: Returns 0 on success or negative error code on failure. This
762 * function will fail if the buffer is set to ready.
763 */
764/* Called under spin_lock(_irqsave)(&ichan->lock) */
765static int ipu_update_channel_buffer(enum ipu_channel channel,
766 int buffer_n, dma_addr_t phyaddr)
767{
768 uint32_t reg;
769 unsigned long flags;
770
771 spin_lock_irqsave(&ipu_data.lock, flags);
772
773 if (buffer_n == 0) {
774 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
775 if (reg & (1UL << channel)) {
776 spin_unlock_irqrestore(&ipu_data.lock, flags);
777 return -EACCES;
778 }
779
780 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
781 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
782 0x0008UL, IPU_IMA_ADDR);
783 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
784 } else {
785 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
786 if (reg & (1UL << channel)) {
787 spin_unlock_irqrestore(&ipu_data.lock, flags);
788 return -EACCES;
789 }
790
791 /* Check if double-buffering is already enabled */
792 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
793
794 if (!(reg & (1UL << channel)))
795 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
796 IPU_CHA_DB_MODE_SEL);
797
798 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
799 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
800 0x0009UL, IPU_IMA_ADDR);
801 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
802 }
803
804 spin_unlock_irqrestore(&ipu_data.lock, flags);
805
806 return 0;
807}
808
809/* Called under spin_lock_irqsave(&ichan->lock) */
810static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
811 struct idmac_tx_desc *desc)
812{
813 struct scatterlist *sg;
814 int i, ret = 0;
815
816 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
817 if (!ichan->sg[i]) {
818 ichan->sg[i] = sg;
819
820 /*
821 * On first invocation this shouldn't be necessary, the
822 * call to ipu_init_channel_buffer() above will set
823 * addresses for us, so we could make it conditional
824 * on status >= IPU_CHANNEL_ENABLED, but doing it again
825 * shouldn't hurt either.
826 */
827 ret = ipu_update_channel_buffer(ichan->dma_chan.chan_id, i,
828 sg_dma_address(sg));
829 if (ret < 0)
830 return ret;
831
832 ipu_select_buffer(ichan->dma_chan.chan_id, i);
833
834 sg = sg_next(sg);
835 }
836 }
837
838 return ret;
839}
840
841static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
842{
843 struct idmac_tx_desc *desc = to_tx_desc(tx);
844 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
845 struct idmac *idmac = to_idmac(tx->chan->device);
846 struct ipu *ipu = to_ipu(idmac);
847 dma_cookie_t cookie;
848 unsigned long flags;
849
850 /* Sanity check */
851 if (!list_empty(&desc->list)) {
852 /* The descriptor doesn't belong to client */
853 dev_err(&ichan->dma_chan.dev->device,
854 "Descriptor %p not prepared!\n", tx);
855 return -EBUSY;
856 }
857
858 mutex_lock(&ichan->chan_mutex);
859
860 if (ichan->status < IPU_CHANNEL_READY) {
861 struct idmac_video_param *video = &ichan->params.video;
862 /*
863 * Initial buffer assignment - the first two sg-entries from
864 * the descriptor will end up in the IDMAC buffers
865 */
866 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
867 sg_dma_address(&desc->sg[1]);
868
869 WARN_ON(ichan->sg[0] || ichan->sg[1]);
870
871 cookie = ipu_init_channel_buffer(ichan,
872 video->out_pixel_fmt,
873 video->out_width,
874 video->out_height,
875 video->out_stride,
876 IPU_ROTATE_NONE,
877 sg_dma_address(&desc->sg[0]),
878 dma_1);
879 if (cookie < 0)
880 goto out;
881 }
882
883 /* ipu->lock can be taken under ichan->lock, but not v.v. */
884 spin_lock_irqsave(&ichan->lock, flags);
885
886 /* submit_buffers() atomically verifies and fills empty sg slots */
887 cookie = ipu_submit_channel_buffers(ichan, desc);
888
889 spin_unlock_irqrestore(&ichan->lock, flags);
890
891 if (cookie < 0)
892 goto out;
893
894 cookie = ichan->dma_chan.cookie;
895
896 if (++cookie < 0)
897 cookie = 1;
898
899 /* from dmaengine.h: "last cookie value returned to client" */
900 ichan->dma_chan.cookie = cookie;
901 tx->cookie = cookie;
902 spin_lock_irqsave(&ichan->lock, flags);
903 list_add_tail(&desc->list, &ichan->queue);
904 spin_unlock_irqrestore(&ichan->lock, flags);
905
906 if (ichan->status < IPU_CHANNEL_ENABLED) {
907 int ret = ipu_enable_channel(idmac, ichan);
908 if (ret < 0) {
909 cookie = ret;
910 spin_lock_irqsave(&ichan->lock, flags);
911 list_del_init(&desc->list);
912 spin_unlock_irqrestore(&ichan->lock, flags);
913 tx->cookie = cookie;
914 ichan->dma_chan.cookie = cookie;
915 }
916 }
917
918 dump_idmac_reg(ipu);
919
920out:
921 mutex_unlock(&ichan->chan_mutex);
922
923 return cookie;
924}
925
926/* Called with ichan->chan_mutex held */
927static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
928{
929 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
930 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
931
932 if (!desc)
933 return -ENOMEM;
934
935 /* No interrupts, just disable the tasklet for a moment */
936 tasklet_disable(&to_ipu(idmac)->tasklet);
937
938 ichan->n_tx_desc = n;
939 ichan->desc = desc;
940 INIT_LIST_HEAD(&ichan->queue);
941 INIT_LIST_HEAD(&ichan->free_list);
942
943 while (n--) {
944 struct dma_async_tx_descriptor *txd = &desc->txd;
945
946 memset(txd, 0, sizeof(*txd));
947 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
948 txd->tx_submit = idmac_tx_submit;
949 txd->chan = &ichan->dma_chan;
950 INIT_LIST_HEAD(&txd->tx_list);
951
952 list_add(&desc->list, &ichan->free_list);
953
954 desc++;
955 }
956
957 tasklet_enable(&to_ipu(idmac)->tasklet);
958
959 return 0;
960}
961
962/**
963 * ipu_init_channel() - initialize an IPU channel.
964 * @idmac: IPU DMAC context.
965 * @ichan: pointer to the channel object.
966 * @return 0 on success or negative error code on failure.
967 */
968static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
969{
970 union ipu_channel_param *params = &ichan->params;
971 uint32_t ipu_conf;
972 enum ipu_channel channel = ichan->dma_chan.chan_id;
973 unsigned long flags;
974 uint32_t reg;
975 struct ipu *ipu = to_ipu(idmac);
976 int ret = 0, n_desc = 0;
977
978 dev_dbg(ipu->dev, "init channel = %d\n", channel);
979
980 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
981 channel != IDMAC_IC_7)
982 return -EINVAL;
983
984 spin_lock_irqsave(&ipu->lock, flags);
985
986 switch (channel) {
987 case IDMAC_IC_7:
988 n_desc = 16;
989 reg = idmac_read_icreg(ipu, IC_CONF);
990 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
991 break;
992 case IDMAC_IC_0:
993 n_desc = 16;
994 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
995 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
996 ret = ipu_ic_init_prpenc(ipu, params, true);
997 break;
998 case IDMAC_SDC_0:
999 case IDMAC_SDC_1:
1000 n_desc = 4;
1001 default:
1002 break;
1003 }
1004
1005 ipu->channel_init_mask |= 1L << channel;
1006
1007 /* Enable IPU sub module */
1008 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1009 ipu_channel_conf_mask(channel);
1010 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1011
1012 spin_unlock_irqrestore(&ipu->lock, flags);
1013
1014 if (n_desc && !ichan->desc)
1015 ret = idmac_desc_alloc(ichan, n_desc);
1016
1017 dump_idmac_reg(ipu);
1018
1019 return ret;
1020}
1021
1022/**
1023 * ipu_uninit_channel() - uninitialize an IPU channel.
1024 * @idmac: IPU DMAC context.
1025 * @ichan: pointer to the channel object.
1026 */
1027static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1028{
1029 enum ipu_channel channel = ichan->dma_chan.chan_id;
1030 unsigned long flags;
1031 uint32_t reg;
1032 unsigned long chan_mask = 1UL << channel;
1033 uint32_t ipu_conf;
1034 struct ipu *ipu = to_ipu(idmac);
1035
1036 spin_lock_irqsave(&ipu->lock, flags);
1037
1038 if (!(ipu->channel_init_mask & chan_mask)) {
1039 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1040 channel);
1041 spin_unlock_irqrestore(&ipu->lock, flags);
1042 return;
1043 }
1044
1045 /* Reset the double buffer */
1046 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1047 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1048
1049 ichan->sec_chan_en = false;
1050
1051 switch (channel) {
1052 case IDMAC_IC_7:
1053 reg = idmac_read_icreg(ipu, IC_CONF);
1054 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1055 IC_CONF);
1056 break;
1057 case IDMAC_IC_0:
1058 reg = idmac_read_icreg(ipu, IC_CONF);
1059 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1060 IC_CONF);
1061 break;
1062 case IDMAC_SDC_0:
1063 case IDMAC_SDC_1:
1064 default:
1065 break;
1066 }
1067
1068 ipu->channel_init_mask &= ~(1L << channel);
1069
1070 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1071 ~ipu_channel_conf_mask(channel);
1072 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1073
1074 spin_unlock_irqrestore(&ipu->lock, flags);
1075
1076 ichan->n_tx_desc = 0;
1077 vfree(ichan->desc);
1078 ichan->desc = NULL;
1079}
1080
1081/**
1082 * ipu_disable_channel() - disable an IPU channel.
1083 * @idmac: IPU DMAC context.
1084 * @ichan: channel object pointer.
1085 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1086 * return immediately.
1087 * @return: 0 on success or negative error code on failure.
1088 */
1089static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1090 bool wait_for_stop)
1091{
1092 enum ipu_channel channel = ichan->dma_chan.chan_id;
1093 struct ipu *ipu = to_ipu(idmac);
1094 uint32_t reg;
1095 unsigned long flags;
1096 unsigned long chan_mask = 1UL << channel;
1097 unsigned int timeout;
1098
1099 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1100 timeout = 40;
1101 /* This waiting always fails. Related to spurious irq problem */
1102 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1103 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1104 timeout--;
1105 msleep(10);
1106
1107 if (!timeout) {
1108 dev_dbg(ipu->dev,
1109 "Warning: timeout waiting for channel %u to "
1110 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1111 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1112 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1113 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1114 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1115 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1116 break;
1117 }
1118 }
1119 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1120 }
1121 /* SDC BG and FG must be disabled before DMA is disabled */
1122 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1123 channel == IDMAC_SDC_1)) {
1124 for (timeout = 5;
1125 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1126 msleep(5);
1127 }
1128
1129 spin_lock_irqsave(&ipu->lock, flags);
1130
1131 /* Disable IC task */
1132 ipu_ic_disable_task(ipu, channel);
1133
1134 /* Disable DMA channel(s) */
1135 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1136 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1137
1138 /*
1139 * Problem (observed with channel DMAIC_7): after enabling the channel
1140 * and initialising buffers, there comes an interrupt with current still
1141 * pointing at buffer 0, whereas it should use buffer 0 first and only
1142 * generate an interrupt when it is done, then current should already
1143 * point to buffer 1. This spurious interrupt also comes on channel
1144 * DMASDC_0. With DMAIC_7 normally, is we just leave the ISR after the
1145 * first interrupt, there comes the second with current correctly
1146 * pointing to buffer 1 this time. But sometimes this second interrupt
1147 * doesn't come and the channel hangs. Clearing BUFx_RDY when disabling
1148 * the channel seems to prevent the channel from hanging, but it doesn't
1149 * prevent the spurious interrupt. This might also be unsafe. Think
1150 * about the IDMAC controller trying to switch to a buffer, when we
1151 * clear the ready bit, and re-enable it a moment later.
1152 */
1153 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY);
1154 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF0_RDY);
1155 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF0_RDY);
1156
1157 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY);
1158 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF1_RDY);
1159 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF1_RDY);
1160
1161 spin_unlock_irqrestore(&ipu->lock, flags);
1162
1163 return 0;
1164}
1165
1166/*
1167 * We have several possibilities here:
1168 * current BUF next BUF
1169 *
1170 * not last sg next not last sg
1171 * not last sg next last sg
1172 * last sg first sg from next descriptor
1173 * last sg NULL
1174 *
1175 * Besides, the descriptor queue might be empty or not. We process all these
1176 * cases carefully.
1177 */
1178static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1179{
1180 struct idmac_channel *ichan = dev_id;
1181 unsigned int chan_id = ichan->dma_chan.chan_id;
1182 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1183 /* Next transfer descriptor */
1184 struct idmac_tx_desc *desc = NULL, *descnew;
1185 dma_async_tx_callback callback;
1186 void *callback_param;
1187 bool done = false;
1188 u32 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY),
1189 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY),
1190 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1191
1192 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1193
1194 pr_debug("IDMAC irq %d\n", irq);
1195 /* Other interrupts do not interfere with this channel */
1196 spin_lock(&ichan->lock);
1197
1198 if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 &&
1199 ((curbuf >> chan_id) & 1) == ichan->active_buffer)) {
1200 int i = 100;
1201
1202 /* This doesn't help. See comment in ipu_disable_channel() */
1203 while (--i) {
1204 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1205 if (((curbuf >> chan_id) & 1) != ichan->active_buffer)
1206 break;
1207 cpu_relax();
1208 }
1209
1210 if (!i) {
1211 spin_unlock(&ichan->lock);
1212 dev_dbg(ichan->dma_chan.device->dev,
1213 "IRQ on active buffer on channel %x, active "
1214 "%d, ready %x, %x, current %x!\n", chan_id,
1215 ichan->active_buffer, ready0, ready1, curbuf);
1216 return IRQ_NONE;
1217 }
1218 }
1219
1220 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1221 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1222 )) {
1223 spin_unlock(&ichan->lock);
1224 dev_dbg(ichan->dma_chan.device->dev,
1225 "IRQ with active buffer still ready on channel %x, "
1226 "active %d, ready %x, %x!\n", chan_id,
1227 ichan->active_buffer, ready0, ready1);
1228 return IRQ_NONE;
1229 }
1230
1231 if (unlikely(list_empty(&ichan->queue))) {
1232 spin_unlock(&ichan->lock);
1233 dev_err(ichan->dma_chan.device->dev,
1234 "IRQ without queued buffers on channel %x, active %d, "
1235 "ready %x, %x!\n", chan_id,
1236 ichan->active_buffer, ready0, ready1);
1237 return IRQ_NONE;
1238 }
1239
1240 /*
1241 * active_buffer is a software flag, it shows which buffer we are
1242 * currently expecting back from the hardware, IDMAC should be
1243 * processing the other buffer already
1244 */
1245 sg = &ichan->sg[ichan->active_buffer];
1246 sgnext = ichan->sg[!ichan->active_buffer];
1247
1248 /*
1249 * if sgnext == NULL sg must be the last element in a scatterlist and
1250 * queue must be empty
1251 */
1252 if (unlikely(!sgnext)) {
1253 if (unlikely(sg_next(*sg))) {
1254 dev_err(ichan->dma_chan.device->dev,
1255 "Broken buffer-update locking on channel %x!\n",
1256 chan_id);
1257 /* We'll let the user catch up */
1258 } else {
1259 /* Underrun */
1260 ipu_ic_disable_task(&ipu_data, chan_id);
1261 dev_dbg(ichan->dma_chan.device->dev,
1262 "Underrun on channel %x\n", chan_id);
1263 ichan->status = IPU_CHANNEL_READY;
1264 /* Continue to check for complete descriptor */
1265 }
1266 }
1267
1268 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1269
1270 /* First calculate and submit the next sg element */
1271 if (likely(sgnext))
1272 sgnew = sg_next(sgnext);
1273
1274 if (unlikely(!sgnew)) {
1275 /* Start a new scatterlist, if any queued */
1276 if (likely(desc->list.next != &ichan->queue)) {
1277 descnew = list_entry(desc->list.next,
1278 struct idmac_tx_desc, list);
1279 sgnew = &descnew->sg[0];
1280 }
1281 }
1282
1283 if (unlikely(!sg_next(*sg)) || !sgnext) {
1284 /*
1285 * Last element in scatterlist done, remove from the queue,
1286 * _init for debugging
1287 */
1288 list_del_init(&desc->list);
1289 done = true;
1290 }
1291
1292 *sg = sgnew;
1293
1294 if (likely(sgnew)) {
1295 int ret;
1296
1297 ret = ipu_update_channel_buffer(chan_id, ichan->active_buffer,
1298 sg_dma_address(*sg));
1299 if (ret < 0)
1300 dev_err(ichan->dma_chan.device->dev,
1301 "Failed to update buffer on channel %x buffer %d!\n",
1302 chan_id, ichan->active_buffer);
1303 else
1304 ipu_select_buffer(chan_id, ichan->active_buffer);
1305 }
1306
1307 /* Flip the active buffer - even if update above failed */
1308 ichan->active_buffer = !ichan->active_buffer;
1309 if (done)
1310 ichan->completed = desc->txd.cookie;
1311
1312 callback = desc->txd.callback;
1313 callback_param = desc->txd.callback_param;
1314
1315 spin_unlock(&ichan->lock);
1316
1317 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1318 callback(callback_param);
1319
1320 return IRQ_HANDLED;
1321}
1322
1323static void ipu_gc_tasklet(unsigned long arg)
1324{
1325 struct ipu *ipu = (struct ipu *)arg;
1326 int i;
1327
1328 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1329 struct idmac_channel *ichan = ipu->channel + i;
1330 struct idmac_tx_desc *desc;
1331 unsigned long flags;
1332 int j;
1333
1334 for (j = 0; j < ichan->n_tx_desc; j++) {
1335 desc = ichan->desc + j;
1336 spin_lock_irqsave(&ichan->lock, flags);
1337 if (async_tx_test_ack(&desc->txd)) {
1338 list_move(&desc->list, &ichan->free_list);
1339 async_tx_clear_ack(&desc->txd);
1340 }
1341 spin_unlock_irqrestore(&ichan->lock, flags);
1342 }
1343 }
1344}
1345
0149f7d5 1346/* Allocate and initialise a transfer descriptor. */
5296b56d
GL		 1347static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1348 struct scatterlist *sgl, unsigned int sg_len,
1349 enum dma_data_direction direction, unsigned long tx_flags)
1350{
1351 struct idmac_channel *ichan = to_idmac_chan(chan);
1352 struct idmac_tx_desc *desc = NULL;
1353 struct dma_async_tx_descriptor *txd = NULL;
1354 unsigned long flags;
1355
1356 /* We only can handle these three channels so far */
1357 if (ichan->dma_chan.chan_id != IDMAC_SDC_0 && ichan->dma_chan.chan_id != IDMAC_SDC_1 &&
1358 ichan->dma_chan.chan_id != IDMAC_IC_7)
1359 return NULL;
1360
1361 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1362 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1363 return NULL;
1364 }
1365
1366 mutex_lock(&ichan->chan_mutex);
1367
1368 spin_lock_irqsave(&ichan->lock, flags);
1369 if (!list_empty(&ichan->free_list)) {
1370 desc = list_entry(ichan->free_list.next,
1371 struct idmac_tx_desc, list);
1372
1373 list_del_init(&desc->list);
1374
1375 desc->sg_len = sg_len;
1376 desc->sg = sgl;
1377 txd = &desc->txd;
1378 txd->flags = tx_flags;
1379 }
1380 spin_unlock_irqrestore(&ichan->lock, flags);
1381
1382 mutex_unlock(&ichan->chan_mutex);
1383
1384 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1385
1386 return txd;
1387}
1388
1389/* Re-select the current buffer and re-activate the channel */
1390static void idmac_issue_pending(struct dma_chan *chan)
1391{
1392 struct idmac_channel *ichan = to_idmac_chan(chan);
1393 struct idmac *idmac = to_idmac(chan->device);
1394 struct ipu *ipu = to_ipu(idmac);
1395 unsigned long flags;
1396
1397 /* This is not always needed, but doesn't hurt either */
1398 spin_lock_irqsave(&ipu->lock, flags);
1399 ipu_select_buffer(ichan->dma_chan.chan_id, ichan->active_buffer);
1400 spin_unlock_irqrestore(&ipu->lock, flags);
1401
1402 /*
1403 * Might need to perform some parts of initialisation from
1404 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1405 * 0, don't need to set priority again either, but re-enabling the task
1406 * and the channel might be a good idea.
1407 */
1408}
1409
1410static void __idmac_terminate_all(struct dma_chan *chan)
1411{
1412 struct idmac_channel *ichan = to_idmac_chan(chan);
1413 struct idmac *idmac = to_idmac(chan->device);
1414 unsigned long flags;
1415 int i;
1416
1417 ipu_disable_channel(idmac, ichan,
1418 ichan->status >= IPU_CHANNEL_ENABLED);
1419
1420 tasklet_disable(&to_ipu(idmac)->tasklet);
1421
1422 /* ichan->queue is modified in ISR, have to spinlock */
1423 spin_lock_irqsave(&ichan->lock, flags);
1424 list_splice_init(&ichan->queue, &ichan->free_list);
1425
1426 if (ichan->desc)
1427 for (i = 0; i < ichan->n_tx_desc; i++) {
1428 struct idmac_tx_desc *desc = ichan->desc + i;
1429 if (list_empty(&desc->list))
1430 /* Descriptor was prepared, but not submitted */
0149f7d5 1431 list_add(&desc->list, &ichan->free_list);
5296b56d
GL		 1432
1433 async_tx_clear_ack(&desc->txd);
1434 }
1435
1436 ichan->sg[0] = NULL;
1437 ichan->sg[1] = NULL;
1438 spin_unlock_irqrestore(&ichan->lock, flags);
1439
1440 tasklet_enable(&to_ipu(idmac)->tasklet);
1441
1442 ichan->status = IPU_CHANNEL_INITIALIZED;
1443}
1444
1445static void idmac_terminate_all(struct dma_chan *chan)
1446{
1447 struct idmac_channel *ichan = to_idmac_chan(chan);
1448
1449 mutex_lock(&ichan->chan_mutex);
1450
1451 __idmac_terminate_all(chan);
1452
1453 mutex_unlock(&ichan->chan_mutex);
1454}
1455
1456static int idmac_alloc_chan_resources(struct dma_chan *chan)
1457{
1458 struct idmac_channel *ichan = to_idmac_chan(chan);
1459 struct idmac *idmac = to_idmac(chan->device);
1460 int ret;
1461
1462 /* dmaengine.c now guarantees to only offer free channels */
1463 BUG_ON(chan->client_count > 1);
1464 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1465
1466 chan->cookie = 1;
1467 ichan->completed = -ENXIO;
1468
1469 ret = ipu_irq_map(ichan->dma_chan.chan_id);
1470 if (ret < 0)
1471 goto eimap;
1472
1473 ichan->eof_irq = ret;
1474 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1475 ichan->eof_name, ichan);
1476 if (ret < 0)
1477 goto erirq;
1478
1479 ret = ipu_init_channel(idmac, ichan);
1480 if (ret < 0)
1481 goto eichan;
1482
1483 ichan->status = IPU_CHANNEL_INITIALIZED;
1484
1485 dev_dbg(&ichan->dma_chan.dev->device, "Found channel 0x%x, irq %d\n",
1486 ichan->dma_chan.chan_id, ichan->eof_irq);
1487
1488 return ret;
1489
1490eichan:
1491 free_irq(ichan->eof_irq, ichan);
1492erirq:
1493 ipu_irq_unmap(ichan->dma_chan.chan_id);
1494eimap:
1495 return ret;
1496}
1497
1498static void idmac_free_chan_resources(struct dma_chan *chan)
1499{
1500 struct idmac_channel *ichan = to_idmac_chan(chan);
1501 struct idmac *idmac = to_idmac(chan->device);
1502
1503 mutex_lock(&ichan->chan_mutex);
1504
1505 __idmac_terminate_all(chan);
1506
1507 if (ichan->status > IPU_CHANNEL_FREE) {
1508 free_irq(ichan->eof_irq, ichan);
1509 ipu_irq_unmap(ichan->dma_chan.chan_id);
1510 }
1511
1512 ichan->status = IPU_CHANNEL_FREE;
1513
1514 ipu_uninit_channel(idmac, ichan);
1515
1516 mutex_unlock(&ichan->chan_mutex);
1517
1518 tasklet_schedule(&to_ipu(idmac)->tasklet);
1519}
1520
1521static enum dma_status idmac_is_tx_complete(struct dma_chan *chan,
1522 dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
1523{
1524 struct idmac_channel *ichan = to_idmac_chan(chan);
1525
1526 if (done)
1527 *done = ichan->completed;
1528 if (used)
1529 *used = chan->cookie;
1530 if (cookie != chan->cookie)
1531 return DMA_ERROR;
1532 return DMA_SUCCESS;
1533}
1534
1535static int __init ipu_idmac_init(struct ipu *ipu)
1536{
1537 struct idmac *idmac = &ipu->idmac;
1538 struct dma_device *dma = &idmac->dma;
1539 int i;
1540
1541 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1542 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1543
1544 /* Compulsory common fields */
1545 dma->dev = ipu->dev;
1546 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1547 dma->device_free_chan_resources = idmac_free_chan_resources;
1548 dma->device_is_tx_complete = idmac_is_tx_complete;
1549 dma->device_issue_pending = idmac_issue_pending;
1550
1551 /* Compulsory for DMA_SLAVE fields */
1552 dma->device_prep_slave_sg = idmac_prep_slave_sg;
1553 dma->device_terminate_all = idmac_terminate_all;
1554
1555 INIT_LIST_HEAD(&dma->channels);
1556 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1557 struct idmac_channel *ichan = ipu->channel + i;
1558 struct dma_chan *dma_chan = &ichan->dma_chan;
1559
1560 spin_lock_init(&ichan->lock);
1561 mutex_init(&ichan->chan_mutex);
1562
1563 ichan->status = IPU_CHANNEL_FREE;
1564 ichan->sec_chan_en = false;
1565 ichan->completed = -ENXIO;
1566 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1567
1568 dma_chan->device = &idmac->dma;
1569 dma_chan->cookie = 1;
1570 dma_chan->chan_id = i;
1571 list_add_tail(&ichan->dma_chan.device_node, &dma->channels);
1572 }
1573
1574 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1575
1576 return dma_async_device_register(&idmac->dma);
1577}
1578
234f2df5 1579static void __exit ipu_idmac_exit(struct ipu *ipu)
5296b56d
GL		 1580{
1581 int i;
1582 struct idmac *idmac = &ipu->idmac;
1583
1584 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1585 struct idmac_channel *ichan = ipu->channel + i;
1586
1587 idmac_terminate_all(&ichan->dma_chan);
1588 idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
1589 }
1590
1591 dma_async_device_unregister(&idmac->dma);
1592}
1593
1594/*****************************************************************************
1595 * IPU common probe / remove
1596 */
1597
234f2df5 1598static int __init ipu_probe(struct platform_device *pdev)
5296b56d
GL		 1599{
1600 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1601 struct resource *mem_ipu, *mem_ic;
1602 int ret;
1603
1604 spin_lock_init(&ipu_data.lock);
1605
1606 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1608 if (!pdata || !mem_ipu || !mem_ic)
1609 return -EINVAL;
1610
1611 ipu_data.dev = &pdev->dev;
1612
1613 platform_set_drvdata(pdev, &ipu_data);
1614
1615 ret = platform_get_irq(pdev, 0);
1616 if (ret < 0)
1617 goto err_noirq;
1618
1619 ipu_data.irq_fn = ret;
1620 ret = platform_get_irq(pdev, 1);
1621 if (ret < 0)
1622 goto err_noirq;
1623
1624 ipu_data.irq_err = ret;
1625 ipu_data.irq_base = pdata->irq_base;
1626
1627 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1628 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1629
1630 /* Remap IPU common registers */
1631 ipu_data.reg_ipu = ioremap(mem_ipu->start,
1632 mem_ipu->end - mem_ipu->start + 1);
1633 if (!ipu_data.reg_ipu) {
1634 ret = -ENOMEM;
1635 goto err_ioremap_ipu;
1636 }
1637
1638 /* Remap Image Converter and Image DMA Controller registers */
1639 ipu_data.reg_ic = ioremap(mem_ic->start,
1640 mem_ic->end - mem_ic->start + 1);
1641 if (!ipu_data.reg_ic) {
1642 ret = -ENOMEM;
1643 goto err_ioremap_ic;
1644 }
1645
1646 /* Get IPU clock */
1647 ipu_data.ipu_clk = clk_get(&pdev->dev, "ipu_clk");
1648 if (IS_ERR(ipu_data.ipu_clk)) {
1649 ret = PTR_ERR(ipu_data.ipu_clk);
1650 goto err_clk_get;
1651 }
1652
1653 /* Make sure IPU HSP clock is running */
1654 clk_enable(ipu_data.ipu_clk);
1655
1656 /* Disable all interrupts */
1657 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1658 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1659 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1660 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1661 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1662
1663 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1664 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1665
1666 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1667 if (ret < 0)
1668 goto err_attach_irq;
1669
1670 /* Initialize DMA engine */
1671 ret = ipu_idmac_init(&ipu_data);
1672 if (ret < 0)
1673 goto err_idmac_init;
1674
1675 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1676
1677 ipu_data.dev = &pdev->dev;
1678
1679 dev_dbg(ipu_data.dev, "IPU initialized\n");
1680
1681 return 0;
1682
1683err_idmac_init:
1684err_attach_irq:
1685 ipu_irq_detach_irq(&ipu_data, pdev);
1686 clk_disable(ipu_data.ipu_clk);
1687 clk_put(ipu_data.ipu_clk);
1688err_clk_get:
1689 iounmap(ipu_data.reg_ic);
1690err_ioremap_ic:
1691 iounmap(ipu_data.reg_ipu);
1692err_ioremap_ipu:
1693err_noirq:
1694 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1695 return ret;
1696}
1697
234f2df5 1698static int __exit ipu_remove(struct platform_device *pdev)
5296b56d
GL		 1699{
1700 struct ipu *ipu = platform_get_drvdata(pdev);
1701
1702 ipu_idmac_exit(ipu);
1703 ipu_irq_detach_irq(ipu, pdev);
1704 clk_disable(ipu->ipu_clk);
1705 clk_put(ipu->ipu_clk);
1706 iounmap(ipu->reg_ic);
1707 iounmap(ipu->reg_ipu);
1708 tasklet_kill(&ipu->tasklet);
1709 platform_set_drvdata(pdev, NULL);
1710
1711 return 0;
1712}
1713
1714/*
1715 * We need two MEM resources - with IPU-common and Image Converter registers,
1716 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1717 */
1718static struct platform_driver ipu_platform_driver = {
1719 .driver = {
1720 .name = "ipu-core",
1721 .owner = THIS_MODULE,
1722 },
234f2df5 1723 .remove = __exit_p(ipu_remove),
5296b56d
GL		 1724};
1725
1726static int __init ipu_init(void)
1727{
1728 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1729}
1730subsys_initcall(ipu_init);
1731
1732MODULE_DESCRIPTION("IPU core driver");
1733MODULE_LICENSE("GPL v2");
1734MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1735MODULE_ALIAS("platform:ipu-core");
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