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dmaengine: move last completed cookie into generic dma_chan structure
[mirror_ubuntu-artful-kernel.git] / drivers / dma / ipu / ipu_idmac.c
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5296b56d
GL		 1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
b7f080cf 12#include <linux/dma-mapping.h>
5296b56d
GL		 13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/err.h>
16#include <linux/spinlock.h>
17#include <linux/delay.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/vmalloc.h>
21#include <linux/string.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
5c45ad77 24#include <linux/module.h>
5296b56d
GL		 25
26#include <mach/ipu.h>
27
28#include "ipu_intern.h"
29
30#define FS_VF_IN_VALID 0x00000002
31#define FS_ENC_IN_VALID 0x00000001
32
8d47bae0
GL		 33static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
34 bool wait_for_stop);
35
5296b56d
GL		 36/*
37 * There can be only one, we could allocate it dynamically, but then we'd have
38 * to add an extra parameter to some functions, and use something as ugly as
39 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
40 * in the ISR
41 */
42static struct ipu ipu_data;
43
44#define to_ipu(id) container_of(id, struct ipu, idmac)
45
46static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
47{
48 return __raw_readl(ipu->reg_ic + reg);
49}
50
51#define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
52
53static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
54{
55 __raw_writel(value, ipu->reg_ic + reg);
56}
57
58#define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
59
60static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
61{
62 return __raw_readl(ipu->reg_ipu + reg);
63}
64
65static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
66{
67 __raw_writel(value, ipu->reg_ipu + reg);
68}
69
70/*****************************************************************************
71 * IPU / IC common functions
72 */
73static void dump_idmac_reg(struct ipu *ipu)
74{
75 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
76 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
77 idmac_read_icreg(ipu, IDMAC_CONF),
78 idmac_read_icreg(ipu, IC_CONF),
79 idmac_read_icreg(ipu, IDMAC_CHA_EN),
80 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
81 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
82 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
83 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
84 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
85 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
86 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
87 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
88 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
89}
90
91static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
92{
93 switch (fmt) {
94 case IPU_PIX_FMT_GENERIC: /* generic data */
95 case IPU_PIX_FMT_RGB332:
96 case IPU_PIX_FMT_YUV420P:
97 case IPU_PIX_FMT_YUV422P:
98 default:
99 return 1;
100 case IPU_PIX_FMT_RGB565:
101 case IPU_PIX_FMT_YUYV:
102 case IPU_PIX_FMT_UYVY:
103 return 2;
104 case IPU_PIX_FMT_BGR24:
105 case IPU_PIX_FMT_RGB24:
106 return 3;
107 case IPU_PIX_FMT_GENERIC_32: /* generic data */
108 case IPU_PIX_FMT_BGR32:
109 case IPU_PIX_FMT_RGB32:
110 case IPU_PIX_FMT_ABGR32:
111 return 4;
112 }
113}
114
0149f7d5 115/* Enable direct write to memory by the Camera Sensor Interface */
5296b56d
GL		 116static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
117{
118 uint32_t ic_conf, mask;
119
120 switch (channel) {
121 case IDMAC_IC_0:
122 mask = IC_CONF_PRPENC_EN;
123 break;
124 case IDMAC_IC_7:
125 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
126 break;
127 default:
128 return;
129 }
130 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
131 idmac_write_icreg(ipu, ic_conf, IC_CONF);
132}
133
0149f7d5 134/* Called under spin_lock_irqsave(&ipu_data.lock) */
5296b56d
GL		 135static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
136{
137 uint32_t ic_conf, mask;
138
139 switch (channel) {
140 case IDMAC_IC_0:
141 mask = IC_CONF_PRPENC_EN;
142 break;
143 case IDMAC_IC_7:
144 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
145 break;
146 default:
147 return;
148 }
149 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
150 idmac_write_icreg(ipu, ic_conf, IC_CONF);
151}
152
153static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
154{
155 uint32_t stat = TASK_STAT_IDLE;
156 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
157
158 switch (channel) {
159 case IDMAC_IC_7:
160 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
161 TSTAT_CSI2MEM_OFFSET;
162 break;
163 case IDMAC_IC_0:
164 case IDMAC_SDC_0:
165 case IDMAC_SDC_1:
166 default:
167 break;
168 }
169 return stat;
170}
171
172struct chan_param_mem_planar {
173 /* Word 0 */
174 u32 xv:10;
175 u32 yv:10;
176 u32 xb:12;
177
178 u32 yb:12;
179 u32 res1:2;
180 u32 nsb:1;
181 u32 lnpb:6;
182 u32 ubo_l:11;
183
184 u32 ubo_h:15;
185 u32 vbo_l:17;
186
187 u32 vbo_h:9;
188 u32 res2:3;
189 u32 fw:12;
190 u32 fh_l:8;
191
192 u32 fh_h:4;
193 u32 res3:28;
194
195 /* Word 1 */
196 u32 eba0;
197
198 u32 eba1;
199
200 u32 bpp:3;
201 u32 sl:14;
202 u32 pfs:3;
203 u32 bam:3;
204 u32 res4:2;
205 u32 npb:6;
206 u32 res5:1;
207
208 u32 sat:2;
209 u32 res6:30;
210} __attribute__ ((packed));
211
212struct chan_param_mem_interleaved {
213 /* Word 0 */
214 u32 xv:10;
215 u32 yv:10;
216 u32 xb:12;
217
218 u32 yb:12;
219 u32 sce:1;
220 u32 res1:1;
221 u32 nsb:1;
222 u32 lnpb:6;
223 u32 sx:10;
224 u32 sy_l:1;
225
226 u32 sy_h:9;
227 u32 ns:10;
228 u32 sm:10;
229 u32 sdx_l:3;
230
231 u32 sdx_h:2;
232 u32 sdy:5;
233 u32 sdrx:1;
234 u32 sdry:1;
235 u32 sdr1:1;
236 u32 res2:2;
237 u32 fw:12;
238 u32 fh_l:8;
239
240 u32 fh_h:4;
241 u32 res3:28;
242
243 /* Word 1 */
244 u32 eba0;
245
246 u32 eba1;
247
248 u32 bpp:3;
249 u32 sl:14;
250 u32 pfs:3;
251 u32 bam:3;
252 u32 res4:2;
253 u32 npb:6;
254 u32 res5:1;
255
256 u32 sat:2;
257 u32 scc:1;
258 u32 ofs0:5;
259 u32 ofs1:5;
260 u32 ofs2:5;
261 u32 ofs3:5;
262 u32 wid0:3;
263 u32 wid1:3;
264 u32 wid2:3;
265
266 u32 wid3:3;
267 u32 dec_sel:1;
268 u32 res6:28;
269} __attribute__ ((packed));
270
271union chan_param_mem {
272 struct chan_param_mem_planar pp;
273 struct chan_param_mem_interleaved ip;
274};
275
276static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
277 u32 u_offset, u32 v_offset)
278{
279 params->pp.ubo_l = u_offset & 0x7ff;
280 params->pp.ubo_h = u_offset >> 11;
281 params->pp.vbo_l = v_offset & 0x1ffff;
282 params->pp.vbo_h = v_offset >> 17;
283}
284
285static void ipu_ch_param_set_size(union chan_param_mem *params,
286 uint32_t pixel_fmt, uint16_t width,
287 uint16_t height, uint16_t stride)
288{
289 u32 u_offset;
290 u32 v_offset;
291
292 params->pp.fw = width - 1;
293 params->pp.fh_l = height - 1;
294 params->pp.fh_h = (height - 1) >> 8;
295 params->pp.sl = stride - 1;
296
297 switch (pixel_fmt) {
298 case IPU_PIX_FMT_GENERIC:
299 /*Represents 8-bit Generic data */
300 params->pp.bpp = 3;
301 params->pp.pfs = 7;
302 params->pp.npb = 31;
303 params->pp.sat = 2; /* SAT = use 32-bit access */
304 break;
305 case IPU_PIX_FMT_GENERIC_32:
306 /*Represents 32-bit Generic data */
307 params->pp.bpp = 0;
308 params->pp.pfs = 7;
309 params->pp.npb = 7;
310 params->pp.sat = 2; /* SAT = use 32-bit access */
311 break;
312 case IPU_PIX_FMT_RGB565:
313 params->ip.bpp = 2;
314 params->ip.pfs = 4;
c99e7843 315 params->ip.npb = 15;
5296b56d
GL		 316 params->ip.sat = 2; /* SAT = 32-bit access */
317 params->ip.ofs0 = 0; /* Red bit offset */
318 params->ip.ofs1 = 5; /* Green bit offset */
319 params->ip.ofs2 = 11; /* Blue bit offset */
320 params->ip.ofs3 = 16; /* Alpha bit offset */
321 params->ip.wid0 = 4; /* Red bit width - 1 */
322 params->ip.wid1 = 5; /* Green bit width - 1 */
323 params->ip.wid2 = 4; /* Blue bit width - 1 */
324 break;
325 case IPU_PIX_FMT_BGR24:
326 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
327 params->ip.pfs = 4;
328 params->ip.npb = 7;
329 params->ip.sat = 2; /* SAT = 32-bit access */
330 params->ip.ofs0 = 0; /* Red bit offset */
331 params->ip.ofs1 = 8; /* Green bit offset */
332 params->ip.ofs2 = 16; /* Blue bit offset */
333 params->ip.ofs3 = 24; /* Alpha bit offset */
334 params->ip.wid0 = 7; /* Red bit width - 1 */
335 params->ip.wid1 = 7; /* Green bit width - 1 */
336 params->ip.wid2 = 7; /* Blue bit width - 1 */
337 break;
338 case IPU_PIX_FMT_RGB24:
339 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
340 params->ip.pfs = 4;
341 params->ip.npb = 7;
342 params->ip.sat = 2; /* SAT = 32-bit access */
343 params->ip.ofs0 = 16; /* Red bit offset */
344 params->ip.ofs1 = 8; /* Green bit offset */
345 params->ip.ofs2 = 0; /* Blue bit offset */
346 params->ip.ofs3 = 24; /* Alpha bit offset */
347 params->ip.wid0 = 7; /* Red bit width - 1 */
348 params->ip.wid1 = 7; /* Green bit width - 1 */
349 params->ip.wid2 = 7; /* Blue bit width - 1 */
350 break;
351 case IPU_PIX_FMT_BGRA32:
352 case IPU_PIX_FMT_BGR32:
9ad7bd29 353 case IPU_PIX_FMT_ABGR32:
5296b56d
GL		 354 params->ip.bpp = 0;
355 params->ip.pfs = 4;
356 params->ip.npb = 7;
357 params->ip.sat = 2; /* SAT = 32-bit access */
358 params->ip.ofs0 = 8; /* Red bit offset */
359 params->ip.ofs1 = 16; /* Green bit offset */
360 params->ip.ofs2 = 24; /* Blue bit offset */
361 params->ip.ofs3 = 0; /* Alpha bit offset */
362 params->ip.wid0 = 7; /* Red bit width - 1 */
363 params->ip.wid1 = 7; /* Green bit width - 1 */
364 params->ip.wid2 = 7; /* Blue bit width - 1 */
365 params->ip.wid3 = 7; /* Alpha bit width - 1 */
366 break;
367 case IPU_PIX_FMT_RGBA32:
368 case IPU_PIX_FMT_RGB32:
369 params->ip.bpp = 0;
370 params->ip.pfs = 4;
371 params->ip.npb = 7;
372 params->ip.sat = 2; /* SAT = 32-bit access */
373 params->ip.ofs0 = 24; /* Red bit offset */
374 params->ip.ofs1 = 16; /* Green bit offset */
375 params->ip.ofs2 = 8; /* Blue bit offset */
376 params->ip.ofs3 = 0; /* Alpha bit offset */
377 params->ip.wid0 = 7; /* Red bit width - 1 */
378 params->ip.wid1 = 7; /* Green bit width - 1 */
379 params->ip.wid2 = 7; /* Blue bit width - 1 */
5296b56d
GL		 380 params->ip.wid3 = 7; /* Alpha bit width - 1 */
381 break;
382 case IPU_PIX_FMT_UYVY:
383 params->ip.bpp = 2;
384 params->ip.pfs = 6;
385 params->ip.npb = 7;
386 params->ip.sat = 2; /* SAT = 32-bit access */
387 break;
388 case IPU_PIX_FMT_YUV420P2:
389 case IPU_PIX_FMT_YUV420P:
390 params->ip.bpp = 3;
391 params->ip.pfs = 3;
392 params->ip.npb = 7;
393 params->ip.sat = 2; /* SAT = 32-bit access */
394 u_offset = stride * height;
395 v_offset = u_offset + u_offset / 4;
396 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
397 break;
398 case IPU_PIX_FMT_YVU422P:
399 params->ip.bpp = 3;
400 params->ip.pfs = 2;
401 params->ip.npb = 7;
402 params->ip.sat = 2; /* SAT = 32-bit access */
403 v_offset = stride * height;
404 u_offset = v_offset + v_offset / 2;
405 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
406 break;
407 case IPU_PIX_FMT_YUV422P:
408 params->ip.bpp = 3;
409 params->ip.pfs = 2;
410 params->ip.npb = 7;
411 params->ip.sat = 2; /* SAT = 32-bit access */
412 u_offset = stride * height;
413 v_offset = u_offset + u_offset / 2;
414 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
415 break;
416 default:
417 dev_err(ipu_data.dev,
0149f7d5 418 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
5296b56d
GL		 419 break;
420 }
421
422 params->pp.nsb = 1;
423}
424
5296b56d
GL		 425static void ipu_ch_param_set_buffer(union chan_param_mem *params,
426 dma_addr_t buf0, dma_addr_t buf1)
427{
428 params->pp.eba0 = buf0;
429 params->pp.eba1 = buf1;
0149f7d5 430}
5296b56d
GL		 431
432static void ipu_ch_param_set_rotation(union chan_param_mem *params,
433 enum ipu_rotate_mode rotate)
434{
435 params->pp.bam = rotate;
0149f7d5 436}
5296b56d
GL		 437
438static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
439 uint32_t num_words)
440{
441 for (; num_words > 0; num_words--) {
442 dev_dbg(ipu_data.dev,
443 "write param mem - addr = 0x%08X, data = 0x%08X\n",
444 addr, *data);
445 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
446 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
447 addr++;
448 if ((addr & 0x7) == 5) {
449 addr &= ~0x7; /* set to word 0 */
450 addr += 8; /* increment to next row */
451 }
452 }
453}
454
455static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
456 uint32_t *resize_coeff,
457 uint32_t *downsize_coeff)
458{
459 uint32_t temp_size;
460 uint32_t temp_downsize;
461
462 *resize_coeff = 1 << 13;
463 *downsize_coeff = 1 << 13;
464
465 /* Cannot downsize more than 8:1 */
466 if (out_size << 3 < in_size)
467 return -EINVAL;
468
469 /* compute downsizing coefficient */
470 temp_downsize = 0;
471 temp_size = in_size;
472 while (temp_size >= out_size * 2 && temp_downsize < 2) {
473 temp_size >>= 1;
474 temp_downsize++;
475 }
476 *downsize_coeff = temp_downsize;
477
478 /*
479 * compute resizing coefficient using the following formula:
480 * resize_coeff = M*(SI -1)/(SO - 1)
481 * where M = 2^13, SI - input size, SO - output size
482 */
483 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
484 if (*resize_coeff >= 16384L) {
485 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
486 *resize_coeff = 0x3FFF;
487 }
488
489 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
490 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
491 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
492 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
493
494 return 0;
495}
496
497static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
498{
499 switch (fmt) {
500 case IPU_PIX_FMT_RGB565:
501 case IPU_PIX_FMT_BGR24:
502 case IPU_PIX_FMT_RGB24:
503 case IPU_PIX_FMT_BGR32:
504 case IPU_PIX_FMT_RGB32:
505 return IPU_COLORSPACE_RGB;
506 default:
507 return IPU_COLORSPACE_YCBCR;
508 }
509}
510
511static int ipu_ic_init_prpenc(struct ipu *ipu,
512 union ipu_channel_param *params, bool src_is_csi)
513{
514 uint32_t reg, ic_conf;
515 uint32_t downsize_coeff, resize_coeff;
516 enum ipu_color_space in_fmt, out_fmt;
517
518 /* Setup vertical resizing */
519 calc_resize_coeffs(params->video.in_height,
520 params->video.out_height,
521 &resize_coeff, &downsize_coeff);
522 reg = (downsize_coeff << 30) | (resize_coeff << 16);
523
524 /* Setup horizontal resizing */
525 calc_resize_coeffs(params->video.in_width,
526 params->video.out_width,
527 &resize_coeff, &downsize_coeff);
528 reg |= (downsize_coeff << 14) | resize_coeff;
529
530 /* Setup color space conversion */
531 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
532 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
533
534 /*
535 * Colourspace conversion unsupported yet - see _init_csc() in
536 * Freescale sources
537 */
538 if (in_fmt != out_fmt) {
539 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
540 return -EOPNOTSUPP;
541 }
542
543 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
544
545 ic_conf = idmac_read_icreg(ipu, IC_CONF);
546
547 if (src_is_csi)
548 ic_conf &= ~IC_CONF_RWS_EN;
549 else
550 ic_conf |= IC_CONF_RWS_EN;
551
552 idmac_write_icreg(ipu, ic_conf, IC_CONF);
553
554 return 0;
555}
556
557static uint32_t dma_param_addr(uint32_t dma_ch)
558{
559 /* Channel Parameter Memory */
560 return 0x10000 | (dma_ch << 4);
0149f7d5 561}
5296b56d
GL		 562
563static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
564 bool prio)
565{
566 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
567
568 if (prio)
569 reg |= 1UL << channel;
570 else
571 reg &= ~(1UL << channel);
572
573 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
574
575 dump_idmac_reg(ipu);
576}
577
578static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
579{
580 uint32_t mask;
581
582 switch (channel) {
583 case IDMAC_IC_0:
584 case IDMAC_IC_7:
585 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
586 break;
587 case IDMAC_SDC_0:
588 case IDMAC_SDC_1:
589 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
590 break;
591 default:
592 mask = 0;
593 break;
594 }
595
596 return mask;
597}
598
599/**
600 * ipu_enable_channel() - enable an IPU channel.
0149f7d5
GL		 601 * @idmac: IPU DMAC context.
602 * @ichan: IDMAC channel.
5296b56d
GL		 603 * @return: 0 on success or negative error code on failure.
604 */
605static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
606{
607 struct ipu *ipu = to_ipu(idmac);
608 enum ipu_channel channel = ichan->dma_chan.chan_id;
609 uint32_t reg;
610 unsigned long flags;
611
612 spin_lock_irqsave(&ipu->lock, flags);
613
614 /* Reset to buffer 0 */
615 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
616 ichan->active_buffer = 0;
617 ichan->status = IPU_CHANNEL_ENABLED;
618
619 switch (channel) {
620 case IDMAC_SDC_0:
621 case IDMAC_SDC_1:
622 case IDMAC_IC_7:
623 ipu_channel_set_priority(ipu, channel, true);
624 default:
625 break;
626 }
627
628 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
629
630 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
631
632 ipu_ic_enable_task(ipu, channel);
633
634 spin_unlock_irqrestore(&ipu->lock, flags);
635 return 0;
636}
637
638/**
639 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
0149f7d5 640 * @ichan: IDMAC channel.
5296b56d
GL		 641 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
642 * @width: width of buffer in pixels.
643 * @height: height of buffer in pixels.
644 * @stride: stride length of buffer in pixels.
645 * @rot_mode: rotation mode of buffer. A rotation setting other than
646 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
647 * rotation channels.
648 * @phyaddr_0: buffer 0 physical address.
649 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
650 * NULL enables double buffering mode.
651 * @return: 0 on success or negative error code on failure.
652 */
653static int ipu_init_channel_buffer(struct idmac_channel *ichan,
654 enum pixel_fmt pixel_fmt,
655 uint16_t width, uint16_t height,
656 uint32_t stride,
657 enum ipu_rotate_mode rot_mode,
658 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
659{
660 enum ipu_channel channel = ichan->dma_chan.chan_id;
661 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
662 struct ipu *ipu = to_ipu(idmac);
663 union chan_param_mem params = {};
664 unsigned long flags;
665 uint32_t reg;
666 uint32_t stride_bytes;
667
668 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
669
670 if (stride_bytes % 4) {
671 dev_err(ipu->dev,
672 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
673 stride, stride_bytes);
674 return -EINVAL;
675 }
676
677 /* IC channel's stride must be a multiple of 8 pixels */
0149f7d5 678 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
5296b56d
GL		 679 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
680 return -EINVAL;
681 }
682
683 /* Build parameter memory data for DMA channel */
684 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
685 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
686 ipu_ch_param_set_rotation(&params, rot_mode);
5296b56d
GL		 687
688 spin_lock_irqsave(&ipu->lock, flags);
689
690 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
691
692 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
693
694 if (phyaddr_1)
695 reg |= 1UL << channel;
696 else
697 reg &= ~(1UL << channel);
698
699 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
700
701 ichan->status = IPU_CHANNEL_READY;
702
c74ef1f8 703 spin_unlock_irqrestore(&ipu->lock, flags);
5296b56d
GL		 704
705 return 0;
706}
707
708/**
709 * ipu_select_buffer() - mark a channel's buffer as ready.
710 * @channel: channel ID.
711 * @buffer_n: buffer number to mark ready.
712 */
713static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
714{
715 /* No locking - this is a write-one-to-set register, cleared by IPU */
716 if (buffer_n == 0)
717 /* Mark buffer 0 as ready. */
718 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
719 else
720 /* Mark buffer 1 as ready. */
721 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
722}
723
724/**
725 * ipu_update_channel_buffer() - update physical address of a channel buffer.
0149f7d5 726 * @ichan: IDMAC channel.
5296b56d
GL		 727 * @buffer_n: buffer number to update.
728 * 0 or 1 are the only valid values.
729 * @phyaddr: buffer physical address.
5296b56d
GL		 730 */
731/* Called under spin_lock(_irqsave)(&ichan->lock) */
8f98781e
GL		 732static void ipu_update_channel_buffer(struct idmac_channel *ichan,
733 int buffer_n, dma_addr_t phyaddr)
5296b56d 734{
8d47bae0 735 enum ipu_channel channel = ichan->dma_chan.chan_id;
5296b56d
GL		 736 uint32_t reg;
737 unsigned long flags;
738
739 spin_lock_irqsave(&ipu_data.lock, flags);
740
741 if (buffer_n == 0) {
742 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
743 if (reg & (1UL << channel)) {
8d47bae0
GL		 744 ipu_ic_disable_task(&ipu_data, channel);
745 ichan->status = IPU_CHANNEL_READY;
5296b56d
GL		 746 }
747
748 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
749 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
750 0x0008UL, IPU_IMA_ADDR);
751 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
752 } else {
753 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
754 if (reg & (1UL << channel)) {
8d47bae0
GL		 755 ipu_ic_disable_task(&ipu_data, channel);
756 ichan->status = IPU_CHANNEL_READY;
5296b56d
GL		 757 }
758
759 /* Check if double-buffering is already enabled */
760 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
761
762 if (!(reg & (1UL << channel)))
763 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
764 IPU_CHA_DB_MODE_SEL);
765
766 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
767 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
768 0x0009UL, IPU_IMA_ADDR);
769 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
770 }
771
772 spin_unlock_irqrestore(&ipu_data.lock, flags);
5296b56d
GL		 773}
774
8d47bae0
GL		 775/* Called under spin_lock_irqsave(&ichan->lock) */
776static int ipu_submit_buffer(struct idmac_channel *ichan,
777 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
778{
779 unsigned int chan_id = ichan->dma_chan.chan_id;
780 struct device *dev = &ichan->dma_chan.dev->device;
8d47bae0
GL		 781
782 if (async_tx_test_ack(&desc->txd))
783 return -EINTR;
784
785 /*
786 * On first invocation this shouldn't be necessary, the call to
787 * ipu_init_channel_buffer() above will set addresses for us, so we
788 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
789 * doing it again shouldn't hurt either.
790 */
8f98781e 791 ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
8d47bae0
GL		 792
793 ipu_select_buffer(chan_id, buf_idx);
794 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
795 sg, chan_id, buf_idx);
796
797 return 0;
798}
799
5296b56d
GL		 800/* Called under spin_lock_irqsave(&ichan->lock) */
801static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
802 struct idmac_tx_desc *desc)
803{
804 struct scatterlist *sg;
805 int i, ret = 0;
806
807 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
808 if (!ichan->sg[i]) {
809 ichan->sg[i] = sg;
810
8d47bae0 811 ret = ipu_submit_buffer(ichan, desc, sg, i);
5296b56d
GL		 812 if (ret < 0)
813 return ret;
814
5296b56d
GL		 815 sg = sg_next(sg);
816 }
817 }
818
819 return ret;
820}
821
822static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
823{
824 struct idmac_tx_desc *desc = to_tx_desc(tx);
825 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
826 struct idmac *idmac = to_idmac(tx->chan->device);
827 struct ipu *ipu = to_ipu(idmac);
8d47bae0 828 struct device *dev = &ichan->dma_chan.dev->device;
5296b56d
GL		 829 dma_cookie_t cookie;
830 unsigned long flags;
8d47bae0 831 int ret;
5296b56d
GL		 832
833 /* Sanity check */
834 if (!list_empty(&desc->list)) {
835 /* The descriptor doesn't belong to client */
8d47bae0 836 dev_err(dev, "Descriptor %p not prepared!\n", tx);
5296b56d
GL		 837 return -EBUSY;
838 }
839
840 mutex_lock(&ichan->chan_mutex);
841
8d47bae0
GL		 842 async_tx_clear_ack(tx);
843
5296b56d
GL		 844 if (ichan->status < IPU_CHANNEL_READY) {
845 struct idmac_video_param *video = &ichan->params.video;
846 /*
847 * Initial buffer assignment - the first two sg-entries from
848 * the descriptor will end up in the IDMAC buffers
849 */
850 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
851 sg_dma_address(&desc->sg[1]);
852
853 WARN_ON(ichan->sg[0] || ichan->sg[1]);
854
855 cookie = ipu_init_channel_buffer(ichan,
856 video->out_pixel_fmt,
857 video->out_width,
858 video->out_height,
859 video->out_stride,
860 IPU_ROTATE_NONE,
861 sg_dma_address(&desc->sg[0]),
862 dma_1);
863 if (cookie < 0)
864 goto out;
865 }
866
8d47bae0 867 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
5296b56d
GL		 868
869 cookie = ichan->dma_chan.cookie;
870
871 if (++cookie < 0)
872 cookie = 1;
873
874 /* from dmaengine.h: "last cookie value returned to client" */
875 ichan->dma_chan.cookie = cookie;
876 tx->cookie = cookie;
8d47bae0
GL		 877
878 /* ipu->lock can be taken under ichan->lock, but not v.v. */
5296b56d 879 spin_lock_irqsave(&ichan->lock, flags);
8d47bae0 880
5296b56d 881 list_add_tail(&desc->list, &ichan->queue);
8d47bae0
GL		 882 /* submit_buffers() atomically verifies and fills empty sg slots */
883 ret = ipu_submit_channel_buffers(ichan, desc);
884
5296b56d
GL		 885 spin_unlock_irqrestore(&ichan->lock, flags);
886
8d47bae0
GL		 887 if (ret < 0) {
888 cookie = ret;
889 goto dequeue;
890 }
891
5296b56d 892 if (ichan->status < IPU_CHANNEL_ENABLED) {
8d47bae0 893 ret = ipu_enable_channel(idmac, ichan);
5296b56d
GL		 894 if (ret < 0) {
895 cookie = ret;
8d47bae0 896 goto dequeue;
5296b56d
GL		 897 }
898 }
899
900 dump_idmac_reg(ipu);
901
8d47bae0
GL		 902dequeue:
903 if (cookie < 0) {
904 spin_lock_irqsave(&ichan->lock, flags);
905 list_del_init(&desc->list);
906 spin_unlock_irqrestore(&ichan->lock, flags);
907 tx->cookie = cookie;
908 ichan->dma_chan.cookie = cookie;
909 }
910
5296b56d
GL		 911out:
912 mutex_unlock(&ichan->chan_mutex);
913
914 return cookie;
915}
916
917/* Called with ichan->chan_mutex held */
918static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
919{
920 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
921 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
922
923 if (!desc)
924 return -ENOMEM;
925
926 /* No interrupts, just disable the tasklet for a moment */
927 tasklet_disable(&to_ipu(idmac)->tasklet);
928
929 ichan->n_tx_desc = n;
930 ichan->desc = desc;
931 INIT_LIST_HEAD(&ichan->queue);
932 INIT_LIST_HEAD(&ichan->free_list);
933
934 while (n--) {
935 struct dma_async_tx_descriptor *txd = &desc->txd;
936
937 memset(txd, 0, sizeof(*txd));
938 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
939 txd->tx_submit = idmac_tx_submit;
5296b56d
GL		 940
941 list_add(&desc->list, &ichan->free_list);
942
943 desc++;
944 }
945
946 tasklet_enable(&to_ipu(idmac)->tasklet);
947
948 return 0;
949}
950
951/**
952 * ipu_init_channel() - initialize an IPU channel.
953 * @idmac: IPU DMAC context.
954 * @ichan: pointer to the channel object.
955 * @return 0 on success or negative error code on failure.
956 */
957static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
958{
959 union ipu_channel_param *params = &ichan->params;
960 uint32_t ipu_conf;
961 enum ipu_channel channel = ichan->dma_chan.chan_id;
962 unsigned long flags;
963 uint32_t reg;
964 struct ipu *ipu = to_ipu(idmac);
965 int ret = 0, n_desc = 0;
966
967 dev_dbg(ipu->dev, "init channel = %d\n", channel);
968
969 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
970 channel != IDMAC_IC_7)
971 return -EINVAL;
972
973 spin_lock_irqsave(&ipu->lock, flags);
974
975 switch (channel) {
976 case IDMAC_IC_7:
977 n_desc = 16;
978 reg = idmac_read_icreg(ipu, IC_CONF);
979 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
980 break;
981 case IDMAC_IC_0:
982 n_desc = 16;
983 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
984 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
985 ret = ipu_ic_init_prpenc(ipu, params, true);
986 break;
987 case IDMAC_SDC_0:
988 case IDMAC_SDC_1:
989 n_desc = 4;
990 default:
991 break;
992 }
993
994 ipu->channel_init_mask |= 1L << channel;
995
996 /* Enable IPU sub module */
997 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
998 ipu_channel_conf_mask(channel);
999 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1000
1001 spin_unlock_irqrestore(&ipu->lock, flags);
1002
1003 if (n_desc && !ichan->desc)
1004 ret = idmac_desc_alloc(ichan, n_desc);
1005
1006 dump_idmac_reg(ipu);
1007
1008 return ret;
1009}
1010
1011/**
1012 * ipu_uninit_channel() - uninitialize an IPU channel.
1013 * @idmac: IPU DMAC context.
1014 * @ichan: pointer to the channel object.
1015 */
1016static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1017{
1018 enum ipu_channel channel = ichan->dma_chan.chan_id;
1019 unsigned long flags;
1020 uint32_t reg;
1021 unsigned long chan_mask = 1UL << channel;
1022 uint32_t ipu_conf;
1023 struct ipu *ipu = to_ipu(idmac);
1024
1025 spin_lock_irqsave(&ipu->lock, flags);
1026
1027 if (!(ipu->channel_init_mask & chan_mask)) {
1028 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1029 channel);
1030 spin_unlock_irqrestore(&ipu->lock, flags);
1031 return;
1032 }
1033
1034 /* Reset the double buffer */
1035 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1036 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1037
1038 ichan->sec_chan_en = false;
1039
1040 switch (channel) {
1041 case IDMAC_IC_7:
1042 reg = idmac_read_icreg(ipu, IC_CONF);
1043 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1044 IC_CONF);
1045 break;
1046 case IDMAC_IC_0:
1047 reg = idmac_read_icreg(ipu, IC_CONF);
1048 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1049 IC_CONF);
1050 break;
1051 case IDMAC_SDC_0:
1052 case IDMAC_SDC_1:
1053 default:
1054 break;
1055 }
1056
1057 ipu->channel_init_mask &= ~(1L << channel);
1058
1059 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1060 ~ipu_channel_conf_mask(channel);
1061 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1062
1063 spin_unlock_irqrestore(&ipu->lock, flags);
1064
1065 ichan->n_tx_desc = 0;
1066 vfree(ichan->desc);
1067 ichan->desc = NULL;
1068}
1069
1070/**
1071 * ipu_disable_channel() - disable an IPU channel.
1072 * @idmac: IPU DMAC context.
1073 * @ichan: channel object pointer.
1074 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1075 * return immediately.
1076 * @return: 0 on success or negative error code on failure.
1077 */
1078static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1079 bool wait_for_stop)
1080{
1081 enum ipu_channel channel = ichan->dma_chan.chan_id;
1082 struct ipu *ipu = to_ipu(idmac);
1083 uint32_t reg;
1084 unsigned long flags;
1085 unsigned long chan_mask = 1UL << channel;
1086 unsigned int timeout;
1087
1088 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1089 timeout = 40;
1090 /* This waiting always fails. Related to spurious irq problem */
1091 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1092 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1093 timeout--;
1094 msleep(10);
1095
1096 if (!timeout) {
1097 dev_dbg(ipu->dev,
1098 "Warning: timeout waiting for channel %u to "
1099 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1100 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1101 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1102 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1103 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1104 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1105 break;
1106 }
1107 }
1108 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1109 }
1110 /* SDC BG and FG must be disabled before DMA is disabled */
1111 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1112 channel == IDMAC_SDC_1)) {
1113 for (timeout = 5;
1114 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1115 msleep(5);
1116 }
1117
1118 spin_lock_irqsave(&ipu->lock, flags);
1119
1120 /* Disable IC task */
1121 ipu_ic_disable_task(ipu, channel);
1122
1123 /* Disable DMA channel(s) */
1124 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1125 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1126
5296b56d
GL		 1127 spin_unlock_irqrestore(&ipu->lock, flags);
1128
1129 return 0;
1130}
1131
8d47bae0
GL		 1132static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1133 struct idmac_tx_desc **desc, struct scatterlist *sg)
1134{
1135 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1136
1137 if (sgnew)
1138 /* next sg-element in this list */
1139 return sgnew;
1140
1141 if ((*desc)->list.next == &ichan->queue)
1142 /* No more descriptors on the queue */
1143 return NULL;
1144
1145 /* Fetch next descriptor */
1146 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1147 return (*desc)->sg;
1148}
1149
5296b56d
GL		 1150/*
1151 * We have several possibilities here:
1152 * current BUF next BUF
1153 *
1154 * not last sg next not last sg
1155 * not last sg next last sg
1156 * last sg first sg from next descriptor
1157 * last sg NULL
1158 *
1159 * Besides, the descriptor queue might be empty or not. We process all these
1160 * cases carefully.
1161 */
1162static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1163{
1164 struct idmac_channel *ichan = dev_id;
8d47bae0 1165 struct device *dev = &ichan->dma_chan.dev->device;
5296b56d
GL		 1166 unsigned int chan_id = ichan->dma_chan.chan_id;
1167 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1168 /* Next transfer descriptor */
8d47bae0 1169 struct idmac_tx_desc *desc, *descnew;
5296b56d
GL		 1170 dma_async_tx_callback callback;
1171 void *callback_param;
1172 bool done = false;
8d47bae0
GL		 1173 u32 ready0, ready1, curbuf, err;
1174 unsigned long flags;
5296b56d
GL		 1175
1176 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1177
8d47bae0
GL		 1178 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1179
1180 spin_lock_irqsave(&ipu_data.lock, flags);
1181
1182 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1183 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1184 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1185 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1186
1187 if (err & (1 << chan_id)) {
1188 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1189 spin_unlock_irqrestore(&ipu_data.lock, flags);
1190 /*
1191 * Doing this
1192 * ichan->sg[0] = ichan->sg[1] = NULL;
1193 * you can force channel re-enable on the next tx_submit(), but
1194 * this is dirty - think about descriptors with multiple
1195 * sg elements.
1196 */
1197 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1198 chan_id, ready0, ready1, curbuf);
1199 return IRQ_HANDLED;
1200 }
1201 spin_unlock_irqrestore(&ipu_data.lock, flags);
1202
5296b56d
GL		 1203 /* Other interrupts do not interfere with this channel */
1204 spin_lock(&ichan->lock);
5296b56d
GL		 1205 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1206 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1207 )) {
1208 spin_unlock(&ichan->lock);
8d47bae0 1209 dev_dbg(dev,
5296b56d
GL		 1210 "IRQ with active buffer still ready on channel %x, "
1211 "active %d, ready %x, %x!\n", chan_id,
1212 ichan->active_buffer, ready0, ready1);
1213 return IRQ_NONE;
1214 }
1215
1216 if (unlikely(list_empty(&ichan->queue))) {
8d47bae0 1217 ichan->sg[ichan->active_buffer] = NULL;
5296b56d 1218 spin_unlock(&ichan->lock);
8d47bae0 1219 dev_err(dev,
5296b56d
GL		 1220 "IRQ without queued buffers on channel %x, active %d, "
1221 "ready %x, %x!\n", chan_id,
1222 ichan->active_buffer, ready0, ready1);
1223 return IRQ_NONE;
1224 }
1225
1226 /*
1227 * active_buffer is a software flag, it shows which buffer we are
1228 * currently expecting back from the hardware, IDMAC should be
1229 * processing the other buffer already
1230 */
1231 sg = &ichan->sg[ichan->active_buffer];
1232 sgnext = ichan->sg[!ichan->active_buffer];
1233
8d47bae0
GL		 1234 if (!*sg) {
1235 spin_unlock(&ichan->lock);
1236 return IRQ_HANDLED;
1237 }
1238
1239 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1240 descnew = desc;
1241
1242 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1243 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1244
1245 /* Find the descriptor of sgnext */
1246 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1247 if (sgnext != sgnew)
1248 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1249
5296b56d
GL		 1250 /*
1251 * if sgnext == NULL sg must be the last element in a scatterlist and
1252 * queue must be empty
1253 */
1254 if (unlikely(!sgnext)) {
8d47bae0
GL		 1255 if (!WARN_ON(sg_next(*sg)))
1256 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1257 ichan->sg[!ichan->active_buffer] = sgnew;
1258
1259 if (unlikely(sgnew)) {
1260 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
5296b56d 1261 } else {
8d47bae0 1262 spin_lock_irqsave(&ipu_data.lock, flags);
5296b56d 1263 ipu_ic_disable_task(&ipu_data, chan_id);
8d47bae0 1264 spin_unlock_irqrestore(&ipu_data.lock, flags);
5296b56d
GL		 1265 ichan->status = IPU_CHANNEL_READY;
1266 /* Continue to check for complete descriptor */
1267 }
1268 }
1269
8d47bae0
GL		 1270 /* Calculate and submit the next sg element */
1271 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
5296b56d
GL		 1272
1273 if (unlikely(!sg_next(*sg)) || !sgnext) {
1274 /*
1275 * Last element in scatterlist done, remove from the queue,
1276 * _init for debugging
1277 */
1278 list_del_init(&desc->list);
1279 done = true;
1280 }
1281
1282 *sg = sgnew;
1283
8d47bae0
GL		 1284 if (likely(sgnew) &&
1285 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
8f98781e
GL		 1286 callback = descnew->txd.callback;
1287 callback_param = descnew->txd.callback_param;
1d3564d9 1288 list_del_init(&descnew->list);
8d47bae0 1289 spin_unlock(&ichan->lock);
8f98781e
GL		 1290 if (callback)
1291 callback(callback_param);
8d47bae0 1292 spin_lock(&ichan->lock);
5296b56d
GL		 1293 }
1294
1295 /* Flip the active buffer - even if update above failed */
1296 ichan->active_buffer = !ichan->active_buffer;
1297 if (done)
4d4e58de 1298 ichan->dma_chan.completed_cookie = desc->txd.cookie;
5296b56d
GL		 1299
1300 callback = desc->txd.callback;
1301 callback_param = desc->txd.callback_param;
1302
1303 spin_unlock(&ichan->lock);
1304
1305 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1306 callback(callback_param);
1307
1308 return IRQ_HANDLED;
1309}
1310
1311static void ipu_gc_tasklet(unsigned long arg)
1312{
1313 struct ipu *ipu = (struct ipu *)arg;
1314 int i;
1315
1316 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1317 struct idmac_channel *ichan = ipu->channel + i;
1318 struct idmac_tx_desc *desc;
1319 unsigned long flags;
8d47bae0
GL		 1320 struct scatterlist *sg;
1321 int j, k;
5296b56d
GL		 1322
1323 for (j = 0; j < ichan->n_tx_desc; j++) {
1324 desc = ichan->desc + j;
1325 spin_lock_irqsave(&ichan->lock, flags);
1326 if (async_tx_test_ack(&desc->txd)) {
1327 list_move(&desc->list, &ichan->free_list);
8d47bae0
GL		 1328 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1329 if (ichan->sg[0] == sg)
1330 ichan->sg[0] = NULL;
1331 else if (ichan->sg[1] == sg)
1332 ichan->sg[1] = NULL;
1333 }
5296b56d
GL		 1334 async_tx_clear_ack(&desc->txd);
1335 }
1336 spin_unlock_irqrestore(&ichan->lock, flags);
1337 }
1338 }
1339}
1340
0149f7d5 1341/* Allocate and initialise a transfer descriptor. */
5296b56d
GL		 1342static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1343 struct scatterlist *sgl, unsigned int sg_len,
db8196df 1344 enum dma_transfer_direction direction, unsigned long tx_flags)
5296b56d
GL		 1345{
1346 struct idmac_channel *ichan = to_idmac_chan(chan);
1347 struct idmac_tx_desc *desc = NULL;
1348 struct dma_async_tx_descriptor *txd = NULL;
1349 unsigned long flags;
1350
1351 /* We only can handle these three channels so far */
8c6db1bb
GL		 1352 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1353 chan->chan_id != IDMAC_IC_7)
5296b56d
GL		 1354 return NULL;
1355
db8196df 1356 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
5296b56d
GL		 1357 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1358 return NULL;
1359 }
1360
1361 mutex_lock(&ichan->chan_mutex);
1362
1363 spin_lock_irqsave(&ichan->lock, flags);
1364 if (!list_empty(&ichan->free_list)) {
1365 desc = list_entry(ichan->free_list.next,
1366 struct idmac_tx_desc, list);
1367
1368 list_del_init(&desc->list);
1369
1370 desc->sg_len = sg_len;
1371 desc->sg = sgl;
1372 txd = &desc->txd;
1373 txd->flags = tx_flags;
1374 }
1375 spin_unlock_irqrestore(&ichan->lock, flags);
1376
1377 mutex_unlock(&ichan->chan_mutex);
1378
1379 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1380
1381 return txd;
1382}
1383
1384/* Re-select the current buffer and re-activate the channel */
1385static void idmac_issue_pending(struct dma_chan *chan)
1386{
1387 struct idmac_channel *ichan = to_idmac_chan(chan);
1388 struct idmac *idmac = to_idmac(chan->device);
1389 struct ipu *ipu = to_ipu(idmac);
1390 unsigned long flags;
1391
1392 /* This is not always needed, but doesn't hurt either */
1393 spin_lock_irqsave(&ipu->lock, flags);
8c6db1bb 1394 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
5296b56d
GL		 1395 spin_unlock_irqrestore(&ipu->lock, flags);
1396
1397 /*
1398 * Might need to perform some parts of initialisation from
1399 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1400 * 0, don't need to set priority again either, but re-enabling the task
1401 * and the channel might be a good idea.
1402 */
1403}
1404
05827630
LW		 1405static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1406 unsigned long arg)
5296b56d
GL		 1407{
1408 struct idmac_channel *ichan = to_idmac_chan(chan);
1409 struct idmac *idmac = to_idmac(chan->device);
1d3564d9
GL		 1410 struct ipu *ipu = to_ipu(idmac);
1411 struct list_head *list, *tmp;
5296b56d
GL		 1412 unsigned long flags;
1413 int i;
1414
1d3564d9
GL		 1415 switch (cmd) {
1416 case DMA_PAUSE:
1417 spin_lock_irqsave(&ipu->lock, flags);
1418 ipu_ic_disable_task(ipu, chan->chan_id);
c3635c78 1419
1d3564d9
GL		 1420 /* Return all descriptors into "prepared" state */
1421 list_for_each_safe(list, tmp, &ichan->queue)
1422 list_del_init(list);
5296b56d 1423
1d3564d9
GL		 1424 ichan->sg[0] = NULL;
1425 ichan->sg[1] = NULL;
5296b56d 1426
1d3564d9 1427 spin_unlock_irqrestore(&ipu->lock, flags);
5296b56d 1428
1d3564d9
GL		 1429 ichan->status = IPU_CHANNEL_INITIALIZED;
1430 break;
1431 case DMA_TERMINATE_ALL:
1432 ipu_disable_channel(idmac, ichan,
1433 ichan->status >= IPU_CHANNEL_ENABLED);
5296b56d 1434
1d3564d9 1435 tasklet_disable(&ipu->tasklet);
5296b56d 1436
1d3564d9
GL		 1437 /* ichan->queue is modified in ISR, have to spinlock */
1438 spin_lock_irqsave(&ichan->lock, flags);
1439 list_splice_init(&ichan->queue, &ichan->free_list);
5296b56d 1440
1d3564d9
GL		 1441 if (ichan->desc)
1442 for (i = 0; i < ichan->n_tx_desc; i++) {
1443 struct idmac_tx_desc *desc = ichan->desc + i;
1444 if (list_empty(&desc->list))
1445 /* Descriptor was prepared, but not submitted */
1446 list_add(&desc->list, &ichan->free_list);
5296b56d 1447
1d3564d9
GL		 1448 async_tx_clear_ack(&desc->txd);
1449 }
1450
1451 ichan->sg[0] = NULL;
1452 ichan->sg[1] = NULL;
1453 spin_unlock_irqrestore(&ichan->lock, flags);
1454
1455 tasklet_enable(&ipu->tasklet);
1456
1457 ichan->status = IPU_CHANNEL_INITIALIZED;
1458 break;
1459 default:
1460 return -ENOSYS;
1461 }
c3635c78
LW		 1462
1463 return 0;
5296b56d
GL		 1464}
1465
05827630
LW		 1466static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1467 unsigned long arg)
5296b56d
GL		 1468{
1469 struct idmac_channel *ichan = to_idmac_chan(chan);
c3635c78 1470 int ret;
5296b56d
GL		 1471
1472 mutex_lock(&ichan->chan_mutex);
1473
05827630 1474 ret = __idmac_control(chan, cmd, arg);
5296b56d
GL		 1475
1476 mutex_unlock(&ichan->chan_mutex);
c3635c78
LW		 1477
1478 return ret;
5296b56d
GL		 1479}
1480
8c6db1bb
GL		 1481#ifdef DEBUG
1482static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1483{
1484 struct idmac_channel *ichan = dev_id;
1485 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1486 irq, ichan->dma_chan.chan_id);
ca50a51e 1487 disable_irq_nosync(irq);
8c6db1bb
GL		 1488 return IRQ_HANDLED;
1489}
1490
1491static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1492{
1493 struct idmac_channel *ichan = dev_id;
1494 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1495 irq, ichan->dma_chan.chan_id);
ca50a51e 1496 disable_irq_nosync(irq);
8c6db1bb
GL		 1497 return IRQ_HANDLED;
1498}
1499
1500static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1501#endif
1502
5296b56d
GL		 1503static int idmac_alloc_chan_resources(struct dma_chan *chan)
1504{
1505 struct idmac_channel *ichan = to_idmac_chan(chan);
1506 struct idmac *idmac = to_idmac(chan->device);
1507 int ret;
1508
1509 /* dmaengine.c now guarantees to only offer free channels */
1510 BUG_ON(chan->client_count > 1);
1511 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1512
1513 chan->cookie = 1;
4d4e58de 1514 chan->completed_cookie = -ENXIO;
5296b56d 1515
8c6db1bb 1516 ret = ipu_irq_map(chan->chan_id);
5296b56d
GL		 1517 if (ret < 0)
1518 goto eimap;
1519
1520 ichan->eof_irq = ret;
8d47bae0
GL		 1521
1522 /*
1523 * Important to first disable the channel, because maybe someone
1524 * used it before us, e.g., the bootloader
1525 */
1526 ipu_disable_channel(idmac, ichan, true);
5296b56d
GL		 1527
1528 ret = ipu_init_channel(idmac, ichan);
1529 if (ret < 0)
1530 goto eichan;
1531
5296b56d
GL		 1532 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1533 ichan->eof_name, ichan);
1534 if (ret < 0)
1535 goto erirq;
1536
8c6db1bb
GL		 1537#ifdef DEBUG
1538 if (chan->chan_id == IDMAC_IC_7) {
1539 ic_sof = ipu_irq_map(69);
1540 if (ic_sof > 0)
1541 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1542 ic_eof = ipu_irq_map(70);
1543 if (ic_eof > 0)
1544 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1545 }
1546#endif
5296b56d
GL		 1547
1548 ichan->status = IPU_CHANNEL_INITIALIZED;
1549
8c6db1bb
GL		 1550 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1551 chan->chan_id, ichan->eof_irq);
5296b56d
GL		 1552
1553 return ret;
1554
5296b56d 1555erirq:
8d47bae0
GL		 1556 ipu_uninit_channel(idmac, ichan);
1557eichan:
8c6db1bb 1558 ipu_irq_unmap(chan->chan_id);
5296b56d
GL		 1559eimap:
1560 return ret;
1561}
1562
1563static void idmac_free_chan_resources(struct dma_chan *chan)
1564{
1565 struct idmac_channel *ichan = to_idmac_chan(chan);
1566 struct idmac *idmac = to_idmac(chan->device);
1567
1568 mutex_lock(&ichan->chan_mutex);
1569
05827630 1570 __idmac_control(chan, DMA_TERMINATE_ALL, 0);
5296b56d
GL		 1571
1572 if (ichan->status > IPU_CHANNEL_FREE) {
8c6db1bb
GL		 1573#ifdef DEBUG
1574 if (chan->chan_id == IDMAC_IC_7) {
1575 if (ic_sof > 0) {
1576 free_irq(ic_sof, ichan);
1577 ipu_irq_unmap(69);
1578 ic_sof = -EINVAL;
1579 }
1580 if (ic_eof > 0) {
1581 free_irq(ic_eof, ichan);
1582 ipu_irq_unmap(70);
1583 ic_eof = -EINVAL;
1584 }
1585 }
1586#endif
5296b56d 1587 free_irq(ichan->eof_irq, ichan);
8c6db1bb 1588 ipu_irq_unmap(chan->chan_id);
5296b56d
GL		 1589 }
1590
1591 ichan->status = IPU_CHANNEL_FREE;
1592
1593 ipu_uninit_channel(idmac, ichan);
1594
1595 mutex_unlock(&ichan->chan_mutex);
1596
1597 tasklet_schedule(&to_ipu(idmac)->tasklet);
1598}
1599
07934481
LW		 1600static enum dma_status idmac_tx_status(struct dma_chan *chan,
1601 dma_cookie_t cookie, struct dma_tx_state *txstate)
5296b56d 1602{
4d4e58de 1603 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
5296b56d
GL		 1604 if (cookie != chan->cookie)
1605 return DMA_ERROR;
1606 return DMA_SUCCESS;
1607}
1608
1609static int __init ipu_idmac_init(struct ipu *ipu)
1610{
1611 struct idmac *idmac = &ipu->idmac;
1612 struct dma_device *dma = &idmac->dma;
1613 int i;
1614
1615 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1616 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1617
1618 /* Compulsory common fields */
1619 dma->dev = ipu->dev;
1620 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1621 dma->device_free_chan_resources = idmac_free_chan_resources;
07934481 1622 dma->device_tx_status = idmac_tx_status;
5296b56d
GL		 1623 dma->device_issue_pending = idmac_issue_pending;
1624
1625 /* Compulsory for DMA_SLAVE fields */
1626 dma->device_prep_slave_sg = idmac_prep_slave_sg;
c3635c78 1627 dma->device_control = idmac_control;
5296b56d
GL		 1628
1629 INIT_LIST_HEAD(&dma->channels);
1630 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1631 struct idmac_channel *ichan = ipu->channel + i;
1632 struct dma_chan *dma_chan = &ichan->dma_chan;
1633
1634 spin_lock_init(&ichan->lock);
1635 mutex_init(&ichan->chan_mutex);
1636
1637 ichan->status = IPU_CHANNEL_FREE;
1638 ichan->sec_chan_en = false;
5296b56d
GL		 1639 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1640
1641 dma_chan->device = &idmac->dma;
1642 dma_chan->cookie = 1;
4d4e58de 1643 dma_chan->completed_cookie = -ENXIO;
5296b56d 1644 dma_chan->chan_id = i;
8c6db1bb 1645 list_add_tail(&dma_chan->device_node, &dma->channels);
5296b56d
GL		 1646 }
1647
1648 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1649
1650 return dma_async_device_register(&idmac->dma);
1651}
1652
234f2df5 1653static void __exit ipu_idmac_exit(struct ipu *ipu)
5296b56d
GL		 1654{
1655 int i;
1656 struct idmac *idmac = &ipu->idmac;
1657
1658 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1659 struct idmac_channel *ichan = ipu->channel + i;
1660
05827630 1661 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
5296b56d
GL		 1662 }
1663
1664 dma_async_device_unregister(&idmac->dma);
1665}
1666
1667/*****************************************************************************
1668 * IPU common probe / remove
1669 */
1670
234f2df5 1671static int __init ipu_probe(struct platform_device *pdev)
5296b56d
GL		 1672{
1673 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1674 struct resource *mem_ipu, *mem_ic;
1675 int ret;
1676
1677 spin_lock_init(&ipu_data.lock);
1678
1679 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1681 if (!pdata || !mem_ipu || !mem_ic)
1682 return -EINVAL;
1683
1684 ipu_data.dev = &pdev->dev;
1685
1686 platform_set_drvdata(pdev, &ipu_data);
1687
1688 ret = platform_get_irq(pdev, 0);
1689 if (ret < 0)
1690 goto err_noirq;
1691
1692 ipu_data.irq_fn = ret;
1693 ret = platform_get_irq(pdev, 1);
1694 if (ret < 0)
1695 goto err_noirq;
1696
1697 ipu_data.irq_err = ret;
1698 ipu_data.irq_base = pdata->irq_base;
1699
1700 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1701 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1702
1703 /* Remap IPU common registers */
7dab35c0 1704 ipu_data.reg_ipu = ioremap(mem_ipu->start, resource_size(mem_ipu));
5296b56d
GL		 1705 if (!ipu_data.reg_ipu) {
1706 ret = -ENOMEM;
1707 goto err_ioremap_ipu;
1708 }
1709
1710 /* Remap Image Converter and Image DMA Controller registers */
7dab35c0 1711 ipu_data.reg_ic = ioremap(mem_ic->start, resource_size(mem_ic));
5296b56d
GL		 1712 if (!ipu_data.reg_ic) {
1713 ret = -ENOMEM;
1714 goto err_ioremap_ic;
1715 }
1716
1717 /* Get IPU clock */
9eb2eb8c 1718 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
5296b56d
GL		 1719 if (IS_ERR(ipu_data.ipu_clk)) {
1720 ret = PTR_ERR(ipu_data.ipu_clk);
1721 goto err_clk_get;
1722 }
1723
1724 /* Make sure IPU HSP clock is running */
1725 clk_enable(ipu_data.ipu_clk);
1726
1727 /* Disable all interrupts */
1728 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1729 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1730 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1731 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1732 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1733
1734 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1735 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1736
1737 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1738 if (ret < 0)
1739 goto err_attach_irq;
1740
1741 /* Initialize DMA engine */
1742 ret = ipu_idmac_init(&ipu_data);
1743 if (ret < 0)
1744 goto err_idmac_init;
1745
1746 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1747
1748 ipu_data.dev = &pdev->dev;
1749
1750 dev_dbg(ipu_data.dev, "IPU initialized\n");
1751
1752 return 0;
1753
1754err_idmac_init:
1755err_attach_irq:
1756 ipu_irq_detach_irq(&ipu_data, pdev);
1757 clk_disable(ipu_data.ipu_clk);
1758 clk_put(ipu_data.ipu_clk);
1759err_clk_get:
1760 iounmap(ipu_data.reg_ic);
1761err_ioremap_ic:
1762 iounmap(ipu_data.reg_ipu);
1763err_ioremap_ipu:
1764err_noirq:
1765 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1766 return ret;
1767}
1768
234f2df5 1769static int __exit ipu_remove(struct platform_device *pdev)
5296b56d
GL		 1770{
1771 struct ipu *ipu = platform_get_drvdata(pdev);
1772
1773 ipu_idmac_exit(ipu);
1774 ipu_irq_detach_irq(ipu, pdev);
1775 clk_disable(ipu->ipu_clk);
1776 clk_put(ipu->ipu_clk);
1777 iounmap(ipu->reg_ic);
1778 iounmap(ipu->reg_ipu);
1779 tasklet_kill(&ipu->tasklet);
1780 platform_set_drvdata(pdev, NULL);
1781
1782 return 0;
1783}
1784
1785/*
1786 * We need two MEM resources - with IPU-common and Image Converter registers,
1787 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1788 */
1789static struct platform_driver ipu_platform_driver = {
1790 .driver = {
1791 .name = "ipu-core",
1792 .owner = THIS_MODULE,
1793 },
234f2df5 1794 .remove = __exit_p(ipu_remove),
5296b56d
GL		 1795};
1796
1797static int __init ipu_init(void)
1798{
1799 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1800}
1801subsys_initcall(ipu_init);
1802
1803MODULE_DESCRIPTION("IPU core driver");
1804MODULE_LICENSE("GPL v2");
1805MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1806MODULE_ALIAS("platform:ipu-core");
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