[mirror_ubuntu-artful-kernel.git] / drivers / dma / ipu / ipu_irq.c

/*
 * Copyright (C) 2008
 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/dma/ipu-dma.h>

#include "ipu_intern.h"

/*
 * Register read / write - shall be inlined by the compiler
 */
static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
{
	return __raw_readl(ipu->reg_ipu + reg);
}

static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
{
	__raw_writel(value, ipu->reg_ipu + reg);
}


/*
 * IPU IRQ chip driver
 */

#define IPU_IRQ_NR_FN_BANKS 3
#define IPU_IRQ_NR_ERR_BANKS 2
#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)

struct ipu_irq_bank {
	unsigned int	control;
	unsigned int	status;
	struct ipu	*ipu;
};

static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
	/* 3 groups of functional interrupts */
	{
		.control	= IPU_INT_CTRL_1,
		.status		= IPU_INT_STAT_1,
	}, {
		.control	= IPU_INT_CTRL_2,
		.status		= IPU_INT_STAT_2,
	}, {
		.control	= IPU_INT_CTRL_3,
		.status		= IPU_INT_STAT_3,
	},
	/* 2 groups of error interrupts */
	{
		.control	= IPU_INT_CTRL_4,
		.status		= IPU_INT_STAT_4,
	}, {
		.control	= IPU_INT_CTRL_5,
		.status		= IPU_INT_STAT_5,
	},
};

struct ipu_irq_map {
	unsigned int		irq;
	int			source;
	struct ipu_irq_bank	*bank;
	struct ipu		*ipu;
};

static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
/* Protects allocations from the above array of maps */
static DEFINE_MUTEX(map_lock);
/* Protects register accesses and individual mappings */
static DEFINE_RAW_SPINLOCK(bank_lock);

static struct ipu_irq_map *src2map(unsigned int src)
{
	int i;

	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
		if (irq_map[i].source == src)
			return irq_map + i;

	return NULL;
}

static void ipu_irq_unmask(struct irq_data *d)
{
	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
	struct ipu_irq_bank *bank;
	uint32_t reg;
	unsigned long lock_flags;

	raw_spin_lock_irqsave(&bank_lock, lock_flags);

	bank = map->bank;
	if (!bank) {
		raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
		pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
		return;
	}

	reg = ipu_read_reg(bank->ipu, bank->control);
	reg |= (1UL << (map->source & 31));
	ipu_write_reg(bank->ipu, reg, bank->control);

	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}

static void ipu_irq_mask(struct irq_data *d)
{
	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
	struct ipu_irq_bank *bank;
	uint32_t reg;
	unsigned long lock_flags;

	raw_spin_lock_irqsave(&bank_lock, lock_flags);

	bank = map->bank;
	if (!bank) {
		raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
		pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
		return;
	}

	reg = ipu_read_reg(bank->ipu, bank->control);
	reg &= ~(1UL << (map->source & 31));
	ipu_write_reg(bank->ipu, reg, bank->control);

	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}

static void ipu_irq_ack(struct irq_data *d)
{
	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
	struct ipu_irq_bank *bank;
	unsigned long lock_flags;

	raw_spin_lock_irqsave(&bank_lock, lock_flags);

	bank = map->bank;
	if (!bank) {
		raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
		pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
		return;
	}

	ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
}

/**
 * ipu_irq_status() - returns the current interrupt status of the specified IRQ.
 * @irq:	interrupt line to get status for.
 * @return:	true if the interrupt is pending/asserted or false if the
 *		interrupt is not pending.
 */
bool ipu_irq_status(unsigned int irq)
{
	struct ipu_irq_map *map = irq_get_chip_data(irq);
	struct ipu_irq_bank *bank;
	unsigned long lock_flags;
	bool ret;

	raw_spin_lock_irqsave(&bank_lock, lock_flags);
	bank = map->bank;
	ret = bank && ipu_read_reg(bank->ipu, bank->status) &
		(1UL << (map->source & 31));
	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);

	return ret;
}

/**
 * ipu_irq_map() - map an IPU interrupt source to an IRQ number
 * @source:	interrupt source bit position (see below)
 * @return:	mapped IRQ number or negative error code
 *
 * The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
 * sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
 * However, the source argument of this function is not the sequence number of
 * the possible IRQ, but rather its bit position. So, first interrupt in fourth
 * register has source number 96, and not 88. This makes calculations easier,
 * and also provides forward compatibility with any future IPU implementations
 * with any interrupt bit assignments.
 */
int ipu_irq_map(unsigned int source)
{
	int i, ret = -ENOMEM;
	struct ipu_irq_map *map;

	might_sleep();

	mutex_lock(&map_lock);
	map = src2map(source);
	if (map) {
		pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
		ret = -EBUSY;
		goto out;
	}

	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
		if (irq_map[i].source < 0) {
			unsigned long lock_flags;

			raw_spin_lock_irqsave(&bank_lock, lock_flags);
			irq_map[i].source = source;
			irq_map[i].bank = irq_bank + source / 32;
			raw_spin_unlock_irqrestore(&bank_lock, lock_flags);

			ret = irq_map[i].irq;
			pr_debug("IPU: mapped source %u to IRQ %u\n",
				 source, ret);
			break;
		}
	}
out:
	mutex_unlock(&map_lock);

	if (ret < 0)
		pr_err("IPU: couldn't map source %u: %d\n", source, ret);

	return ret;
}

/**
 * ipu_irq_map() - map an IPU interrupt source to an IRQ number
 * @source:	interrupt source bit position (see ipu_irq_map())
 * @return:	0 or negative error code
 */
int ipu_irq_unmap(unsigned int source)
{
	int i, ret = -EINVAL;

	might_sleep();

	mutex_lock(&map_lock);
	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
		if (irq_map[i].source == source) {
			unsigned long lock_flags;

			pr_debug("IPU: unmapped source %u from IRQ %u\n",
				 source, irq_map[i].irq);

			raw_spin_lock_irqsave(&bank_lock, lock_flags);
			irq_map[i].source = -EINVAL;
			irq_map[i].bank = NULL;
			raw_spin_unlock_irqrestore(&bank_lock, lock_flags);

			ret = 0;
			break;
		}
	}
	mutex_unlock(&map_lock);

	return ret;
}

/* Chained IRQ handler for IPU function and error interrupt */
static void ipu_irq_handler(struct irq_desc *desc)
{
	struct ipu *ipu = irq_desc_get_handler_data(desc);
	u32 status;
	int i, line;

	for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
		struct ipu_irq_bank *bank = irq_bank + i;

		raw_spin_lock(&bank_lock);
		status = ipu_read_reg(ipu, bank->status);
		/*
		 * Don't think we have to clear all interrupts here, they will
		 * be acked by ->handle_irq() (handle_level_irq). However, we
		 * might want to clear unhandled interrupts after the loop...
		 */
		status &= ipu_read_reg(ipu, bank->control);
		raw_spin_unlock(&bank_lock);
		while ((line = ffs(status))) {
			struct ipu_irq_map *map;
			unsigned int irq = NO_IRQ;

			line--;
			status &= ~(1UL << line);

			raw_spin_lock(&bank_lock);
			map = src2map(32 * i + line);
			if (map)
				irq = map->irq;
			raw_spin_unlock(&bank_lock);

			if (!map) {
				pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
				       line, i);
				continue;
			}
			generic_handle_irq(irq);
		}
	}
}

static struct irq_chip ipu_irq_chip = {
	.name		= "ipu_irq",
	.irq_ack	= ipu_irq_ack,
	.irq_mask	= ipu_irq_mask,
	.irq_unmask	= ipu_irq_unmask,
};

/* Install the IRQ handler */
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
{
	unsigned int irq, i;
	int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
				       numa_node_id());

	if (irq_base < 0)
		return irq_base;

	for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
		irq_bank[i].ipu = ipu;

	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
		int ret;

		irq = irq_base + i;
		ret = irq_set_chip(irq, &ipu_irq_chip);
		if (ret < 0)
			return ret;
		ret = irq_set_chip_data(irq, irq_map + i);
		if (ret < 0)
			return ret;
		irq_map[i].ipu = ipu;
		irq_map[i].irq = irq;
		irq_map[i].source = -EINVAL;
		irq_set_handler(irq, handle_level_irq);
		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu);

	irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu);

	ipu->irq_base = irq_base;

	return 0;
}

void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev)
{
	unsigned int irq, irq_base;

	irq_base = ipu->irq_base;

	irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL);

	irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);

	for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
		irq_set_status_flags(irq, IRQ_NOREQUEST);
		irq_set_chip(irq, NULL);
		irq_set_chip_data(irq, NULL);
	}
}
Commit	Line	Data
5296b56d GL	1	/*
	2	* Copyright (C) 2008
	3	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/err.h>
	12	#include <linux/spinlock.h>
	13	#include <linux/delay.h>
	14	#include <linux/clk.h>
	15	#include <linux/irq.h>
	16	#include <linux/io.h>
88289c80	17	#include <linux/module.h>
b8a6d998	18	#include <linux/dma/ipu-dma.h>
5296b56d GL	19
	20	#include "ipu_intern.h"
	21
	22	/*
	23	* Register read / write - shall be inlined by the compiler
	24	*/
	25	static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg)
	26	{
	27	return __raw_readl(ipu->reg_ipu + reg);
	28	}
	29
	30	static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg)
	31	{
	32	__raw_writel(value, ipu->reg_ipu + reg);
	33	}
	34
	35
	36	/*
	37	* IPU IRQ chip driver
	38	*/
	39
	40	#define IPU_IRQ_NR_FN_BANKS 3
	41	#define IPU_IRQ_NR_ERR_BANKS 2
	42	#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS)
	43
	44	struct ipu_irq_bank {
	45	unsigned int control;
	46	unsigned int status;
5296b56d GL	47	struct ipu *ipu;
	48	};
	49
	50	static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = {
	51	/* 3 groups of functional interrupts */
	52	{
	53	.control = IPU_INT_CTRL_1,
	54	.status = IPU_INT_STAT_1,
	55	}, {
	56	.control = IPU_INT_CTRL_2,
	57	.status = IPU_INT_STAT_2,
	58	}, {
	59	.control = IPU_INT_CTRL_3,
	60	.status = IPU_INT_STAT_3,
	61	},
	62	/* 2 groups of error interrupts */
	63	{
	64	.control = IPU_INT_CTRL_4,
	65	.status = IPU_INT_STAT_4,
	66	}, {
	67	.control = IPU_INT_CTRL_5,
	68	.status = IPU_INT_STAT_5,
	69	},
	70	};
	71
	72	struct ipu_irq_map {
	73	unsigned int irq;
	74	int source;
	75	struct ipu_irq_bank *bank;
	76	struct ipu *ipu;
	77	};
	78
	79	static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
	80	/* Protects allocations from the above array of maps */
	81	static DEFINE_MUTEX(map_lock);
	82	/* Protects register accesses and individual mappings */
289b4e7a	83	static DEFINE_RAW_SPINLOCK(bank_lock);
5296b56d GL	84
	85	static struct ipu_irq_map *src2map(unsigned int src)
	86	{
	87	int i;
	88
	89	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++)
	90	if (irq_map[i].source == src)
	91	return irq_map + i;
	92
	93	return NULL;
	94	}
	95
6a035138	96	static void ipu_irq_unmask(struct irq_data *d)
5296b56d	97	{
6a035138	98	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
5296b56d GL	99	struct ipu_irq_bank *bank;
	100	uint32_t reg;
	101	unsigned long lock_flags;
	102
289b4e7a	103	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	104
	105	bank = map->bank;
	106	if (!bank) {
289b4e7a	107	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
6a035138	108	pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
5296b56d GL	109	return;
	110	}
	111
	112	reg = ipu_read_reg(bank->ipu, bank->control);
	113	reg \|= (1UL << (map->source & 31));
	114	ipu_write_reg(bank->ipu, reg, bank->control);
	115
289b4e7a	116	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	117	}
5296b56d GL	118
6a035138	119	static void ipu_irq_mask(struct irq_data *d)
5296b56d	120	{
6a035138	121	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
5296b56d GL	122	struct ipu_irq_bank *bank;
	123	uint32_t reg;
	124	unsigned long lock_flags;
	125
289b4e7a	126	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	127
	128	bank = map->bank;
	129	if (!bank) {
289b4e7a	130	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
6a035138	131	pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
5296b56d GL	132	return;
	133	}
	134
	135	reg = ipu_read_reg(bank->ipu, bank->control);
	136	reg &= ~(1UL << (map->source & 31));
	137	ipu_write_reg(bank->ipu, reg, bank->control);
	138
289b4e7a	139	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	140	}
5296b56d GL	141
6a035138	142	static void ipu_irq_ack(struct irq_data *d)
5296b56d	143	{
6a035138	144	struct ipu_irq_map *map = irq_data_get_irq_chip_data(d);
5296b56d GL	145	struct ipu_irq_bank *bank;
	146	unsigned long lock_flags;
	147
289b4e7a	148	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	149
	150	bank = map->bank;
	151	if (!bank) {
289b4e7a	152	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
6a035138	153	pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
5296b56d GL	154	return;
	155	}
	156
	157	ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
289b4e7a	158	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	159	}
	160
	161	/**
	162	* ipu_irq_status() - returns the current interrupt status of the specified IRQ.
	163	* @irq: interrupt line to get status for.
	164	* @return: true if the interrupt is pending/asserted or false if the
	165	* interrupt is not pending.
	166	*/
	167	bool ipu_irq_status(unsigned int irq)
	168	{
6a035138	169	struct ipu_irq_map *map = irq_get_chip_data(irq);
5296b56d GL	170	struct ipu_irq_bank *bank;
	171	unsigned long lock_flags;
	172	bool ret;
	173
289b4e7a	174	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	175	bank = map->bank;
	176	ret = bank && ipu_read_reg(bank->ipu, bank->status) &
	177	(1UL << (map->source & 31));
289b4e7a	178	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	179
	180	return ret;
	181	}
	182
	183	/**
	184	* ipu_irq_map() - map an IPU interrupt source to an IRQ number
	185	* @source: interrupt source bit position (see below)
	186	* @return: mapped IRQ number or negative error code
	187	*
	188	* The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ
	189	* sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17.
	190	* However, the source argument of this function is not the sequence number of
	191	* the possible IRQ, but rather its bit position. So, first interrupt in fourth
	192	* register has source number 96, and not 88. This makes calculations easier,
	193	* and also provides forward compatibility with any future IPU implementations
	194	* with any interrupt bit assignments.
	195	*/
	196	int ipu_irq_map(unsigned int source)
	197	{
	198	int i, ret = -ENOMEM;
	199	struct ipu_irq_map *map;
	200
	201	might_sleep();
	202
	203	mutex_lock(&map_lock);
	204	map = src2map(source);
	205	if (map) {
	206	pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq);
	207	ret = -EBUSY;
	208	goto out;
	209	}
	210
	211	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
	212	if (irq_map[i].source < 0) {
	213	unsigned long lock_flags;
	214
289b4e7a	215	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	216	irq_map[i].source = source;
5296b56d GL	217	irq_map[i].bank = irq_bank + source / 32;
289b4e7a	218	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	219
	220	ret = irq_map[i].irq;
	221	pr_debug("IPU: mapped source %u to IRQ %u\n",
	222	source, ret);
	223	break;
	224	}
	225	}
	226	out:
	227	mutex_unlock(&map_lock);
	228
	229	if (ret < 0)
	230	pr_err("IPU: couldn't map source %u: %d\n", source, ret);
	231
	232	return ret;
	233	}
	234
	235	/**
	236	* ipu_irq_map() - map an IPU interrupt source to an IRQ number
	237	* @source: interrupt source bit position (see ipu_irq_map())
	238	* @return: 0 or negative error code
	239	*/
	240	int ipu_irq_unmap(unsigned int source)
	241	{
	242	int i, ret = -EINVAL;
	243
	244	might_sleep();
	245
	246	mutex_lock(&map_lock);
	247	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
	248	if (irq_map[i].source == source) {
	249	unsigned long lock_flags;
	250
	251	pr_debug("IPU: unmapped source %u from IRQ %u\n",
	252	source, irq_map[i].irq);
	253
289b4e7a	254	raw_spin_lock_irqsave(&bank_lock, lock_flags);
5296b56d GL	255	irq_map[i].source = -EINVAL;
5296b56d GL	256	irq_map[i].bank = NULL;
289b4e7a	257	raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
5296b56d GL	258
	259	ret = 0;
	260	break;
	261	}
	262	}
	263	mutex_unlock(&map_lock);
	264
	265	return ret;
	266	}
	267
3d8cc000	268	/* Chained IRQ handler for IPU function and error interrupt */
bd0b9ac4	269	static void ipu_irq_handler(struct irq_desc *desc)
5296b56d	270	{
4d9efdfc	271	struct ipu *ipu = irq_desc_get_handler_data(desc);
5296b56d GL	272	u32 status;
	273	int i, line;
	274
	275	for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
	276	struct ipu_irq_bank *bank = irq_bank + i;
	277
289b4e7a	278	raw_spin_lock(&bank_lock);
5296b56d GL	279	status = ipu_read_reg(ipu, bank->status);
	280	/*
	281	* Don't think we have to clear all interrupts here, they will
	282	* be acked by ->handle_irq() (handle_level_irq). However, we
	283	* might want to clear unhandled interrupts after the loop...
	284	*/
	285	status &= ipu_read_reg(ipu, bank->control);
289b4e7a	286	raw_spin_unlock(&bank_lock);
5296b56d GL	287	while ((line = ffs(status))) {
5296b56d GL	288	struct ipu_irq_map *map;
6ef41cf6	289	unsigned int irq = NO_IRQ;
5296b56d GL	290
	291	line--;
	292	status &= ~(1UL << line);
	293
289b4e7a	294	raw_spin_lock(&bank_lock);
5296b56d GL	295	map = src2map(32 * i + line);
	296	if (map)
	297	irq = map->irq;
289b4e7a	298	raw_spin_unlock(&bank_lock);
5296b56d GL	299
	300	if (!map) {
	301	pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
	302	line, i);
	303	continue;
	304	}
	305	generic_handle_irq(irq);
	306	}
	307	}
	308	}
	309
5296b56d	310	static struct irq_chip ipu_irq_chip = {
6a035138 TG	311	.name = "ipu_irq",
	312	.irq_ack = ipu_irq_ack,
	313	.irq_mask = ipu_irq_mask,
	314	.irq_unmask = ipu_irq_unmask,
5296b56d GL	315	};
	316
	317	/* Install the IRQ handler */
234f2df5	318	int __init ipu_irq_attach_irq(struct ipu ipu, struct platform_device dev)
5296b56d	319	{
88289c80 SG	320	unsigned int irq, i;
	321	int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS,
	322	numa_node_id());
5296b56d	323
88289c80 SG	324	if (irq_base < 0)
88289c80 SG	325	return irq_base;
5296b56d GL	326
	327	for (i = 0; i < IPU_IRQ_NR_BANKS; i++)
	328	irq_bank[i].ipu = ipu;
	329
	330	for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) {
	331	int ret;
	332
	333	irq = irq_base + i;
6a035138	334	ret = irq_set_chip(irq, &ipu_irq_chip);
5296b56d GL	335	if (ret < 0)
5296b56d GL	336	return ret;
6a035138	337	ret = irq_set_chip_data(irq, irq_map + i);
5296b56d GL	338	if (ret < 0)
	339	return ret;
	340	irq_map[i].ipu = ipu;
	341	irq_map[i].irq = irq;
	342	irq_map[i].source = -EINVAL;
6a035138	343	irq_set_handler(irq, handle_level_irq);
2f27b81c	344	irq_clear_status_flags(irq, IRQ_NOREQUEST \| IRQ_NOPROBE);
5296b56d GL	345	}
5296b56d GL	346
3d8cc000	347	irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu);
5296b56d	348
3d8cc000	349	irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu);
5296b56d	350
88289c80 SG	351	ipu->irq_base = irq_base;
88289c80 SG	352
5296b56d GL	353	return 0;
	354	}
	355
	356	void ipu_irq_detach_irq(struct ipu ipu, struct platform_device dev)
	357	{
5296b56d GL	358	unsigned int irq, irq_base;
5296b56d GL	359
88289c80	360	irq_base = ipu->irq_base;
5296b56d	361
d7fdb356	362	irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL);
5296b56d	363
d7fdb356	364	irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
5296b56d GL	365
5296b56d GL	366	for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) {
2f27b81c	367	irq_set_status_flags(irq, IRQ_NOREQUEST);
6a035138 TG	368	irq_set_chip(irq, NULL);
6a035138 TG	369	irq_set_chip_data(irq, NULL);
5296b56d GL	370	}
5296b56d GL	371	}