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c8acd6aa ZG |
1 | /* |
2 | * Copyright 2012 Marvell International Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
7331205a | 8 | #include <linux/err.h> |
c8acd6aa ZG |
9 | #include <linux/module.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/platform_data/mmp_dma.h> | |
19 | #include <linux/dmapool.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/of.h> | |
13b3006b | 22 | #include <linux/dma/mmp-pdma.h> |
c8acd6aa ZG |
23 | |
24 | #include "dmaengine.h" | |
25 | ||
26 | #define DCSR 0x0000 | |
27 | #define DALGN 0x00a0 | |
28 | #define DINT 0x00f0 | |
29 | #define DDADR 0x0200 | |
30 | #define DSADR 0x0204 | |
31 | #define DTADR 0x0208 | |
32 | #define DCMD 0x020c | |
33 | ||
34 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | |
35 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | |
36 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | |
37 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | |
38 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | |
39 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | |
40 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | |
41 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | |
42 | ||
43 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | |
44 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | |
45 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | |
46 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | |
47 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | |
48 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | |
49 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | |
50 | ||
8b298ded DM |
51 | #define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + \ |
52 | (((n) & 0x3f) << 2)) | |
c8acd6aa ZG |
53 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ |
54 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | |
55 | ||
56 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | |
57 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | |
58 | ||
59 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | |
60 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | |
61 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | |
62 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | |
63 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | |
64 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | |
65 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | |
66 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | |
67 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | |
68 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | |
69 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | |
70 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | |
71 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | |
72 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | |
73 | ||
74 | #define PDMA_ALIGNMENT 3 | |
1ac0e845 | 75 | #define PDMA_MAX_DESC_BYTES DCMD_LENGTH |
c8acd6aa ZG |
76 | |
77 | struct mmp_pdma_desc_hw { | |
78 | u32 ddadr; /* Points to the next descriptor + flags */ | |
79 | u32 dsadr; /* DSADR value for the current transfer */ | |
80 | u32 dtadr; /* DTADR value for the current transfer */ | |
81 | u32 dcmd; /* DCMD value for the current transfer */ | |
82 | } __aligned(32); | |
83 | ||
84 | struct mmp_pdma_desc_sw { | |
85 | struct mmp_pdma_desc_hw desc; | |
86 | struct list_head node; | |
87 | struct list_head tx_list; | |
88 | struct dma_async_tx_descriptor async_tx; | |
89 | }; | |
90 | ||
91 | struct mmp_pdma_phy; | |
92 | ||
93 | struct mmp_pdma_chan { | |
94 | struct device *dev; | |
95 | struct dma_chan chan; | |
96 | struct dma_async_tx_descriptor desc; | |
97 | struct mmp_pdma_phy *phy; | |
98 | enum dma_transfer_direction dir; | |
99 | ||
100 | /* channel's basic info */ | |
101 | struct tasklet_struct tasklet; | |
102 | u32 dcmd; | |
103 | u32 drcmr; | |
104 | u32 dev_addr; | |
105 | ||
106 | /* list for desc */ | |
107 | spinlock_t desc_lock; /* Descriptor list lock */ | |
108 | struct list_head chain_pending; /* Link descriptors queue for pending */ | |
109 | struct list_head chain_running; /* Link descriptors queue for running */ | |
110 | bool idle; /* channel statue machine */ | |
111 | ||
112 | struct dma_pool *desc_pool; /* Descriptors pool */ | |
113 | }; | |
114 | ||
115 | struct mmp_pdma_phy { | |
116 | int idx; | |
117 | void __iomem *base; | |
118 | struct mmp_pdma_chan *vchan; | |
119 | }; | |
120 | ||
121 | struct mmp_pdma_device { | |
122 | int dma_channels; | |
123 | void __iomem *base; | |
124 | struct device *dev; | |
125 | struct dma_device device; | |
126 | struct mmp_pdma_phy *phy; | |
027f28b7 | 127 | spinlock_t phy_lock; /* protect alloc/free phy channels */ |
c8acd6aa ZG |
128 | }; |
129 | ||
130 | #define tx_to_mmp_pdma_desc(tx) container_of(tx, struct mmp_pdma_desc_sw, async_tx) | |
131 | #define to_mmp_pdma_desc(lh) container_of(lh, struct mmp_pdma_desc_sw, node) | |
132 | #define to_mmp_pdma_chan(dchan) container_of(dchan, struct mmp_pdma_chan, chan) | |
133 | #define to_mmp_pdma_dev(dmadev) container_of(dmadev, struct mmp_pdma_device, device) | |
134 | ||
135 | static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr) | |
136 | { | |
137 | u32 reg = (phy->idx << 4) + DDADR; | |
138 | ||
139 | writel(addr, phy->base + reg); | |
140 | } | |
141 | ||
142 | static void enable_chan(struct mmp_pdma_phy *phy) | |
143 | { | |
144 | u32 reg; | |
145 | ||
146 | if (!phy->vchan) | |
147 | return; | |
148 | ||
8b298ded | 149 | reg = DRCMR(phy->vchan->drcmr); |
c8acd6aa ZG |
150 | writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); |
151 | ||
152 | reg = (phy->idx << 2) + DCSR; | |
153 | writel(readl(phy->base + reg) | DCSR_RUN, | |
154 | phy->base + reg); | |
155 | } | |
156 | ||
157 | static void disable_chan(struct mmp_pdma_phy *phy) | |
158 | { | |
159 | u32 reg; | |
160 | ||
161 | if (phy) { | |
162 | reg = (phy->idx << 2) + DCSR; | |
163 | writel(readl(phy->base + reg) & ~DCSR_RUN, | |
164 | phy->base + reg); | |
165 | } | |
166 | } | |
167 | ||
168 | static int clear_chan_irq(struct mmp_pdma_phy *phy) | |
169 | { | |
170 | u32 dcsr; | |
171 | u32 dint = readl(phy->base + DINT); | |
172 | u32 reg = (phy->idx << 2) + DCSR; | |
173 | ||
174 | if (dint & BIT(phy->idx)) { | |
175 | /* clear irq */ | |
176 | dcsr = readl(phy->base + reg); | |
177 | writel(dcsr, phy->base + reg); | |
178 | if ((dcsr & DCSR_BUSERR) && (phy->vchan)) | |
179 | dev_warn(phy->vchan->dev, "DCSR_BUSERR\n"); | |
180 | return 0; | |
181 | } | |
182 | return -EAGAIN; | |
183 | } | |
184 | ||
185 | static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id) | |
186 | { | |
187 | struct mmp_pdma_phy *phy = dev_id; | |
188 | ||
189 | if (clear_chan_irq(phy) == 0) { | |
190 | tasklet_schedule(&phy->vchan->tasklet); | |
191 | return IRQ_HANDLED; | |
192 | } else | |
193 | return IRQ_NONE; | |
194 | } | |
195 | ||
196 | static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id) | |
197 | { | |
198 | struct mmp_pdma_device *pdev = dev_id; | |
199 | struct mmp_pdma_phy *phy; | |
200 | u32 dint = readl(pdev->base + DINT); | |
201 | int i, ret; | |
202 | int irq_num = 0; | |
203 | ||
204 | while (dint) { | |
205 | i = __ffs(dint); | |
206 | dint &= (dint - 1); | |
207 | phy = &pdev->phy[i]; | |
208 | ret = mmp_pdma_chan_handler(irq, phy); | |
209 | if (ret == IRQ_HANDLED) | |
210 | irq_num++; | |
211 | } | |
212 | ||
213 | if (irq_num) | |
214 | return IRQ_HANDLED; | |
215 | else | |
216 | return IRQ_NONE; | |
217 | } | |
218 | ||
219 | /* lookup free phy channel as descending priority */ | |
220 | static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan) | |
221 | { | |
222 | int prio, i; | |
223 | struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); | |
638a542c | 224 | struct mmp_pdma_phy *phy, *found = NULL; |
027f28b7 | 225 | unsigned long flags; |
c8acd6aa ZG |
226 | |
227 | /* | |
228 | * dma channel priorities | |
229 | * ch 0 - 3, 16 - 19 <--> (0) | |
230 | * ch 4 - 7, 20 - 23 <--> (1) | |
231 | * ch 8 - 11, 24 - 27 <--> (2) | |
232 | * ch 12 - 15, 28 - 31 <--> (3) | |
233 | */ | |
027f28b7 XW |
234 | |
235 | spin_lock_irqsave(&pdev->phy_lock, flags); | |
c8acd6aa ZG |
236 | for (prio = 0; prio <= (((pdev->dma_channels - 1) & 0xf) >> 2); prio++) { |
237 | for (i = 0; i < pdev->dma_channels; i++) { | |
238 | if (prio != ((i & 0xf) >> 2)) | |
239 | continue; | |
240 | phy = &pdev->phy[i]; | |
241 | if (!phy->vchan) { | |
242 | phy->vchan = pchan; | |
638a542c DM |
243 | found = phy; |
244 | goto out_unlock; | |
c8acd6aa ZG |
245 | } |
246 | } | |
247 | } | |
248 | ||
638a542c | 249 | out_unlock: |
027f28b7 | 250 | spin_unlock_irqrestore(&pdev->phy_lock, flags); |
638a542c | 251 | return found; |
c8acd6aa ZG |
252 | } |
253 | ||
027f28b7 XW |
254 | static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) |
255 | { | |
256 | struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); | |
257 | unsigned long flags; | |
26a2dfde | 258 | u32 reg; |
027f28b7 XW |
259 | |
260 | if (!pchan->phy) | |
261 | return; | |
262 | ||
26a2dfde | 263 | /* clear the channel mapping in DRCMR */ |
8b298ded | 264 | reg = DRCMR(pchan->phy->vchan->drcmr); |
26a2dfde XW |
265 | writel(0, pchan->phy->base + reg); |
266 | ||
027f28b7 XW |
267 | spin_lock_irqsave(&pdev->phy_lock, flags); |
268 | pchan->phy->vchan = NULL; | |
269 | pchan->phy = NULL; | |
270 | spin_unlock_irqrestore(&pdev->phy_lock, flags); | |
271 | } | |
272 | ||
c8acd6aa ZG |
273 | /* desc->tx_list ==> pending list */ |
274 | static void append_pending_queue(struct mmp_pdma_chan *chan, | |
275 | struct mmp_pdma_desc_sw *desc) | |
276 | { | |
277 | struct mmp_pdma_desc_sw *tail = | |
278 | to_mmp_pdma_desc(chan->chain_pending.prev); | |
279 | ||
280 | if (list_empty(&chan->chain_pending)) | |
281 | goto out_splice; | |
282 | ||
283 | /* one irq per queue, even appended */ | |
284 | tail->desc.ddadr = desc->async_tx.phys; | |
285 | tail->desc.dcmd &= ~DCMD_ENDIRQEN; | |
286 | ||
287 | /* softly link to pending list */ | |
288 | out_splice: | |
289 | list_splice_tail_init(&desc->tx_list, &chan->chain_pending); | |
290 | } | |
291 | ||
292 | /** | |
293 | * start_pending_queue - transfer any pending transactions | |
294 | * pending list ==> running list | |
295 | */ | |
296 | static void start_pending_queue(struct mmp_pdma_chan *chan) | |
297 | { | |
298 | struct mmp_pdma_desc_sw *desc; | |
299 | ||
300 | /* still in running, irq will start the pending list */ | |
301 | if (!chan->idle) { | |
302 | dev_dbg(chan->dev, "DMA controller still busy\n"); | |
303 | return; | |
304 | } | |
305 | ||
306 | if (list_empty(&chan->chain_pending)) { | |
307 | /* chance to re-fetch phy channel with higher prio */ | |
027f28b7 | 308 | mmp_pdma_free_phy(chan); |
c8acd6aa ZG |
309 | dev_dbg(chan->dev, "no pending list\n"); |
310 | return; | |
311 | } | |
312 | ||
313 | if (!chan->phy) { | |
314 | chan->phy = lookup_phy(chan); | |
315 | if (!chan->phy) { | |
316 | dev_dbg(chan->dev, "no free dma channel\n"); | |
317 | return; | |
318 | } | |
319 | } | |
320 | ||
321 | /* | |
322 | * pending -> running | |
323 | * reintilize pending list | |
324 | */ | |
325 | desc = list_first_entry(&chan->chain_pending, | |
326 | struct mmp_pdma_desc_sw, node); | |
327 | list_splice_tail_init(&chan->chain_pending, &chan->chain_running); | |
328 | ||
329 | /* | |
330 | * Program the descriptor's address into the DMA controller, | |
331 | * then start the DMA transaction | |
332 | */ | |
333 | set_desc(chan->phy, desc->async_tx.phys); | |
334 | enable_chan(chan->phy); | |
335 | chan->idle = false; | |
336 | } | |
337 | ||
338 | ||
339 | /* desc->tx_list ==> pending list */ | |
340 | static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
341 | { | |
342 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan); | |
343 | struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx); | |
344 | struct mmp_pdma_desc_sw *child; | |
345 | unsigned long flags; | |
346 | dma_cookie_t cookie = -EBUSY; | |
347 | ||
348 | spin_lock_irqsave(&chan->desc_lock, flags); | |
349 | ||
350 | list_for_each_entry(child, &desc->tx_list, node) { | |
351 | cookie = dma_cookie_assign(&child->async_tx); | |
352 | } | |
353 | ||
354 | append_pending_queue(chan, desc); | |
355 | ||
356 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
357 | ||
358 | return cookie; | |
359 | } | |
360 | ||
69c9f0ae JH |
361 | static struct mmp_pdma_desc_sw * |
362 | mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan) | |
c8acd6aa ZG |
363 | { |
364 | struct mmp_pdma_desc_sw *desc; | |
365 | dma_addr_t pdesc; | |
366 | ||
367 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
368 | if (!desc) { | |
369 | dev_err(chan->dev, "out of memory for link descriptor\n"); | |
370 | return NULL; | |
371 | } | |
372 | ||
373 | memset(desc, 0, sizeof(*desc)); | |
374 | INIT_LIST_HEAD(&desc->tx_list); | |
375 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan); | |
376 | /* each desc has submit */ | |
377 | desc->async_tx.tx_submit = mmp_pdma_tx_submit; | |
378 | desc->async_tx.phys = pdesc; | |
379 | ||
380 | return desc; | |
381 | } | |
382 | ||
383 | /** | |
384 | * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel. | |
385 | * | |
386 | * This function will create a dma pool for descriptor allocation. | |
387 | * Request irq only when channel is requested | |
388 | * Return - The number of allocated descriptors. | |
389 | */ | |
390 | ||
391 | static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan) | |
392 | { | |
393 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); | |
394 | ||
395 | if (chan->desc_pool) | |
396 | return 1; | |
397 | ||
398 | chan->desc_pool = | |
399 | dma_pool_create(dev_name(&dchan->dev->device), chan->dev, | |
400 | sizeof(struct mmp_pdma_desc_sw), | |
401 | __alignof__(struct mmp_pdma_desc_sw), 0); | |
402 | if (!chan->desc_pool) { | |
403 | dev_err(chan->dev, "unable to allocate descriptor pool\n"); | |
404 | return -ENOMEM; | |
405 | } | |
027f28b7 | 406 | mmp_pdma_free_phy(chan); |
c8acd6aa ZG |
407 | chan->idle = true; |
408 | chan->dev_addr = 0; | |
409 | return 1; | |
410 | } | |
411 | ||
412 | static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan, | |
413 | struct list_head *list) | |
414 | { | |
415 | struct mmp_pdma_desc_sw *desc, *_desc; | |
416 | ||
417 | list_for_each_entry_safe(desc, _desc, list, node) { | |
418 | list_del(&desc->node); | |
419 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
420 | } | |
421 | } | |
422 | ||
423 | static void mmp_pdma_free_chan_resources(struct dma_chan *dchan) | |
424 | { | |
425 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); | |
426 | unsigned long flags; | |
427 | ||
428 | spin_lock_irqsave(&chan->desc_lock, flags); | |
429 | mmp_pdma_free_desc_list(chan, &chan->chain_pending); | |
430 | mmp_pdma_free_desc_list(chan, &chan->chain_running); | |
431 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
432 | ||
433 | dma_pool_destroy(chan->desc_pool); | |
434 | chan->desc_pool = NULL; | |
435 | chan->idle = true; | |
436 | chan->dev_addr = 0; | |
027f28b7 | 437 | mmp_pdma_free_phy(chan); |
c8acd6aa ZG |
438 | return; |
439 | } | |
440 | ||
441 | static struct dma_async_tx_descriptor * | |
442 | mmp_pdma_prep_memcpy(struct dma_chan *dchan, | |
443 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
444 | size_t len, unsigned long flags) | |
445 | { | |
446 | struct mmp_pdma_chan *chan; | |
447 | struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new; | |
448 | size_t copy = 0; | |
449 | ||
450 | if (!dchan) | |
451 | return NULL; | |
452 | ||
453 | if (!len) | |
454 | return NULL; | |
455 | ||
456 | chan = to_mmp_pdma_chan(dchan); | |
457 | ||
458 | if (!chan->dir) { | |
459 | chan->dir = DMA_MEM_TO_MEM; | |
460 | chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR; | |
461 | chan->dcmd |= DCMD_BURST32; | |
462 | } | |
463 | ||
464 | do { | |
465 | /* Allocate the link descriptor from DMA pool */ | |
466 | new = mmp_pdma_alloc_descriptor(chan); | |
467 | if (!new) { | |
468 | dev_err(chan->dev, "no memory for desc\n"); | |
469 | goto fail; | |
470 | } | |
471 | ||
472 | copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); | |
473 | ||
474 | new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy); | |
475 | new->desc.dsadr = dma_src; | |
476 | new->desc.dtadr = dma_dst; | |
477 | ||
478 | if (!first) | |
479 | first = new; | |
480 | else | |
481 | prev->desc.ddadr = new->async_tx.phys; | |
482 | ||
483 | new->async_tx.cookie = 0; | |
484 | async_tx_ack(&new->async_tx); | |
485 | ||
486 | prev = new; | |
487 | len -= copy; | |
488 | ||
489 | if (chan->dir == DMA_MEM_TO_DEV) { | |
490 | dma_src += copy; | |
491 | } else if (chan->dir == DMA_DEV_TO_MEM) { | |
492 | dma_dst += copy; | |
493 | } else if (chan->dir == DMA_MEM_TO_MEM) { | |
494 | dma_src += copy; | |
495 | dma_dst += copy; | |
496 | } | |
497 | ||
498 | /* Insert the link descriptor to the LD ring */ | |
499 | list_add_tail(&new->node, &first->tx_list); | |
500 | } while (len); | |
501 | ||
502 | first->async_tx.flags = flags; /* client is in control of this ack */ | |
503 | first->async_tx.cookie = -EBUSY; | |
504 | ||
505 | /* last desc and fire IRQ */ | |
506 | new->desc.ddadr = DDADR_STOP; | |
507 | new->desc.dcmd |= DCMD_ENDIRQEN; | |
508 | ||
509 | return &first->async_tx; | |
510 | ||
511 | fail: | |
512 | if (first) | |
513 | mmp_pdma_free_desc_list(chan, &first->tx_list); | |
514 | return NULL; | |
515 | } | |
516 | ||
517 | static struct dma_async_tx_descriptor * | |
518 | mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, | |
519 | unsigned int sg_len, enum dma_transfer_direction dir, | |
520 | unsigned long flags, void *context) | |
521 | { | |
522 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); | |
523 | struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
524 | size_t len, avail; | |
525 | struct scatterlist *sg; | |
526 | dma_addr_t addr; | |
527 | int i; | |
528 | ||
529 | if ((sgl == NULL) || (sg_len == 0)) | |
530 | return NULL; | |
531 | ||
532 | for_each_sg(sgl, sg, sg_len, i) { | |
533 | addr = sg_dma_address(sg); | |
534 | avail = sg_dma_len(sgl); | |
535 | ||
536 | do { | |
537 | len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); | |
538 | ||
539 | /* allocate and populate the descriptor */ | |
540 | new = mmp_pdma_alloc_descriptor(chan); | |
541 | if (!new) { | |
542 | dev_err(chan->dev, "no memory for desc\n"); | |
543 | goto fail; | |
544 | } | |
545 | ||
546 | new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len); | |
547 | if (dir == DMA_MEM_TO_DEV) { | |
548 | new->desc.dsadr = addr; | |
549 | new->desc.dtadr = chan->dev_addr; | |
550 | } else { | |
551 | new->desc.dsadr = chan->dev_addr; | |
552 | new->desc.dtadr = addr; | |
553 | } | |
554 | ||
555 | if (!first) | |
556 | first = new; | |
557 | else | |
558 | prev->desc.ddadr = new->async_tx.phys; | |
559 | ||
560 | new->async_tx.cookie = 0; | |
561 | async_tx_ack(&new->async_tx); | |
562 | prev = new; | |
563 | ||
564 | /* Insert the link descriptor to the LD ring */ | |
565 | list_add_tail(&new->node, &first->tx_list); | |
566 | ||
567 | /* update metadata */ | |
568 | addr += len; | |
569 | avail -= len; | |
570 | } while (avail); | |
571 | } | |
572 | ||
573 | first->async_tx.cookie = -EBUSY; | |
574 | first->async_tx.flags = flags; | |
575 | ||
576 | /* last desc and fire IRQ */ | |
577 | new->desc.ddadr = DDADR_STOP; | |
578 | new->desc.dcmd |= DCMD_ENDIRQEN; | |
579 | ||
580 | return &first->async_tx; | |
581 | ||
582 | fail: | |
583 | if (first) | |
584 | mmp_pdma_free_desc_list(chan, &first->tx_list); | |
585 | return NULL; | |
586 | } | |
587 | ||
588 | static int mmp_pdma_control(struct dma_chan *dchan, enum dma_ctrl_cmd cmd, | |
589 | unsigned long arg) | |
590 | { | |
591 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); | |
592 | struct dma_slave_config *cfg = (void *)arg; | |
593 | unsigned long flags; | |
594 | int ret = 0; | |
595 | u32 maxburst = 0, addr = 0; | |
596 | enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
597 | ||
598 | if (!dchan) | |
599 | return -EINVAL; | |
600 | ||
601 | switch (cmd) { | |
602 | case DMA_TERMINATE_ALL: | |
603 | disable_chan(chan->phy); | |
027f28b7 | 604 | mmp_pdma_free_phy(chan); |
c8acd6aa ZG |
605 | spin_lock_irqsave(&chan->desc_lock, flags); |
606 | mmp_pdma_free_desc_list(chan, &chan->chain_pending); | |
607 | mmp_pdma_free_desc_list(chan, &chan->chain_running); | |
608 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
609 | chan->idle = true; | |
610 | break; | |
611 | case DMA_SLAVE_CONFIG: | |
612 | if (cfg->direction == DMA_DEV_TO_MEM) { | |
613 | chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; | |
614 | maxburst = cfg->src_maxburst; | |
615 | width = cfg->src_addr_width; | |
616 | addr = cfg->src_addr; | |
617 | } else if (cfg->direction == DMA_MEM_TO_DEV) { | |
618 | chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; | |
619 | maxburst = cfg->dst_maxburst; | |
620 | width = cfg->dst_addr_width; | |
621 | addr = cfg->dst_addr; | |
622 | } | |
623 | ||
624 | if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) | |
625 | chan->dcmd |= DCMD_WIDTH1; | |
626 | else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) | |
627 | chan->dcmd |= DCMD_WIDTH2; | |
628 | else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES) | |
629 | chan->dcmd |= DCMD_WIDTH4; | |
630 | ||
631 | if (maxburst == 8) | |
632 | chan->dcmd |= DCMD_BURST8; | |
633 | else if (maxburst == 16) | |
634 | chan->dcmd |= DCMD_BURST16; | |
635 | else if (maxburst == 32) | |
636 | chan->dcmd |= DCMD_BURST32; | |
637 | ||
ed30933e | 638 | chan->dir = cfg->direction; |
c8acd6aa | 639 | chan->dev_addr = addr; |
13b3006b DM |
640 | /* FIXME: drivers should be ported over to use the filter |
641 | * function. Once that's done, the following two lines can | |
642 | * be removed. | |
643 | */ | |
644 | if (cfg->slave_id) | |
645 | chan->drcmr = cfg->slave_id; | |
c8acd6aa ZG |
646 | break; |
647 | default: | |
648 | return -ENOSYS; | |
649 | } | |
650 | ||
651 | return ret; | |
652 | } | |
653 | ||
654 | static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan, | |
655 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
656 | { | |
4aa9fe0a | 657 | return dma_cookie_status(dchan, cookie, txstate); |
c8acd6aa ZG |
658 | } |
659 | ||
660 | /** | |
661 | * mmp_pdma_issue_pending - Issue the DMA start command | |
662 | * pending list ==> running list | |
663 | */ | |
664 | static void mmp_pdma_issue_pending(struct dma_chan *dchan) | |
665 | { | |
666 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); | |
667 | unsigned long flags; | |
668 | ||
669 | spin_lock_irqsave(&chan->desc_lock, flags); | |
670 | start_pending_queue(chan); | |
671 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
672 | } | |
673 | ||
674 | /* | |
675 | * dma_do_tasklet | |
676 | * Do call back | |
677 | * Start pending list | |
678 | */ | |
679 | static void dma_do_tasklet(unsigned long data) | |
680 | { | |
681 | struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data; | |
682 | struct mmp_pdma_desc_sw *desc, *_desc; | |
683 | LIST_HEAD(chain_cleanup); | |
684 | unsigned long flags; | |
685 | ||
686 | /* submit pending list; callback for each desc; free desc */ | |
687 | ||
688 | spin_lock_irqsave(&chan->desc_lock, flags); | |
689 | ||
690 | /* update the cookie if we have some descriptors to cleanup */ | |
691 | if (!list_empty(&chan->chain_running)) { | |
692 | dma_cookie_t cookie; | |
693 | ||
694 | desc = to_mmp_pdma_desc(chan->chain_running.prev); | |
695 | cookie = desc->async_tx.cookie; | |
696 | dma_cookie_complete(&desc->async_tx); | |
697 | ||
698 | dev_dbg(chan->dev, "completed_cookie=%d\n", cookie); | |
699 | } | |
700 | ||
701 | /* | |
702 | * move the descriptors to a temporary list so we can drop the lock | |
703 | * during the entire cleanup operation | |
704 | */ | |
705 | list_splice_tail_init(&chan->chain_running, &chain_cleanup); | |
706 | ||
707 | /* the hardware is now idle and ready for more */ | |
708 | chan->idle = true; | |
709 | ||
710 | /* Start any pending transactions automatically */ | |
711 | start_pending_queue(chan); | |
712 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
713 | ||
714 | /* Run the callback for each descriptor, in order */ | |
715 | list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) { | |
716 | struct dma_async_tx_descriptor *txd = &desc->async_tx; | |
717 | ||
718 | /* Remove from the list of transactions */ | |
719 | list_del(&desc->node); | |
720 | /* Run the link descriptor callback function */ | |
721 | if (txd->callback) | |
722 | txd->callback(txd->callback_param); | |
723 | ||
724 | dma_pool_free(chan->desc_pool, desc, txd->phys); | |
725 | } | |
726 | } | |
727 | ||
4bf27b8b | 728 | static int mmp_pdma_remove(struct platform_device *op) |
c8acd6aa ZG |
729 | { |
730 | struct mmp_pdma_device *pdev = platform_get_drvdata(op); | |
731 | ||
732 | dma_async_device_unregister(&pdev->device); | |
733 | return 0; | |
734 | } | |
735 | ||
463a1f8b | 736 | static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, |
c8acd6aa ZG |
737 | int idx, int irq) |
738 | { | |
739 | struct mmp_pdma_phy *phy = &pdev->phy[idx]; | |
740 | struct mmp_pdma_chan *chan; | |
741 | int ret; | |
742 | ||
743 | chan = devm_kzalloc(pdev->dev, | |
744 | sizeof(struct mmp_pdma_chan), GFP_KERNEL); | |
745 | if (chan == NULL) | |
746 | return -ENOMEM; | |
747 | ||
748 | phy->idx = idx; | |
749 | phy->base = pdev->base; | |
750 | ||
751 | if (irq) { | |
752 | ret = devm_request_irq(pdev->dev, irq, | |
753 | mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy); | |
754 | if (ret) { | |
755 | dev_err(pdev->dev, "channel request irq fail!\n"); | |
756 | return ret; | |
757 | } | |
758 | } | |
759 | ||
760 | spin_lock_init(&chan->desc_lock); | |
761 | chan->dev = pdev->dev; | |
762 | chan->chan.device = &pdev->device; | |
763 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
764 | INIT_LIST_HEAD(&chan->chain_pending); | |
765 | INIT_LIST_HEAD(&chan->chain_running); | |
766 | ||
767 | /* register virt channel to dma engine */ | |
768 | list_add_tail(&chan->chan.device_node, | |
769 | &pdev->device.channels); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static struct of_device_id mmp_pdma_dt_ids[] = { | |
775 | { .compatible = "marvell,pdma-1.0", }, | |
776 | {} | |
777 | }; | |
778 | MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids); | |
779 | ||
463a1f8b | 780 | static int mmp_pdma_probe(struct platform_device *op) |
c8acd6aa ZG |
781 | { |
782 | struct mmp_pdma_device *pdev; | |
783 | const struct of_device_id *of_id; | |
784 | struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); | |
785 | struct resource *iores; | |
786 | int i, ret, irq = 0; | |
787 | int dma_channels = 0, irq_num = 0; | |
788 | ||
789 | pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); | |
790 | if (!pdev) | |
791 | return -ENOMEM; | |
792 | pdev->dev = &op->dev; | |
793 | ||
027f28b7 XW |
794 | spin_lock_init(&pdev->phy_lock); |
795 | ||
c8acd6aa ZG |
796 | iores = platform_get_resource(op, IORESOURCE_MEM, 0); |
797 | if (!iores) | |
798 | return -EINVAL; | |
799 | ||
7331205a TR |
800 | pdev->base = devm_ioremap_resource(pdev->dev, iores); |
801 | if (IS_ERR(pdev->base)) | |
802 | return PTR_ERR(pdev->base); | |
c8acd6aa ZG |
803 | |
804 | of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev); | |
805 | if (of_id) | |
806 | of_property_read_u32(pdev->dev->of_node, | |
807 | "#dma-channels", &dma_channels); | |
808 | else if (pdata && pdata->dma_channels) | |
809 | dma_channels = pdata->dma_channels; | |
810 | else | |
811 | dma_channels = 32; /* default 32 channel */ | |
812 | pdev->dma_channels = dma_channels; | |
813 | ||
814 | for (i = 0; i < dma_channels; i++) { | |
815 | if (platform_get_irq(op, i) > 0) | |
816 | irq_num++; | |
817 | } | |
818 | ||
819 | pdev->phy = devm_kzalloc(pdev->dev, | |
820 | dma_channels * sizeof(struct mmp_pdma_chan), GFP_KERNEL); | |
821 | if (pdev->phy == NULL) | |
822 | return -ENOMEM; | |
823 | ||
824 | INIT_LIST_HEAD(&pdev->device.channels); | |
825 | ||
826 | if (irq_num != dma_channels) { | |
827 | /* all chan share one irq, demux inside */ | |
828 | irq = platform_get_irq(op, 0); | |
829 | ret = devm_request_irq(pdev->dev, irq, | |
830 | mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev); | |
831 | if (ret) | |
832 | return ret; | |
833 | } | |
834 | ||
835 | for (i = 0; i < dma_channels; i++) { | |
836 | irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i); | |
837 | ret = mmp_pdma_chan_init(pdev, i, irq); | |
838 | if (ret) | |
839 | return ret; | |
840 | } | |
841 | ||
842 | dma_cap_set(DMA_SLAVE, pdev->device.cap_mask); | |
843 | dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask); | |
844 | dma_cap_set(DMA_SLAVE, pdev->device.cap_mask); | |
845 | pdev->device.dev = &op->dev; | |
846 | pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources; | |
847 | pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources; | |
848 | pdev->device.device_tx_status = mmp_pdma_tx_status; | |
849 | pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy; | |
850 | pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg; | |
851 | pdev->device.device_issue_pending = mmp_pdma_issue_pending; | |
852 | pdev->device.device_control = mmp_pdma_control; | |
853 | pdev->device.copy_align = PDMA_ALIGNMENT; | |
854 | ||
855 | if (pdev->dev->coherent_dma_mask) | |
856 | dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask); | |
857 | else | |
858 | dma_set_mask(pdev->dev, DMA_BIT_MASK(64)); | |
859 | ||
860 | ret = dma_async_device_register(&pdev->device); | |
861 | if (ret) { | |
862 | dev_err(pdev->device.dev, "unable to register\n"); | |
863 | return ret; | |
864 | } | |
865 | ||
866 | dev_info(pdev->device.dev, "initialized\n"); | |
867 | return 0; | |
868 | } | |
869 | ||
870 | static const struct platform_device_id mmp_pdma_id_table[] = { | |
871 | { "mmp-pdma", }, | |
872 | { }, | |
873 | }; | |
874 | ||
875 | static struct platform_driver mmp_pdma_driver = { | |
876 | .driver = { | |
877 | .name = "mmp-pdma", | |
878 | .owner = THIS_MODULE, | |
879 | .of_match_table = mmp_pdma_dt_ids, | |
880 | }, | |
881 | .id_table = mmp_pdma_id_table, | |
882 | .probe = mmp_pdma_probe, | |
a7d6e3ec | 883 | .remove = mmp_pdma_remove, |
c8acd6aa ZG |
884 | }; |
885 | ||
13b3006b DM |
886 | bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param) |
887 | { | |
888 | struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan); | |
889 | ||
890 | if (chan->device->dev->driver != &mmp_pdma_driver.driver) | |
891 | return false; | |
892 | ||
893 | c->drcmr = *(unsigned int *) param; | |
894 | ||
895 | return true; | |
896 | } | |
897 | EXPORT_SYMBOL_GPL(mmp_pdma_filter_fn); | |
898 | ||
c8acd6aa ZG |
899 | module_platform_driver(mmp_pdma_driver); |
900 | ||
901 | MODULE_DESCRIPTION("MARVELL MMP Periphera DMA Driver"); | |
902 | MODULE_AUTHOR("Marvell International Ltd."); | |
903 | MODULE_LICENSE("GPL v2"); |