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c6da0ba8 ZG |
1 | /* |
2 | * Driver For Marvell Two-channel DMA Engine | |
3 | * | |
4 | * Copyright: Marvell International Ltd. | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/dmaengine.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/device.h> | |
21 | #include <mach/regs-icu.h> | |
293b2da1 | 22 | #include <linux/platform_data/dma-mmp_tdma.h> |
f1a77570 | 23 | #include <linux/of_device.h> |
c6da0ba8 ZG |
24 | |
25 | #include "dmaengine.h" | |
26 | ||
27 | /* | |
28 | * Two-Channel DMA registers | |
29 | */ | |
30 | #define TDBCR 0x00 /* Byte Count */ | |
31 | #define TDSAR 0x10 /* Src Addr */ | |
32 | #define TDDAR 0x20 /* Dst Addr */ | |
33 | #define TDNDPR 0x30 /* Next Desc */ | |
34 | #define TDCR 0x40 /* Control */ | |
35 | #define TDCP 0x60 /* Priority*/ | |
36 | #define TDCDPR 0x70 /* Current Desc */ | |
37 | #define TDIMR 0x80 /* Int Mask */ | |
38 | #define TDISR 0xa0 /* Int Status */ | |
39 | ||
40 | /* Two-Channel DMA Control Register */ | |
41 | #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ | |
42 | #define TDCR_SSZ_12_BITS (0x1 << 22) | |
43 | #define TDCR_SSZ_16_BITS (0x2 << 22) | |
44 | #define TDCR_SSZ_20_BITS (0x3 << 22) | |
45 | #define TDCR_SSZ_24_BITS (0x4 << 22) | |
46 | #define TDCR_SSZ_32_BITS (0x5 << 22) | |
47 | #define TDCR_SSZ_SHIFT (0x1 << 22) | |
48 | #define TDCR_SSZ_MASK (0x7 << 22) | |
49 | #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ | |
50 | #define TDCR_ABR (0x1 << 20) /* Channel Abort */ | |
51 | #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ | |
52 | #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ | |
53 | #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ | |
54 | #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ | |
55 | #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ | |
56 | #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ | |
57 | #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ | |
58 | #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ | |
59 | #define TDCR_BURSTSZ_4B (0x0 << 6) | |
60 | #define TDCR_BURSTSZ_8B (0x1 << 6) | |
61 | #define TDCR_BURSTSZ_16B (0x3 << 6) | |
62 | #define TDCR_BURSTSZ_32B (0x6 << 6) | |
63 | #define TDCR_BURSTSZ_64B (0x7 << 6) | |
64 | #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) | |
65 | #define TDCR_BURSTSZ_128B (0x5 << 6) | |
66 | #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ | |
67 | #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ | |
68 | #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ | |
69 | #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ | |
70 | #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ | |
71 | #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ | |
72 | #define TDCR_DSTDESCCONT (0x1 << 1) | |
73 | #define TDCR_SRCDESTCONT (0x1 << 0) | |
74 | ||
75 | /* Two-Channel DMA Int Mask Register */ | |
76 | #define TDIMR_COMP (0x1 << 0) | |
77 | ||
78 | /* Two-Channel DMA Int Status Register */ | |
79 | #define TDISR_COMP (0x1 << 0) | |
80 | ||
81 | /* | |
82 | * Two-Channel DMA Descriptor Struct | |
83 | * NOTE: desc's buf must be aligned to 16 bytes. | |
84 | */ | |
85 | struct mmp_tdma_desc { | |
86 | u32 byte_cnt; | |
87 | u32 src_addr; | |
88 | u32 dst_addr; | |
89 | u32 nxt_desc; | |
90 | }; | |
91 | ||
92 | enum mmp_tdma_type { | |
93 | MMP_AUD_TDMA = 0, | |
94 | PXA910_SQU, | |
95 | }; | |
96 | ||
97 | #define TDMA_ALIGNMENT 3 | |
98 | #define TDMA_MAX_XFER_BYTES SZ_64K | |
99 | ||
100 | struct mmp_tdma_chan { | |
101 | struct device *dev; | |
102 | struct dma_chan chan; | |
103 | struct dma_async_tx_descriptor desc; | |
104 | struct tasklet_struct tasklet; | |
105 | ||
106 | struct mmp_tdma_desc *desc_arr; | |
107 | phys_addr_t desc_arr_phys; | |
108 | int desc_num; | |
109 | enum dma_transfer_direction dir; | |
110 | dma_addr_t dev_addr; | |
111 | u32 burst_sz; | |
112 | enum dma_slave_buswidth buswidth; | |
113 | enum dma_status status; | |
114 | ||
115 | int idx; | |
116 | enum mmp_tdma_type type; | |
117 | int irq; | |
118 | unsigned long reg_base; | |
119 | ||
120 | size_t buf_len; | |
121 | size_t period_len; | |
122 | size_t pos; | |
123 | }; | |
124 | ||
125 | #define TDMA_CHANNEL_NUM 2 | |
126 | struct mmp_tdma_device { | |
127 | struct device *dev; | |
128 | void __iomem *base; | |
129 | struct dma_device device; | |
130 | struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; | |
c6da0ba8 ZG |
131 | }; |
132 | ||
133 | #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) | |
134 | ||
135 | static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) | |
136 | { | |
137 | writel(phys, tdmac->reg_base + TDNDPR); | |
138 | writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, | |
139 | tdmac->reg_base + TDCR); | |
140 | } | |
141 | ||
142 | static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) | |
143 | { | |
144 | /* enable irq */ | |
145 | writel(TDIMR_COMP, tdmac->reg_base + TDIMR); | |
146 | /* enable dma chan */ | |
147 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, | |
148 | tdmac->reg_base + TDCR); | |
149 | tdmac->status = DMA_IN_PROGRESS; | |
150 | } | |
151 | ||
152 | static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac) | |
153 | { | |
154 | writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, | |
155 | tdmac->reg_base + TDCR); | |
156 | tdmac->status = DMA_SUCCESS; | |
157 | } | |
158 | ||
159 | static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac) | |
160 | { | |
161 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, | |
162 | tdmac->reg_base + TDCR); | |
163 | tdmac->status = DMA_IN_PROGRESS; | |
164 | } | |
165 | ||
166 | static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac) | |
167 | { | |
168 | writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, | |
169 | tdmac->reg_base + TDCR); | |
170 | tdmac->status = DMA_PAUSED; | |
171 | } | |
172 | ||
173 | static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) | |
174 | { | |
175 | unsigned int tdcr; | |
176 | ||
177 | mmp_tdma_disable_chan(tdmac); | |
178 | ||
179 | if (tdmac->dir == DMA_MEM_TO_DEV) | |
180 | tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; | |
181 | else if (tdmac->dir == DMA_DEV_TO_MEM) | |
182 | tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; | |
183 | ||
184 | if (tdmac->type == MMP_AUD_TDMA) { | |
185 | tdcr |= TDCR_PACKMOD; | |
186 | ||
187 | switch (tdmac->burst_sz) { | |
188 | case 4: | |
189 | tdcr |= TDCR_BURSTSZ_4B; | |
190 | break; | |
191 | case 8: | |
192 | tdcr |= TDCR_BURSTSZ_8B; | |
193 | break; | |
194 | case 16: | |
195 | tdcr |= TDCR_BURSTSZ_16B; | |
196 | break; | |
197 | case 32: | |
198 | tdcr |= TDCR_BURSTSZ_32B; | |
199 | break; | |
200 | case 64: | |
201 | tdcr |= TDCR_BURSTSZ_64B; | |
202 | break; | |
203 | case 128: | |
204 | tdcr |= TDCR_BURSTSZ_128B; | |
205 | break; | |
206 | default: | |
207 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | |
208 | return -EINVAL; | |
209 | } | |
210 | ||
211 | switch (tdmac->buswidth) { | |
212 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
213 | tdcr |= TDCR_SSZ_8_BITS; | |
214 | break; | |
215 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
216 | tdcr |= TDCR_SSZ_16_BITS; | |
217 | break; | |
218 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
219 | tdcr |= TDCR_SSZ_32_BITS; | |
220 | break; | |
221 | default: | |
222 | dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); | |
223 | return -EINVAL; | |
224 | } | |
225 | } else if (tdmac->type == PXA910_SQU) { | |
226 | tdcr |= TDCR_BURSTSZ_SQU_32B; | |
227 | tdcr |= TDCR_SSPMOD; | |
228 | } | |
229 | ||
230 | writel(tdcr, tdmac->reg_base + TDCR); | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) | |
235 | { | |
236 | u32 reg = readl(tdmac->reg_base + TDISR); | |
237 | ||
238 | if (reg & TDISR_COMP) { | |
239 | /* clear irq */ | |
240 | reg &= ~TDISR_COMP; | |
241 | writel(reg, tdmac->reg_base + TDISR); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | return -EAGAIN; | |
246 | } | |
247 | ||
248 | static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) | |
249 | { | |
250 | struct mmp_tdma_chan *tdmac = dev_id; | |
251 | ||
252 | if (mmp_tdma_clear_chan_irq(tdmac) == 0) { | |
253 | tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len; | |
254 | tasklet_schedule(&tdmac->tasklet); | |
255 | return IRQ_HANDLED; | |
256 | } else | |
257 | return IRQ_NONE; | |
258 | } | |
259 | ||
260 | static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) | |
261 | { | |
262 | struct mmp_tdma_device *tdev = dev_id; | |
263 | int i, ret; | |
264 | int irq_num = 0; | |
265 | ||
266 | for (i = 0; i < TDMA_CHANNEL_NUM; i++) { | |
267 | struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; | |
268 | ||
269 | ret = mmp_tdma_chan_handler(irq, tdmac); | |
270 | if (ret == IRQ_HANDLED) | |
271 | irq_num++; | |
272 | } | |
273 | ||
274 | if (irq_num) | |
275 | return IRQ_HANDLED; | |
276 | else | |
277 | return IRQ_NONE; | |
278 | } | |
279 | ||
280 | static void dma_do_tasklet(unsigned long data) | |
281 | { | |
282 | struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; | |
283 | ||
284 | if (tdmac->desc.callback) | |
285 | tdmac->desc.callback(tdmac->desc.callback_param); | |
286 | ||
287 | } | |
288 | ||
289 | static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) | |
290 | { | |
291 | struct gen_pool *gpool; | |
292 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
293 | ||
294 | gpool = sram_get_gpool("asram"); | |
295 | if (tdmac->desc_arr) | |
296 | gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, | |
297 | size); | |
298 | tdmac->desc_arr = NULL; | |
299 | ||
300 | return; | |
301 | } | |
302 | ||
303 | static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
304 | { | |
305 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); | |
306 | ||
307 | mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) | |
313 | { | |
314 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
315 | int ret; | |
316 | ||
317 | dma_async_tx_descriptor_init(&tdmac->desc, chan); | |
318 | tdmac->desc.tx_submit = mmp_tdma_tx_submit; | |
319 | ||
320 | if (tdmac->irq) { | |
321 | ret = devm_request_irq(tdmac->dev, tdmac->irq, | |
322 | mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac); | |
323 | if (ret) | |
324 | return ret; | |
325 | } | |
326 | return 1; | |
327 | } | |
328 | ||
329 | static void mmp_tdma_free_chan_resources(struct dma_chan *chan) | |
330 | { | |
331 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
332 | ||
333 | if (tdmac->irq) | |
334 | devm_free_irq(tdmac->dev, tdmac->irq, tdmac); | |
335 | mmp_tdma_free_descriptor(tdmac); | |
336 | return; | |
337 | } | |
338 | ||
339 | struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) | |
340 | { | |
341 | struct gen_pool *gpool; | |
342 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
343 | ||
344 | gpool = sram_get_gpool("asram"); | |
345 | if (!gpool) | |
346 | return NULL; | |
347 | ||
348 | tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size); | |
349 | if (!tdmac->desc_arr) | |
350 | return NULL; | |
351 | ||
352 | tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool, | |
353 | (unsigned long)tdmac->desc_arr); | |
354 | ||
355 | return tdmac->desc_arr; | |
356 | } | |
357 | ||
358 | static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( | |
359 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
360 | size_t period_len, enum dma_transfer_direction direction, | |
ec8b5e48 | 361 | unsigned long flags, void *context) |
c6da0ba8 ZG |
362 | { |
363 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
364 | struct mmp_tdma_desc *desc; | |
365 | int num_periods = buf_len / period_len; | |
366 | int i = 0, buf = 0; | |
367 | ||
368 | if (tdmac->status != DMA_SUCCESS) | |
369 | return NULL; | |
370 | ||
371 | if (period_len > TDMA_MAX_XFER_BYTES) { | |
372 | dev_err(tdmac->dev, | |
373 | "maximum period size exceeded: %d > %d\n", | |
374 | period_len, TDMA_MAX_XFER_BYTES); | |
375 | goto err_out; | |
376 | } | |
377 | ||
378 | tdmac->status = DMA_IN_PROGRESS; | |
379 | tdmac->desc_num = num_periods; | |
380 | desc = mmp_tdma_alloc_descriptor(tdmac); | |
381 | if (!desc) | |
382 | goto err_out; | |
383 | ||
384 | while (buf < buf_len) { | |
385 | desc = &tdmac->desc_arr[i]; | |
386 | ||
387 | if (i + 1 == num_periods) | |
388 | desc->nxt_desc = tdmac->desc_arr_phys; | |
389 | else | |
390 | desc->nxt_desc = tdmac->desc_arr_phys + | |
391 | sizeof(*desc) * (i + 1); | |
392 | ||
393 | if (direction == DMA_MEM_TO_DEV) { | |
394 | desc->src_addr = dma_addr; | |
395 | desc->dst_addr = tdmac->dev_addr; | |
396 | } else { | |
397 | desc->src_addr = tdmac->dev_addr; | |
398 | desc->dst_addr = dma_addr; | |
399 | } | |
400 | desc->byte_cnt = period_len; | |
401 | dma_addr += period_len; | |
402 | buf += period_len; | |
403 | i++; | |
404 | } | |
405 | ||
406 | tdmac->buf_len = buf_len; | |
407 | tdmac->period_len = period_len; | |
408 | tdmac->pos = 0; | |
409 | ||
410 | return &tdmac->desc; | |
411 | ||
412 | err_out: | |
413 | tdmac->status = DMA_ERROR; | |
414 | return NULL; | |
415 | } | |
416 | ||
417 | static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
418 | unsigned long arg) | |
419 | { | |
420 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
421 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
422 | int ret = 0; | |
423 | ||
424 | switch (cmd) { | |
425 | case DMA_TERMINATE_ALL: | |
426 | mmp_tdma_disable_chan(tdmac); | |
427 | break; | |
428 | case DMA_PAUSE: | |
429 | mmp_tdma_pause_chan(tdmac); | |
430 | break; | |
431 | case DMA_RESUME: | |
432 | mmp_tdma_resume_chan(tdmac); | |
433 | break; | |
434 | case DMA_SLAVE_CONFIG: | |
435 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { | |
436 | tdmac->dev_addr = dmaengine_cfg->src_addr; | |
437 | tdmac->burst_sz = dmaengine_cfg->src_maxburst; | |
438 | tdmac->buswidth = dmaengine_cfg->src_addr_width; | |
439 | } else { | |
440 | tdmac->dev_addr = dmaengine_cfg->dst_addr; | |
441 | tdmac->burst_sz = dmaengine_cfg->dst_maxburst; | |
442 | tdmac->buswidth = dmaengine_cfg->dst_addr_width; | |
443 | } | |
444 | tdmac->dir = dmaengine_cfg->direction; | |
445 | return mmp_tdma_config_chan(tdmac); | |
446 | default: | |
447 | ret = -ENOSYS; | |
448 | } | |
449 | ||
450 | return ret; | |
451 | } | |
452 | ||
453 | static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, | |
454 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
455 | { | |
456 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
457 | ||
458 | dma_set_residue(txstate, tdmac->buf_len - tdmac->pos); | |
459 | ||
460 | return tdmac->status; | |
461 | } | |
462 | ||
463 | static void mmp_tdma_issue_pending(struct dma_chan *chan) | |
464 | { | |
465 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
466 | ||
467 | mmp_tdma_enable_chan(tdmac); | |
468 | } | |
469 | ||
470 | static int __devexit mmp_tdma_remove(struct platform_device *pdev) | |
471 | { | |
472 | struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); | |
473 | ||
474 | dma_async_device_unregister(&tdev->device); | |
475 | return 0; | |
476 | } | |
477 | ||
463a1f8b | 478 | static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, |
c6da0ba8 ZG |
479 | int idx, int irq, int type) |
480 | { | |
481 | struct mmp_tdma_chan *tdmac; | |
482 | ||
483 | if (idx >= TDMA_CHANNEL_NUM) { | |
484 | dev_err(tdev->dev, "too many channels for device!\n"); | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | /* alloc channel */ | |
489 | tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); | |
490 | if (!tdmac) { | |
491 | dev_err(tdev->dev, "no free memory for DMA channels!\n"); | |
492 | return -ENOMEM; | |
493 | } | |
494 | if (irq) | |
f1a77570 | 495 | tdmac->irq = irq; |
c6da0ba8 ZG |
496 | tdmac->dev = tdev->dev; |
497 | tdmac->chan.device = &tdev->device; | |
498 | tdmac->idx = idx; | |
499 | tdmac->type = type; | |
500 | tdmac->reg_base = (unsigned long)tdev->base + idx * 4; | |
501 | tdmac->status = DMA_SUCCESS; | |
502 | tdev->tdmac[tdmac->idx] = tdmac; | |
503 | tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); | |
504 | ||
505 | /* add the channel to tdma_chan list */ | |
506 | list_add_tail(&tdmac->chan.device_node, | |
507 | &tdev->device.channels); | |
c6da0ba8 ZG |
508 | return 0; |
509 | } | |
510 | ||
f1a77570 ZG |
511 | static struct of_device_id mmp_tdma_dt_ids[] = { |
512 | { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, | |
513 | { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, | |
514 | {} | |
515 | }; | |
516 | MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); | |
517 | ||
463a1f8b | 518 | static int mmp_tdma_probe(struct platform_device *pdev) |
c6da0ba8 | 519 | { |
f1a77570 ZG |
520 | enum mmp_tdma_type type; |
521 | const struct of_device_id *of_id; | |
c6da0ba8 ZG |
522 | struct mmp_tdma_device *tdev; |
523 | struct resource *iores; | |
524 | int i, ret; | |
f1a77570 | 525 | int irq = 0, irq_num = 0; |
c6da0ba8 ZG |
526 | int chan_num = TDMA_CHANNEL_NUM; |
527 | ||
f1a77570 ZG |
528 | of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); |
529 | if (of_id) | |
530 | type = (enum mmp_tdma_type) of_id->data; | |
531 | else | |
532 | type = platform_get_device_id(pdev)->driver_data; | |
533 | ||
c6da0ba8 ZG |
534 | /* always have couple channels */ |
535 | tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); | |
536 | if (!tdev) | |
537 | return -ENOMEM; | |
538 | ||
539 | tdev->dev = &pdev->dev; | |
c6da0ba8 | 540 | |
f1a77570 ZG |
541 | for (i = 0; i < chan_num; i++) { |
542 | if (platform_get_irq(pdev, i) > 0) | |
543 | irq_num++; | |
544 | } | |
c6da0ba8 ZG |
545 | |
546 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
547 | if (!iores) | |
548 | return -EINVAL; | |
549 | ||
550 | tdev->base = devm_request_and_ioremap(&pdev->dev, iores); | |
551 | if (!tdev->base) | |
552 | return -EADDRNOTAVAIL; | |
553 | ||
f1a77570 ZG |
554 | INIT_LIST_HEAD(&tdev->device.channels); |
555 | ||
556 | if (irq_num != chan_num) { | |
557 | irq = platform_get_irq(pdev, 0); | |
558 | ret = devm_request_irq(&pdev->dev, irq, | |
c6da0ba8 ZG |
559 | mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev); |
560 | if (ret) | |
561 | return ret; | |
562 | } | |
563 | ||
c6da0ba8 ZG |
564 | /* initialize channel parameters */ |
565 | for (i = 0; i < chan_num; i++) { | |
f1a77570 | 566 | irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); |
c6da0ba8 ZG |
567 | ret = mmp_tdma_chan_init(tdev, i, irq, type); |
568 | if (ret) | |
569 | return ret; | |
570 | } | |
571 | ||
f1a77570 ZG |
572 | dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); |
573 | dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); | |
c6da0ba8 ZG |
574 | tdev->device.dev = &pdev->dev; |
575 | tdev->device.device_alloc_chan_resources = | |
576 | mmp_tdma_alloc_chan_resources; | |
577 | tdev->device.device_free_chan_resources = | |
578 | mmp_tdma_free_chan_resources; | |
579 | tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; | |
580 | tdev->device.device_tx_status = mmp_tdma_tx_status; | |
581 | tdev->device.device_issue_pending = mmp_tdma_issue_pending; | |
582 | tdev->device.device_control = mmp_tdma_control; | |
583 | tdev->device.copy_align = TDMA_ALIGNMENT; | |
584 | ||
585 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
586 | platform_set_drvdata(pdev, tdev); | |
587 | ||
588 | ret = dma_async_device_register(&tdev->device); | |
589 | if (ret) { | |
590 | dev_err(tdev->device.dev, "unable to register\n"); | |
591 | return ret; | |
592 | } | |
593 | ||
594 | dev_info(tdev->device.dev, "initialized\n"); | |
595 | return 0; | |
596 | } | |
597 | ||
598 | static const struct platform_device_id mmp_tdma_id_table[] = { | |
599 | { "mmp-adma", MMP_AUD_TDMA }, | |
600 | { "pxa910-squ", PXA910_SQU }, | |
601 | { }, | |
602 | }; | |
603 | ||
604 | static struct platform_driver mmp_tdma_driver = { | |
605 | .driver = { | |
606 | .name = "mmp-tdma", | |
607 | .owner = THIS_MODULE, | |
f1a77570 | 608 | .of_match_table = mmp_tdma_dt_ids, |
c6da0ba8 ZG |
609 | }, |
610 | .id_table = mmp_tdma_id_table, | |
611 | .probe = mmp_tdma_probe, | |
a7d6e3ec | 612 | .remove = mmp_tdma_remove, |
c6da0ba8 ZG |
613 | }; |
614 | ||
615 | module_platform_driver(mmp_tdma_driver); | |
616 | ||
617 | MODULE_LICENSE("GPL"); | |
618 | MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); | |
619 | MODULE_ALIAS("platform:mmp-tdma"); | |
620 | MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); | |
621 | MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); |