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Commit | Line | Data |
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ff7b0479 SB |
1 | /* |
2 | * offload engine driver for the Marvell XOR engine | |
3 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ff7b0479 SB |
22 | #include <linux/delay.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/memory.h> | |
c510182b | 28 | #include <linux/clk.h> |
f7d12ef5 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/irqdomain.h> | |
c02cecb9 | 32 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
33 | |
34 | #include "dmaengine.h" | |
ff7b0479 SB |
35 | #include "mv_xor.h" |
36 | ||
37 | static void mv_xor_issue_pending(struct dma_chan *chan); | |
38 | ||
39 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
41 | |
42 | #define to_mv_xor_slot(tx) \ | |
43 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
44 | ||
c98c1781 | 45 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 46 | ((chan)->dmadev.dev) |
c98c1781 | 47 | |
dfc97661 LA |
48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
49 | dma_addr_t addr, u32 byte_count) | |
ff7b0479 SB |
50 | { |
51 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
52 | ||
0e7488ed | 53 | hw_desc->status = XOR_DESC_DMA_OWNED; |
ff7b0479 | 54 | hw_desc->phy_next_desc = 0; |
0e7488ed | 55 | hw_desc->desc_command = XOR_DESC_EOD_INT_EN; |
dfc97661 | 56 | hw_desc->phy_dest_addr = addr; |
ff7b0479 SB |
57 | hw_desc->byte_count = byte_count; |
58 | } | |
59 | ||
60 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, | |
61 | u32 next_desc_addr) | |
62 | { | |
63 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
64 | BUG_ON(hw_desc->phy_next_desc); | |
65 | hw_desc->phy_next_desc = next_desc_addr; | |
66 | } | |
67 | ||
68 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) | |
69 | { | |
70 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
71 | hw_desc->phy_next_desc = 0; | |
72 | } | |
73 | ||
ff7b0479 SB |
74 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
75 | int index, dma_addr_t addr) | |
76 | { | |
77 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 78 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
79 | if (desc->type == DMA_XOR) |
80 | hw_desc->desc_command |= (1 << index); | |
81 | } | |
82 | ||
83 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
84 | { | |
5733c38a | 85 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
86 | } |
87 | ||
88 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
89 | u32 next_desc_addr) | |
90 | { | |
5733c38a | 91 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
92 | } |
93 | ||
ff7b0479 SB |
94 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
95 | { | |
5733c38a | 96 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 97 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 98 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
99 | } |
100 | ||
101 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
102 | { | |
5733c38a | 103 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
104 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
105 | return intr_cause; | |
106 | } | |
107 | ||
ff7b0479 SB |
108 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
109 | { | |
0e7488ed | 110 | u32 val = ~(XOR_INT_END_OF_DESC << (chan->idx * 16)); |
c98c1781 | 111 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 112 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
113 | } |
114 | ||
115 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) | |
116 | { | |
117 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 118 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
119 | } |
120 | ||
ff7b0479 SB |
121 | static void mv_set_mode(struct mv_xor_chan *chan, |
122 | enum dma_transaction_type type) | |
123 | { | |
124 | u32 op_mode; | |
5733c38a | 125 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 SB |
126 | |
127 | switch (type) { | |
128 | case DMA_XOR: | |
129 | op_mode = XOR_OPERATION_MODE_XOR; | |
130 | break; | |
131 | case DMA_MEMCPY: | |
132 | op_mode = XOR_OPERATION_MODE_MEMCPY; | |
133 | break; | |
ff7b0479 | 134 | default: |
c98c1781 | 135 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 136 | "error: unsupported operation %d\n", |
a3fc74bc | 137 | type); |
ff7b0479 SB |
138 | BUG(); |
139 | return; | |
140 | } | |
141 | ||
142 | config &= ~0x7; | |
143 | config |= op_mode; | |
e03bc654 TP |
144 | |
145 | #if defined(__BIG_ENDIAN) | |
146 | config |= XOR_DESCRIPTOR_SWAP; | |
147 | #else | |
148 | config &= ~XOR_DESCRIPTOR_SWAP; | |
149 | #endif | |
150 | ||
5733c38a | 151 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
152 | chan->current_type = type; |
153 | } | |
154 | ||
155 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
156 | { | |
c98c1781 | 157 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5a9a55bf EG |
158 | |
159 | /* writel ensures all descriptors are flushed before activation */ | |
160 | writel(BIT(0), XOR_ACTIVATION(chan)); | |
ff7b0479 SB |
161 | } |
162 | ||
163 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
164 | { | |
5733c38a | 165 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
166 | |
167 | state = (state >> 4) & 0x3; | |
168 | ||
169 | return (state == 1) ? 1 : 0; | |
170 | } | |
171 | ||
ff7b0479 SB |
172 | /** |
173 | * mv_xor_free_slots - flags descriptor slots for reuse | |
174 | * @slot: Slot to free | |
175 | * Caller must hold &mv_chan->lock while calling this function | |
176 | */ | |
177 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, | |
178 | struct mv_xor_desc_slot *slot) | |
179 | { | |
c98c1781 | 180 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
ff7b0479 SB |
181 | __func__, __LINE__, slot); |
182 | ||
dfc97661 | 183 | slot->slot_used = 0; |
ff7b0479 SB |
184 | |
185 | } | |
186 | ||
187 | /* | |
188 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by | |
189 | * sw_desc | |
190 | * Caller must hold &mv_chan->lock while calling this function | |
191 | */ | |
192 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, | |
193 | struct mv_xor_desc_slot *sw_desc) | |
194 | { | |
c98c1781 | 195 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 | 196 | __func__, __LINE__, sw_desc); |
ff7b0479 | 197 | |
48a9db46 BZ |
198 | /* set the hardware chain */ |
199 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
200 | ||
dfc97661 | 201 | mv_chan->pending++; |
98817b99 | 202 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
203 | } |
204 | ||
205 | static dma_cookie_t | |
206 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, | |
207 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) | |
208 | { | |
209 | BUG_ON(desc->async_tx.cookie < 0); | |
210 | ||
211 | if (desc->async_tx.cookie > 0) { | |
212 | cookie = desc->async_tx.cookie; | |
213 | ||
214 | /* call the callback (must not sleep or submit new | |
215 | * operations to this channel) | |
216 | */ | |
217 | if (desc->async_tx.callback) | |
218 | desc->async_tx.callback( | |
219 | desc->async_tx.callback_param); | |
220 | ||
d38a8c62 | 221 | dma_descriptor_unmap(&desc->async_tx); |
ff7b0479 SB |
222 | } |
223 | ||
224 | /* run dependent operations */ | |
07f2211e | 225 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
226 | |
227 | return cookie; | |
228 | } | |
229 | ||
230 | static int | |
231 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) | |
232 | { | |
233 | struct mv_xor_desc_slot *iter, *_iter; | |
234 | ||
c98c1781 | 235 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 SB |
236 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
237 | completed_node) { | |
238 | ||
239 | if (async_tx_test_ack(&iter->async_tx)) { | |
240 | list_del(&iter->completed_node); | |
241 | mv_xor_free_slots(mv_chan, iter); | |
242 | } | |
243 | } | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static int | |
248 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, | |
249 | struct mv_xor_chan *mv_chan) | |
250 | { | |
c98c1781 | 251 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 SB |
252 | __func__, __LINE__, desc, desc->async_tx.flags); |
253 | list_del(&desc->chain_node); | |
254 | /* the client is allowed to attach dependent operations | |
255 | * until 'ack' is set | |
256 | */ | |
257 | if (!async_tx_test_ack(&desc->async_tx)) { | |
258 | /* move this slot to the completed_slots */ | |
259 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); | |
260 | return 0; | |
261 | } | |
262 | ||
263 | mv_xor_free_slots(mv_chan, desc); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
268 | { | |
269 | struct mv_xor_desc_slot *iter, *_iter; | |
270 | dma_cookie_t cookie = 0; | |
271 | int busy = mv_chan_is_busy(mv_chan); | |
272 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
273 | int seen_current = 0; | |
274 | ||
c98c1781 TP |
275 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
276 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
ff7b0479 SB |
277 | mv_xor_clean_completed_slots(mv_chan); |
278 | ||
279 | /* free completed slots from the chain starting with | |
280 | * the oldest descriptor | |
281 | */ | |
282 | ||
283 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
284 | chain_node) { | |
285 | prefetch(_iter); | |
286 | prefetch(&_iter->async_tx); | |
287 | ||
288 | /* do not advance past the current descriptor loaded into the | |
289 | * hardware channel, subsequent descriptors are either in | |
290 | * process or have not been submitted | |
291 | */ | |
292 | if (seen_current) | |
293 | break; | |
294 | ||
295 | /* stop the search if we reach the current descriptor and the | |
296 | * channel is busy | |
297 | */ | |
298 | if (iter->async_tx.phys == current_desc) { | |
299 | seen_current = 1; | |
300 | if (busy) | |
301 | break; | |
302 | } | |
303 | ||
304 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); | |
305 | ||
306 | if (mv_xor_clean_slot(iter, mv_chan)) | |
307 | break; | |
308 | } | |
309 | ||
310 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
311 | struct mv_xor_desc_slot *chain_head; | |
312 | chain_head = list_entry(mv_chan->chain.next, | |
313 | struct mv_xor_desc_slot, | |
314 | chain_node); | |
315 | ||
316 | mv_xor_start_new_chain(mv_chan, chain_head); | |
317 | } | |
318 | ||
319 | if (cookie > 0) | |
98817b99 | 320 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
321 | } |
322 | ||
323 | static void | |
324 | mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
325 | { | |
326 | spin_lock_bh(&mv_chan->lock); | |
327 | __mv_xor_slot_cleanup(mv_chan); | |
328 | spin_unlock_bh(&mv_chan->lock); | |
329 | } | |
330 | ||
331 | static void mv_xor_tasklet(unsigned long data) | |
332 | { | |
333 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; | |
8333f65e | 334 | mv_xor_slot_cleanup(chan); |
ff7b0479 SB |
335 | } |
336 | ||
337 | static struct mv_xor_desc_slot * | |
dfc97661 | 338 | mv_xor_alloc_slot(struct mv_xor_chan *mv_chan) |
ff7b0479 | 339 | { |
dfc97661 LA |
340 | struct mv_xor_desc_slot *iter, *_iter; |
341 | int retry = 0; | |
ff7b0479 SB |
342 | |
343 | /* start search from the last allocated descrtiptor | |
344 | * if a contiguous allocation can not be found start searching | |
345 | * from the beginning of the list | |
346 | */ | |
347 | retry: | |
ff7b0479 SB |
348 | if (retry == 0) |
349 | iter = mv_chan->last_used; | |
350 | else | |
351 | iter = list_entry(&mv_chan->all_slots, | |
352 | struct mv_xor_desc_slot, | |
353 | slot_node); | |
354 | ||
355 | list_for_each_entry_safe_continue( | |
356 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
dfc97661 | 357 | |
ff7b0479 SB |
358 | prefetch(_iter); |
359 | prefetch(&_iter->async_tx); | |
dfc97661 | 360 | if (iter->slot_used) { |
ff7b0479 SB |
361 | /* give up after finding the first busy slot |
362 | * on the second pass through the list | |
363 | */ | |
364 | if (retry) | |
365 | break; | |
ff7b0479 SB |
366 | continue; |
367 | } | |
368 | ||
dfc97661 LA |
369 | /* pre-ack descriptor */ |
370 | async_tx_ack(&iter->async_tx); | |
371 | ||
372 | iter->slot_used = 1; | |
373 | INIT_LIST_HEAD(&iter->chain_node); | |
374 | iter->async_tx.cookie = -EBUSY; | |
375 | mv_chan->last_used = iter; | |
376 | mv_desc_clear_next_desc(iter); | |
377 | ||
378 | return iter; | |
379 | ||
ff7b0479 SB |
380 | } |
381 | if (!retry++) | |
382 | goto retry; | |
383 | ||
384 | /* try to free some slots if the allocation fails */ | |
385 | tasklet_schedule(&mv_chan->irq_tasklet); | |
386 | ||
387 | return NULL; | |
388 | } | |
389 | ||
ff7b0479 SB |
390 | /************************ DMA engine API functions ****************************/ |
391 | static dma_cookie_t | |
392 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
393 | { | |
394 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
395 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
dfc97661 | 396 | struct mv_xor_desc_slot *old_chain_tail; |
ff7b0479 SB |
397 | dma_cookie_t cookie; |
398 | int new_hw_chain = 1; | |
399 | ||
c98c1781 | 400 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
401 | "%s sw_desc %p: async_tx %p\n", |
402 | __func__, sw_desc, &sw_desc->async_tx); | |
403 | ||
ff7b0479 | 404 | spin_lock_bh(&mv_chan->lock); |
884485e1 | 405 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
406 | |
407 | if (list_empty(&mv_chan->chain)) | |
dfc97661 | 408 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
ff7b0479 SB |
409 | else { |
410 | new_hw_chain = 0; | |
411 | ||
412 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
413 | struct mv_xor_desc_slot, | |
414 | chain_node); | |
dfc97661 | 415 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
ff7b0479 | 416 | |
31fd8f5b OJ |
417 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
418 | &old_chain_tail->async_tx.phys); | |
ff7b0479 SB |
419 | |
420 | /* fix up the hardware chain */ | |
dfc97661 | 421 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
ff7b0479 SB |
422 | |
423 | /* if the channel is not busy */ | |
424 | if (!mv_chan_is_busy(mv_chan)) { | |
425 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
426 | /* | |
427 | * and the curren desc is the end of the chain before | |
428 | * the append, then we need to start the channel | |
429 | */ | |
430 | if (current_desc == old_chain_tail->async_tx.phys) | |
431 | new_hw_chain = 1; | |
432 | } | |
433 | } | |
434 | ||
435 | if (new_hw_chain) | |
dfc97661 | 436 | mv_xor_start_new_chain(mv_chan, sw_desc); |
ff7b0479 | 437 | |
ff7b0479 SB |
438 | spin_unlock_bh(&mv_chan->lock); |
439 | ||
440 | return cookie; | |
441 | } | |
442 | ||
443 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 444 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 | 445 | { |
31fd8f5b OJ |
446 | void *virt_desc; |
447 | dma_addr_t dma_desc; | |
ff7b0479 SB |
448 | int idx; |
449 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
450 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 451 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
452 | |
453 | /* Allocate descriptor slots */ | |
454 | idx = mv_chan->slots_allocated; | |
455 | while (idx < num_descs_in_pool) { | |
456 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
457 | if (!slot) { | |
b8291dde EG |
458 | dev_info(mv_chan_to_devp(mv_chan), |
459 | "channel only initialized %d descriptor slots", | |
460 | idx); | |
ff7b0479 SB |
461 | break; |
462 | } | |
31fd8f5b OJ |
463 | virt_desc = mv_chan->dma_desc_pool_virt; |
464 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
465 | |
466 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
467 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
468 | INIT_LIST_HEAD(&slot->chain_node); | |
469 | INIT_LIST_HEAD(&slot->slot_node); | |
31fd8f5b OJ |
470 | dma_desc = mv_chan->dma_desc_pool; |
471 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
472 | slot->idx = idx++; |
473 | ||
474 | spin_lock_bh(&mv_chan->lock); | |
475 | mv_chan->slots_allocated = idx; | |
476 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); | |
477 | spin_unlock_bh(&mv_chan->lock); | |
478 | } | |
479 | ||
480 | if (mv_chan->slots_allocated && !mv_chan->last_used) | |
481 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, | |
482 | struct mv_xor_desc_slot, | |
483 | slot_node); | |
484 | ||
c98c1781 | 485 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
486 | "allocated %d descriptor slots last_used: %p\n", |
487 | mv_chan->slots_allocated, mv_chan->last_used); | |
488 | ||
489 | return mv_chan->slots_allocated ? : -ENOMEM; | |
490 | } | |
491 | ||
ff7b0479 SB |
492 | static struct dma_async_tx_descriptor * |
493 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
494 | unsigned int src_cnt, size_t len, unsigned long flags) | |
495 | { | |
496 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
dfc97661 | 497 | struct mv_xor_desc_slot *sw_desc; |
ff7b0479 SB |
498 | |
499 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
500 | return NULL; | |
501 | ||
7912d300 | 502 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 503 | |
c98c1781 | 504 | dev_dbg(mv_chan_to_devp(mv_chan), |
31fd8f5b OJ |
505 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
506 | __func__, src_cnt, len, &dest, flags); | |
ff7b0479 SB |
507 | |
508 | spin_lock_bh(&mv_chan->lock); | |
dfc97661 | 509 | sw_desc = mv_xor_alloc_slot(mv_chan); |
ff7b0479 SB |
510 | if (sw_desc) { |
511 | sw_desc->type = DMA_XOR; | |
512 | sw_desc->async_tx.flags = flags; | |
dfc97661 | 513 | mv_desc_init(sw_desc, dest, len); |
ff7b0479 SB |
514 | sw_desc->unmap_src_cnt = src_cnt; |
515 | sw_desc->unmap_len = len; | |
516 | while (src_cnt--) | |
dfc97661 | 517 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
ff7b0479 SB |
518 | } |
519 | spin_unlock_bh(&mv_chan->lock); | |
c98c1781 | 520 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
521 | "%s sw_desc %p async_tx %p \n", |
522 | __func__, sw_desc, &sw_desc->async_tx); | |
523 | return sw_desc ? &sw_desc->async_tx : NULL; | |
524 | } | |
525 | ||
3e4f52e2 LA |
526 | static struct dma_async_tx_descriptor * |
527 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
528 | size_t len, unsigned long flags) | |
529 | { | |
530 | /* | |
531 | * A MEMCPY operation is identical to an XOR operation with only | |
532 | * a single source address. | |
533 | */ | |
534 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
535 | } | |
536 | ||
ff7b0479 SB |
537 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
538 | { | |
539 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
540 | struct mv_xor_desc_slot *iter, *_iter; | |
541 | int in_use_descs = 0; | |
542 | ||
543 | mv_xor_slot_cleanup(mv_chan); | |
544 | ||
545 | spin_lock_bh(&mv_chan->lock); | |
546 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
547 | chain_node) { | |
548 | in_use_descs++; | |
549 | list_del(&iter->chain_node); | |
550 | } | |
551 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
552 | completed_node) { | |
553 | in_use_descs++; | |
554 | list_del(&iter->completed_node); | |
555 | } | |
556 | list_for_each_entry_safe_reverse( | |
557 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
558 | list_del(&iter->slot_node); | |
559 | kfree(iter); | |
560 | mv_chan->slots_allocated--; | |
561 | } | |
562 | mv_chan->last_used = NULL; | |
563 | ||
c98c1781 | 564 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
565 | __func__, mv_chan->slots_allocated); |
566 | spin_unlock_bh(&mv_chan->lock); | |
567 | ||
568 | if (in_use_descs) | |
c98c1781 | 569 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
570 | "freeing %d in use descriptors!\n", in_use_descs); |
571 | } | |
572 | ||
573 | /** | |
07934481 | 574 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
575 | * @chan: XOR channel handle |
576 | * @cookie: XOR transaction identifier | |
07934481 | 577 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 578 | */ |
07934481 | 579 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 580 | dma_cookie_t cookie, |
07934481 | 581 | struct dma_tx_state *txstate) |
ff7b0479 SB |
582 | { |
583 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
584 | enum dma_status ret; |
585 | ||
96a2af41 | 586 | ret = dma_cookie_status(chan, cookie, txstate); |
b3efb8fc | 587 | if (ret == DMA_COMPLETE) { |
ff7b0479 SB |
588 | mv_xor_clean_completed_slots(mv_chan); |
589 | return ret; | |
590 | } | |
591 | mv_xor_slot_cleanup(mv_chan); | |
592 | ||
96a2af41 | 593 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
594 | } |
595 | ||
596 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) | |
597 | { | |
598 | u32 val; | |
599 | ||
5733c38a | 600 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 601 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 602 | |
5733c38a | 603 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 604 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 605 | |
5733c38a | 606 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 607 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 608 | |
5733c38a | 609 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 610 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 611 | |
5733c38a | 612 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 613 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 614 | |
5733c38a | 615 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 616 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
617 | } |
618 | ||
619 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, | |
620 | u32 intr_cause) | |
621 | { | |
0e7488ed EG |
622 | if (intr_cause & XOR_INT_ERR_DECODE) { |
623 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); | |
624 | return; | |
ff7b0479 SB |
625 | } |
626 | ||
0e7488ed | 627 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 628 | chan->idx, intr_cause); |
ff7b0479 SB |
629 | |
630 | mv_dump_xor_regs(chan); | |
0e7488ed | 631 | WARN_ON(1); |
ff7b0479 SB |
632 | } |
633 | ||
634 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
635 | { | |
636 | struct mv_xor_chan *chan = data; | |
637 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
638 | ||
c98c1781 | 639 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 | 640 | |
0e7488ed | 641 | if (intr_cause & XOR_INTR_ERRORS) |
ff7b0479 SB |
642 | mv_xor_err_interrupt_handler(chan, intr_cause); |
643 | ||
644 | tasklet_schedule(&chan->irq_tasklet); | |
645 | ||
646 | mv_xor_device_clear_eoc_cause(chan); | |
647 | ||
648 | return IRQ_HANDLED; | |
649 | } | |
650 | ||
651 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
652 | { | |
653 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
654 | ||
655 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
656 | mv_chan->pending = 0; | |
657 | mv_chan_activate(mv_chan); | |
658 | } | |
659 | } | |
660 | ||
661 | /* | |
662 | * Perform a transaction to verify the HW works. | |
663 | */ | |
ff7b0479 | 664 | |
c2714334 | 665 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
666 | { |
667 | int i; | |
668 | void *src, *dest; | |
669 | dma_addr_t src_dma, dest_dma; | |
670 | struct dma_chan *dma_chan; | |
671 | dma_cookie_t cookie; | |
672 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 673 | struct dmaengine_unmap_data *unmap; |
ff7b0479 | 674 | int err = 0; |
ff7b0479 | 675 | |
d16695a7 | 676 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
677 | if (!src) |
678 | return -ENOMEM; | |
679 | ||
d16695a7 | 680 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
681 | if (!dest) { |
682 | kfree(src); | |
683 | return -ENOMEM; | |
684 | } | |
685 | ||
686 | /* Fill in src buffer */ | |
d16695a7 | 687 | for (i = 0; i < PAGE_SIZE; i++) |
ff7b0479 SB |
688 | ((u8 *) src)[i] = (u8)i; |
689 | ||
275cc0c8 | 690 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 691 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
692 | err = -ENODEV; |
693 | goto out; | |
694 | } | |
695 | ||
d16695a7 EG |
696 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
697 | if (!unmap) { | |
698 | err = -ENOMEM; | |
699 | goto free_resources; | |
700 | } | |
701 | ||
702 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, | |
703 | PAGE_SIZE, DMA_TO_DEVICE); | |
704 | unmap->to_cnt = 1; | |
705 | unmap->addr[0] = src_dma; | |
ff7b0479 | 706 | |
d16695a7 EG |
707 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
708 | PAGE_SIZE, DMA_FROM_DEVICE); | |
709 | unmap->from_cnt = 1; | |
710 | unmap->addr[1] = dest_dma; | |
711 | ||
712 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
713 | |
714 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
d16695a7 | 715 | PAGE_SIZE, 0); |
ff7b0479 SB |
716 | cookie = mv_xor_tx_submit(tx); |
717 | mv_xor_issue_pending(dma_chan); | |
718 | async_tx_ack(tx); | |
719 | msleep(1); | |
720 | ||
07934481 | 721 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 722 | DMA_COMPLETE) { |
a3fc74bc TP |
723 | dev_err(dma_chan->device->dev, |
724 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
725 | err = -ENODEV; |
726 | goto free_resources; | |
727 | } | |
728 | ||
c35064c4 | 729 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
d16695a7 EG |
730 | PAGE_SIZE, DMA_FROM_DEVICE); |
731 | if (memcmp(src, dest, PAGE_SIZE)) { | |
a3fc74bc TP |
732 | dev_err(dma_chan->device->dev, |
733 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
734 | err = -ENODEV; |
735 | goto free_resources; | |
736 | } | |
737 | ||
738 | free_resources: | |
d16695a7 | 739 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
740 | mv_xor_free_chan_resources(dma_chan); |
741 | out: | |
742 | kfree(src); | |
743 | kfree(dest); | |
744 | return err; | |
745 | } | |
746 | ||
747 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 748 | static int |
275cc0c8 | 749 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
750 | { |
751 | int i, src_idx; | |
752 | struct page *dest; | |
753 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
754 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
755 | dma_addr_t dest_dma; | |
756 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 757 | struct dmaengine_unmap_data *unmap; |
ff7b0479 SB |
758 | struct dma_chan *dma_chan; |
759 | dma_cookie_t cookie; | |
760 | u8 cmp_byte = 0; | |
761 | u32 cmp_word; | |
762 | int err = 0; | |
d16695a7 | 763 | int src_count = MV_XOR_NUM_SRC_TEST; |
ff7b0479 | 764 | |
d16695a7 | 765 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 | 766 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae RK |
767 | if (!xor_srcs[src_idx]) { |
768 | while (src_idx--) | |
ff7b0479 | 769 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
770 | return -ENOMEM; |
771 | } | |
ff7b0479 SB |
772 | } |
773 | ||
774 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
775 | if (!dest) { |
776 | while (src_idx--) | |
ff7b0479 | 777 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
778 | return -ENOMEM; |
779 | } | |
ff7b0479 SB |
780 | |
781 | /* Fill in src buffers */ | |
d16695a7 | 782 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 SB |
783 | u8 *ptr = page_address(xor_srcs[src_idx]); |
784 | for (i = 0; i < PAGE_SIZE; i++) | |
785 | ptr[i] = (1 << src_idx); | |
786 | } | |
787 | ||
d16695a7 | 788 | for (src_idx = 0; src_idx < src_count; src_idx++) |
ff7b0479 SB |
789 | cmp_byte ^= (u8) (1 << src_idx); |
790 | ||
791 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
792 | (cmp_byte << 8) | cmp_byte; | |
793 | ||
794 | memset(page_address(dest), 0, PAGE_SIZE); | |
795 | ||
275cc0c8 | 796 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 797 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
798 | err = -ENODEV; |
799 | goto out; | |
800 | } | |
801 | ||
d16695a7 EG |
802 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
803 | GFP_KERNEL); | |
804 | if (!unmap) { | |
805 | err = -ENOMEM; | |
806 | goto free_resources; | |
807 | } | |
808 | ||
ff7b0479 | 809 | /* test xor */ |
d16695a7 EG |
810 | for (i = 0; i < src_count; i++) { |
811 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
812 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
813 | dma_srcs[i] = unmap->addr[i]; | |
814 | unmap->to_cnt++; | |
815 | } | |
ff7b0479 | 816 | |
d16695a7 EG |
817 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
818 | DMA_FROM_DEVICE); | |
819 | dest_dma = unmap->addr[src_count]; | |
820 | unmap->from_cnt = 1; | |
821 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
822 | |
823 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
d16695a7 | 824 | src_count, PAGE_SIZE, 0); |
ff7b0479 SB |
825 | |
826 | cookie = mv_xor_tx_submit(tx); | |
827 | mv_xor_issue_pending(dma_chan); | |
828 | async_tx_ack(tx); | |
829 | msleep(8); | |
830 | ||
07934481 | 831 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 832 | DMA_COMPLETE) { |
a3fc74bc TP |
833 | dev_err(dma_chan->device->dev, |
834 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
835 | err = -ENODEV; |
836 | goto free_resources; | |
837 | } | |
838 | ||
c35064c4 | 839 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
840 | PAGE_SIZE, DMA_FROM_DEVICE); |
841 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
842 | u32 *ptr = page_address(dest); | |
843 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 844 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
845 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
846 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
847 | err = -ENODEV; |
848 | goto free_resources; | |
849 | } | |
850 | } | |
851 | ||
852 | free_resources: | |
d16695a7 | 853 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
854 | mv_xor_free_chan_resources(dma_chan); |
855 | out: | |
d16695a7 | 856 | src_idx = src_count; |
ff7b0479 SB |
857 | while (src_idx--) |
858 | __free_page(xor_srcs[src_idx]); | |
859 | __free_page(dest); | |
860 | return err; | |
861 | } | |
862 | ||
34c93c86 AL |
863 | /* This driver does not implement any of the optional DMA operations. */ |
864 | static int | |
865 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
866 | unsigned long arg) | |
867 | { | |
868 | return -ENOSYS; | |
869 | } | |
870 | ||
1ef48a26 | 871 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 872 | { |
ff7b0479 | 873 | struct dma_chan *chan, *_chan; |
1ef48a26 | 874 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 875 | |
1ef48a26 | 876 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 877 | |
b503fa01 | 878 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 879 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
ff7b0479 | 880 | |
1ef48a26 | 881 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 882 | device_node) { |
ff7b0479 SB |
883 | list_del(&chan->device_node); |
884 | } | |
885 | ||
88eb92cb TP |
886 | free_irq(mv_chan->irq, mv_chan); |
887 | ||
ff7b0479 SB |
888 | return 0; |
889 | } | |
890 | ||
1ef48a26 | 891 | static struct mv_xor_chan * |
297eedba | 892 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 893 | struct platform_device *pdev, |
b503fa01 | 894 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
895 | { |
896 | int ret = 0; | |
ff7b0479 SB |
897 | struct mv_xor_chan *mv_chan; |
898 | struct dma_device *dma_dev; | |
ff7b0479 | 899 | |
1ef48a26 | 900 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
901 | if (!mv_chan) |
902 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 903 | |
9aedbdba | 904 | mv_chan->idx = idx; |
88eb92cb | 905 | mv_chan->irq = irq; |
ff7b0479 | 906 | |
1ef48a26 | 907 | dma_dev = &mv_chan->dmadev; |
ff7b0479 SB |
908 | |
909 | /* allocate coherent memory for hardware descriptors | |
910 | * note: writecombine gives slightly better performance, but | |
911 | * requires that we explicitly flush the writes | |
912 | */ | |
1ef48a26 | 913 | mv_chan->dma_desc_pool_virt = |
b503fa01 | 914 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 TP |
915 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
916 | if (!mv_chan->dma_desc_pool_virt) | |
a6b4a9d2 | 917 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
918 | |
919 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 920 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
921 | |
922 | INIT_LIST_HEAD(&dma_dev->channels); | |
923 | ||
924 | /* set base routines */ | |
925 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
926 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 927 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 | 928 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
34c93c86 | 929 | dma_dev->device_control = mv_xor_control; |
ff7b0479 SB |
930 | dma_dev->dev = &pdev->dev; |
931 | ||
932 | /* set prep routines based on capability */ | |
933 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
934 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 935 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 936 | dma_dev->max_xor = 8; |
ff7b0479 SB |
937 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
938 | } | |
939 | ||
297eedba | 940 | mv_chan->mmr_base = xordev->xor_base; |
82a1402e | 941 | mv_chan->mmr_high_base = xordev->xor_high_base; |
ff7b0479 SB |
942 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
943 | mv_chan); | |
944 | ||
945 | /* clear errors before enabling interrupts */ | |
946 | mv_xor_device_clear_err_status(mv_chan); | |
947 | ||
2d0a0745 TP |
948 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
949 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
950 | if (ret) |
951 | goto err_free_dma; | |
952 | ||
953 | mv_chan_unmask_interrupts(mv_chan); | |
954 | ||
3e4f52e2 | 955 | mv_set_mode(mv_chan, DMA_XOR); |
ff7b0479 SB |
956 | |
957 | spin_lock_init(&mv_chan->lock); | |
958 | INIT_LIST_HEAD(&mv_chan->chain); | |
959 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
960 | INIT_LIST_HEAD(&mv_chan->all_slots); | |
98817b99 TP |
961 | mv_chan->dmachan.device = dma_dev; |
962 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 963 | |
98817b99 | 964 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
965 | |
966 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
275cc0c8 | 967 | ret = mv_xor_memcpy_self_test(mv_chan); |
ff7b0479 SB |
968 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
969 | if (ret) | |
2d0a0745 | 970 | goto err_free_irq; |
ff7b0479 SB |
971 | } |
972 | ||
973 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
275cc0c8 | 974 | ret = mv_xor_xor_self_test(mv_chan); |
ff7b0479 SB |
975 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
976 | if (ret) | |
2d0a0745 | 977 | goto err_free_irq; |
ff7b0479 SB |
978 | } |
979 | ||
48a9db46 | 980 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
1ba151cd | 981 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
982 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
983 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 SB |
984 | |
985 | dma_async_device_register(dma_dev); | |
1ef48a26 | 986 | return mv_chan; |
ff7b0479 | 987 | |
2d0a0745 TP |
988 | err_free_irq: |
989 | free_irq(mv_chan->irq, mv_chan); | |
ff7b0479 | 990 | err_free_dma: |
b503fa01 | 991 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 992 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 993 | return ERR_PTR(ret); |
ff7b0479 SB |
994 | } |
995 | ||
996 | static void | |
297eedba | 997 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 998 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 999 | { |
82a1402e | 1000 | void __iomem *base = xordev->xor_high_base; |
ff7b0479 SB |
1001 | u32 win_enable = 0; |
1002 | int i; | |
1003 | ||
1004 | for (i = 0; i < 8; i++) { | |
1005 | writel(0, base + WINDOW_BASE(i)); | |
1006 | writel(0, base + WINDOW_SIZE(i)); | |
1007 | if (i < 4) | |
1008 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1009 | } | |
1010 | ||
1011 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1012 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1013 | |
1014 | writel((cs->base & 0xffff0000) | | |
1015 | (cs->mbus_attr << 8) | | |
1016 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1017 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1018 | ||
1019 | win_enable |= (1 << i); | |
1020 | win_enable |= 3 << (16 + (2 * i)); | |
1021 | } | |
1022 | ||
1023 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1024 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1025 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1026 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1027 | } |
1028 | ||
c2714334 | 1029 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1030 | { |
63a9332b | 1031 | const struct mbus_dram_target_info *dram; |
297eedba | 1032 | struct mv_xor_device *xordev; |
d4adcc01 | 1033 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1034 | struct resource *res; |
60d151f3 | 1035 | int i, ret; |
ff7b0479 | 1036 | |
1ba151cd | 1037 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1038 | |
297eedba TP |
1039 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1040 | if (!xordev) | |
ff7b0479 SB |
1041 | return -ENOMEM; |
1042 | ||
1043 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1044 | if (!res) | |
1045 | return -ENODEV; | |
1046 | ||
297eedba TP |
1047 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1048 | resource_size(res)); | |
1049 | if (!xordev->xor_base) | |
ff7b0479 SB |
1050 | return -EBUSY; |
1051 | ||
1052 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1053 | if (!res) | |
1054 | return -ENODEV; | |
1055 | ||
297eedba TP |
1056 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1057 | resource_size(res)); | |
1058 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1059 | return -EBUSY; |
1060 | ||
297eedba | 1061 | platform_set_drvdata(pdev, xordev); |
ff7b0479 SB |
1062 | |
1063 | /* | |
1064 | * (Re-)program MBUS remapping windows if we are asked to. | |
1065 | */ | |
63a9332b AL |
1066 | dram = mv_mbus_dram_info(); |
1067 | if (dram) | |
297eedba | 1068 | mv_xor_conf_mbus_windows(xordev, dram); |
ff7b0479 | 1069 | |
c510182b AL |
1070 | /* Not all platforms can gate the clock, so it is not |
1071 | * an error if the clock does not exists. | |
1072 | */ | |
297eedba TP |
1073 | xordev->clk = clk_get(&pdev->dev, NULL); |
1074 | if (!IS_ERR(xordev->clk)) | |
1075 | clk_prepare_enable(xordev->clk); | |
c510182b | 1076 | |
f7d12ef5 TP |
1077 | if (pdev->dev.of_node) { |
1078 | struct device_node *np; | |
1079 | int i = 0; | |
1080 | ||
1081 | for_each_child_of_node(pdev->dev.of_node, np) { | |
0be8253f | 1082 | struct mv_xor_chan *chan; |
f7d12ef5 TP |
1083 | dma_cap_mask_t cap_mask; |
1084 | int irq; | |
1085 | ||
1086 | dma_cap_zero(cap_mask); | |
1087 | if (of_property_read_bool(np, "dmacap,memcpy")) | |
1088 | dma_cap_set(DMA_MEMCPY, cap_mask); | |
1089 | if (of_property_read_bool(np, "dmacap,xor")) | |
1090 | dma_cap_set(DMA_XOR, cap_mask); | |
f7d12ef5 TP |
1091 | if (of_property_read_bool(np, "dmacap,interrupt")) |
1092 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
1093 | ||
1094 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1095 | if (!irq) { |
1096 | ret = -ENODEV; | |
f7d12ef5 TP |
1097 | goto err_channel_add; |
1098 | } | |
1099 | ||
0be8253f RK |
1100 | chan = mv_xor_channel_add(xordev, pdev, i, |
1101 | cap_mask, irq); | |
1102 | if (IS_ERR(chan)) { | |
1103 | ret = PTR_ERR(chan); | |
f7d12ef5 TP |
1104 | irq_dispose_mapping(irq); |
1105 | goto err_channel_add; | |
1106 | } | |
1107 | ||
0be8253f | 1108 | xordev->channels[i] = chan; |
f7d12ef5 TP |
1109 | i++; |
1110 | } | |
1111 | } else if (pdata && pdata->channels) { | |
60d151f3 | 1112 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
e39f6ec1 | 1113 | struct mv_xor_channel_data *cd; |
0be8253f | 1114 | struct mv_xor_chan *chan; |
60d151f3 TP |
1115 | int irq; |
1116 | ||
1117 | cd = &pdata->channels[i]; | |
1118 | if (!cd) { | |
1119 | ret = -ENODEV; | |
1120 | goto err_channel_add; | |
1121 | } | |
1122 | ||
1123 | irq = platform_get_irq(pdev, i); | |
1124 | if (irq < 0) { | |
1125 | ret = irq; | |
1126 | goto err_channel_add; | |
1127 | } | |
1128 | ||
0be8253f RK |
1129 | chan = mv_xor_channel_add(xordev, pdev, i, |
1130 | cd->cap_mask, irq); | |
1131 | if (IS_ERR(chan)) { | |
1132 | ret = PTR_ERR(chan); | |
60d151f3 TP |
1133 | goto err_channel_add; |
1134 | } | |
0be8253f RK |
1135 | |
1136 | xordev->channels[i] = chan; | |
60d151f3 TP |
1137 | } |
1138 | } | |
c510182b | 1139 | |
ff7b0479 | 1140 | return 0; |
60d151f3 TP |
1141 | |
1142 | err_channel_add: | |
1143 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1144 | if (xordev->channels[i]) { |
ab6e439f | 1145 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1146 | if (pdev->dev.of_node) |
1147 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1148 | } |
60d151f3 | 1149 | |
dab92064 TP |
1150 | if (!IS_ERR(xordev->clk)) { |
1151 | clk_disable_unprepare(xordev->clk); | |
1152 | clk_put(xordev->clk); | |
1153 | } | |
1154 | ||
60d151f3 | 1155 | return ret; |
ff7b0479 SB |
1156 | } |
1157 | ||
c2714334 | 1158 | static int mv_xor_remove(struct platform_device *pdev) |
ff7b0479 | 1159 | { |
297eedba | 1160 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
60d151f3 TP |
1161 | int i; |
1162 | ||
1163 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
297eedba TP |
1164 | if (xordev->channels[i]) |
1165 | mv_xor_channel_remove(xordev->channels[i]); | |
60d151f3 | 1166 | } |
c510182b | 1167 | |
297eedba TP |
1168 | if (!IS_ERR(xordev->clk)) { |
1169 | clk_disable_unprepare(xordev->clk); | |
1170 | clk_put(xordev->clk); | |
c510182b AL |
1171 | } |
1172 | ||
ff7b0479 SB |
1173 | return 0; |
1174 | } | |
1175 | ||
f7d12ef5 | 1176 | #ifdef CONFIG_OF |
c2714334 | 1177 | static struct of_device_id mv_xor_dt_ids[] = { |
f7d12ef5 TP |
1178 | { .compatible = "marvell,orion-xor", }, |
1179 | {}, | |
1180 | }; | |
1181 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); | |
1182 | #endif | |
1183 | ||
61971656 TP |
1184 | static struct platform_driver mv_xor_driver = { |
1185 | .probe = mv_xor_probe, | |
c2714334 | 1186 | .remove = mv_xor_remove, |
ff7b0479 | 1187 | .driver = { |
f7d12ef5 TP |
1188 | .owner = THIS_MODULE, |
1189 | .name = MV_XOR_NAME, | |
1190 | .of_match_table = of_match_ptr(mv_xor_dt_ids), | |
ff7b0479 SB |
1191 | }, |
1192 | }; | |
1193 | ||
1194 | ||
1195 | static int __init mv_xor_init(void) | |
1196 | { | |
61971656 | 1197 | return platform_driver_register(&mv_xor_driver); |
ff7b0479 SB |
1198 | } |
1199 | module_init(mv_xor_init); | |
1200 | ||
1201 | /* it's currently unsafe to unload this module */ | |
1202 | #if 0 | |
1203 | static void __exit mv_xor_exit(void) | |
1204 | { | |
1205 | platform_driver_unregister(&mv_xor_driver); | |
ff7b0479 SB |
1206 | return; |
1207 | } | |
1208 | ||
1209 | module_exit(mv_xor_exit); | |
1210 | #endif | |
1211 | ||
1212 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); | |
1213 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1214 | MODULE_LICENSE("GPL"); |